target-mips/cpu.c

   1 /*
   2  * QEMU MIPS CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "qemu/osdep.h"
  22 #include "cpu.h"
  23 #include "kvm_mips.h"
  24 #include "qemu-common.h"
  25 #include "sysemu/kvm.h"
  26
  27
  28 static void mips_cpu_set_pc(CPUState *cs, vaddr value)
  29 {
  30     MIPSCPU *cpu = MIPS_CPU(cs);
  31     CPUMIPSState *env = &cpu->env;
  32
  33     env->active_tc.PC = value & ~(target_ulong)1;
  34     if (value & 1) {
  35         env->hflags |= MIPS_HFLAG_M16;
  36     } else {
  37         env->hflags &= ~(MIPS_HFLAG_M16);
  38     }
  39 }
  40
  41 static void mips_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
  42 {
  43     MIPSCPU *cpu = MIPS_CPU(cs);
  44     CPUMIPSState *env = &cpu->env;
  45
  46     env->active_tc.PC = tb->pc;
  47     env->hflags &= ~MIPS_HFLAG_BMASK;
  48     env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
  49 }
  50
  51 static bool mips_cpu_has_work(CPUState *cs)
  52 {
  53     MIPSCPU *cpu = MIPS_CPU(cs);
  54     CPUMIPSState *env = &cpu->env;
  55     bool has_work = false;
  56
  57     /* Prior to MIPS Release 6 it is implementation dependent if non-enabled
  58        interrupts wake-up the CPU, however most of the implementations only
  59        check for interrupts that can be taken. */
  60     if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
  61         cpu_mips_hw_interrupts_pending(env)) {
  62         if (cpu_mips_hw_interrupts_enabled(env) ||
  63             (env->insn_flags & ISA_MIPS32R6)) {
  64             has_work = true;
  65         }
  66     }
  67
  68     /* MIPS-MT has the ability to halt the CPU.  */
  69     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
  70         /* The QEMU model will issue an _WAKE request whenever the CPUs
  71            should be woken up.  */
  72         if (cs->interrupt_request & CPU_INTERRUPT_WAKE) {
  73             has_work = true;
  74         }
  75
  76         if (!mips_vpe_active(env)) {
  77             has_work = false;
  78         }
  79     }
  80     return has_work;
  81 }
  82
  83 /* CPUClass::reset() */
  84 static void mips_cpu_reset(CPUState *s)
  85 {
  86     MIPSCPU *cpu = MIPS_CPU(s);
  87     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu);
  88     CPUMIPSState *env = &cpu->env;
  89
  90     mcc->parent_reset(s);
  91
  92     memset(env, 0, offsetof(CPUMIPSState, mvp));
  93     tlb_flush(s, 1);
  94
  95     cpu_state_reset(env);
  96
  97 #ifndef CONFIG_USER_ONLY
  98     if (kvm_enabled()) {
  99         kvm_mips_reset_vcpu(cpu);
 100     }
 101 #endif
 102 }
 103
 104 static void mips_cpu_disas_set_info(CPUState *s, disassemble_info *info) {
 105 #ifdef TARGET_WORDS_BIGENDIAN
 106     info->print_insn = print_insn_big_mips;
 107 #else
 108     info->print_insn = print_insn_little_mips;
 109 #endif
 110 }
 111
 112 static void mips_cpu_realizefn(DeviceState *dev, Error **errp)
 113 {
 114     CPUState *cs = CPU(dev);
 115     MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev);
 116
 117     cpu_reset(cs);
 118     qemu_init_vcpu(cs);
 119
 120     mcc->parent_realize(dev, errp);
 121 }
 122
 123 static void mips_cpu_initfn(Object *obj)
 124 {
 125     CPUState *cs = CPU(obj);
 126     MIPSCPU *cpu = MIPS_CPU(obj);
 127     CPUMIPSState *env = &cpu->env;
 128
 129     cs->env_ptr = env;
 130     cpu_exec_init(cs, &error_abort);
 131
 132     if (tcg_enabled()) {
 133         mips_tcg_init();
 134     }
 135 }
 136
 137 static void mips_cpu_class_init(ObjectClass *c, void *data)
 138 {
 139     MIPSCPUClass *mcc = MIPS_CPU_CLASS(c);
 140     CPUClass *cc = CPU_CLASS(c);
 141     DeviceClass *dc = DEVICE_CLASS(c);
 142
 143     mcc->parent_realize = dc->realize;
 144     dc->realize = mips_cpu_realizefn;
 145
 146     mcc->parent_reset = cc->reset;
 147     cc->reset = mips_cpu_reset;
 148
 149     cc->has_work = mips_cpu_has_work;
 150     cc->do_interrupt = mips_cpu_do_interrupt;
 151     cc->cpu_exec_interrupt = mips_cpu_exec_interrupt;
 152     cc->dump_state = mips_cpu_dump_state;
 153     cc->set_pc = mips_cpu_set_pc;
 154     cc->synchronize_from_tb = mips_cpu_synchronize_from_tb;
 155     cc->gdb_read_register = mips_cpu_gdb_read_register;
 156     cc->gdb_write_register = mips_cpu_gdb_write_register;
 157 #ifdef CONFIG_USER_ONLY
 158     cc->handle_mmu_fault = mips_cpu_handle_mmu_fault;
 159 #else
 160     cc->do_unassigned_access = mips_cpu_unassigned_access;
 161     cc->do_unaligned_access = mips_cpu_do_unaligned_access;
 162     cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
 163     cc->vmsd = &vmstate_mips_cpu;
 164 #endif
 165     cc->disas_set_info = mips_cpu_disas_set_info;
 166
 167     cc->gdb_num_core_regs = 73;
 168     cc->gdb_stop_before_watchpoint = true;
 169
 170     /*
 171      * Reason: mips_cpu_initfn() calls cpu_exec_init(), which saves
 172      * the object in cpus -> dangling pointer after final
 173      * object_unref().
 174      */
 175     dc->cannot_destroy_with_object_finalize_yet = true;
 176 }
 177
 178 static const TypeInfo mips_cpu_type_info = {
 179     .name = TYPE_MIPS_CPU,
 180     .parent = TYPE_CPU,
 181     .instance_size = sizeof(MIPSCPU),
 182     .instance_init = mips_cpu_initfn,
 183     .abstract = false,
 184     .class_size = sizeof(MIPSCPUClass),
 185     .class_init = mips_cpu_class_init,
 186 };
 187
 188 static void mips_cpu_register_types(void)
 189 {
 190     type_register_static(&mips_cpu_type_info);
 191 }
 192
 193 type_init(mips_cpu_register_types)