target-arm/op_helper.c

   1 /*
   2  *  ARM helper routines
   3  *
   4  *  Copyright (c) 2005-2007 CodeSourcery, LLC
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "cpu.h"
  21 #include "exec/helper-proto.h"
  22 #include "internals.h"
  23 #include "exec/cpu_ldst.h"
  24
  25 #define SIGNBIT (uint32_t)0x80000000
  26 #define SIGNBIT64 ((uint64_t)1 << 63)
  27
  28 static void raise_exception(CPUARMState *env, uint32_t excp,
  29                             uint32_t syndrome, uint32_t target_el)
  30 {
  31     CPUState *cs = CPU(arm_env_get_cpu(env));
  32
  33     assert(!excp_is_internal(excp));
  34     cs->exception_index = excp;
  35     env->exception.syndrome = syndrome;
  36     env->exception.target_el = target_el;
  37     cpu_loop_exit(cs);
  38 }
  39
  40 static int exception_target_el(CPUARMState *env)
  41 {
  42     int target_el = MAX(1, arm_current_el(env));
  43
  44     /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL
  45      * to EL3 in this case.
  46      */
  47     if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
  48         target_el = 3;
  49     }
  50
  51     return target_el;
  52 }
  53
  54 uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
  55                           uint32_t rn, uint32_t maxindex)
  56 {
  57     uint32_t val;
  58     uint32_t tmp;
  59     int index;
  60     int shift;
  61     uint64_t *table;
  62     table = (uint64_t *)&env->vfp.regs[rn];
  63     val = 0;
  64     for (shift = 0; shift < 32; shift += 8) {
  65         index = (ireg >> shift) & 0xff;
  66         if (index < maxindex) {
  67             tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
  68             val |= tmp << shift;
  69         } else {
  70             val |= def & (0xff << shift);
  71         }
  72     }
  73     return val;
  74 }
  75
  76 #if !defined(CONFIG_USER_ONLY)
  77
  78 /* try to fill the TLB and return an exception if error. If retaddr is
  79  * NULL, it means that the function was called in C code (i.e. not
  80  * from generated code or from helper.c)
  81  */
  82 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
  83               uintptr_t retaddr)
  84 {
  85     bool ret;
  86     uint32_t fsr = 0;
  87     ARMMMUFaultInfo fi = {};
  88
  89     ret = arm_tlb_fill(cs, addr, is_write, mmu_idx, &fsr, &fi);
  90     if (unlikely(ret)) {
  91         ARMCPU *cpu = ARM_CPU(cs);
  92         CPUARMState *env = &cpu->env;
  93         uint32_t syn, exc;
  94         unsigned int target_el;
  95         bool same_el;
  96
  97         if (retaddr) {
  98             /* now we have a real cpu fault */
  99             cpu_restore_state(cs, retaddr);
 100         }
 101
 102         target_el = exception_target_el(env);
 103         if (fi.stage2) {
 104             target_el = 2;
 105             env->cp15.hpfar_el2 = extract64(fi.s2addr, 12, 47) << 4;
 106         }
 107         same_el = arm_current_el(env) == target_el;
 108         /* AArch64 syndrome does not have an LPAE bit */
 109         syn = fsr & ~(1 << 9);
 110
 111         /* For insn and data aborts we assume there is no instruction syndrome
 112          * information; this is always true for exceptions reported to EL1.
 113          */
 114         if (is_write == 2) {
 115             syn = syn_insn_abort(same_el, 0, fi.s1ptw, syn);
 116             exc = EXCP_PREFETCH_ABORT;
 117         } else {
 118             syn = syn_data_abort(same_el, 0, 0, fi.s1ptw, is_write == 1, syn);
 119             if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) {
 120                 fsr |= (1 << 11);
 121             }
 122             exc = EXCP_DATA_ABORT;
 123         }
 124
 125         env->exception.vaddress = addr;
 126         env->exception.fsr = fsr;
 127         raise_exception(env, exc, syn, target_el);
 128     }
 129 }
 130
 131 /* Raise a data fault alignment exception for the specified virtual address */
 132 void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, int is_write,
 133                                  int is_user, uintptr_t retaddr)
 134 {
 135     ARMCPU *cpu = ARM_CPU(cs);
 136     CPUARMState *env = &cpu->env;
 137     int target_el;
 138     bool same_el;
 139
 140     if (retaddr) {
 141         /* now we have a real cpu fault */
 142         cpu_restore_state(cs, retaddr);
 143     }
 144
 145     target_el = exception_target_el(env);
 146     same_el = (arm_current_el(env) == target_el);
 147
 148     env->exception.vaddress = vaddr;
 149
 150     /* the DFSR for an alignment fault depends on whether we're using
 151      * the LPAE long descriptor format, or the short descriptor format
 152      */
 153     if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) {
 154         env->exception.fsr = 0x21;
 155     } else {
 156         env->exception.fsr = 0x1;
 157     }
 158
 159     if (is_write == 1 && arm_feature(env, ARM_FEATURE_V6)) {
 160         env->exception.fsr |= (1 << 11);
 161     }
 162
 163     raise_exception(env, EXCP_DATA_ABORT,
 164                     syn_data_abort(same_el, 0, 0, 0, is_write == 1, 0x21),
 165                     target_el);
 166 }
 167
 168 #endif /* !defined(CONFIG_USER_ONLY) */
 169
 170 uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
 171 {
 172     uint32_t res = a + b;
 173     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
 174         env->QF = 1;
 175     return res;
 176 }
 177
 178 uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 179 {
 180     uint32_t res = a + b;
 181     if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
 182         env->QF = 1;
 183         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
 184     }
 185     return res;
 186 }
 187
 188 uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
 189 {
 190     uint32_t res = a - b;
 191     if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
 192         env->QF = 1;
 193         res = ~(((int32_t)a >> 31) ^ SIGNBIT);
 194     }
 195     return res;
 196 }
 197
 198 uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
 199 {
 200     uint32_t res;
 201     if (val >= 0x40000000) {
 202         res = ~SIGNBIT;
 203         env->QF = 1;
 204     } else if (val <= (int32_t)0xc0000000) {
 205         res = SIGNBIT;
 206         env->QF = 1;
 207     } else {
 208         res = val << 1;
 209     }
 210     return res;
 211 }
 212
 213 uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 214 {
 215     uint32_t res = a + b;
 216     if (res < a) {
 217         env->QF = 1;
 218         res = ~0;
 219     }
 220     return res;
 221 }
 222
 223 uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
 224 {
 225     uint32_t res = a - b;
 226     if (res > a) {
 227         env->QF = 1;
 228         res = 0;
 229     }
 230     return res;
 231 }
 232
 233 /* Signed saturation.  */
 234 static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
 235 {
 236     int32_t top;
 237     uint32_t mask;
 238
 239     top = val >> shift;
 240     mask = (1u << shift) - 1;
 241     if (top > 0) {
 242         env->QF = 1;
 243         return mask;
 244     } else if (top < -1) {
 245         env->QF = 1;
 246         return ~mask;
 247     }
 248     return val;
 249 }
 250
 251 /* Unsigned saturation.  */
 252 static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
 253 {
 254     uint32_t max;
 255
 256     max = (1u << shift) - 1;
 257     if (val < 0) {
 258         env->QF = 1;
 259         return 0;
 260     } else if (val > max) {
 261         env->QF = 1;
 262         return max;
 263     }
 264     return val;
 265 }
 266
 267 /* Signed saturate.  */
 268 uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
 269 {
 270     return do_ssat(env, x, shift);
 271 }
 272
 273 /* Dual halfword signed saturate.  */
 274 uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 275 {
 276     uint32_t res;
 277
 278     res = (uint16_t)do_ssat(env, (int16_t)x, shift);
 279     res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
 280     return res;
 281 }
 282
 283 /* Unsigned saturate.  */
 284 uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
 285 {
 286     return do_usat(env, x, shift);
 287 }
 288
 289 /* Dual halfword unsigned saturate.  */
 290 uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
 291 {
 292     uint32_t res;
 293
 294     res = (uint16_t)do_usat(env, (int16_t)x, shift);
 295     res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
 296     return res;
 297 }
 298
 299 void HELPER(setend)(CPUARMState *env)
 300 {
 301     env->uncached_cpsr ^= CPSR_E;
 302 }
 303
 304 /* Function checks whether WFx (WFI/WFE) instructions are set up to be trapped.
 305  * The function returns the target EL (1-3) if the instruction is to be trapped;
 306  * otherwise it returns 0 indicating it is not trapped.
 307  */
 308 static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
 309 {
 310     int cur_el = arm_current_el(env);
 311     uint64_t mask;
 312
 313     /* If we are currently in EL0 then we need to check if SCTLR is set up for
 314      * WFx instructions being trapped to EL1. These trap bits don't exist in v7.
 315      */
 316     if (cur_el < 1 && arm_feature(env, ARM_FEATURE_V8)) {
 317         int target_el;
 318
 319         mask = is_wfe ? SCTLR_nTWE : SCTLR_nTWI;
 320         if (arm_is_secure_below_el3(env) && !arm_el_is_aa64(env, 3)) {
 321             /* Secure EL0 and Secure PL1 is at EL3 */
 322             target_el = 3;
 323         } else {
 324             target_el = 1;
 325         }
 326
 327         if (!(env->cp15.sctlr_el[target_el] & mask)) {
 328             return target_el;
 329         }
 330     }
 331
 332     /* We are not trapping to EL1; trap to EL2 if HCR_EL2 requires it
 333      * No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
 334      * bits will be zero indicating no trap.
 335      */
 336     if (cur_el < 2 && !arm_is_secure(env)) {
 337         mask = (is_wfe) ? HCR_TWE : HCR_TWI;
 338         if (env->cp15.hcr_el2 & mask) {
 339             return 2;
 340         }
 341     }
 342
 343     /* We are not trapping to EL1 or EL2; trap to EL3 if SCR_EL3 requires it */
 344     if (cur_el < 3) {
 345         mask = (is_wfe) ? SCR_TWE : SCR_TWI;
 346         if (env->cp15.scr_el3 & mask) {
 347             return 3;
 348         }
 349     }
 350
 351     return 0;
 352 }
 353
 354 void HELPER(wfi)(CPUARMState *env)
 355 {
 356     CPUState *cs = CPU(arm_env_get_cpu(env));
 357     int target_el = check_wfx_trap(env, false);
 358
 359     if (cpu_has_work(cs)) {
 360         /* Don't bother to go into our "low power state" if
 361          * we would just wake up immediately.
 362          */
 363         return;
 364     }
 365
 366     if (target_el) {
 367         env->pc -= 4;
 368         raise_exception(env, EXCP_UDEF, syn_wfx(1, 0xe, 0), target_el);
 369     }
 370
 371     cs->exception_index = EXCP_HLT;
 372     cs->halted = 1;
 373     cpu_loop_exit(cs);
 374 }
 375
 376 void HELPER(wfe)(CPUARMState *env)
 377 {
 378     /* This is a hint instruction that is semantically different
 379      * from YIELD even though we currently implement it identically.
 380      * Don't actually halt the CPU, just yield back to top
 381      * level loop. This is not going into a "low power state"
 382      * (ie halting until some event occurs), so we never take
 383      * a configurable trap to a different exception level.
 384      */
 385     HELPER(yield)(env);
 386 }
 387
 388 void HELPER(yield)(CPUARMState *env)
 389 {
 390     ARMCPU *cpu = arm_env_get_cpu(env);
 391     CPUState *cs = CPU(cpu);
 392
 393     /* This is a non-trappable hint instruction that generally indicates
 394      * that the guest is currently busy-looping. Yield control back to the
 395      * top level loop so that a more deserving VCPU has a chance to run.
 396      */
 397     cs->exception_index = EXCP_YIELD;
 398     cpu_loop_exit(cs);
 399 }
 400
 401 /* Raise an internal-to-QEMU exception. This is limited to only
 402  * those EXCP values which are special cases for QEMU to interrupt
 403  * execution and not to be used for exceptions which are passed to
 404  * the guest (those must all have syndrome information and thus should
 405  * use exception_with_syndrome).
 406  */
 407 void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
 408 {
 409     CPUState *cs = CPU(arm_env_get_cpu(env));
 410
 411     assert(excp_is_internal(excp));
 412     cs->exception_index = excp;
 413     cpu_loop_exit(cs);
 414 }
 415
 416 /* Raise an exception with the specified syndrome register value */
 417 void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
 418                                      uint32_t syndrome, uint32_t target_el)
 419 {
 420     raise_exception(env, excp, syndrome, target_el);
 421 }
 422
 423 uint32_t HELPER(cpsr_read)(CPUARMState *env)
 424 {
 425     return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED);
 426 }
 427
 428 void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
 429 {
 430     cpsr_write(env, val, mask, CPSRWriteByInstr);
 431 }
 432
 433 /* Write the CPSR for a 32-bit exception return */
 434 void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val)
 435 {
 436     cpsr_write(env, val, CPSR_ERET_MASK, CPSRWriteExceptionReturn);
 437 }
 438
 439 /* Access to user mode registers from privileged modes.  */
 440 uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
 441 {
 442     uint32_t val;
 443
 444     if (regno == 13) {
 445         val = env->banked_r13[BANK_USRSYS];
 446     } else if (regno == 14) {
 447         val = env->banked_r14[BANK_USRSYS];
 448     } else if (regno >= 8
 449                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 450         val = env->usr_regs[regno - 8];
 451     } else {
 452         val = env->regs[regno];
 453     }
 454     return val;
 455 }
 456
 457 void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
 458 {
 459     if (regno == 13) {
 460         env->banked_r13[BANK_USRSYS] = val;
 461     } else if (regno == 14) {
 462         env->banked_r14[BANK_USRSYS] = val;
 463     } else if (regno >= 8
 464                && (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
 465         env->usr_regs[regno - 8] = val;
 466     } else {
 467         env->regs[regno] = val;
 468     }
 469 }
 470
 471 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
 472 {
 473     if ((env->uncached_cpsr & CPSR_M) == mode) {
 474         env->regs[13] = val;
 475     } else {
 476         env->banked_r13[bank_number(mode)] = val;
 477     }
 478 }
 479
 480 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
 481 {
 482     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SYS) {
 483         /* SRS instruction is UNPREDICTABLE from System mode; we UNDEF.
 484          * Other UNPREDICTABLE and UNDEF cases were caught at translate time.
 485          */
 486         raise_exception(env, EXCP_UDEF, syn_uncategorized(),
 487                         exception_target_el(env));
 488     }
 489
 490     if ((env->uncached_cpsr & CPSR_M) == mode) {
 491         return env->regs[13];
 492     } else {
 493         return env->banked_r13[bank_number(mode)];
 494     }
 495 }
 496
 497 void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome,
 498                                  uint32_t isread)
 499 {
 500     const ARMCPRegInfo *ri = rip;
 501     int target_el;
 502
 503     if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14
 504         && extract32(env->cp15.c15_cpar, ri->cp, 1) == 0) {
 505         raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
 506     }
 507
 508     if (!ri->accessfn) {
 509         return;
 510     }
 511
 512     switch (ri->accessfn(env, ri, isread)) {
 513     case CP_ACCESS_OK:
 514         return;
 515     case CP_ACCESS_TRAP:
 516         target_el = exception_target_el(env);
 517         break;
 518     case CP_ACCESS_TRAP_EL2:
 519         /* Requesting a trap to EL2 when we're in EL3 or S-EL0/1 is
 520          * a bug in the access function.
 521          */
 522         assert(!arm_is_secure(env) && arm_current_el(env) != 3);
 523         target_el = 2;
 524         break;
 525     case CP_ACCESS_TRAP_EL3:
 526         target_el = 3;
 527         break;
 528     case CP_ACCESS_TRAP_UNCATEGORIZED:
 529         target_el = exception_target_el(env);
 530         syndrome = syn_uncategorized();
 531         break;
 532     case CP_ACCESS_TRAP_UNCATEGORIZED_EL2:
 533         target_el = 2;
 534         syndrome = syn_uncategorized();
 535         break;
 536     case CP_ACCESS_TRAP_UNCATEGORIZED_EL3:
 537         target_el = 3;
 538         syndrome = syn_uncategorized();
 539         break;
 540     case CP_ACCESS_TRAP_FP_EL2:
 541         target_el = 2;
 542         /* Since we are an implementation that takes exceptions on a trapped
 543          * conditional insn only if the insn has passed its condition code
 544          * check, we take the IMPDEF choice to always report CV=1 COND=0xe
 545          * (which is also the required value for AArch64 traps).
 546          */
 547         syndrome = syn_fp_access_trap(1, 0xe, false);
 548         break;
 549     case CP_ACCESS_TRAP_FP_EL3:
 550         target_el = 3;
 551         syndrome = syn_fp_access_trap(1, 0xe, false);
 552         break;
 553     default:
 554         g_assert_not_reached();
 555     }
 556
 557     raise_exception(env, EXCP_UDEF, syndrome, target_el);
 558 }
 559
 560 void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
 561 {
 562     const ARMCPRegInfo *ri = rip;
 563
 564     ri->writefn(env, ri, value);
 565 }
 566
 567 uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
 568 {
 569     const ARMCPRegInfo *ri = rip;
 570
 571     return ri->readfn(env, ri);
 572 }
 573
 574 void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
 575 {
 576     const ARMCPRegInfo *ri = rip;
 577
 578     ri->writefn(env, ri, value);
 579 }
 580
 581 uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
 582 {
 583     const ARMCPRegInfo *ri = rip;
 584
 585     return ri->readfn(env, ri);
 586 }
 587
 588 void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
 589 {
 590     /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
 591      * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
 592      * to catch that case at translate time.
 593      */
 594     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
 595         uint32_t syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3),
 596                                                 extract32(op, 3, 3), 4,
 597                                                 imm, 0x1f, 0);
 598         raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
 599     }
 600
 601     switch (op) {
 602     case 0x05: /* SPSel */
 603         update_spsel(env, imm);
 604         break;
 605     case 0x1e: /* DAIFSet */
 606         env->daif |= (imm << 6) & PSTATE_DAIF;
 607         break;
 608     case 0x1f: /* DAIFClear */
 609         env->daif &= ~((imm << 6) & PSTATE_DAIF);
 610         break;
 611     default:
 612         g_assert_not_reached();
 613     }
 614 }
 615
 616 void HELPER(clear_pstate_ss)(CPUARMState *env)
 617 {
 618     env->pstate &= ~PSTATE_SS;
 619 }
 620
 621 void HELPER(pre_hvc)(CPUARMState *env)
 622 {
 623     ARMCPU *cpu = arm_env_get_cpu(env);
 624     int cur_el = arm_current_el(env);
 625     /* FIXME: Use actual secure state.  */
 626     bool secure = false;
 627     bool undef;
 628
 629     if (arm_is_psci_call(cpu, EXCP_HVC)) {
 630         /* If PSCI is enabled and this looks like a valid PSCI call then
 631          * that overrides the architecturally mandated HVC behaviour.
 632          */
 633         return;
 634     }
 635
 636     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 637         /* If EL2 doesn't exist, HVC always UNDEFs */
 638         undef = true;
 639     } else if (arm_feature(env, ARM_FEATURE_EL3)) {
 640         /* EL3.HCE has priority over EL2.HCD. */
 641         undef = !(env->cp15.scr_el3 & SCR_HCE);
 642     } else {
 643         undef = env->cp15.hcr_el2 & HCR_HCD;
 644     }
 645
 646     /* In ARMv7 and ARMv8/AArch32, HVC is undef in secure state.
 647      * For ARMv8/AArch64, HVC is allowed in EL3.
 648      * Note that we've already trapped HVC from EL0 at translation
 649      * time.
 650      */
 651     if (secure && (!is_a64(env) || cur_el == 1)) {
 652         undef = true;
 653     }
 654
 655     if (undef) {
 656         raise_exception(env, EXCP_UDEF, syn_uncategorized(),
 657                         exception_target_el(env));
 658     }
 659 }
 660
 661 void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
 662 {
 663     ARMCPU *cpu = arm_env_get_cpu(env);
 664     int cur_el = arm_current_el(env);
 665     bool secure = arm_is_secure(env);
 666     bool smd = env->cp15.scr_el3 & SCR_SMD;
 667     /* On ARMv8 with EL3 AArch64, SMD applies to both S and NS state.
 668      * On ARMv8 with EL3 AArch32, or ARMv7 with the Virtualization
 669      *  extensions, SMD only applies to NS state.
 670      * On ARMv7 without the Virtualization extensions, the SMD bit
 671      * doesn't exist, but we forbid the guest to set it to 1 in scr_write(),
 672      * so we need not special case this here.
 673      */
 674     bool undef = arm_feature(env, ARM_FEATURE_AARCH64) ? smd : smd && !secure;
 675
 676     if (arm_is_psci_call(cpu, EXCP_SMC)) {
 677         /* If PSCI is enabled and this looks like a valid PSCI call then
 678          * that overrides the architecturally mandated SMC behaviour.
 679          */
 680         return;
 681     }
 682
 683     if (!arm_feature(env, ARM_FEATURE_EL3)) {
 684         /* If we have no EL3 then SMC always UNDEFs */
 685         undef = true;
 686     } else if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
 687         /* In NS EL1, HCR controlled routing to EL2 has priority over SMD. */
 688         raise_exception(env, EXCP_HYP_TRAP, syndrome, 2);
 689     }
 690
 691     if (undef) {
 692         raise_exception(env, EXCP_UDEF, syn_uncategorized(),
 693                         exception_target_el(env));
 694     }
 695 }
 696
 697 static int el_from_spsr(uint32_t spsr)
 698 {
 699     /* Return the exception level that this SPSR is requesting a return to,
 700      * or -1 if it is invalid (an illegal return)
 701      */
 702     if (spsr & PSTATE_nRW) {
 703         switch (spsr & CPSR_M) {
 704         case ARM_CPU_MODE_USR:
 705             return 0;
 706         case ARM_CPU_MODE_HYP:
 707             return 2;
 708         case ARM_CPU_MODE_FIQ:
 709         case ARM_CPU_MODE_IRQ:
 710         case ARM_CPU_MODE_SVC:
 711         case ARM_CPU_MODE_ABT:
 712         case ARM_CPU_MODE_UND:
 713         case ARM_CPU_MODE_SYS:
 714             return 1;
 715         case ARM_CPU_MODE_MON:
 716             /* Returning to Mon from AArch64 is never possible,
 717              * so this is an illegal return.
 718              */
 719         default:
 720             return -1;
 721         }
 722     } else {
 723         if (extract32(spsr, 1, 1)) {
 724             /* Return with reserved M[1] bit set */
 725             return -1;
 726         }
 727         if (extract32(spsr, 0, 4) == 1) {
 728             /* return to EL0 with M[0] bit set */
 729             return -1;
 730         }
 731         return extract32(spsr, 2, 2);
 732     }
 733 }
 734
 735 void HELPER(exception_return)(CPUARMState *env)
 736 {
 737     int cur_el = arm_current_el(env);
 738     unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
 739     uint32_t spsr = env->banked_spsr[spsr_idx];
 740     int new_el;
 741     bool return_to_aa64 = (spsr & PSTATE_nRW) == 0;
 742
 743     aarch64_save_sp(env, cur_el);
 744
 745     env->exclusive_addr = -1;
 746
 747     /* We must squash the PSTATE.SS bit to zero unless both of the
 748      * following hold:
 749      *  1. debug exceptions are currently disabled
 750      *  2. singlestep will be active in the EL we return to
 751      * We check 1 here and 2 after we've done the pstate/cpsr write() to
 752      * transition to the EL we're going to.
 753      */
 754     if (arm_generate_debug_exceptions(env)) {
 755         spsr &= ~PSTATE_SS;
 756     }
 757
 758     new_el = el_from_spsr(spsr);
 759     if (new_el == -1) {
 760         goto illegal_return;
 761     }
 762     if (new_el > cur_el
 763         || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) {
 764         /* Disallow return to an EL which is unimplemented or higher
 765          * than the current one.
 766          */
 767         goto illegal_return;
 768     }
 769
 770     if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) {
 771         /* Return to an EL which is configured for a different register width */
 772         goto illegal_return;
 773     }
 774
 775     if (new_el == 2 && arm_is_secure_below_el3(env)) {
 776         /* Return to the non-existent secure-EL2 */
 777         goto illegal_return;
 778     }
 779
 780     if (new_el == 1 && (env->cp15.hcr_el2 & HCR_TGE)
 781         && !arm_is_secure_below_el3(env)) {
 782         goto illegal_return;
 783     }
 784
 785     if (!return_to_aa64) {
 786         env->aarch64 = 0;
 787         /* We do a raw CPSR write because aarch64_sync_64_to_32()
 788          * will sort the register banks out for us, and we've already
 789          * caught all the bad-mode cases in el_from_spsr().
 790          */
 791         cpsr_write(env, spsr, ~0, CPSRWriteRaw);
 792         if (!arm_singlestep_active(env)) {
 793             env->uncached_cpsr &= ~PSTATE_SS;
 794         }
 795         aarch64_sync_64_to_32(env);
 796
 797         if (spsr & CPSR_T) {
 798             env->regs[15] = env->elr_el[cur_el] & ~0x1;
 799         } else {
 800             env->regs[15] = env->elr_el[cur_el] & ~0x3;
 801         }
 802     } else {
 803         env->aarch64 = 1;
 804         pstate_write(env, spsr);
 805         if (!arm_singlestep_active(env)) {
 806             env->pstate &= ~PSTATE_SS;
 807         }
 808         aarch64_restore_sp(env, new_el);
 809         env->pc = env->elr_el[cur_el];
 810     }
 811
 812     return;
 813
 814 illegal_return:
 815     /* Illegal return events of various kinds have architecturally
 816      * mandated behaviour:
 817      * restore NZCV and DAIF from SPSR_ELx
 818      * set PSTATE.IL
 819      * restore PC from ELR_ELx
 820      * no change to exception level, execution state or stack pointer
 821      */
 822     env->pstate |= PSTATE_IL;
 823     env->pc = env->elr_el[cur_el];
 824     spsr &= PSTATE_NZCV | PSTATE_DAIF;
 825     spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
 826     pstate_write(env, spsr);
 827     if (!arm_singlestep_active(env)) {
 828         env->pstate &= ~PSTATE_SS;
 829     }
 830 }
 831
 832 /* Return true if the linked breakpoint entry lbn passes its checks */
 833 static bool linked_bp_matches(ARMCPU *cpu, int lbn)
 834 {
 835     CPUARMState *env = &cpu->env;
 836     uint64_t bcr = env->cp15.dbgbcr[lbn];
 837     int brps = extract32(cpu->dbgdidr, 24, 4);
 838     int ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
 839     int bt;
 840     uint32_t contextidr;
 841
 842     /* Links to unimplemented or non-context aware breakpoints are
 843      * CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
 844      * as if linked to an UNKNOWN context-aware breakpoint (in which
 845      * case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
 846      * We choose the former.
 847      */
 848     if (lbn > brps || lbn < (brps - ctx_cmps)) {
 849         return false;
 850     }
 851
 852     bcr = env->cp15.dbgbcr[lbn];
 853
 854     if (extract64(bcr, 0, 1) == 0) {
 855         /* Linked breakpoint disabled : generate no events */
 856         return false;
 857     }
 858
 859     bt = extract64(bcr, 20, 4);
 860
 861     /* We match the whole register even if this is AArch32 using the
 862      * short descriptor format (in which case it holds both PROCID and ASID),
 863      * since we don't implement the optional v7 context ID masking.
 864      */
 865     contextidr = extract64(env->cp15.contextidr_el[1], 0, 32);
 866
 867     switch (bt) {
 868     case 3: /* linked context ID match */
 869         if (arm_current_el(env) > 1) {
 870             /* Context matches never fire in EL2 or (AArch64) EL3 */
 871             return false;
 872         }
 873         return (contextidr == extract64(env->cp15.dbgbvr[lbn], 0, 32));
 874     case 5: /* linked address mismatch (reserved in AArch64) */
 875     case 9: /* linked VMID match (reserved if no EL2) */
 876     case 11: /* linked context ID and VMID match (reserved if no EL2) */
 877     default:
 878         /* Links to Unlinked context breakpoints must generate no
 879          * events; we choose to do the same for reserved values too.
 880          */
 881         return false;
 882     }
 883
 884     return false;
 885 }
 886
 887 static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_wp)
 888 {
 889     CPUARMState *env = &cpu->env;
 890     uint64_t cr;
 891     int pac, hmc, ssc, wt, lbn;
 892     /* Note that for watchpoints the check is against the CPU security
 893      * state, not the S/NS attribute on the offending data access.
 894      */
 895     bool is_secure = arm_is_secure(env);
 896     int access_el = arm_current_el(env);
 897
 898     if (is_wp) {
 899         CPUWatchpoint *wp = env->cpu_watchpoint[n];
 900
 901         if (!wp || !(wp->flags & BP_WATCHPOINT_HIT)) {
 902             return false;
 903         }
 904         cr = env->cp15.dbgwcr[n];
 905         if (wp->hitattrs.user) {
 906             /* The LDRT/STRT/LDT/STT "unprivileged access" instructions should
 907              * match watchpoints as if they were accesses done at EL0, even if
 908              * the CPU is at EL1 or higher.
 909              */
 910             access_el = 0;
 911         }
 912     } else {
 913         uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
 914
 915         if (!env->cpu_breakpoint[n] || env->cpu_breakpoint[n]->pc != pc) {
 916             return false;
 917         }
 918         cr = env->cp15.dbgbcr[n];
 919     }
 920     /* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
 921      * enabled and that the address and access type match; for breakpoints
 922      * we know the address matched; check the remaining fields, including
 923      * linked breakpoints. We rely on WCR and BCR having the same layout
 924      * for the LBN, SSC, HMC, PAC/PMC and is-linked fields.
 925      * Note that some combinations of {PAC, HMC, SSC} are reserved and
 926      * must act either like some valid combination or as if the watchpoint
 927      * were disabled. We choose the former, and use this together with
 928      * the fact that EL3 must always be Secure and EL2 must always be
 929      * Non-Secure to simplify the code slightly compared to the full
 930      * table in the ARM ARM.
 931      */
 932     pac = extract64(cr, 1, 2);
 933     hmc = extract64(cr, 13, 1);
 934     ssc = extract64(cr, 14, 2);
 935
 936     switch (ssc) {
 937     case 0:
 938         break;
 939     case 1:
 940     case 3:
 941         if (is_secure) {
 942             return false;
 943         }
 944         break;
 945     case 2:
 946         if (!is_secure) {
 947             return false;
 948         }
 949         break;
 950     }
 951
 952     switch (access_el) {
 953     case 3:
 954     case 2:
 955         if (!hmc) {
 956             return false;
 957         }
 958         break;
 959     case 1:
 960         if (extract32(pac, 0, 1) == 0) {
 961             return false;
 962         }
 963         break;
 964     case 0:
 965         if (extract32(pac, 1, 1) == 0) {
 966             return false;
 967         }
 968         break;
 969     default:
 970         g_assert_not_reached();
 971     }
 972
 973     wt = extract64(cr, 20, 1);
 974     lbn = extract64(cr, 16, 4);
 975
 976     if (wt && !linked_bp_matches(cpu, lbn)) {
 977         return false;
 978     }
 979
 980     return true;
 981 }
 982
 983 static bool check_watchpoints(ARMCPU *cpu)
 984 {
 985     CPUARMState *env = &cpu->env;
 986     int n;
 987
 988     /* If watchpoints are disabled globally or we can't take debug
 989      * exceptions here then watchpoint firings are ignored.
 990      */
 991     if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
 992         || !arm_generate_debug_exceptions(env)) {
 993         return false;
 994     }
 995
 996     for (n = 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) {
 997         if (bp_wp_matches(cpu, n, true)) {
 998             return true;
 999         }
1000     }
1001     return false;
1002 }
1003
1004 static bool check_breakpoints(ARMCPU *cpu)
1005 {
1006     CPUARMState *env = &cpu->env;
1007     int n;
1008
1009     /* If breakpoints are disabled globally or we can't take debug
1010      * exceptions here then breakpoint firings are ignored.
1011      */
1012     if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
1013         || !arm_generate_debug_exceptions(env)) {
1014         return false;
1015     }
1016
1017     for (n = 0; n < ARRAY_SIZE(env->cpu_breakpoint); n++) {
1018         if (bp_wp_matches(cpu, n, false)) {
1019             return true;
1020         }
1021     }
1022     return false;
1023 }
1024
1025 void HELPER(check_breakpoints)(CPUARMState *env)
1026 {
1027     ARMCPU *cpu = arm_env_get_cpu(env);
1028
1029     if (check_breakpoints(cpu)) {
1030         HELPER(exception_internal(env, EXCP_DEBUG));
1031     }
1032 }
1033
1034 bool arm_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
1035 {
1036     /* Called by core code when a CPU watchpoint fires; need to check if this
1037      * is also an architectural watchpoint match.
1038      */
1039     ARMCPU *cpu = ARM_CPU(cs);
1040
1041     return check_watchpoints(cpu);
1042 }
1043
1044 void arm_debug_excp_handler(CPUState *cs)
1045 {
1046     /* Called by core code when a watchpoint or breakpoint fires;
1047      * need to check which one and raise the appropriate exception.
1048      */
1049     ARMCPU *cpu = ARM_CPU(cs);
1050     CPUARMState *env = &cpu->env;
1051     CPUWatchpoint *wp_hit = cs->watchpoint_hit;
1052
1053     if (wp_hit) {
1054         if (wp_hit->flags & BP_CPU) {
1055             bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
1056             bool same_el = arm_debug_target_el(env) == arm_current_el(env);
1057
1058             cs->watchpoint_hit = NULL;
1059
1060             if (extended_addresses_enabled(env)) {
1061                 env->exception.fsr = (1 << 9) | 0x22;
1062             } else {
1063                 env->exception.fsr = 0x2;
1064             }
1065             env->exception.vaddress = wp_hit->hitaddr;
1066             raise_exception(env, EXCP_DATA_ABORT,
1067                     syn_watchpoint(same_el, 0, wnr),
1068                     arm_debug_target_el(env));
1069         }
1070     } else {
1071         uint64_t pc = is_a64(env) ? env->pc : env->regs[15];
1072         bool same_el = (arm_debug_target_el(env) == arm_current_el(env));
1073
1074         /* (1) GDB breakpoints should be handled first.
1075          * (2) Do not raise a CPU exception if no CPU breakpoint has fired,
1076          * since singlestep is also done by generating a debug internal
1077          * exception.
1078          */
1079         if (cpu_breakpoint_test(cs, pc, BP_GDB)
1080             || !cpu_breakpoint_test(cs, pc, BP_CPU)) {
1081             return;
1082         }
1083
1084         if (extended_addresses_enabled(env)) {
1085             env->exception.fsr = (1 << 9) | 0x22;
1086         } else {
1087             env->exception.fsr = 0x2;
1088         }
1089         /* FAR is UNKNOWN, so doesn't need setting */
1090         raise_exception(env, EXCP_PREFETCH_ABORT,
1091                         syn_breakpoint(same_el),
1092                         arm_debug_target_el(env));
1093     }
1094 }
1095
1096 /* ??? Flag setting arithmetic is awkward because we need to do comparisons.
1097    The only way to do that in TCG is a conditional branch, which clobbers
1098    all our temporaries.  For now implement these as helper functions.  */
1099
1100 /* Similarly for variable shift instructions.  */
1101
1102 uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
1103 {
1104     int shift = i & 0xff;
1105     if (shift >= 32) {
1106         if (shift == 32)
1107             env->CF = x & 1;
1108         else
1109             env->CF = 0;
1110         return 0;
1111     } else if (shift != 0) {
1112         env->CF = (x >> (32 - shift)) & 1;
1113         return x << shift;
1114     }
1115     return x;
1116 }
1117
1118 uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
1119 {
1120     int shift = i & 0xff;
1121     if (shift >= 32) {
1122         if (shift == 32)
1123             env->CF = (x >> 31) & 1;
1124         else
1125             env->CF = 0;
1126         return 0;
1127     } else if (shift != 0) {
1128         env->CF = (x >> (shift - 1)) & 1;
1129         return x >> shift;
1130     }
1131     return x;
1132 }
1133
1134 uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
1135 {
1136     int shift = i & 0xff;
1137     if (shift >= 32) {
1138         env->CF = (x >> 31) & 1;
1139         return (int32_t)x >> 31;
1140     } else if (shift != 0) {
1141         env->CF = (x >> (shift - 1)) & 1;
1142         return (int32_t)x >> shift;
1143     }
1144     return x;
1145 }
1146
1147 uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
1148 {
1149     int shift1, shift;
1150     shift1 = i & 0xff;
1151     shift = shift1 & 0x1f;
1152     if (shift == 0) {
1153         if (shift1 != 0)
1154             env->CF = (x >> 31) & 1;
1155         return x;
1156     } else {
1157         env->CF = (x >> (shift - 1)) & 1;
1158         return ((uint32_t)x >> shift) | (x << (32 - shift));
1159     }
1160 }