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linux-user: don't zero a buffer twice
[qemu.git] / hw / fdc.c
bloba21e05f0eb96bbfa08a07e7ce34564cad8f6482c
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "block.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37
38 /********************************************************/
39 /* debug Floppy devices */
40 //#define DEBUG_FLOPPY
41
42 #ifdef DEBUG_FLOPPY
43 #define FLOPPY_DPRINTF(fmt, ...) \
44 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
45 #else
46 #define FLOPPY_DPRINTF(fmt, ...)
47 #endif
48
49 #define FLOPPY_ERROR(fmt, ...) \
50 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
51
52 /********************************************************/
53 /* Floppy drive emulation */
54
55 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
56 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
57
58 /* Will always be a fixed parameter for us */
59 #define FD_SECTOR_LEN 512
60 #define FD_SECTOR_SC 2 /* Sector size code */
61 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
62
63 /* Floppy disk drive emulation */
64 typedef enum fdisk_type_t {
65 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
66 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
67 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
68 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
69 FDRIVE_DISK_NONE = 0x05, /* No disk */
70 } fdisk_type_t;
71
72 typedef enum fdrive_type_t {
73 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
74 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
75 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
76 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
77 } fdrive_type_t;
78
79 typedef enum fdisk_flags_t {
80 FDISK_DBL_SIDES = 0x01,
81 } fdisk_flags_t;
82
83 typedef struct fdrive_t {
84 DriveInfo *dinfo;
85 BlockDriverState *bs;
86 /* Drive status */
87 fdrive_type_t drive;
88 uint8_t perpendicular; /* 2.88 MB access mode */
89 /* Position */
90 uint8_t head;
91 uint8_t track;
92 uint8_t sect;
93 /* Media */
94 fdisk_flags_t flags;
95 uint8_t last_sect; /* Nb sector per track */
96 uint8_t max_track; /* Nb of tracks */
97 uint16_t bps; /* Bytes per sector */
98 uint8_t ro; /* Is read-only */
99 } fdrive_t;
100
101 static void fd_init (fdrive_t *drv)
102 {
103 /* Drive */
104 drv->bs = drv->dinfo ? drv->dinfo->bdrv : NULL;
105 drv->drive = FDRIVE_DRV_NONE;
106 drv->perpendicular = 0;
107 /* Disk */
108 drv->last_sect = 0;
109 drv->max_track = 0;
110 }
111
112 static int _fd_sector (uint8_t head, uint8_t track,
113 uint8_t sect, uint8_t last_sect)
114 {
115 return (((track * 2) + head) * last_sect) + sect - 1;
116 }
117
118 /* Returns current position, in sectors, for given drive */
119 static int fd_sector (fdrive_t *drv)
120 {
121 return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
122 }
123
124 /* Seek to a new position:
125 * returns 0 if already on right track
126 * returns 1 if track changed
127 * returns 2 if track is invalid
128 * returns 3 if sector is invalid
129 * returns 4 if seek is disabled
130 */
131 static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
132 int enable_seek)
133 {
134 uint32_t sector;
135 int ret;
136
137 if (track > drv->max_track ||
138 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
139 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
140 head, track, sect, 1,
141 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
142 drv->max_track, drv->last_sect);
143 return 2;
144 }
145 if (sect > drv->last_sect) {
146 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
147 head, track, sect, 1,
148 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
149 drv->max_track, drv->last_sect);
150 return 3;
151 }
152 sector = _fd_sector(head, track, sect, drv->last_sect);
153 ret = 0;
154 if (sector != fd_sector(drv)) {
155 #if 0
156 if (!enable_seek) {
157 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
158 head, track, sect, 1, drv->max_track, drv->last_sect);
159 return 4;
160 }
161 #endif
162 drv->head = head;
163 if (drv->track != track)
164 ret = 1;
165 drv->track = track;
166 drv->sect = sect;
167 }
168
169 return ret;
170 }
171
172 /* Set drive back to track 0 */
173 static void fd_recalibrate (fdrive_t *drv)
174 {
175 FLOPPY_DPRINTF("recalibrate\n");
176 drv->head = 0;
177 drv->track = 0;
178 drv->sect = 1;
179 }
180
181 /* Recognize floppy formats */
182 typedef struct fd_format_t {
183 fdrive_type_t drive;
184 fdisk_type_t disk;
185 uint8_t last_sect;
186 uint8_t max_track;
187 uint8_t max_head;
188 const char *str;
189 } fd_format_t;
190
191 static const fd_format_t fd_formats[] = {
192 /* First entry is default format */
193 /* 1.44 MB 3"1/2 floppy disks */
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
197 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
198 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
199 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
200 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
201 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
202 /* 2.88 MB 3"1/2 floppy disks */
203 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
204 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
205 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
206 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
207 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
208 /* 720 kB 3"1/2 floppy disks */
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
210 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
211 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
212 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
213 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
214 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
215 /* 1.2 MB 5"1/4 floppy disks */
216 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
219 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
220 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
221 /* 720 kB 5"1/4 floppy disks */
222 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
224 /* 360 kB 5"1/4 floppy disks */
225 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
226 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
227 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
228 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
229 /* 320 kB 5"1/4 floppy disks */
230 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
231 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
232 /* 360 kB must match 5"1/4 better than 3"1/2... */
233 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
234 /* end */
235 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
236 };
237
238 /* Revalidate a disk drive after a disk change */
239 static void fd_revalidate (fdrive_t *drv)
240 {
241 const fd_format_t *parse;
242 uint64_t nb_sectors, size;
243 int i, first_match, match;
244 int nb_heads, max_track, last_sect, ro;
245
246 FLOPPY_DPRINTF("revalidate\n");
247 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
248 ro = bdrv_is_read_only(drv->bs);
249 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
250 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
251 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
252 nb_heads - 1, max_track, last_sect);
253 } else {
254 bdrv_get_geometry(drv->bs, &nb_sectors);
255 match = -1;
256 first_match = -1;
257 for (i = 0;; i++) {
258 parse = &fd_formats[i];
259 if (parse->drive == FDRIVE_DRV_NONE)
260 break;
261 if (drv->drive == parse->drive ||
262 drv->drive == FDRIVE_DRV_NONE) {
263 size = (parse->max_head + 1) * parse->max_track *
264 parse->last_sect;
265 if (nb_sectors == size) {
266 match = i;
267 break;
268 }
269 if (first_match == -1)
270 first_match = i;
271 }
272 }
273 if (match == -1) {
274 if (first_match == -1)
275 match = 1;
276 else
277 match = first_match;
278 parse = &fd_formats[match];
279 }
280 nb_heads = parse->max_head + 1;
281 max_track = parse->max_track;
282 last_sect = parse->last_sect;
283 drv->drive = parse->drive;
284 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
285 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
286 }
287 if (nb_heads == 1) {
288 drv->flags &= ~FDISK_DBL_SIDES;
289 } else {
290 drv->flags |= FDISK_DBL_SIDES;
291 }
292 drv->max_track = max_track;
293 drv->last_sect = last_sect;
294 drv->ro = ro;
295 } else {
296 FLOPPY_DPRINTF("No disk in drive\n");
297 drv->last_sect = 0;
298 drv->max_track = 0;
299 drv->flags &= ~FDISK_DBL_SIDES;
300 }
301 }
302
303 /********************************************************/
304 /* Intel 82078 floppy disk controller emulation */
305
306 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
307 static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
308 static int fdctrl_transfer_handler (void *opaque, int nchan,
309 int dma_pos, int dma_len);
310 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
311
312 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
313 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
314 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
315 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
316 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
317 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
318 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
319 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
320 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
321 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
322 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
323
324 enum {
325 FD_DIR_WRITE = 0,
326 FD_DIR_READ = 1,
327 FD_DIR_SCANE = 2,
328 FD_DIR_SCANL = 3,
329 FD_DIR_SCANH = 4,
330 };
331
332 enum {
333 FD_STATE_MULTI = 0x01, /* multi track flag */
334 FD_STATE_FORMAT = 0x02, /* format flag */
335 FD_STATE_SEEK = 0x04, /* seek flag */
336 };
337
338 enum {
339 FD_REG_SRA = 0x00,
340 FD_REG_SRB = 0x01,
341 FD_REG_DOR = 0x02,
342 FD_REG_TDR = 0x03,
343 FD_REG_MSR = 0x04,
344 FD_REG_DSR = 0x04,
345 FD_REG_FIFO = 0x05,
346 FD_REG_DIR = 0x07,
347 };
348
349 enum {
350 FD_CMD_READ_TRACK = 0x02,
351 FD_CMD_SPECIFY = 0x03,
352 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
353 FD_CMD_WRITE = 0x05,
354 FD_CMD_READ = 0x06,
355 FD_CMD_RECALIBRATE = 0x07,
356 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
357 FD_CMD_WRITE_DELETED = 0x09,
358 FD_CMD_READ_ID = 0x0a,
359 FD_CMD_READ_DELETED = 0x0c,
360 FD_CMD_FORMAT_TRACK = 0x0d,
361 FD_CMD_DUMPREG = 0x0e,
362 FD_CMD_SEEK = 0x0f,
363 FD_CMD_VERSION = 0x10,
364 FD_CMD_SCAN_EQUAL = 0x11,
365 FD_CMD_PERPENDICULAR_MODE = 0x12,
366 FD_CMD_CONFIGURE = 0x13,
367 FD_CMD_LOCK = 0x14,
368 FD_CMD_VERIFY = 0x16,
369 FD_CMD_POWERDOWN_MODE = 0x17,
370 FD_CMD_PART_ID = 0x18,
371 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
372 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
373 FD_CMD_SAVE = 0x2c,
374 FD_CMD_OPTION = 0x33,
375 FD_CMD_RESTORE = 0x4c,
376 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
377 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
378 FD_CMD_FORMAT_AND_WRITE = 0xcd,
379 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
380 };
381
382 enum {
383 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
384 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
385 FD_CONFIG_POLL = 0x10, /* Poll enabled */
386 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
387 FD_CONFIG_EIS = 0x40, /* No implied seeks */
388 };
389
390 enum {
391 FD_SR0_EQPMT = 0x10,
392 FD_SR0_SEEK = 0x20,
393 FD_SR0_ABNTERM = 0x40,
394 FD_SR0_INVCMD = 0x80,
395 FD_SR0_RDYCHG = 0xc0,
396 };
397
398 enum {
399 FD_SR1_EC = 0x80, /* End of cylinder */
400 };
401
402 enum {
403 FD_SR2_SNS = 0x04, /* Scan not satisfied */
404 FD_SR2_SEH = 0x08, /* Scan equal hit */
405 };
406
407 enum {
408 FD_SRA_DIR = 0x01,
409 FD_SRA_nWP = 0x02,
410 FD_SRA_nINDX = 0x04,
411 FD_SRA_HDSEL = 0x08,
412 FD_SRA_nTRK0 = 0x10,
413 FD_SRA_STEP = 0x20,
414 FD_SRA_nDRV2 = 0x40,
415 FD_SRA_INTPEND = 0x80,
416 };
417
418 enum {
419 FD_SRB_MTR0 = 0x01,
420 FD_SRB_MTR1 = 0x02,
421 FD_SRB_WGATE = 0x04,
422 FD_SRB_RDATA = 0x08,
423 FD_SRB_WDATA = 0x10,
424 FD_SRB_DR0 = 0x20,
425 };
426
427 enum {
428 #if MAX_FD == 4
429 FD_DOR_SELMASK = 0x03,
430 #else
431 FD_DOR_SELMASK = 0x01,
432 #endif
433 FD_DOR_nRESET = 0x04,
434 FD_DOR_DMAEN = 0x08,
435 FD_DOR_MOTEN0 = 0x10,
436 FD_DOR_MOTEN1 = 0x20,
437 FD_DOR_MOTEN2 = 0x40,
438 FD_DOR_MOTEN3 = 0x80,
439 };
440
441 enum {
442 #if MAX_FD == 4
443 FD_TDR_BOOTSEL = 0x0c,
444 #else
445 FD_TDR_BOOTSEL = 0x04,
446 #endif
447 };
448
449 enum {
450 FD_DSR_DRATEMASK= 0x03,
451 FD_DSR_PWRDOWN = 0x40,
452 FD_DSR_SWRESET = 0x80,
453 };
454
455 enum {
456 FD_MSR_DRV0BUSY = 0x01,
457 FD_MSR_DRV1BUSY = 0x02,
458 FD_MSR_DRV2BUSY = 0x04,
459 FD_MSR_DRV3BUSY = 0x08,
460 FD_MSR_CMDBUSY = 0x10,
461 FD_MSR_NONDMA = 0x20,
462 FD_MSR_DIO = 0x40,
463 FD_MSR_RQM = 0x80,
464 };
465
466 enum {
467 FD_DIR_DSKCHG = 0x80,
468 };
469
470 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
471 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
472 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
473
474 struct fdctrl_t {
475 /* Controller's identification */
476 uint8_t version;
477 /* HW */
478 qemu_irq irq;
479 int dma_chann;
480 /* Controller state */
481 QEMUTimer *result_timer;
482 uint8_t sra;
483 uint8_t srb;
484 uint8_t dor;
485 uint8_t dor_vmstate; /* only used as temp during vmstate */
486 uint8_t tdr;
487 uint8_t dsr;
488 uint8_t msr;
489 uint8_t cur_drv;
490 uint8_t status0;
491 uint8_t status1;
492 uint8_t status2;
493 /* Command FIFO */
494 uint8_t *fifo;
495 int32_t fifo_size;
496 uint32_t data_pos;
497 uint32_t data_len;
498 uint8_t data_state;
499 uint8_t data_dir;
500 uint8_t eot; /* last wanted sector */
501 /* States kept only to be returned back */
502 /* Timers state */
503 uint8_t timer0;
504 uint8_t timer1;
505 /* precompensation */
506 uint8_t precomp_trk;
507 uint8_t config;
508 uint8_t lock;
509 /* Power down config (also with status regB access mode */
510 uint8_t pwrd;
511 /* Sun4m quirks? */
512 int sun4m;
513 /* Floppy drives */
514 uint8_t num_floppies;
515 fdrive_t drives[MAX_FD];
516 int reset_sensei;
517 };
518
519 typedef struct fdctrl_sysbus_t {
520 SysBusDevice busdev;
521 struct fdctrl_t state;
522 } fdctrl_sysbus_t;
523
524 typedef struct fdctrl_isabus_t {
525 ISADevice busdev;
526 struct fdctrl_t state;
527 } fdctrl_isabus_t;
528
529 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
530 {
531 fdctrl_t *fdctrl = opaque;
532 uint32_t retval;
533
534 switch (reg) {
535 case FD_REG_SRA:
536 retval = fdctrl_read_statusA(fdctrl);
537 break;
538 case FD_REG_SRB:
539 retval = fdctrl_read_statusB(fdctrl);
540 break;
541 case FD_REG_DOR:
542 retval = fdctrl_read_dor(fdctrl);
543 break;
544 case FD_REG_TDR:
545 retval = fdctrl_read_tape(fdctrl);
546 break;
547 case FD_REG_MSR:
548 retval = fdctrl_read_main_status(fdctrl);
549 break;
550 case FD_REG_FIFO:
551 retval = fdctrl_read_data(fdctrl);
552 break;
553 case FD_REG_DIR:
554 retval = fdctrl_read_dir(fdctrl);
555 break;
556 default:
557 retval = (uint32_t)(-1);
558 break;
559 }
560 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
561
562 return retval;
563 }
564
565 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
566 {
567 fdctrl_t *fdctrl = opaque;
568
569 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
570
571 switch (reg) {
572 case FD_REG_DOR:
573 fdctrl_write_dor(fdctrl, value);
574 break;
575 case FD_REG_TDR:
576 fdctrl_write_tape(fdctrl, value);
577 break;
578 case FD_REG_DSR:
579 fdctrl_write_rate(fdctrl, value);
580 break;
581 case FD_REG_FIFO:
582 fdctrl_write_data(fdctrl, value);
583 break;
584 default:
585 break;
586 }
587 }
588
589 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
590 {
591 return fdctrl_read(opaque, reg & 7);
592 }
593
594 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
595 {
596 fdctrl_write(opaque, reg & 7, value);
597 }
598
599 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
600 {
601 return fdctrl_read(opaque, (uint32_t)reg);
602 }
603
604 static void fdctrl_write_mem (void *opaque,
605 target_phys_addr_t reg, uint32_t value)
606 {
607 fdctrl_write(opaque, (uint32_t)reg, value);
608 }
609
610 static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
611 fdctrl_read_mem,
612 fdctrl_read_mem,
613 fdctrl_read_mem,
614 };
615
616 static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
617 fdctrl_write_mem,
618 fdctrl_write_mem,
619 fdctrl_write_mem,
620 };
621
622 static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
623 fdctrl_read_mem,
624 NULL,
625 NULL,
626 };
627
628 static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
629 fdctrl_write_mem,
630 NULL,
631 NULL,
632 };
633
634 static const VMStateDescription vmstate_fdrive = {
635 .name = "fdrive",
636 .version_id = 1,
637 .minimum_version_id = 1,
638 .minimum_version_id_old = 1,
639 .fields = (VMStateField []) {
640 VMSTATE_UINT8(head, fdrive_t),
641 VMSTATE_UINT8(track, fdrive_t),
642 VMSTATE_UINT8(sect, fdrive_t),
643 VMSTATE_END_OF_LIST()
644 }
645 };
646
647 static void fdc_pre_save(void *opaque)
648 {
649 fdctrl_t *s = opaque;
650
651 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
652 }
653
654 static int fdc_post_load(void *opaque, int version_id)
655 {
656 fdctrl_t *s = opaque;
657
658 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
659 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
660 return 0;
661 }
662
663 static const VMStateDescription vmstate_fdc = {
664 .name = "fdc",
665 .version_id = 2,
666 .minimum_version_id = 2,
667 .minimum_version_id_old = 2,
668 .pre_save = fdc_pre_save,
669 .post_load = fdc_post_load,
670 .fields = (VMStateField []) {
671 /* Controller State */
672 VMSTATE_UINT8(sra, fdctrl_t),
673 VMSTATE_UINT8(srb, fdctrl_t),
674 VMSTATE_UINT8(dor_vmstate, fdctrl_t),
675 VMSTATE_UINT8(tdr, fdctrl_t),
676 VMSTATE_UINT8(dsr, fdctrl_t),
677 VMSTATE_UINT8(msr, fdctrl_t),
678 VMSTATE_UINT8(status0, fdctrl_t),
679 VMSTATE_UINT8(status1, fdctrl_t),
680 VMSTATE_UINT8(status2, fdctrl_t),
681 /* Command FIFO */
682 VMSTATE_VARRAY(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8),
683 VMSTATE_UINT32(data_pos, fdctrl_t),
684 VMSTATE_UINT32(data_len, fdctrl_t),
685 VMSTATE_UINT8(data_state, fdctrl_t),
686 VMSTATE_UINT8(data_dir, fdctrl_t),
687 VMSTATE_UINT8(eot, fdctrl_t),
688 /* States kept only to be returned back */
689 VMSTATE_UINT8(timer0, fdctrl_t),
690 VMSTATE_UINT8(timer1, fdctrl_t),
691 VMSTATE_UINT8(precomp_trk, fdctrl_t),
692 VMSTATE_UINT8(config, fdctrl_t),
693 VMSTATE_UINT8(lock, fdctrl_t),
694 VMSTATE_UINT8(pwrd, fdctrl_t),
695 VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t),
696 VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1,
697 vmstate_fdrive, fdrive_t),
698 VMSTATE_END_OF_LIST()
699 }
700 };
701
702 static void fdctrl_external_reset(void *opaque)
703 {
704 fdctrl_t *s = opaque;
705
706 fdctrl_reset(s, 0);
707 }
708
709 static void fdctrl_handle_tc(void *opaque, int irq, int level)
710 {
711 //fdctrl_t *s = opaque;
712
713 if (level) {
714 // XXX
715 FLOPPY_DPRINTF("TC pulsed\n");
716 }
717 }
718
719 /* XXX: may change if moved to bdrv */
720 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
721 {
722 return fdctrl->drives[drive_num].drive;
723 }
724
725 /* Change IRQ state */
726 static void fdctrl_reset_irq (fdctrl_t *fdctrl)
727 {
728 if (!(fdctrl->sra & FD_SRA_INTPEND))
729 return;
730 FLOPPY_DPRINTF("Reset interrupt\n");
731 qemu_set_irq(fdctrl->irq, 0);
732 fdctrl->sra &= ~FD_SRA_INTPEND;
733 }
734
735 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
736 {
737 /* Sparc mutation */
738 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
739 /* XXX: not sure */
740 fdctrl->msr &= ~FD_MSR_CMDBUSY;
741 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
742 fdctrl->status0 = status0;
743 return;
744 }
745 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
746 qemu_set_irq(fdctrl->irq, 1);
747 fdctrl->sra |= FD_SRA_INTPEND;
748 }
749 fdctrl->reset_sensei = 0;
750 fdctrl->status0 = status0;
751 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
752 }
753
754 /* Reset controller */
755 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
756 {
757 int i;
758
759 FLOPPY_DPRINTF("reset controller\n");
760 fdctrl_reset_irq(fdctrl);
761 /* Initialise controller */
762 fdctrl->sra = 0;
763 fdctrl->srb = 0xc0;
764 if (!fdctrl->drives[1].bs)
765 fdctrl->sra |= FD_SRA_nDRV2;
766 fdctrl->cur_drv = 0;
767 fdctrl->dor = FD_DOR_nRESET;
768 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
769 fdctrl->msr = FD_MSR_RQM;
770 /* FIFO state */
771 fdctrl->data_pos = 0;
772 fdctrl->data_len = 0;
773 fdctrl->data_state = 0;
774 fdctrl->data_dir = FD_DIR_WRITE;
775 for (i = 0; i < MAX_FD; i++)
776 fd_recalibrate(&fdctrl->drives[i]);
777 fdctrl_reset_fifo(fdctrl);
778 if (do_irq) {
779 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
780 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
781 }
782 }
783
784 static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
785 {
786 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
787 }
788
789 static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
790 {
791 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
792 return &fdctrl->drives[1];
793 else
794 return &fdctrl->drives[0];
795 }
796
797 #if MAX_FD == 4
798 static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
799 {
800 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
801 return &fdctrl->drives[2];
802 else
803 return &fdctrl->drives[1];
804 }
805
806 static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
807 {
808 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
809 return &fdctrl->drives[3];
810 else
811 return &fdctrl->drives[2];
812 }
813 #endif
814
815 static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
816 {
817 switch (fdctrl->cur_drv) {
818 case 0: return drv0(fdctrl);
819 case 1: return drv1(fdctrl);
820 #if MAX_FD == 4
821 case 2: return drv2(fdctrl);
822 case 3: return drv3(fdctrl);
823 #endif
824 default: return NULL;
825 }
826 }
827
828 /* Status A register : 0x00 (read-only) */
829 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
830 {
831 uint32_t retval = fdctrl->sra;
832
833 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
834
835 return retval;
836 }
837
838 /* Status B register : 0x01 (read-only) */
839 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
840 {
841 uint32_t retval = fdctrl->srb;
842
843 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
844
845 return retval;
846 }
847
848 /* Digital output register : 0x02 */
849 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
850 {
851 uint32_t retval = fdctrl->dor;
852
853 /* Selected drive */
854 retval |= fdctrl->cur_drv;
855 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
856
857 return retval;
858 }
859
860 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
861 {
862 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
863
864 /* Motors */
865 if (value & FD_DOR_MOTEN0)
866 fdctrl->srb |= FD_SRB_MTR0;
867 else
868 fdctrl->srb &= ~FD_SRB_MTR0;
869 if (value & FD_DOR_MOTEN1)
870 fdctrl->srb |= FD_SRB_MTR1;
871 else
872 fdctrl->srb &= ~FD_SRB_MTR1;
873
874 /* Drive */
875 if (value & 1)
876 fdctrl->srb |= FD_SRB_DR0;
877 else
878 fdctrl->srb &= ~FD_SRB_DR0;
879
880 /* Reset */
881 if (!(value & FD_DOR_nRESET)) {
882 if (fdctrl->dor & FD_DOR_nRESET) {
883 FLOPPY_DPRINTF("controller enter RESET state\n");
884 }
885 } else {
886 if (!(fdctrl->dor & FD_DOR_nRESET)) {
887 FLOPPY_DPRINTF("controller out of RESET state\n");
888 fdctrl_reset(fdctrl, 1);
889 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
890 }
891 }
892 /* Selected drive */
893 fdctrl->cur_drv = value & FD_DOR_SELMASK;
894
895 fdctrl->dor = value;
896 }
897
898 /* Tape drive register : 0x03 */
899 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
900 {
901 uint32_t retval = fdctrl->tdr;
902
903 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
904
905 return retval;
906 }
907
908 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
909 {
910 /* Reset mode */
911 if (!(fdctrl->dor & FD_DOR_nRESET)) {
912 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
913 return;
914 }
915 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
916 /* Disk boot selection indicator */
917 fdctrl->tdr = value & FD_TDR_BOOTSEL;
918 /* Tape indicators: never allow */
919 }
920
921 /* Main status register : 0x04 (read) */
922 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
923 {
924 uint32_t retval = fdctrl->msr;
925
926 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
927 fdctrl->dor |= FD_DOR_nRESET;
928
929 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
930
931 return retval;
932 }
933
934 /* Data select rate register : 0x04 (write) */
935 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
936 {
937 /* Reset mode */
938 if (!(fdctrl->dor & FD_DOR_nRESET)) {
939 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
940 return;
941 }
942 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
943 /* Reset: autoclear */
944 if (value & FD_DSR_SWRESET) {
945 fdctrl->dor &= ~FD_DOR_nRESET;
946 fdctrl_reset(fdctrl, 1);
947 fdctrl->dor |= FD_DOR_nRESET;
948 }
949 if (value & FD_DSR_PWRDOWN) {
950 fdctrl_reset(fdctrl, 1);
951 }
952 fdctrl->dsr = value;
953 }
954
955 static int fdctrl_media_changed(fdrive_t *drv)
956 {
957 int ret;
958
959 if (!drv->bs)
960 return 0;
961 ret = bdrv_media_changed(drv->bs);
962 if (ret) {
963 fd_revalidate(drv);
964 }
965 return ret;
966 }
967
968 /* Digital input register : 0x07 (read-only) */
969 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
970 {
971 uint32_t retval = 0;
972
973 if (fdctrl_media_changed(drv0(fdctrl))
974 || fdctrl_media_changed(drv1(fdctrl))
975 #if MAX_FD == 4
976 || fdctrl_media_changed(drv2(fdctrl))
977 || fdctrl_media_changed(drv3(fdctrl))
978 #endif
979 )
980 retval |= FD_DIR_DSKCHG;
981 if (retval != 0)
982 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
983
984 return retval;
985 }
986
987 /* FIFO state control */
988 static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
989 {
990 fdctrl->data_dir = FD_DIR_WRITE;
991 fdctrl->data_pos = 0;
992 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
993 }
994
995 /* Set FIFO status for the host to read */
996 static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
997 {
998 fdctrl->data_dir = FD_DIR_READ;
999 fdctrl->data_len = fifo_len;
1000 fdctrl->data_pos = 0;
1001 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1002 if (do_irq)
1003 fdctrl_raise_irq(fdctrl, 0x00);
1004 }
1005
1006 /* Set an error: unimplemented/unknown command */
1007 static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1008 {
1009 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1010 fdctrl->fifo[0] = FD_SR0_INVCMD;
1011 fdctrl_set_fifo(fdctrl, 1, 0);
1012 }
1013
1014 /* Seek to next sector */
1015 static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1016 {
1017 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1018 cur_drv->head, cur_drv->track, cur_drv->sect,
1019 fd_sector(cur_drv));
1020 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1021 error in fact */
1022 if (cur_drv->sect >= cur_drv->last_sect ||
1023 cur_drv->sect == fdctrl->eot) {
1024 cur_drv->sect = 1;
1025 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1026 if (cur_drv->head == 0 &&
1027 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1028 cur_drv->head = 1;
1029 } else {
1030 cur_drv->head = 0;
1031 cur_drv->track++;
1032 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1033 return 0;
1034 }
1035 } else {
1036 cur_drv->track++;
1037 return 0;
1038 }
1039 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1040 cur_drv->head, cur_drv->track,
1041 cur_drv->sect, fd_sector(cur_drv));
1042 } else {
1043 cur_drv->sect++;
1044 }
1045 return 1;
1046 }
1047
1048 /* Callback for transfer end (stop or abort) */
1049 static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1050 uint8_t status1, uint8_t status2)
1051 {
1052 fdrive_t *cur_drv;
1053
1054 cur_drv = get_cur_drv(fdctrl);
1055 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1056 status0, status1, status2,
1057 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1058 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1059 fdctrl->fifo[1] = status1;
1060 fdctrl->fifo[2] = status2;
1061 fdctrl->fifo[3] = cur_drv->track;
1062 fdctrl->fifo[4] = cur_drv->head;
1063 fdctrl->fifo[5] = cur_drv->sect;
1064 fdctrl->fifo[6] = FD_SECTOR_SC;
1065 fdctrl->data_dir = FD_DIR_READ;
1066 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1067 DMA_release_DREQ(fdctrl->dma_chann);
1068 }
1069 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1070 fdctrl->msr &= ~FD_MSR_NONDMA;
1071 fdctrl_set_fifo(fdctrl, 7, 1);
1072 }
1073
1074 /* Prepare a data transfer (either DMA or FIFO) */
1075 static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1076 {
1077 fdrive_t *cur_drv;
1078 uint8_t kh, kt, ks;
1079 int did_seek = 0;
1080
1081 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1082 cur_drv = get_cur_drv(fdctrl);
1083 kt = fdctrl->fifo[2];
1084 kh = fdctrl->fifo[3];
1085 ks = fdctrl->fifo[4];
1086 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1087 GET_CUR_DRV(fdctrl), kh, kt, ks,
1088 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1089 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1090 case 2:
1091 /* sect too big */
1092 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1093 fdctrl->fifo[3] = kt;
1094 fdctrl->fifo[4] = kh;
1095 fdctrl->fifo[5] = ks;
1096 return;
1097 case 3:
1098 /* track too big */
1099 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1100 fdctrl->fifo[3] = kt;
1101 fdctrl->fifo[4] = kh;
1102 fdctrl->fifo[5] = ks;
1103 return;
1104 case 4:
1105 /* No seek enabled */
1106 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1107 fdctrl->fifo[3] = kt;
1108 fdctrl->fifo[4] = kh;
1109 fdctrl->fifo[5] = ks;
1110 return;
1111 case 1:
1112 did_seek = 1;
1113 break;
1114 default:
1115 break;
1116 }
1117
1118 /* Set the FIFO state */
1119 fdctrl->data_dir = direction;
1120 fdctrl->data_pos = 0;
1121 fdctrl->msr |= FD_MSR_CMDBUSY;
1122 if (fdctrl->fifo[0] & 0x80)
1123 fdctrl->data_state |= FD_STATE_MULTI;
1124 else
1125 fdctrl->data_state &= ~FD_STATE_MULTI;
1126 if (did_seek)
1127 fdctrl->data_state |= FD_STATE_SEEK;
1128 else
1129 fdctrl->data_state &= ~FD_STATE_SEEK;
1130 if (fdctrl->fifo[5] == 00) {
1131 fdctrl->data_len = fdctrl->fifo[8];
1132 } else {
1133 int tmp;
1134 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1135 tmp = (fdctrl->fifo[6] - ks + 1);
1136 if (fdctrl->fifo[0] & 0x80)
1137 tmp += fdctrl->fifo[6];
1138 fdctrl->data_len *= tmp;
1139 }
1140 fdctrl->eot = fdctrl->fifo[6];
1141 if (fdctrl->dor & FD_DOR_DMAEN) {
1142 int dma_mode;
1143 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1144 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1145 dma_mode = (dma_mode >> 2) & 3;
1146 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1147 dma_mode, direction,
1148 (128 << fdctrl->fifo[5]) *
1149 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1150 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1151 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1152 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1153 (direction == FD_DIR_READ && dma_mode == 1)) {
1154 /* No access is allowed until DMA transfer has completed */
1155 fdctrl->msr &= ~FD_MSR_RQM;
1156 /* Now, we just have to wait for the DMA controller to
1157 * recall us...
1158 */
1159 DMA_hold_DREQ(fdctrl->dma_chann);
1160 DMA_schedule(fdctrl->dma_chann);
1161 return;
1162 } else {
1163 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1164 }
1165 }
1166 FLOPPY_DPRINTF("start non-DMA transfer\n");
1167 fdctrl->msr |= FD_MSR_NONDMA;
1168 if (direction != FD_DIR_WRITE)
1169 fdctrl->msr |= FD_MSR_DIO;
1170 /* IO based transfer: calculate len */
1171 fdctrl_raise_irq(fdctrl, 0x00);
1172
1173 return;
1174 }
1175
1176 /* Prepare a transfer of deleted data */
1177 static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1178 {
1179 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1180
1181 /* We don't handle deleted data,
1182 * so we don't return *ANYTHING*
1183 */
1184 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1185 }
1186
1187 /* handlers for DMA transfers */
1188 static int fdctrl_transfer_handler (void *opaque, int nchan,
1189 int dma_pos, int dma_len)
1190 {
1191 fdctrl_t *fdctrl;
1192 fdrive_t *cur_drv;
1193 int len, start_pos, rel_pos;
1194 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1195
1196 fdctrl = opaque;
1197 if (fdctrl->msr & FD_MSR_RQM) {
1198 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1199 return 0;
1200 }
1201 cur_drv = get_cur_drv(fdctrl);
1202 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1203 fdctrl->data_dir == FD_DIR_SCANH)
1204 status2 = FD_SR2_SNS;
1205 if (dma_len > fdctrl->data_len)
1206 dma_len = fdctrl->data_len;
1207 if (cur_drv->bs == NULL) {
1208 if (fdctrl->data_dir == FD_DIR_WRITE)
1209 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1210 else
1211 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1212 len = 0;
1213 goto transfer_error;
1214 }
1215 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1216 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1217 len = dma_len - fdctrl->data_pos;
1218 if (len + rel_pos > FD_SECTOR_LEN)
1219 len = FD_SECTOR_LEN - rel_pos;
1220 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1221 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1222 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1223 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1224 fd_sector(cur_drv) * FD_SECTOR_LEN);
1225 if (fdctrl->data_dir != FD_DIR_WRITE ||
1226 len < FD_SECTOR_LEN || rel_pos != 0) {
1227 /* READ & SCAN commands and realign to a sector for WRITE */
1228 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1229 fdctrl->fifo, 1) < 0) {
1230 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1231 fd_sector(cur_drv));
1232 /* Sure, image size is too small... */
1233 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1234 }
1235 }
1236 switch (fdctrl->data_dir) {
1237 case FD_DIR_READ:
1238 /* READ commands */
1239 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1240 fdctrl->data_pos, len);
1241 break;
1242 case FD_DIR_WRITE:
1243 /* WRITE commands */
1244 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1245 fdctrl->data_pos, len);
1246 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1247 fdctrl->fifo, 1) < 0) {
1248 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1249 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1250 goto transfer_error;
1251 }
1252 break;
1253 default:
1254 /* SCAN commands */
1255 {
1256 uint8_t tmpbuf[FD_SECTOR_LEN];
1257 int ret;
1258 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1259 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1260 if (ret == 0) {
1261 status2 = FD_SR2_SEH;
1262 goto end_transfer;
1263 }
1264 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1265 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1266 status2 = 0x00;
1267 goto end_transfer;
1268 }
1269 }
1270 break;
1271 }
1272 fdctrl->data_pos += len;
1273 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1274 if (rel_pos == 0) {
1275 /* Seek to next sector */
1276 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1277 break;
1278 }
1279 }
1280 end_transfer:
1281 len = fdctrl->data_pos - start_pos;
1282 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1283 fdctrl->data_pos, len, fdctrl->data_len);
1284 if (fdctrl->data_dir == FD_DIR_SCANE ||
1285 fdctrl->data_dir == FD_DIR_SCANL ||
1286 fdctrl->data_dir == FD_DIR_SCANH)
1287 status2 = FD_SR2_SEH;
1288 if (FD_DID_SEEK(fdctrl->data_state))
1289 status0 |= FD_SR0_SEEK;
1290 fdctrl->data_len -= len;
1291 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1292 transfer_error:
1293
1294 return len;
1295 }
1296
1297 /* Data register : 0x05 */
1298 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1299 {
1300 fdrive_t *cur_drv;
1301 uint32_t retval = 0;
1302 int pos;
1303
1304 cur_drv = get_cur_drv(fdctrl);
1305 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1306 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1307 FLOPPY_ERROR("controller not ready for reading\n");
1308 return 0;
1309 }
1310 pos = fdctrl->data_pos;
1311 if (fdctrl->msr & FD_MSR_NONDMA) {
1312 pos %= FD_SECTOR_LEN;
1313 if (pos == 0) {
1314 if (fdctrl->data_pos != 0)
1315 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1316 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1317 fd_sector(cur_drv));
1318 return 0;
1319 }
1320 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1321 FLOPPY_DPRINTF("error getting sector %d\n",
1322 fd_sector(cur_drv));
1323 /* Sure, image size is too small... */
1324 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1325 }
1326 }
1327 }
1328 retval = fdctrl->fifo[pos];
1329 if (++fdctrl->data_pos == fdctrl->data_len) {
1330 fdctrl->data_pos = 0;
1331 /* Switch from transfer mode to status mode
1332 * then from status mode to command mode
1333 */
1334 if (fdctrl->msr & FD_MSR_NONDMA) {
1335 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1336 } else {
1337 fdctrl_reset_fifo(fdctrl);
1338 fdctrl_reset_irq(fdctrl);
1339 }
1340 }
1341 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1342
1343 return retval;
1344 }
1345
1346 static void fdctrl_format_sector (fdctrl_t *fdctrl)
1347 {
1348 fdrive_t *cur_drv;
1349 uint8_t kh, kt, ks;
1350
1351 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1352 cur_drv = get_cur_drv(fdctrl);
1353 kt = fdctrl->fifo[6];
1354 kh = fdctrl->fifo[7];
1355 ks = fdctrl->fifo[8];
1356 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1357 GET_CUR_DRV(fdctrl), kh, kt, ks,
1358 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1359 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1360 case 2:
1361 /* sect too big */
1362 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1363 fdctrl->fifo[3] = kt;
1364 fdctrl->fifo[4] = kh;
1365 fdctrl->fifo[5] = ks;
1366 return;
1367 case 3:
1368 /* track too big */
1369 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1370 fdctrl->fifo[3] = kt;
1371 fdctrl->fifo[4] = kh;
1372 fdctrl->fifo[5] = ks;
1373 return;
1374 case 4:
1375 /* No seek enabled */
1376 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1377 fdctrl->fifo[3] = kt;
1378 fdctrl->fifo[4] = kh;
1379 fdctrl->fifo[5] = ks;
1380 return;
1381 case 1:
1382 fdctrl->data_state |= FD_STATE_SEEK;
1383 break;
1384 default:
1385 break;
1386 }
1387 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1388 if (cur_drv->bs == NULL ||
1389 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1390 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1391 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1392 } else {
1393 if (cur_drv->sect == cur_drv->last_sect) {
1394 fdctrl->data_state &= ~FD_STATE_FORMAT;
1395 /* Last sector done */
1396 if (FD_DID_SEEK(fdctrl->data_state))
1397 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1398 else
1399 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1400 } else {
1401 /* More to do */
1402 fdctrl->data_pos = 0;
1403 fdctrl->data_len = 4;
1404 }
1405 }
1406 }
1407
1408 static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1409 {
1410 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1411 fdctrl->fifo[0] = fdctrl->lock << 4;
1412 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1413 }
1414
1415 static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1416 {
1417 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1418
1419 /* Drives position */
1420 fdctrl->fifo[0] = drv0(fdctrl)->track;
1421 fdctrl->fifo[1] = drv1(fdctrl)->track;
1422 #if MAX_FD == 4
1423 fdctrl->fifo[2] = drv2(fdctrl)->track;
1424 fdctrl->fifo[3] = drv3(fdctrl)->track;
1425 #else
1426 fdctrl->fifo[2] = 0;
1427 fdctrl->fifo[3] = 0;
1428 #endif
1429 /* timers */
1430 fdctrl->fifo[4] = fdctrl->timer0;
1431 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1432 fdctrl->fifo[6] = cur_drv->last_sect;
1433 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1434 (cur_drv->perpendicular << 2);
1435 fdctrl->fifo[8] = fdctrl->config;
1436 fdctrl->fifo[9] = fdctrl->precomp_trk;
1437 fdctrl_set_fifo(fdctrl, 10, 0);
1438 }
1439
1440 static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1441 {
1442 /* Controller's version */
1443 fdctrl->fifo[0] = fdctrl->version;
1444 fdctrl_set_fifo(fdctrl, 1, 1);
1445 }
1446
1447 static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1448 {
1449 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1450 fdctrl_set_fifo(fdctrl, 1, 0);
1451 }
1452
1453 static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1454 {
1455 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1456
1457 /* Drives position */
1458 drv0(fdctrl)->track = fdctrl->fifo[3];
1459 drv1(fdctrl)->track = fdctrl->fifo[4];
1460 #if MAX_FD == 4
1461 drv2(fdctrl)->track = fdctrl->fifo[5];
1462 drv3(fdctrl)->track = fdctrl->fifo[6];
1463 #endif
1464 /* timers */
1465 fdctrl->timer0 = fdctrl->fifo[7];
1466 fdctrl->timer1 = fdctrl->fifo[8];
1467 cur_drv->last_sect = fdctrl->fifo[9];
1468 fdctrl->lock = fdctrl->fifo[10] >> 7;
1469 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1470 fdctrl->config = fdctrl->fifo[11];
1471 fdctrl->precomp_trk = fdctrl->fifo[12];
1472 fdctrl->pwrd = fdctrl->fifo[13];
1473 fdctrl_reset_fifo(fdctrl);
1474 }
1475
1476 static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1477 {
1478 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1479
1480 fdctrl->fifo[0] = 0;
1481 fdctrl->fifo[1] = 0;
1482 /* Drives position */
1483 fdctrl->fifo[2] = drv0(fdctrl)->track;
1484 fdctrl->fifo[3] = drv1(fdctrl)->track;
1485 #if MAX_FD == 4
1486 fdctrl->fifo[4] = drv2(fdctrl)->track;
1487 fdctrl->fifo[5] = drv3(fdctrl)->track;
1488 #else
1489 fdctrl->fifo[4] = 0;
1490 fdctrl->fifo[5] = 0;
1491 #endif
1492 /* timers */
1493 fdctrl->fifo[6] = fdctrl->timer0;
1494 fdctrl->fifo[7] = fdctrl->timer1;
1495 fdctrl->fifo[8] = cur_drv->last_sect;
1496 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1497 (cur_drv->perpendicular << 2);
1498 fdctrl->fifo[10] = fdctrl->config;
1499 fdctrl->fifo[11] = fdctrl->precomp_trk;
1500 fdctrl->fifo[12] = fdctrl->pwrd;
1501 fdctrl->fifo[13] = 0;
1502 fdctrl->fifo[14] = 0;
1503 fdctrl_set_fifo(fdctrl, 15, 1);
1504 }
1505
1506 static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1507 {
1508 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1509
1510 /* XXX: should set main status register to busy */
1511 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1512 qemu_mod_timer(fdctrl->result_timer,
1513 qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
1514 }
1515
1516 static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1517 {
1518 fdrive_t *cur_drv;
1519
1520 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1521 cur_drv = get_cur_drv(fdctrl);
1522 fdctrl->data_state |= FD_STATE_FORMAT;
1523 if (fdctrl->fifo[0] & 0x80)
1524 fdctrl->data_state |= FD_STATE_MULTI;
1525 else
1526 fdctrl->data_state &= ~FD_STATE_MULTI;
1527 fdctrl->data_state &= ~FD_STATE_SEEK;
1528 cur_drv->bps =
1529 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1530 #if 0
1531 cur_drv->last_sect =
1532 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1533 fdctrl->fifo[3] / 2;
1534 #else
1535 cur_drv->last_sect = fdctrl->fifo[3];
1536 #endif
1537 /* TODO: implement format using DMA expected by the Bochs BIOS
1538 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1539 * the sector with the specified fill byte
1540 */
1541 fdctrl->data_state &= ~FD_STATE_FORMAT;
1542 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1543 }
1544
1545 static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1546 {
1547 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1548 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1549 if (fdctrl->fifo[2] & 1)
1550 fdctrl->dor &= ~FD_DOR_DMAEN;
1551 else
1552 fdctrl->dor |= FD_DOR_DMAEN;
1553 /* No result back */
1554 fdctrl_reset_fifo(fdctrl);
1555 }
1556
1557 static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1558 {
1559 fdrive_t *cur_drv;
1560
1561 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1562 cur_drv = get_cur_drv(fdctrl);
1563 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1564 /* 1 Byte status back */
1565 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1566 (cur_drv->track == 0 ? 0x10 : 0x00) |
1567 (cur_drv->head << 2) |
1568 GET_CUR_DRV(fdctrl) |
1569 0x28;
1570 fdctrl_set_fifo(fdctrl, 1, 0);
1571 }
1572
1573 static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1574 {
1575 fdrive_t *cur_drv;
1576
1577 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1578 cur_drv = get_cur_drv(fdctrl);
1579 fd_recalibrate(cur_drv);
1580 fdctrl_reset_fifo(fdctrl);
1581 /* Raise Interrupt */
1582 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1583 }
1584
1585 static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1586 {
1587 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1588
1589 if(fdctrl->reset_sensei > 0) {
1590 fdctrl->fifo[0] =
1591 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1592 fdctrl->reset_sensei--;
1593 } else {
1594 /* XXX: status0 handling is broken for read/write
1595 commands, so we do this hack. It should be suppressed
1596 ASAP */
1597 fdctrl->fifo[0] =
1598 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1599 }
1600
1601 fdctrl->fifo[1] = cur_drv->track;
1602 fdctrl_set_fifo(fdctrl, 2, 0);
1603 fdctrl_reset_irq(fdctrl);
1604 fdctrl->status0 = FD_SR0_RDYCHG;
1605 }
1606
1607 static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1608 {
1609 fdrive_t *cur_drv;
1610
1611 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1612 cur_drv = get_cur_drv(fdctrl);
1613 fdctrl_reset_fifo(fdctrl);
1614 if (fdctrl->fifo[2] > cur_drv->max_track) {
1615 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1616 } else {
1617 cur_drv->track = fdctrl->fifo[2];
1618 /* Raise Interrupt */
1619 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1620 }
1621 }
1622
1623 static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1624 {
1625 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1626
1627 if (fdctrl->fifo[1] & 0x80)
1628 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1629 /* No result back */
1630 fdctrl_reset_fifo(fdctrl);
1631 }
1632
1633 static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1634 {
1635 fdctrl->config = fdctrl->fifo[2];
1636 fdctrl->precomp_trk = fdctrl->fifo[3];
1637 /* No result back */
1638 fdctrl_reset_fifo(fdctrl);
1639 }
1640
1641 static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1642 {
1643 fdctrl->pwrd = fdctrl->fifo[1];
1644 fdctrl->fifo[0] = fdctrl->fifo[1];
1645 fdctrl_set_fifo(fdctrl, 1, 1);
1646 }
1647
1648 static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1649 {
1650 /* No result back */
1651 fdctrl_reset_fifo(fdctrl);
1652 }
1653
1654 static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1655 {
1656 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1657
1658 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1659 /* Command parameters done */
1660 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1661 fdctrl->fifo[0] = fdctrl->fifo[1];
1662 fdctrl->fifo[2] = 0;
1663 fdctrl->fifo[3] = 0;
1664 fdctrl_set_fifo(fdctrl, 4, 1);
1665 } else {
1666 fdctrl_reset_fifo(fdctrl);
1667 }
1668 } else if (fdctrl->data_len > 7) {
1669 /* ERROR */
1670 fdctrl->fifo[0] = 0x80 |
1671 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1672 fdctrl_set_fifo(fdctrl, 1, 1);
1673 }
1674 }
1675
1676 static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1677 {
1678 fdrive_t *cur_drv;
1679
1680 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1681 cur_drv = get_cur_drv(fdctrl);
1682 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1683 cur_drv->track = cur_drv->max_track - 1;
1684 } else {
1685 cur_drv->track += fdctrl->fifo[2];
1686 }
1687 fdctrl_reset_fifo(fdctrl);
1688 /* Raise Interrupt */
1689 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1690 }
1691
1692 static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1693 {
1694 fdrive_t *cur_drv;
1695
1696 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1697 cur_drv = get_cur_drv(fdctrl);
1698 if (fdctrl->fifo[2] > cur_drv->track) {
1699 cur_drv->track = 0;
1700 } else {
1701 cur_drv->track -= fdctrl->fifo[2];
1702 }
1703 fdctrl_reset_fifo(fdctrl);
1704 /* Raise Interrupt */
1705 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1706 }
1707
1708 static const struct {
1709 uint8_t value;
1710 uint8_t mask;
1711 const char* name;
1712 int parameters;
1713 void (*handler)(fdctrl_t *fdctrl, int direction);
1714 int direction;
1715 } handlers[] = {
1716 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1717 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1718 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1719 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1720 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1721 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1722 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1723 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1724 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1725 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1726 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1727 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1728 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1729 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1730 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1731 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1732 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1733 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1734 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1735 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1736 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1737 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1738 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1739 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1740 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1741 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1742 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1743 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1744 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1745 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1746 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1747 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1748 };
1749 /* Associate command to an index in the 'handlers' array */
1750 static uint8_t command_to_handler[256];
1751
1752 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1753 {
1754 fdrive_t *cur_drv;
1755 int pos;
1756
1757 /* Reset mode */
1758 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1759 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1760 return;
1761 }
1762 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1763 FLOPPY_ERROR("controller not ready for writing\n");
1764 return;
1765 }
1766 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1767 /* Is it write command time ? */
1768 if (fdctrl->msr & FD_MSR_NONDMA) {
1769 /* FIFO data write */
1770 pos = fdctrl->data_pos++;
1771 pos %= FD_SECTOR_LEN;
1772 fdctrl->fifo[pos] = value;
1773 if (pos == FD_SECTOR_LEN - 1 ||
1774 fdctrl->data_pos == fdctrl->data_len) {
1775 cur_drv = get_cur_drv(fdctrl);
1776 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1777 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1778 return;
1779 }
1780 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1781 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1782 fd_sector(cur_drv));
1783 return;
1784 }
1785 }
1786 /* Switch from transfer mode to status mode
1787 * then from status mode to command mode
1788 */
1789 if (fdctrl->data_pos == fdctrl->data_len)
1790 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1791 return;
1792 }
1793 if (fdctrl->data_pos == 0) {
1794 /* Command */
1795 pos = command_to_handler[value & 0xff];
1796 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1797 fdctrl->data_len = handlers[pos].parameters + 1;
1798 }
1799
1800 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1801 fdctrl->fifo[fdctrl->data_pos++] = value;
1802 if (fdctrl->data_pos == fdctrl->data_len) {
1803 /* We now have all parameters
1804 * and will be able to treat the command
1805 */
1806 if (fdctrl->data_state & FD_STATE_FORMAT) {
1807 fdctrl_format_sector(fdctrl);
1808 return;
1809 }
1810
1811 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1812 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1813 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1814 }
1815 }
1816
1817 static void fdctrl_result_timer(void *opaque)
1818 {
1819 fdctrl_t *fdctrl = opaque;
1820 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1821
1822 /* Pretend we are spinning.
1823 * This is needed for Coherent, which uses READ ID to check for
1824 * sector interleaving.
1825 */
1826 if (cur_drv->last_sect != 0) {
1827 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1828 }
1829 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1830 }
1831
1832 /* Init functions */
1833 static void fdctrl_connect_drives(fdctrl_t *fdctrl)
1834 {
1835 unsigned int i;
1836
1837 for (i = 0; i < MAX_FD; i++) {
1838 fd_init(&fdctrl->drives[i]);
1839 fd_revalidate(&fdctrl->drives[i]);
1840 }
1841 }
1842
1843 fdctrl_t *fdctrl_init_isa(DriveInfo **fds)
1844 {
1845 ISADevice *dev;
1846
1847 dev = isa_create("isa-fdc");
1848 qdev_prop_set_drive(&dev->qdev, "driveA", fds[0]);
1849 qdev_prop_set_drive(&dev->qdev, "driveB", fds[1]);
1850 if (qdev_init(&dev->qdev) < 0)
1851 return NULL;
1852 return &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state);
1853 }
1854
1855 fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1856 target_phys_addr_t mmio_base,
1857 DriveInfo **fds)
1858 {
1859 fdctrl_t *fdctrl;
1860 DeviceState *dev;
1861 fdctrl_sysbus_t *sys;
1862
1863 dev = qdev_create(NULL, "sysbus-fdc");
1864 sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1865 fdctrl = &sys->state;
1866 fdctrl->dma_chann = dma_chann; /* FIXME */
1867 qdev_prop_set_drive(dev, "driveA", fds[0]);
1868 qdev_prop_set_drive(dev, "driveB", fds[1]);
1869 qdev_init_nofail(dev);
1870 sysbus_connect_irq(&sys->busdev, 0, irq);
1871 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1872
1873 return fdctrl;
1874 }
1875
1876 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1877 DriveInfo **fds, qemu_irq *fdc_tc)
1878 {
1879 DeviceState *dev;
1880 fdctrl_sysbus_t *sys;
1881 fdctrl_t *fdctrl;
1882
1883 dev = qdev_create(NULL, "SUNW,fdtwo");
1884 qdev_prop_set_drive(dev, "drive", fds[0]);
1885 qdev_init_nofail(dev);
1886 sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1887 fdctrl = &sys->state;
1888 sysbus_connect_irq(&sys->busdev, 0, irq);
1889 sysbus_mmio_map(&sys->busdev, 0, io_base);
1890 *fdc_tc = qdev_get_gpio_in(dev, 0);
1891
1892 return fdctrl;
1893 }
1894
1895 static int fdctrl_init_common(fdctrl_t *fdctrl)
1896 {
1897 int i, j;
1898 static int command_tables_inited = 0;
1899
1900 /* Fill 'command_to_handler' lookup table */
1901 if (!command_tables_inited) {
1902 command_tables_inited = 1;
1903 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1904 for (j = 0; j < sizeof(command_to_handler); j++) {
1905 if ((j & handlers[i].mask) == handlers[i].value) {
1906 command_to_handler[j] = i;
1907 }
1908 }
1909 }
1910 }
1911
1912 FLOPPY_DPRINTF("init controller\n");
1913 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1914 fdctrl->fifo_size = 512;
1915 fdctrl->result_timer = qemu_new_timer(vm_clock,
1916 fdctrl_result_timer, fdctrl);
1917
1918 fdctrl->version = 0x90; /* Intel 82078 controller */
1919 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1920 fdctrl->num_floppies = MAX_FD;
1921
1922 if (fdctrl->dma_chann != -1)
1923 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1924 fdctrl_connect_drives(fdctrl);
1925
1926 fdctrl_external_reset(fdctrl);
1927 vmstate_register(-1, &vmstate_fdc, fdctrl);
1928 qemu_register_reset(fdctrl_external_reset, fdctrl);
1929 return 0;
1930 }
1931
1932 static int isabus_fdc_init1(ISADevice *dev)
1933 {
1934 fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev);
1935 fdctrl_t *fdctrl = &isa->state;
1936 int iobase = 0x3f0;
1937 int isairq = 6;
1938 int dma_chann = 2;
1939
1940 register_ioport_read(iobase + 0x01, 5, 1,
1941 &fdctrl_read_port, fdctrl);
1942 register_ioport_read(iobase + 0x07, 1, 1,
1943 &fdctrl_read_port, fdctrl);
1944 register_ioport_write(iobase + 0x01, 5, 1,
1945 &fdctrl_write_port, fdctrl);
1946 register_ioport_write(iobase + 0x07, 1, 1,
1947 &fdctrl_write_port, fdctrl);
1948 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1949 fdctrl->dma_chann = dma_chann;
1950
1951 return fdctrl_init_common(fdctrl);
1952 }
1953
1954 static int sysbus_fdc_init1(SysBusDevice *dev)
1955 {
1956 fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
1957 int io;
1958
1959 io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
1960 sysbus_init_mmio(dev, 0x08, io);
1961 sysbus_init_irq(dev, &fdctrl->irq);
1962 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1963 fdctrl->dma_chann = -1;
1964
1965 return fdctrl_init_common(fdctrl);
1966 }
1967
1968 static int sun4m_fdc_init1(SysBusDevice *dev)
1969 {
1970 fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
1971 int io;
1972
1973 io = cpu_register_io_memory(fdctrl_mem_read_strict,
1974 fdctrl_mem_write_strict, fdctrl);
1975 sysbus_init_mmio(dev, 0x08, io);
1976 sysbus_init_irq(dev, &fdctrl->irq);
1977 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1978
1979 fdctrl->sun4m = 1;
1980 return fdctrl_init_common(fdctrl);
1981 }
1982
1983 static ISADeviceInfo isa_fdc_info = {
1984 .init = isabus_fdc_init1,
1985 .qdev.name = "isa-fdc",
1986 .qdev.size = sizeof(fdctrl_isabus_t),
1987 .qdev.props = (Property[]) {
1988 DEFINE_PROP_DRIVE("driveA", fdctrl_isabus_t, state.drives[0].dinfo),
1989 DEFINE_PROP_DRIVE("driveB", fdctrl_isabus_t, state.drives[1].dinfo),
1990 DEFINE_PROP_END_OF_LIST(),
1991 },
1992 };
1993
1994 static SysBusDeviceInfo sysbus_fdc_info = {
1995 .init = sysbus_fdc_init1,
1996 .qdev.name = "sysbus-fdc",
1997 .qdev.size = sizeof(fdctrl_sysbus_t),
1998 .qdev.props = (Property[]) {
1999 DEFINE_PROP_DRIVE("driveA", fdctrl_sysbus_t, state.drives[0].dinfo),
2000 DEFINE_PROP_DRIVE("driveB", fdctrl_sysbus_t, state.drives[1].dinfo),
2001 DEFINE_PROP_END_OF_LIST(),
2002 },
2003 };
2004
2005 static SysBusDeviceInfo sun4m_fdc_info = {
2006 .init = sun4m_fdc_init1,
2007 .qdev.name = "SUNW,fdtwo",
2008 .qdev.size = sizeof(fdctrl_sysbus_t),
2009 .qdev.props = (Property[]) {
2010 DEFINE_PROP_DRIVE("drive", fdctrl_sysbus_t, state.drives[0].dinfo),
2011 DEFINE_PROP_END_OF_LIST(),
2012 },
2013 };
2014
2015 static void fdc_register_devices(void)
2016 {
2017 isa_qdev_register(&isa_fdc_info);
2018 sysbus_register_withprop(&sysbus_fdc_info);
2019 sysbus_register_withprop(&sun4m_fdc_info);
2020 }
2021
2022 device_init(fdc_register_devices)
QEmu