nbd: make client request fixed new style if advertised
[qemu.git] / hw / misc / omap_clk.c
blob19151d07d62c22da52ed3c6f0452373e0982ded1
1 /*
2 * OMAP clocks.
4 * Copyright (C) 2006-2008 Andrzej Zaborowski <balrog@zabor.org>
6 * Clocks data comes in part from arch/arm/mach-omap1/clock.h in Linux.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include "qemu/osdep.h"
22 #include "hw/hw.h"
23 #include "hw/arm/omap.h"
25 struct clk {
26 const char *name;
27 const char *alias;
28 struct clk *parent;
29 struct clk *child1;
30 struct clk *sibling;
31 #define ALWAYS_ENABLED (1 << 0)
32 #define CLOCK_IN_OMAP310 (1 << 10)
33 #define CLOCK_IN_OMAP730 (1 << 11)
34 #define CLOCK_IN_OMAP1510 (1 << 12)
35 #define CLOCK_IN_OMAP16XX (1 << 13)
36 #define CLOCK_IN_OMAP242X (1 << 14)
37 #define CLOCK_IN_OMAP243X (1 << 15)
38 #define CLOCK_IN_OMAP343X (1 << 16)
39 uint32_t flags;
40 int id;
42 int running; /* Is currently ticking */
43 int enabled; /* Is enabled, regardless of its input clk */
44 unsigned long rate; /* Current rate (if .running) */
45 unsigned int divisor; /* Rate relative to input (if .enabled) */
46 unsigned int multiplier; /* Rate relative to input (if .enabled) */
47 qemu_irq users[16]; /* Who to notify on change */
48 int usecount; /* Automatically idle when unused */
51 static struct clk xtal_osc12m = {
52 .name = "xtal_osc_12m",
53 .rate = 12000000,
54 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
57 static struct clk xtal_osc32k = {
58 .name = "xtal_osc_32k",
59 .rate = 32768,
60 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
61 CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
64 static struct clk ck_ref = {
65 .name = "ck_ref",
66 .alias = "clkin",
67 .parent = &xtal_osc12m,
68 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
69 ALWAYS_ENABLED,
72 /* If a dpll is disabled it becomes a bypass, child clocks don't stop */
73 static struct clk dpll1 = {
74 .name = "dpll1",
75 .parent = &ck_ref,
76 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
77 ALWAYS_ENABLED,
80 static struct clk dpll2 = {
81 .name = "dpll2",
82 .parent = &ck_ref,
83 .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
86 static struct clk dpll3 = {
87 .name = "dpll3",
88 .parent = &ck_ref,
89 .flags = CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
92 static struct clk dpll4 = {
93 .name = "dpll4",
94 .parent = &ck_ref,
95 .multiplier = 4,
96 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
99 static struct clk apll = {
100 .name = "apll",
101 .parent = &ck_ref,
102 .multiplier = 48,
103 .divisor = 12,
104 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
107 static struct clk ck_48m = {
108 .name = "ck_48m",
109 .parent = &dpll4, /* either dpll4 or apll */
110 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
113 static struct clk ck_dpll1out = {
114 .name = "ck_dpll1out",
115 .parent = &dpll1,
116 .flags = CLOCK_IN_OMAP16XX,
119 static struct clk sossi_ck = {
120 .name = "ck_sossi",
121 .parent = &ck_dpll1out,
122 .flags = CLOCK_IN_OMAP16XX,
125 static struct clk clkm1 = {
126 .name = "clkm1",
127 .alias = "ck_gen1",
128 .parent = &dpll1,
129 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
130 ALWAYS_ENABLED,
133 static struct clk clkm2 = {
134 .name = "clkm2",
135 .alias = "ck_gen2",
136 .parent = &dpll1,
137 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
138 ALWAYS_ENABLED,
141 static struct clk clkm3 = {
142 .name = "clkm3",
143 .alias = "ck_gen3",
144 .parent = &dpll1, /* either dpll1 or ck_ref */
145 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
146 ALWAYS_ENABLED,
149 static struct clk arm_ck = {
150 .name = "arm_ck",
151 .alias = "mpu_ck",
152 .parent = &clkm1,
153 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
154 ALWAYS_ENABLED,
157 static struct clk armper_ck = {
158 .name = "armper_ck",
159 .alias = "mpuper_ck",
160 .parent = &clkm1,
161 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
164 static struct clk arm_gpio_ck = {
165 .name = "arm_gpio_ck",
166 .alias = "mpu_gpio_ck",
167 .parent = &clkm1,
168 .divisor = 1,
169 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
172 static struct clk armxor_ck = {
173 .name = "armxor_ck",
174 .alias = "mpuxor_ck",
175 .parent = &ck_ref,
176 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
179 static struct clk armtim_ck = {
180 .name = "armtim_ck",
181 .alias = "mputim_ck",
182 .parent = &ck_ref, /* either CLKIN or DPLL1 */
183 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
186 static struct clk armwdt_ck = {
187 .name = "armwdt_ck",
188 .alias = "mpuwd_ck",
189 .parent = &clkm1,
190 .divisor = 14,
191 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
192 ALWAYS_ENABLED,
195 static struct clk arminth_ck16xx = {
196 .name = "arminth_ck",
197 .parent = &arm_ck,
198 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
199 /* Note: On 16xx the frequency can be divided by 2 by programming
200 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
202 * 1510 version is in TC clocks.
206 static struct clk dsp_ck = {
207 .name = "dsp_ck",
208 .parent = &clkm2,
209 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
212 static struct clk dspmmu_ck = {
213 .name = "dspmmu_ck",
214 .parent = &clkm2,
215 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
216 ALWAYS_ENABLED,
219 static struct clk dspper_ck = {
220 .name = "dspper_ck",
221 .parent = &clkm2,
222 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
225 static struct clk dspxor_ck = {
226 .name = "dspxor_ck",
227 .parent = &ck_ref,
228 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
231 static struct clk dsptim_ck = {
232 .name = "dsptim_ck",
233 .parent = &ck_ref,
234 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
237 static struct clk tc_ck = {
238 .name = "tc_ck",
239 .parent = &clkm3,
240 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
241 CLOCK_IN_OMAP730 | CLOCK_IN_OMAP310 |
242 ALWAYS_ENABLED,
245 static struct clk arminth_ck15xx = {
246 .name = "arminth_ck",
247 .parent = &tc_ck,
248 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
249 /* Note: On 1510 the frequency follows TC_CK
251 * 16xx version is in MPU clocks.
255 static struct clk tipb_ck = {
256 /* No-idle controlled by "tc_ck" */
257 .name = "tipb_ck",
258 .parent = &tc_ck,
259 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
262 static struct clk l3_ocpi_ck = {
263 /* No-idle controlled by "tc_ck" */
264 .name = "l3_ocpi_ck",
265 .parent = &tc_ck,
266 .flags = CLOCK_IN_OMAP16XX,
269 static struct clk tc1_ck = {
270 .name = "tc1_ck",
271 .parent = &tc_ck,
272 .flags = CLOCK_IN_OMAP16XX,
275 static struct clk tc2_ck = {
276 .name = "tc2_ck",
277 .parent = &tc_ck,
278 .flags = CLOCK_IN_OMAP16XX,
281 static struct clk dma_ck = {
282 /* No-idle controlled by "tc_ck" */
283 .name = "dma_ck",
284 .parent = &tc_ck,
285 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
286 ALWAYS_ENABLED,
289 static struct clk dma_lcdfree_ck = {
290 .name = "dma_lcdfree_ck",
291 .parent = &tc_ck,
292 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
295 static struct clk api_ck = {
296 .name = "api_ck",
297 .alias = "mpui_ck",
298 .parent = &tc_ck,
299 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
302 static struct clk lb_ck = {
303 .name = "lb_ck",
304 .parent = &tc_ck,
305 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
308 static struct clk lbfree_ck = {
309 .name = "lbfree_ck",
310 .parent = &tc_ck,
311 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
314 static struct clk hsab_ck = {
315 .name = "hsab_ck",
316 .parent = &tc_ck,
317 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
320 static struct clk rhea1_ck = {
321 .name = "rhea1_ck",
322 .parent = &tc_ck,
323 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
326 static struct clk rhea2_ck = {
327 .name = "rhea2_ck",
328 .parent = &tc_ck,
329 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
332 static struct clk lcd_ck_16xx = {
333 .name = "lcd_ck",
334 .parent = &clkm3,
335 .flags = CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP730,
338 static struct clk lcd_ck_1510 = {
339 .name = "lcd_ck",
340 .parent = &clkm3,
341 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
344 static struct clk uart1_1510 = {
345 .name = "uart1_ck",
346 /* Direct from ULPD, no real parent */
347 .parent = &armper_ck, /* either armper_ck or dpll4 */
348 .rate = 12000000,
349 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
352 static struct clk uart1_16xx = {
353 .name = "uart1_ck",
354 /* Direct from ULPD, no real parent */
355 .parent = &armper_ck,
356 .rate = 48000000,
357 .flags = CLOCK_IN_OMAP16XX,
360 static struct clk uart2_ck = {
361 .name = "uart2_ck",
362 /* Direct from ULPD, no real parent */
363 .parent = &armper_ck, /* either armper_ck or dpll4 */
364 .rate = 12000000,
365 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310 |
366 ALWAYS_ENABLED,
369 static struct clk uart3_1510 = {
370 .name = "uart3_ck",
371 /* Direct from ULPD, no real parent */
372 .parent = &armper_ck, /* either armper_ck or dpll4 */
373 .rate = 12000000,
374 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310 | ALWAYS_ENABLED,
377 static struct clk uart3_16xx = {
378 .name = "uart3_ck",
379 /* Direct from ULPD, no real parent */
380 .parent = &armper_ck,
381 .rate = 48000000,
382 .flags = CLOCK_IN_OMAP16XX,
385 static struct clk usb_clk0 = { /* 6 MHz output on W4_USB_CLK0 */
386 .name = "usb_clk0",
387 .alias = "usb.clko",
388 /* Direct from ULPD, no parent */
389 .rate = 6000000,
390 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
393 static struct clk usb_hhc_ck1510 = {
394 .name = "usb_hhc_ck",
395 /* Direct from ULPD, no parent */
396 .rate = 48000000, /* Actually 2 clocks, 12MHz and 48MHz */
397 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP310,
400 static struct clk usb_hhc_ck16xx = {
401 .name = "usb_hhc_ck",
402 /* Direct from ULPD, no parent */
403 .rate = 48000000,
404 /* OTG_SYSCON_2.OTG_PADEN == 0 (not 1510-compatible) */
405 .flags = CLOCK_IN_OMAP16XX,
408 static struct clk usb_w2fc_mclk = {
409 .name = "usb_w2fc_mclk",
410 .alias = "usb_w2fc_ck",
411 .parent = &ck_48m,
412 .rate = 48000000,
413 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
416 static struct clk mclk_1510 = {
417 .name = "mclk",
418 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
419 .rate = 12000000,
420 .flags = CLOCK_IN_OMAP1510,
423 static struct clk bclk_310 = {
424 .name = "bt_mclk_out", /* Alias midi_mclk_out? */
425 .parent = &armper_ck,
426 .flags = CLOCK_IN_OMAP310,
429 static struct clk mclk_310 = {
430 .name = "com_mclk_out",
431 .parent = &armper_ck,
432 .flags = CLOCK_IN_OMAP310,
435 static struct clk mclk_16xx = {
436 .name = "mclk",
437 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
438 .flags = CLOCK_IN_OMAP16XX,
441 static struct clk bclk_1510 = {
442 .name = "bclk",
443 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
444 .rate = 12000000,
445 .flags = CLOCK_IN_OMAP1510,
448 static struct clk bclk_16xx = {
449 .name = "bclk",
450 /* Direct from ULPD, no parent. May be enabled by ext hardware. */
451 .flags = CLOCK_IN_OMAP16XX,
454 static struct clk mmc1_ck = {
455 .name = "mmc_ck",
456 .id = 1,
457 /* Functional clock is direct from ULPD, interface clock is ARMPER */
458 .parent = &armper_ck, /* either armper_ck or dpll4 */
459 .rate = 48000000,
460 .flags = CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX | CLOCK_IN_OMAP310,
463 static struct clk mmc2_ck = {
464 .name = "mmc_ck",
465 .id = 2,
466 /* Functional clock is direct from ULPD, interface clock is ARMPER */
467 .parent = &armper_ck,
468 .rate = 48000000,
469 .flags = CLOCK_IN_OMAP16XX,
472 static struct clk cam_mclk = {
473 .name = "cam.mclk",
474 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
475 .rate = 12000000,
478 static struct clk cam_exclk = {
479 .name = "cam.exclk",
480 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
481 /* Either 12M from cam.mclk or 48M from dpll4 */
482 .parent = &cam_mclk,
485 static struct clk cam_lclk = {
486 .name = "cam.lclk",
487 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX,
490 static struct clk i2c_fck = {
491 .name = "i2c_fck",
492 .id = 1,
493 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
494 ALWAYS_ENABLED,
495 .parent = &armxor_ck,
498 static struct clk i2c_ick = {
499 .name = "i2c_ick",
500 .id = 1,
501 .flags = CLOCK_IN_OMAP16XX | ALWAYS_ENABLED,
502 .parent = &armper_ck,
505 static struct clk clk32k = {
506 .name = "clk32-kHz",
507 .flags = CLOCK_IN_OMAP310 | CLOCK_IN_OMAP1510 | CLOCK_IN_OMAP16XX |
508 CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
509 .parent = &xtal_osc32k,
512 static struct clk ref_clk = {
513 .name = "ref_clk",
514 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
515 .rate = 12000000, /* 12 MHz or 13 MHz or 19.2 MHz */
516 /*.parent = sys.xtalin */
519 static struct clk apll_96m = {
520 .name = "apll_96m",
521 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
522 .rate = 96000000,
523 /*.parent = ref_clk */
526 static struct clk apll_54m = {
527 .name = "apll_54m",
528 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
529 .rate = 54000000,
530 /*.parent = ref_clk */
533 static struct clk sys_clk = {
534 .name = "sys_clk",
535 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
536 .rate = 32768,
537 /*.parent = sys.xtalin */
540 static struct clk sleep_clk = {
541 .name = "sleep_clk",
542 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
543 .rate = 32768,
544 /*.parent = sys.xtalin */
547 static struct clk dpll_ck = {
548 .name = "dpll",
549 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
550 .parent = &ref_clk,
553 static struct clk dpll_x2_ck = {
554 .name = "dpll_x2",
555 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
556 .parent = &ref_clk,
559 static struct clk wdt1_sys_clk = {
560 .name = "wdt1_sys_clk",
561 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X | ALWAYS_ENABLED,
562 .rate = 32768,
563 /*.parent = sys.xtalin */
566 static struct clk func_96m_clk = {
567 .name = "func_96m_clk",
568 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
569 .divisor = 1,
570 .parent = &apll_96m,
573 static struct clk func_48m_clk = {
574 .name = "func_48m_clk",
575 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
576 .divisor = 2,
577 .parent = &apll_96m,
580 static struct clk func_12m_clk = {
581 .name = "func_12m_clk",
582 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
583 .divisor = 8,
584 .parent = &apll_96m,
587 static struct clk func_54m_clk = {
588 .name = "func_54m_clk",
589 .flags = CLOCK_IN_OMAP242X,
590 .divisor = 1,
591 .parent = &apll_54m,
594 static struct clk sys_clkout = {
595 .name = "clkout",
596 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
597 .parent = &sys_clk,
600 static struct clk sys_clkout2 = {
601 .name = "clkout2",
602 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
603 .parent = &sys_clk,
606 static struct clk core_clk = {
607 .name = "core_clk",
608 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
609 .parent = &dpll_x2_ck, /* Switchable between dpll_ck and clk32k */
612 static struct clk l3_clk = {
613 .name = "l3_clk",
614 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
615 .parent = &core_clk,
618 static struct clk core_l4_iclk = {
619 .name = "core_l4_iclk",
620 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
621 .parent = &l3_clk,
624 static struct clk wu_l4_iclk = {
625 .name = "wu_l4_iclk",
626 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
627 .parent = &l3_clk,
630 static struct clk core_l3_iclk = {
631 .name = "core_l3_iclk",
632 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
633 .parent = &core_clk,
636 static struct clk core_l4_usb_clk = {
637 .name = "core_l4_usb_clk",
638 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
639 .parent = &l3_clk,
642 static struct clk wu_gpt1_clk = {
643 .name = "wu_gpt1_clk",
644 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
645 .parent = &sys_clk,
648 static struct clk wu_32k_clk = {
649 .name = "wu_32k_clk",
650 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
651 .parent = &sys_clk,
654 static struct clk uart1_fclk = {
655 .name = "uart1_fclk",
656 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
657 .parent = &func_48m_clk,
660 static struct clk uart1_iclk = {
661 .name = "uart1_iclk",
662 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
663 .parent = &core_l4_iclk,
666 static struct clk uart2_fclk = {
667 .name = "uart2_fclk",
668 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
669 .parent = &func_48m_clk,
672 static struct clk uart2_iclk = {
673 .name = "uart2_iclk",
674 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
675 .parent = &core_l4_iclk,
678 static struct clk uart3_fclk = {
679 .name = "uart3_fclk",
680 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
681 .parent = &func_48m_clk,
684 static struct clk uart3_iclk = {
685 .name = "uart3_iclk",
686 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
687 .parent = &core_l4_iclk,
690 static struct clk mpu_fclk = {
691 .name = "mpu_fclk",
692 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
693 .parent = &core_clk,
696 static struct clk mpu_iclk = {
697 .name = "mpu_iclk",
698 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
699 .parent = &core_clk,
702 static struct clk int_m_fclk = {
703 .name = "int_m_fclk",
704 .alias = "mpu_intc_fclk",
705 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
706 .parent = &core_clk,
709 static struct clk int_m_iclk = {
710 .name = "int_m_iclk",
711 .alias = "mpu_intc_iclk",
712 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
713 .parent = &core_clk,
716 static struct clk core_gpt2_clk = {
717 .name = "core_gpt2_clk",
718 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
719 .parent = &sys_clk,
722 static struct clk core_gpt3_clk = {
723 .name = "core_gpt3_clk",
724 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
725 .parent = &sys_clk,
728 static struct clk core_gpt4_clk = {
729 .name = "core_gpt4_clk",
730 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
731 .parent = &sys_clk,
734 static struct clk core_gpt5_clk = {
735 .name = "core_gpt5_clk",
736 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
737 .parent = &sys_clk,
740 static struct clk core_gpt6_clk = {
741 .name = "core_gpt6_clk",
742 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
743 .parent = &sys_clk,
746 static struct clk core_gpt7_clk = {
747 .name = "core_gpt7_clk",
748 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
749 .parent = &sys_clk,
752 static struct clk core_gpt8_clk = {
753 .name = "core_gpt8_clk",
754 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
755 .parent = &sys_clk,
758 static struct clk core_gpt9_clk = {
759 .name = "core_gpt9_clk",
760 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
761 .parent = &sys_clk,
764 static struct clk core_gpt10_clk = {
765 .name = "core_gpt10_clk",
766 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
767 .parent = &sys_clk,
770 static struct clk core_gpt11_clk = {
771 .name = "core_gpt11_clk",
772 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
773 .parent = &sys_clk,
776 static struct clk core_gpt12_clk = {
777 .name = "core_gpt12_clk",
778 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
779 .parent = &sys_clk,
782 static struct clk mcbsp1_clk = {
783 .name = "mcbsp1_cg",
784 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
785 .divisor = 2,
786 .parent = &func_96m_clk,
789 static struct clk mcbsp2_clk = {
790 .name = "mcbsp2_cg",
791 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
792 .divisor = 2,
793 .parent = &func_96m_clk,
796 static struct clk emul_clk = {
797 .name = "emul_ck",
798 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
799 .parent = &func_54m_clk,
802 static struct clk sdma_fclk = {
803 .name = "sdma_fclk",
804 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
805 .parent = &l3_clk,
808 static struct clk sdma_iclk = {
809 .name = "sdma_iclk",
810 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
811 .parent = &core_l3_iclk, /* core_l4_iclk for the configuration port */
814 static struct clk i2c1_fclk = {
815 .name = "i2c1.fclk",
816 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
817 .parent = &func_12m_clk,
818 .divisor = 1,
821 static struct clk i2c1_iclk = {
822 .name = "i2c1.iclk",
823 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
824 .parent = &core_l4_iclk,
827 static struct clk i2c2_fclk = {
828 .name = "i2c2.fclk",
829 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
830 .parent = &func_12m_clk,
831 .divisor = 1,
834 static struct clk i2c2_iclk = {
835 .name = "i2c2.iclk",
836 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
837 .parent = &core_l4_iclk,
840 static struct clk gpio_dbclk[5] = {
842 .name = "gpio1_dbclk",
843 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
844 .parent = &wu_32k_clk,
845 }, {
846 .name = "gpio2_dbclk",
847 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
848 .parent = &wu_32k_clk,
849 }, {
850 .name = "gpio3_dbclk",
851 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
852 .parent = &wu_32k_clk,
853 }, {
854 .name = "gpio4_dbclk",
855 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
856 .parent = &wu_32k_clk,
857 }, {
858 .name = "gpio5_dbclk",
859 .flags = CLOCK_IN_OMAP243X,
860 .parent = &wu_32k_clk,
864 static struct clk gpio_iclk = {
865 .name = "gpio_iclk",
866 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
867 .parent = &wu_l4_iclk,
870 static struct clk mmc_fck = {
871 .name = "mmc_fclk",
872 .flags = CLOCK_IN_OMAP242X,
873 .parent = &func_96m_clk,
876 static struct clk mmc_ick = {
877 .name = "mmc_iclk",
878 .flags = CLOCK_IN_OMAP242X,
879 .parent = &core_l4_iclk,
882 static struct clk spi_fclk[3] = {
884 .name = "spi1_fclk",
885 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
886 .parent = &func_48m_clk,
887 }, {
888 .name = "spi2_fclk",
889 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
890 .parent = &func_48m_clk,
891 }, {
892 .name = "spi3_fclk",
893 .flags = CLOCK_IN_OMAP243X,
894 .parent = &func_48m_clk,
898 static struct clk dss_clk[2] = {
900 .name = "dss_clk1",
901 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
902 .parent = &core_clk,
903 }, {
904 .name = "dss_clk2",
905 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
906 .parent = &sys_clk,
910 static struct clk dss_54m_clk = {
911 .name = "dss_54m_clk",
912 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
913 .parent = &func_54m_clk,
916 static struct clk dss_l3_iclk = {
917 .name = "dss_l3_iclk",
918 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
919 .parent = &core_l3_iclk,
922 static struct clk dss_l4_iclk = {
923 .name = "dss_l4_iclk",
924 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
925 .parent = &core_l4_iclk,
928 static struct clk spi_iclk[3] = {
930 .name = "spi1_iclk",
931 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
932 .parent = &core_l4_iclk,
933 }, {
934 .name = "spi2_iclk",
935 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
936 .parent = &core_l4_iclk,
937 }, {
938 .name = "spi3_iclk",
939 .flags = CLOCK_IN_OMAP243X,
940 .parent = &core_l4_iclk,
944 static struct clk omapctrl_clk = {
945 .name = "omapctrl_iclk",
946 .flags = CLOCK_IN_OMAP242X | CLOCK_IN_OMAP243X,
947 /* XXX Should be in WKUP domain */
948 .parent = &core_l4_iclk,
951 static struct clk *onchip_clks[] = {
952 /* OMAP 1 */
954 /* non-ULPD clocks */
955 &xtal_osc12m,
956 &xtal_osc32k,
957 &ck_ref,
958 &dpll1,
959 &dpll2,
960 &dpll3,
961 &dpll4,
962 &apll,
963 &ck_48m,
964 /* CK_GEN1 clocks */
965 &clkm1,
966 &ck_dpll1out,
967 &sossi_ck,
968 &arm_ck,
969 &armper_ck,
970 &arm_gpio_ck,
971 &armxor_ck,
972 &armtim_ck,
973 &armwdt_ck,
974 &arminth_ck15xx, &arminth_ck16xx,
975 /* CK_GEN2 clocks */
976 &clkm2,
977 &dsp_ck,
978 &dspmmu_ck,
979 &dspper_ck,
980 &dspxor_ck,
981 &dsptim_ck,
982 /* CK_GEN3 clocks */
983 &clkm3,
984 &tc_ck,
985 &tipb_ck,
986 &l3_ocpi_ck,
987 &tc1_ck,
988 &tc2_ck,
989 &dma_ck,
990 &dma_lcdfree_ck,
991 &api_ck,
992 &lb_ck,
993 &lbfree_ck,
994 &hsab_ck,
995 &rhea1_ck,
996 &rhea2_ck,
997 &lcd_ck_16xx,
998 &lcd_ck_1510,
999 /* ULPD clocks */
1000 &uart1_1510,
1001 &uart1_16xx,
1002 &uart2_ck,
1003 &uart3_1510,
1004 &uart3_16xx,
1005 &usb_clk0,
1006 &usb_hhc_ck1510, &usb_hhc_ck16xx,
1007 &mclk_1510, &mclk_16xx, &mclk_310,
1008 &bclk_1510, &bclk_16xx, &bclk_310,
1009 &mmc1_ck,
1010 &mmc2_ck,
1011 &cam_mclk,
1012 &cam_exclk,
1013 &cam_lclk,
1014 &clk32k,
1015 &usb_w2fc_mclk,
1016 /* Virtual clocks */
1017 &i2c_fck,
1018 &i2c_ick,
1020 /* OMAP 2 */
1022 &ref_clk,
1023 &apll_96m,
1024 &apll_54m,
1025 &sys_clk,
1026 &sleep_clk,
1027 &dpll_ck,
1028 &dpll_x2_ck,
1029 &wdt1_sys_clk,
1030 &func_96m_clk,
1031 &func_48m_clk,
1032 &func_12m_clk,
1033 &func_54m_clk,
1034 &sys_clkout,
1035 &sys_clkout2,
1036 &core_clk,
1037 &l3_clk,
1038 &core_l4_iclk,
1039 &wu_l4_iclk,
1040 &core_l3_iclk,
1041 &core_l4_usb_clk,
1042 &wu_gpt1_clk,
1043 &wu_32k_clk,
1044 &uart1_fclk,
1045 &uart1_iclk,
1046 &uart2_fclk,
1047 &uart2_iclk,
1048 &uart3_fclk,
1049 &uart3_iclk,
1050 &mpu_fclk,
1051 &mpu_iclk,
1052 &int_m_fclk,
1053 &int_m_iclk,
1054 &core_gpt2_clk,
1055 &core_gpt3_clk,
1056 &core_gpt4_clk,
1057 &core_gpt5_clk,
1058 &core_gpt6_clk,
1059 &core_gpt7_clk,
1060 &core_gpt8_clk,
1061 &core_gpt9_clk,
1062 &core_gpt10_clk,
1063 &core_gpt11_clk,
1064 &core_gpt12_clk,
1065 &mcbsp1_clk,
1066 &mcbsp2_clk,
1067 &emul_clk,
1068 &sdma_fclk,
1069 &sdma_iclk,
1070 &i2c1_fclk,
1071 &i2c1_iclk,
1072 &i2c2_fclk,
1073 &i2c2_iclk,
1074 &gpio_dbclk[0],
1075 &gpio_dbclk[1],
1076 &gpio_dbclk[2],
1077 &gpio_dbclk[3],
1078 &gpio_iclk,
1079 &mmc_fck,
1080 &mmc_ick,
1081 &spi_fclk[0],
1082 &spi_iclk[0],
1083 &spi_fclk[1],
1084 &spi_iclk[1],
1085 &spi_fclk[2],
1086 &spi_iclk[2],
1087 &dss_clk[0],
1088 &dss_clk[1],
1089 &dss_54m_clk,
1090 &dss_l3_iclk,
1091 &dss_l4_iclk,
1092 &omapctrl_clk,
1094 NULL
1097 void omap_clk_adduser(struct clk *clk, qemu_irq user)
1099 qemu_irq *i;
1101 for (i = clk->users; *i; i ++);
1102 *i = user;
1105 struct clk *omap_findclk(struct omap_mpu_state_s *mpu, const char *name)
1107 struct clk *i;
1109 for (i = mpu->clks; i->name; i ++)
1110 if (!strcmp(i->name, name) || (i->alias && !strcmp(i->alias, name)))
1111 return i;
1112 hw_error("%s: %s not found\n", __FUNCTION__, name);
1115 void omap_clk_get(struct clk *clk)
1117 clk->usecount ++;
1120 void omap_clk_put(struct clk *clk)
1122 if (!(clk->usecount --))
1123 hw_error("%s: %s is not in use\n", __FUNCTION__, clk->name);
1126 static void omap_clk_update(struct clk *clk)
1128 int parent, running;
1129 qemu_irq *user;
1130 struct clk *i;
1132 if (clk->parent)
1133 parent = clk->parent->running;
1134 else
1135 parent = 1;
1137 running = parent && (clk->enabled ||
1138 ((clk->flags & ALWAYS_ENABLED) && clk->usecount));
1139 if (clk->running != running) {
1140 clk->running = running;
1141 for (user = clk->users; *user; user ++)
1142 qemu_set_irq(*user, running);
1143 for (i = clk->child1; i; i = i->sibling)
1144 omap_clk_update(i);
1148 static void omap_clk_rate_update_full(struct clk *clk, unsigned long int rate,
1149 unsigned long int div, unsigned long int mult)
1151 struct clk *i;
1152 qemu_irq *user;
1154 clk->rate = muldiv64(rate, mult, div);
1155 if (clk->running)
1156 for (user = clk->users; *user; user ++)
1157 qemu_irq_raise(*user);
1158 for (i = clk->child1; i; i = i->sibling)
1159 omap_clk_rate_update_full(i, rate,
1160 div * i->divisor, mult * i->multiplier);
1163 static void omap_clk_rate_update(struct clk *clk)
1165 struct clk *i;
1166 unsigned long int div, mult = div = 1;
1168 for (i = clk; i->parent; i = i->parent) {
1169 div *= i->divisor;
1170 mult *= i->multiplier;
1173 omap_clk_rate_update_full(clk, i->rate, div, mult);
1176 void omap_clk_reparent(struct clk *clk, struct clk *parent)
1178 struct clk **p;
1180 if (clk->parent) {
1181 for (p = &clk->parent->child1; *p != clk; p = &(*p)->sibling);
1182 *p = clk->sibling;
1185 clk->parent = parent;
1186 if (parent) {
1187 clk->sibling = parent->child1;
1188 parent->child1 = clk;
1189 omap_clk_update(clk);
1190 omap_clk_rate_update(clk);
1191 } else
1192 clk->sibling = NULL;
1195 void omap_clk_onoff(struct clk *clk, int on)
1197 clk->enabled = on;
1198 omap_clk_update(clk);
1201 void omap_clk_canidle(struct clk *clk, int can)
1203 if (can)
1204 omap_clk_put(clk);
1205 else
1206 omap_clk_get(clk);
1209 void omap_clk_setrate(struct clk *clk, int divide, int multiply)
1211 clk->divisor = divide;
1212 clk->multiplier = multiply;
1213 omap_clk_rate_update(clk);
1216 int64_t omap_clk_getrate(omap_clk clk)
1218 return clk->rate;
1221 void omap_clk_init(struct omap_mpu_state_s *mpu)
1223 struct clk **i, *j, *k;
1224 int count;
1225 int flag;
1227 if (cpu_is_omap310(mpu))
1228 flag = CLOCK_IN_OMAP310;
1229 else if (cpu_is_omap1510(mpu))
1230 flag = CLOCK_IN_OMAP1510;
1231 else if (cpu_is_omap2410(mpu) || cpu_is_omap2420(mpu))
1232 flag = CLOCK_IN_OMAP242X;
1233 else if (cpu_is_omap2430(mpu))
1234 flag = CLOCK_IN_OMAP243X;
1235 else if (cpu_is_omap3430(mpu))
1236 flag = CLOCK_IN_OMAP243X;
1237 else
1238 return;
1240 for (i = onchip_clks, count = 0; *i; i ++)
1241 if ((*i)->flags & flag)
1242 count ++;
1243 mpu->clks = g_new0(struct clk, count + 1);
1244 for (i = onchip_clks, j = mpu->clks; *i; i ++)
1245 if ((*i)->flags & flag) {
1246 memcpy(j, *i, sizeof(struct clk));
1247 for (k = mpu->clks; k < j; k ++)
1248 if (j->parent && !strcmp(j->parent->name, k->name)) {
1249 j->parent = k;
1250 j->sibling = k->child1;
1251 k->child1 = j;
1252 } else if (k->parent && !strcmp(k->parent->name, j->name)) {
1253 k->parent = j;
1254 k->sibling = j->child1;
1255 j->child1 = k;
1257 j->divisor = j->divisor ?: 1;
1258 j->multiplier = j->multiplier ?: 1;
1259 j ++;
1261 for (j = mpu->clks; count --; j ++) {
1262 omap_clk_update(j);
1263 omap_clk_rate_update(j);