4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
34 #include "fpu/softfloat.h"
35 #include "qemu/module.h"
36 #include "migration/vmstate.h"
39 static void xtensa_cpu_set_pc(CPUState
*cs
, vaddr value
)
41 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
46 static bool xtensa_cpu_has_work(CPUState
*cs
)
48 #ifndef CONFIG_USER_ONLY
49 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
51 return !cpu
->env
.runstall
&& cpu
->env
.pending_irq_level
;
57 #ifdef CONFIG_USER_ONLY
58 static bool abi_call0
;
60 void xtensa_set_abi_call0(void)
65 bool xtensa_abi_call0(void)
71 static void xtensa_cpu_reset(DeviceState
*dev
)
73 CPUState
*s
= CPU(dev
);
74 XtensaCPU
*cpu
= XTENSA_CPU(s
);
75 XtensaCPUClass
*xcc
= XTENSA_CPU_GET_CLASS(cpu
);
76 CPUXtensaState
*env
= &cpu
->env
;
77 bool dfpu
= xtensa_option_enabled(env
->config
,
78 XTENSA_OPTION_DFP_COPROCESSOR
);
80 xcc
->parent_reset(dev
);
82 env
->exception_taken
= 0;
83 env
->pc
= env
->config
->exception_vector
[EXC_RESET0
+ env
->static_vectors
];
84 env
->sregs
[LITBASE
] &= ~1;
85 #ifndef CONFIG_USER_ONLY
86 env
->sregs
[PS
] = xtensa_option_enabled(env
->config
,
87 XTENSA_OPTION_INTERRUPT
) ? 0x1f : 0x10;
88 env
->pending_irq_level
= 0;
90 env
->sregs
[PS
] = PS_UM
| (3 << PS_RING_SHIFT
);
91 if (xtensa_option_enabled(env
->config
,
92 XTENSA_OPTION_WINDOWED_REGISTER
) &&
93 !xtensa_abi_call0()) {
94 env
->sregs
[PS
] |= PS_WOE
;
97 env
->sregs
[VECBASE
] = env
->config
->vecbase
;
98 env
->sregs
[IBREAKENABLE
] = 0;
99 env
->sregs
[MEMCTL
] = MEMCTL_IL0EN
& env
->config
->memctl_mask
;
100 env
->sregs
[ATOMCTL
] = xtensa_option_enabled(env
->config
,
101 XTENSA_OPTION_ATOMCTL
) ? 0x28 : 0x15;
102 env
->sregs
[CONFIGID0
] = env
->config
->configid
[0];
103 env
->sregs
[CONFIGID1
] = env
->config
->configid
[1];
104 env
->exclusive_addr
= -1;
106 #ifndef CONFIG_USER_ONLY
108 s
->halted
= env
->runstall
;
110 set_no_signaling_nans(!dfpu
, &env
->fp_status
);
111 set_use_first_nan(!dfpu
, &env
->fp_status
);
114 static ObjectClass
*xtensa_cpu_class_by_name(const char *cpu_model
)
119 typename
= g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model
);
120 oc
= object_class_by_name(typename
);
122 if (oc
== NULL
|| !object_class_dynamic_cast(oc
, TYPE_XTENSA_CPU
) ||
123 object_class_is_abstract(oc
)) {
129 static void xtensa_cpu_disas_set_info(CPUState
*cs
, disassemble_info
*info
)
131 XtensaCPU
*cpu
= XTENSA_CPU(cs
);
133 info
->private_data
= cpu
->env
.config
->isa
;
134 info
->print_insn
= print_insn_xtensa
;
137 static void xtensa_cpu_realizefn(DeviceState
*dev
, Error
**errp
)
139 CPUState
*cs
= CPU(dev
);
140 XtensaCPUClass
*xcc
= XTENSA_CPU_GET_CLASS(dev
);
141 Error
*local_err
= NULL
;
143 #ifndef CONFIG_USER_ONLY
144 xtensa_irq_init(&XTENSA_CPU(dev
)->env
);
147 cpu_exec_realizefn(cs
, &local_err
);
148 if (local_err
!= NULL
) {
149 error_propagate(errp
, local_err
);
153 cs
->gdb_num_regs
= xcc
->config
->gdb_regmap
.num_regs
;
157 xcc
->parent_realize(dev
, errp
);
160 static void xtensa_cpu_initfn(Object
*obj
)
162 XtensaCPU
*cpu
= XTENSA_CPU(obj
);
163 XtensaCPUClass
*xcc
= XTENSA_CPU_GET_CLASS(obj
);
164 CPUXtensaState
*env
= &cpu
->env
;
166 cpu_set_cpustate_pointers(cpu
);
167 env
->config
= xcc
->config
;
169 #ifndef CONFIG_USER_ONLY
170 env
->address_space_er
= g_malloc(sizeof(*env
->address_space_er
));
171 env
->system_er
= g_malloc(sizeof(*env
->system_er
));
172 memory_region_init_io(env
->system_er
, obj
, NULL
, env
, "er",
173 UINT64_C(0x100000000));
174 address_space_init(env
->address_space_er
, env
->system_er
, "ER");
178 static const VMStateDescription vmstate_xtensa_cpu
= {
183 static void xtensa_cpu_class_init(ObjectClass
*oc
, void *data
)
185 DeviceClass
*dc
= DEVICE_CLASS(oc
);
186 CPUClass
*cc
= CPU_CLASS(oc
);
187 XtensaCPUClass
*xcc
= XTENSA_CPU_CLASS(cc
);
189 device_class_set_parent_realize(dc
, xtensa_cpu_realizefn
,
190 &xcc
->parent_realize
);
192 device_class_set_parent_reset(dc
, xtensa_cpu_reset
, &xcc
->parent_reset
);
194 cc
->class_by_name
= xtensa_cpu_class_by_name
;
195 cc
->has_work
= xtensa_cpu_has_work
;
196 cc
->do_interrupt
= xtensa_cpu_do_interrupt
;
197 cc
->cpu_exec_interrupt
= xtensa_cpu_exec_interrupt
;
198 cc
->dump_state
= xtensa_cpu_dump_state
;
199 cc
->set_pc
= xtensa_cpu_set_pc
;
200 cc
->gdb_read_register
= xtensa_cpu_gdb_read_register
;
201 cc
->gdb_write_register
= xtensa_cpu_gdb_write_register
;
202 cc
->gdb_stop_before_watchpoint
= true;
203 cc
->tlb_fill
= xtensa_cpu_tlb_fill
;
204 #ifndef CONFIG_USER_ONLY
205 cc
->do_unaligned_access
= xtensa_cpu_do_unaligned_access
;
206 cc
->get_phys_page_debug
= xtensa_cpu_get_phys_page_debug
;
207 cc
->do_transaction_failed
= xtensa_cpu_do_transaction_failed
;
209 cc
->debug_excp_handler
= xtensa_breakpoint_handler
;
210 cc
->disas_set_info
= xtensa_cpu_disas_set_info
;
211 cc
->tcg_initialize
= xtensa_translate_init
;
212 dc
->vmsd
= &vmstate_xtensa_cpu
;
215 static const TypeInfo xtensa_cpu_type_info
= {
216 .name
= TYPE_XTENSA_CPU
,
218 .instance_size
= sizeof(XtensaCPU
),
219 .instance_init
= xtensa_cpu_initfn
,
221 .class_size
= sizeof(XtensaCPUClass
),
222 .class_init
= xtensa_cpu_class_init
,
225 static void xtensa_cpu_register_types(void)
227 type_register_static(&xtensa_cpu_type_info
);
230 type_init(xtensa_cpu_register_types
)