target-arm/helper.c

   1 #include "qemu/osdep.h"
   2 #include "cpu.h"
   3 #include "internals.h"
   4 #include "exec/gdbstub.h"
   5 #include "exec/helper-proto.h"
   6 #include "qemu/host-utils.h"
   7 #include "sysemu/arch_init.h"
   8 #include "sysemu/sysemu.h"
   9 #include "qemu/bitops.h"
  10 #include "qemu/crc32c.h"
  11 #include "exec/cpu_ldst.h"
  12 #include "arm_ldst.h"
  13 #include <zlib.h> /* For crc32 */
  14 #include "exec/semihost.h"
  15 #include "sysemu/kvm.h"
  16
  17 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */
  18
  19 #ifndef CONFIG_USER_ONLY
  20 static bool get_phys_addr(CPUARMState *env, target_ulong address,
  21                           int access_type, ARMMMUIdx mmu_idx,
  22                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
  23                           target_ulong *page_size, uint32_t *fsr,
  24                           ARMMMUFaultInfo *fi);
  25
  26 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
  27                                int access_type, ARMMMUIdx mmu_idx,
  28                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
  29                                target_ulong *page_size_ptr, uint32_t *fsr,
  30                                ARMMMUFaultInfo *fi);
  31
  32 /* Definitions for the PMCCNTR and PMCR registers */
  33 #define PMCRD   0x8
  34 #define PMCRC   0x4
  35 #define PMCRE   0x1
  36 #endif
  37
  38 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  39 {
  40     int nregs;
  41
  42     /* VFP data registers are always little-endian.  */
  43     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  44     if (reg < nregs) {
  45         stfq_le_p(buf, env->vfp.regs[reg]);
  46         return 8;
  47     }
  48     if (arm_feature(env, ARM_FEATURE_NEON)) {
  49         /* Aliases for Q regs.  */
  50         nregs += 16;
  51         if (reg < nregs) {
  52             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  53             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  54             return 16;
  55         }
  56     }
  57     switch (reg - nregs) {
  58     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  59     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  60     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  61     }
  62     return 0;
  63 }
  64
  65 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  66 {
  67     int nregs;
  68
  69     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  70     if (reg < nregs) {
  71         env->vfp.regs[reg] = ldfq_le_p(buf);
  72         return 8;
  73     }
  74     if (arm_feature(env, ARM_FEATURE_NEON)) {
  75         nregs += 16;
  76         if (reg < nregs) {
  77             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  78             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  79             return 16;
  80         }
  81     }
  82     switch (reg - nregs) {
  83     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  84     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  85     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  86     }
  87     return 0;
  88 }
  89
  90 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  91 {
  92     switch (reg) {
  93     case 0 ... 31:
  94         /* 128 bit FP register */
  95         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  96         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  97         return 16;
  98     case 32:
  99         /* FPSR */
 100         stl_p(buf, vfp_get_fpsr(env));
 101         return 4;
 102     case 33:
 103         /* FPCR */
 104         stl_p(buf, vfp_get_fpcr(env));
 105         return 4;
 106     default:
 107         return 0;
 108     }
 109 }
 110
 111 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 112 {
 113     switch (reg) {
 114     case 0 ... 31:
 115         /* 128 bit FP register */
 116         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 117         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 118         return 16;
 119     case 32:
 120         /* FPSR */
 121         vfp_set_fpsr(env, ldl_p(buf));
 122         return 4;
 123     case 33:
 124         /* FPCR */
 125         vfp_set_fpcr(env, ldl_p(buf));
 126         return 4;
 127     default:
 128         return 0;
 129     }
 130 }
 131
 132 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 133 {
 134     assert(ri->fieldoffset);
 135     if (cpreg_field_is_64bit(ri)) {
 136         return CPREG_FIELD64(env, ri);
 137     } else {
 138         return CPREG_FIELD32(env, ri);
 139     }
 140 }
 141
 142 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 143                       uint64_t value)
 144 {
 145     assert(ri->fieldoffset);
 146     if (cpreg_field_is_64bit(ri)) {
 147         CPREG_FIELD64(env, ri) = value;
 148     } else {
 149         CPREG_FIELD32(env, ri) = value;
 150     }
 151 }
 152
 153 static void *raw_ptr(CPUARMState *env, const ARMCPRegInfo *ri)
 154 {
 155     return (char *)env + ri->fieldoffset;
 156 }
 157
 158 uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 159 {
 160     /* Raw read of a coprocessor register (as needed for migration, etc). */
 161     if (ri->type & ARM_CP_CONST) {
 162         return ri->resetvalue;
 163     } else if (ri->raw_readfn) {
 164         return ri->raw_readfn(env, ri);
 165     } else if (ri->readfn) {
 166         return ri->readfn(env, ri);
 167     } else {
 168         return raw_read(env, ri);
 169     }
 170 }
 171
 172 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 173                              uint64_t v)
 174 {
 175     /* Raw write of a coprocessor register (as needed for migration, etc).
 176      * Note that constant registers are treated as write-ignored; the
 177      * caller should check for success by whether a readback gives the
 178      * value written.
 179      */
 180     if (ri->type & ARM_CP_CONST) {
 181         return;
 182     } else if (ri->raw_writefn) {
 183         ri->raw_writefn(env, ri, v);
 184     } else if (ri->writefn) {
 185         ri->writefn(env, ri, v);
 186     } else {
 187         raw_write(env, ri, v);
 188     }
 189 }
 190
 191 static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
 192 {
 193    /* Return true if the regdef would cause an assertion if you called
 194     * read_raw_cp_reg() or write_raw_cp_reg() on it (ie if it is a
 195     * program bug for it not to have the NO_RAW flag).
 196     * NB that returning false here doesn't necessarily mean that calling
 197     * read/write_raw_cp_reg() is safe, because we can't distinguish "has
 198     * read/write access functions which are safe for raw use" from "has
 199     * read/write access functions which have side effects but has forgotten
 200     * to provide raw access functions".
 201     * The tests here line up with the conditions in read/write_raw_cp_reg()
 202     * and assertions in raw_read()/raw_write().
 203     */
 204     if ((ri->type & ARM_CP_CONST) ||
 205         ri->fieldoffset ||
 206         ((ri->raw_writefn || ri->writefn) && (ri->raw_readfn || ri->readfn))) {
 207         return false;
 208     }
 209     return true;
 210 }
 211
 212 bool write_cpustate_to_list(ARMCPU *cpu)
 213 {
 214     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 215     int i;
 216     bool ok = true;
 217
 218     for (i = 0; i < cpu->cpreg_array_len; i++) {
 219         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 220         const ARMCPRegInfo *ri;
 221
 222         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 223         if (!ri) {
 224             ok = false;
 225             continue;
 226         }
 227         if (ri->type & ARM_CP_NO_RAW) {
 228             continue;
 229         }
 230         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 231     }
 232     return ok;
 233 }
 234
 235 bool write_list_to_cpustate(ARMCPU *cpu)
 236 {
 237     int i;
 238     bool ok = true;
 239
 240     for (i = 0; i < cpu->cpreg_array_len; i++) {
 241         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 242         uint64_t v = cpu->cpreg_values[i];
 243         const ARMCPRegInfo *ri;
 244
 245         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 246         if (!ri) {
 247             ok = false;
 248             continue;
 249         }
 250         if (ri->type & ARM_CP_NO_RAW) {
 251             continue;
 252         }
 253         /* Write value and confirm it reads back as written
 254          * (to catch read-only registers and partially read-only
 255          * registers where the incoming migration value doesn't match)
 256          */
 257         write_raw_cp_reg(&cpu->env, ri, v);
 258         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 259             ok = false;
 260         }
 261     }
 262     return ok;
 263 }
 264
 265 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 266 {
 267     ARMCPU *cpu = opaque;
 268     uint64_t regidx;
 269     const ARMCPRegInfo *ri;
 270
 271     regidx = *(uint32_t *)key;
 272     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 273
 274     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 275         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 276         /* The value array need not be initialized at this point */
 277         cpu->cpreg_array_len++;
 278     }
 279 }
 280
 281 static void count_cpreg(gpointer key, gpointer opaque)
 282 {
 283     ARMCPU *cpu = opaque;
 284     uint64_t regidx;
 285     const ARMCPRegInfo *ri;
 286
 287     regidx = *(uint32_t *)key;
 288     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 289
 290     if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) {
 291         cpu->cpreg_array_len++;
 292     }
 293 }
 294
 295 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 296 {
 297     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 298     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 299
 300     if (aidx > bidx) {
 301         return 1;
 302     }
 303     if (aidx < bidx) {
 304         return -1;
 305     }
 306     return 0;
 307 }
 308
 309 void init_cpreg_list(ARMCPU *cpu)
 310 {
 311     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 312      * Note that we require cpreg_tuples[] to be sorted by key ID.
 313      */
 314     GList *keys;
 315     int arraylen;
 316
 317     keys = g_hash_table_get_keys(cpu->cp_regs);
 318     keys = g_list_sort(keys, cpreg_key_compare);
 319
 320     cpu->cpreg_array_len = 0;
 321
 322     g_list_foreach(keys, count_cpreg, cpu);
 323
 324     arraylen = cpu->cpreg_array_len;
 325     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 326     cpu->cpreg_values = g_new(uint64_t, arraylen);
 327     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 328     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 329     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 330     cpu->cpreg_array_len = 0;
 331
 332     g_list_foreach(keys, add_cpreg_to_list, cpu);
 333
 334     assert(cpu->cpreg_array_len == arraylen);
 335
 336     g_list_free(keys);
 337 }
 338
 339 /*
 340  * Some registers are not accessible if EL3.NS=0 and EL3 is using AArch32 but
 341  * they are accessible when EL3 is using AArch64 regardless of EL3.NS.
 342  *
 343  * access_el3_aa32ns: Used to check AArch32 register views.
 344  * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views.
 345  */
 346 static CPAccessResult access_el3_aa32ns(CPUARMState *env,
 347                                         const ARMCPRegInfo *ri,
 348                                         bool isread)
 349 {
 350     bool secure = arm_is_secure_below_el3(env);
 351
 352     assert(!arm_el_is_aa64(env, 3));
 353     if (secure) {
 354         return CP_ACCESS_TRAP_UNCATEGORIZED;
 355     }
 356     return CP_ACCESS_OK;
 357 }
 358
 359 static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env,
 360                                                 const ARMCPRegInfo *ri,
 361                                                 bool isread)
 362 {
 363     if (!arm_el_is_aa64(env, 3)) {
 364         return access_el3_aa32ns(env, ri, isread);
 365     }
 366     return CP_ACCESS_OK;
 367 }
 368
 369 /* Some secure-only AArch32 registers trap to EL3 if used from
 370  * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts).
 371  * Note that an access from Secure EL1 can only happen if EL3 is AArch64.
 372  * We assume that the .access field is set to PL1_RW.
 373  */
 374 static CPAccessResult access_trap_aa32s_el1(CPUARMState *env,
 375                                             const ARMCPRegInfo *ri,
 376                                             bool isread)
 377 {
 378     if (arm_current_el(env) == 3) {
 379         return CP_ACCESS_OK;
 380     }
 381     if (arm_is_secure_below_el3(env)) {
 382         return CP_ACCESS_TRAP_EL3;
 383     }
 384     /* This will be EL1 NS and EL2 NS, which just UNDEF */
 385     return CP_ACCESS_TRAP_UNCATEGORIZED;
 386 }
 387
 388 /* Check for traps to "powerdown debug" registers, which are controlled
 389  * by MDCR.TDOSA
 390  */
 391 static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
 392                                    bool isread)
 393 {
 394     int el = arm_current_el(env);
 395
 396     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDOSA)
 397         && !arm_is_secure_below_el3(env)) {
 398         return CP_ACCESS_TRAP_EL2;
 399     }
 400     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDOSA)) {
 401         return CP_ACCESS_TRAP_EL3;
 402     }
 403     return CP_ACCESS_OK;
 404 }
 405
 406 /* Check for traps to "debug ROM" registers, which are controlled
 407  * by MDCR_EL2.TDRA for EL2 but by the more general MDCR_EL3.TDA for EL3.
 408  */
 409 static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
 410                                   bool isread)
 411 {
 412     int el = arm_current_el(env);
 413
 414     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDRA)
 415         && !arm_is_secure_below_el3(env)) {
 416         return CP_ACCESS_TRAP_EL2;
 417     }
 418     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
 419         return CP_ACCESS_TRAP_EL3;
 420     }
 421     return CP_ACCESS_OK;
 422 }
 423
 424 /* Check for traps to general debug registers, which are controlled
 425  * by MDCR_EL2.TDA for EL2 and MDCR_EL3.TDA for EL3.
 426  */
 427 static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
 428                                   bool isread)
 429 {
 430     int el = arm_current_el(env);
 431
 432     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TDA)
 433         && !arm_is_secure_below_el3(env)) {
 434         return CP_ACCESS_TRAP_EL2;
 435     }
 436     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TDA)) {
 437         return CP_ACCESS_TRAP_EL3;
 438     }
 439     return CP_ACCESS_OK;
 440 }
 441
 442 /* Check for traps to performance monitor registers, which are controlled
 443  * by MDCR_EL2.TPM for EL2 and MDCR_EL3.TPM for EL3.
 444  */
 445 static CPAccessResult access_tpm(CPUARMState *env, const ARMCPRegInfo *ri,
 446                                  bool isread)
 447 {
 448     int el = arm_current_el(env);
 449
 450     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
 451         && !arm_is_secure_below_el3(env)) {
 452         return CP_ACCESS_TRAP_EL2;
 453     }
 454     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
 455         return CP_ACCESS_TRAP_EL3;
 456     }
 457     return CP_ACCESS_OK;
 458 }
 459
 460 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 461 {
 462     ARMCPU *cpu = arm_env_get_cpu(env);
 463
 464     raw_write(env, ri, value);
 465     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 466 }
 467
 468 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 469 {
 470     ARMCPU *cpu = arm_env_get_cpu(env);
 471
 472     if (raw_read(env, ri) != value) {
 473         /* Unlike real hardware the qemu TLB uses virtual addresses,
 474          * not modified virtual addresses, so this causes a TLB flush.
 475          */
 476         tlb_flush(CPU(cpu), 1);
 477         raw_write(env, ri, value);
 478     }
 479 }
 480
 481 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 482                              uint64_t value)
 483 {
 484     ARMCPU *cpu = arm_env_get_cpu(env);
 485
 486     if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_MPU)
 487         && !extended_addresses_enabled(env)) {
 488         /* For VMSA (when not using the LPAE long descriptor page table
 489          * format) this register includes the ASID, so do a TLB flush.
 490          * For PMSA it is purely a process ID and no action is needed.
 491          */
 492         tlb_flush(CPU(cpu), 1);
 493     }
 494     raw_write(env, ri, value);
 495 }
 496
 497 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 498                           uint64_t value)
 499 {
 500     /* Invalidate all (TLBIALL) */
 501     ARMCPU *cpu = arm_env_get_cpu(env);
 502
 503     tlb_flush(CPU(cpu), 1);
 504 }
 505
 506 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 507                           uint64_t value)
 508 {
 509     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 510     ARMCPU *cpu = arm_env_get_cpu(env);
 511
 512     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 513 }
 514
 515 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 516                            uint64_t value)
 517 {
 518     /* Invalidate by ASID (TLBIASID) */
 519     ARMCPU *cpu = arm_env_get_cpu(env);
 520
 521     tlb_flush(CPU(cpu), value == 0);
 522 }
 523
 524 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 525                            uint64_t value)
 526 {
 527     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 528     ARMCPU *cpu = arm_env_get_cpu(env);
 529
 530     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 531 }
 532
 533 /* IS variants of TLB operations must affect all cores */
 534 static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 535                              uint64_t value)
 536 {
 537     CPUState *other_cs;
 538
 539     CPU_FOREACH(other_cs) {
 540         tlb_flush(other_cs, 1);
 541     }
 542 }
 543
 544 static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 545                              uint64_t value)
 546 {
 547     CPUState *other_cs;
 548
 549     CPU_FOREACH(other_cs) {
 550         tlb_flush(other_cs, value == 0);
 551     }
 552 }
 553
 554 static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 555                              uint64_t value)
 556 {
 557     CPUState *other_cs;
 558
 559     CPU_FOREACH(other_cs) {
 560         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 561     }
 562 }
 563
 564 static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
 565                              uint64_t value)
 566 {
 567     CPUState *other_cs;
 568
 569     CPU_FOREACH(other_cs) {
 570         tlb_flush_page(other_cs, value & TARGET_PAGE_MASK);
 571     }
 572 }
 573
 574 static const ARMCPRegInfo cp_reginfo[] = {
 575     /* Define the secure and non-secure FCSE identifier CP registers
 576      * separately because there is no secure bank in V8 (no _EL3).  This allows
 577      * the secure register to be properly reset and migrated. There is also no
 578      * v8 EL1 version of the register so the non-secure instance stands alone.
 579      */
 580     { .name = "FCSEIDR(NS)",
 581       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 582       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 583       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_ns),
 584       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 585     { .name = "FCSEIDR(S)",
 586       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 0,
 587       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 588       .fieldoffset = offsetof(CPUARMState, cp15.fcseidr_s),
 589       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 590     /* Define the secure and non-secure context identifier CP registers
 591      * separately because there is no secure bank in V8 (no _EL3).  This allows
 592      * the secure register to be properly reset and migrated.  In the
 593      * non-secure case, the 32-bit register will have reset and migration
 594      * disabled during registration as it is handled by the 64-bit instance.
 595      */
 596     { .name = "CONTEXTIDR_EL1", .state = ARM_CP_STATE_BOTH,
 597       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 598       .access = PL1_RW, .secure = ARM_CP_SECSTATE_NS,
 599       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el[1]),
 600       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 601     { .name = "CONTEXTIDR(S)", .state = ARM_CP_STATE_AA32,
 602       .cp = 15, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 603       .access = PL1_RW, .secure = ARM_CP_SECSTATE_S,
 604       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_s),
 605       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 606     REGINFO_SENTINEL
 607 };
 608
 609 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 610     /* NB: Some of these registers exist in v8 but with more precise
 611      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 612      */
 613     /* MMU Domain access control / MPU write buffer control */
 614     { .name = "DACR",
 615       .cp = 15, .opc1 = CP_ANY, .crn = 3, .crm = CP_ANY, .opc2 = CP_ANY,
 616       .access = PL1_RW, .resetvalue = 0,
 617       .writefn = dacr_write, .raw_writefn = raw_write,
 618       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
 619                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
 620     /* ARMv7 allocates a range of implementation defined TLB LOCKDOWN regs.
 621      * For v6 and v5, these mappings are overly broad.
 622      */
 623     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 0,
 624       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 625     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 1,
 626       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 627     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 4,
 628       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 629     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = 8,
 630       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 631     /* Cache maintenance ops; some of this space may be overridden later. */
 632     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 633       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 634       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 635     REGINFO_SENTINEL
 636 };
 637
 638 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 639     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 640      * over-broad.
 641      */
 642     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 643       .access = PL1_W, .type = ARM_CP_WFI },
 644     REGINFO_SENTINEL
 645 };
 646
 647 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 648     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 649      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 650      */
 651     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 652       .access = PL1_W, .type = ARM_CP_WFI },
 653     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 654      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 655      * OMAPCP will override this space.
 656      */
 657     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 658       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 659       .resetvalue = 0 },
 660     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 661       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 662       .resetvalue = 0 },
 663     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 664     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 665       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
 666       .resetvalue = 0 },
 667     /* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
 668      * implementing it as RAZ means the "debug architecture version" bits
 669      * will read as a reserved value, which should cause Linux to not try
 670      * to use the debug hardware.
 671      */
 672     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 673       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 674     /* MMU TLB control. Note that the wildcarding means we cover not just
 675      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 676      */
 677     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 678       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 679       .type = ARM_CP_NO_RAW },
 680     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 681       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 682       .type = ARM_CP_NO_RAW },
 683     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 684       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 685       .type = ARM_CP_NO_RAW },
 686     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 687       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 688       .type = ARM_CP_NO_RAW },
 689     { .name = "PRRR", .cp = 15, .crn = 10, .crm = 2,
 690       .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP },
 691     { .name = "NMRR", .cp = 15, .crn = 10, .crm = 2,
 692       .opc1 = 0, .opc2 = 1, .access = PL1_RW, .type = ARM_CP_NOP },
 693     REGINFO_SENTINEL
 694 };
 695
 696 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 697                         uint64_t value)
 698 {
 699     uint32_t mask = 0;
 700
 701     /* In ARMv8 most bits of CPACR_EL1 are RES0. */
 702     if (!arm_feature(env, ARM_FEATURE_V8)) {
 703         /* ARMv7 defines bits for unimplemented coprocessors as RAZ/WI.
 704          * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP.
 705          * TRCDIS [28] is RAZ/WI since we do not implement a trace macrocell.
 706          */
 707         if (arm_feature(env, ARM_FEATURE_VFP)) {
 708             /* VFP coprocessor: cp10 & cp11 [23:20] */
 709             mask |= (1 << 31) | (1 << 30) | (0xf << 20);
 710
 711             if (!arm_feature(env, ARM_FEATURE_NEON)) {
 712                 /* ASEDIS [31] bit is RAO/WI */
 713                 value |= (1 << 31);
 714             }
 715
 716             /* VFPv3 and upwards with NEON implement 32 double precision
 717              * registers (D0-D31).
 718              */
 719             if (!arm_feature(env, ARM_FEATURE_NEON) ||
 720                     !arm_feature(env, ARM_FEATURE_VFP3)) {
 721                 /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */
 722                 value |= (1 << 30);
 723             }
 724         }
 725         value &= mask;
 726     }
 727     env->cp15.cpacr_el1 = value;
 728 }
 729
 730 static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 731                                    bool isread)
 732 {
 733     if (arm_feature(env, ARM_FEATURE_V8)) {
 734         /* Check if CPACR accesses are to be trapped to EL2 */
 735         if (arm_current_el(env) == 1 &&
 736             (env->cp15.cptr_el[2] & CPTR_TCPAC) && !arm_is_secure(env)) {
 737             return CP_ACCESS_TRAP_EL2;
 738         /* Check if CPACR accesses are to be trapped to EL3 */
 739         } else if (arm_current_el(env) < 3 &&
 740                    (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 741             return CP_ACCESS_TRAP_EL3;
 742         }
 743     }
 744
 745     return CP_ACCESS_OK;
 746 }
 747
 748 static CPAccessResult cptr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 749                                   bool isread)
 750 {
 751     /* Check if CPTR accesses are set to trap to EL3 */
 752     if (arm_current_el(env) == 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC)) {
 753         return CP_ACCESS_TRAP_EL3;
 754     }
 755
 756     return CP_ACCESS_OK;
 757 }
 758
 759 static const ARMCPRegInfo v6_cp_reginfo[] = {
 760     /* prefetch by MVA in v6, NOP in v7 */
 761     { .name = "MVA_prefetch",
 762       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 763       .access = PL1_W, .type = ARM_CP_NOP },
 764     /* We need to break the TB after ISB to execute self-modifying code
 765      * correctly and also to take any pending interrupts immediately.
 766      * So use arm_cp_write_ignore() function instead of ARM_CP_NOP flag.
 767      */
 768     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 769       .access = PL0_W, .type = ARM_CP_NO_RAW, .writefn = arm_cp_write_ignore },
 770     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 771       .access = PL0_W, .type = ARM_CP_NOP },
 772     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 773       .access = PL0_W, .type = ARM_CP_NOP },
 774     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 775       .access = PL1_RW,
 776       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
 777                              offsetof(CPUARMState, cp15.ifar_ns) },
 778       .resetvalue = 0, },
 779     /* Watchpoint Fault Address Register : should actually only be present
 780      * for 1136, 1176, 11MPCore.
 781      */
 782     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 783       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 784     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 785       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
 786       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
 787       .resetvalue = 0, .writefn = cpacr_write },
 788     REGINFO_SENTINEL
 789 };
 790
 791 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
 792                                    bool isread)
 793 {
 794     /* Performance monitor registers user accessibility is controlled
 795      * by PMUSERENR. MDCR_EL2.TPM and MDCR_EL3.TPM allow configurable
 796      * trapping to EL2 or EL3 for other accesses.
 797      */
 798     int el = arm_current_el(env);
 799
 800     if (el == 0 && !env->cp15.c9_pmuserenr) {
 801         return CP_ACCESS_TRAP;
 802     }
 803     if (el < 2 && (env->cp15.mdcr_el2 & MDCR_TPM)
 804         && !arm_is_secure_below_el3(env)) {
 805         return CP_ACCESS_TRAP_EL2;
 806     }
 807     if (el < 3 && (env->cp15.mdcr_el3 & MDCR_TPM)) {
 808         return CP_ACCESS_TRAP_EL3;
 809     }
 810
 811     return CP_ACCESS_OK;
 812 }
 813
 814 #ifndef CONFIG_USER_ONLY
 815
 816 static inline bool arm_ccnt_enabled(CPUARMState *env)
 817 {
 818     /* This does not support checking PMCCFILTR_EL0 register */
 819
 820     if (!(env->cp15.c9_pmcr & PMCRE)) {
 821         return false;
 822     }
 823
 824     return true;
 825 }
 826
 827 void pmccntr_sync(CPUARMState *env)
 828 {
 829     uint64_t temp_ticks;
 830
 831     temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 832                           ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 833
 834     if (env->cp15.c9_pmcr & PMCRD) {
 835         /* Increment once every 64 processor clock cycles */
 836         temp_ticks /= 64;
 837     }
 838
 839     if (arm_ccnt_enabled(env)) {
 840         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 841     }
 842 }
 843
 844 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 845                        uint64_t value)
 846 {
 847     pmccntr_sync(env);
 848
 849     if (value & PMCRC) {
 850         /* The counter has been reset */
 851         env->cp15.c15_ccnt = 0;
 852     }
 853
 854     /* only the DP, X, D and E bits are writable */
 855     env->cp15.c9_pmcr &= ~0x39;
 856     env->cp15.c9_pmcr |= (value & 0x39);
 857
 858     pmccntr_sync(env);
 859 }
 860
 861 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 862 {
 863     uint64_t total_ticks;
 864
 865     if (!arm_ccnt_enabled(env)) {
 866         /* Counter is disabled, do not change value */
 867         return env->cp15.c15_ccnt;
 868     }
 869
 870     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 871                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 872
 873     if (env->cp15.c9_pmcr & PMCRD) {
 874         /* Increment once every 64 processor clock cycles */
 875         total_ticks /= 64;
 876     }
 877     return total_ticks - env->cp15.c15_ccnt;
 878 }
 879
 880 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 881                         uint64_t value)
 882 {
 883     uint64_t total_ticks;
 884
 885     if (!arm_ccnt_enabled(env)) {
 886         /* Counter is disabled, set the absolute value */
 887         env->cp15.c15_ccnt = value;
 888         return;
 889     }
 890
 891     total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
 892                            ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
 893
 894     if (env->cp15.c9_pmcr & PMCRD) {
 895         /* Increment once every 64 processor clock cycles */
 896         total_ticks /= 64;
 897     }
 898     env->cp15.c15_ccnt = total_ticks - value;
 899 }
 900
 901 static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
 902                             uint64_t value)
 903 {
 904     uint64_t cur_val = pmccntr_read(env, NULL);
 905
 906     pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
 907 }
 908
 909 #else /* CONFIG_USER_ONLY */
 910
 911 void pmccntr_sync(CPUARMState *env)
 912 {
 913 }
 914
 915 #endif
 916
 917 static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 918                             uint64_t value)
 919 {
 920     pmccntr_sync(env);
 921     env->cp15.pmccfiltr_el0 = value & 0x7E000000;
 922     pmccntr_sync(env);
 923 }
 924
 925 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 926                             uint64_t value)
 927 {
 928     value &= (1 << 31);
 929     env->cp15.c9_pmcnten |= value;
 930 }
 931
 932 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 933                              uint64_t value)
 934 {
 935     value &= (1 << 31);
 936     env->cp15.c9_pmcnten &= ~value;
 937 }
 938
 939 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 940                          uint64_t value)
 941 {
 942     env->cp15.c9_pmovsr &= ~value;
 943 }
 944
 945 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 946                              uint64_t value)
 947 {
 948     env->cp15.c9_pmxevtyper = value & 0xff;
 949 }
 950
 951 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 952                             uint64_t value)
 953 {
 954     env->cp15.c9_pmuserenr = value & 1;
 955 }
 956
 957 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 958                              uint64_t value)
 959 {
 960     /* We have no event counters so only the C bit can be changed */
 961     value &= (1 << 31);
 962     env->cp15.c9_pminten |= value;
 963 }
 964
 965 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 966                              uint64_t value)
 967 {
 968     value &= (1 << 31);
 969     env->cp15.c9_pminten &= ~value;
 970 }
 971
 972 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 973                        uint64_t value)
 974 {
 975     /* Note that even though the AArch64 view of this register has bits
 976      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 977      * architectural requirements for bits which are RES0 only in some
 978      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 979      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 980      */
 981     raw_write(env, ri, value & ~0x1FULL);
 982 }
 983
 984 static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 985 {
 986     /* We only mask off bits that are RES0 both for AArch64 and AArch32.
 987      * For bits that vary between AArch32/64, code needs to check the
 988      * current execution mode before directly using the feature bit.
 989      */
 990     uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
 991
 992     if (!arm_feature(env, ARM_FEATURE_EL2)) {
 993         valid_mask &= ~SCR_HCE;
 994
 995         /* On ARMv7, SMD (or SCD as it is called in v7) is only
 996          * supported if EL2 exists. The bit is UNK/SBZP when
 997          * EL2 is unavailable. In QEMU ARMv7, we force it to always zero
 998          * when EL2 is unavailable.
 999          * On ARMv8, this bit is always available.
1000          */
1001         if (arm_feature(env, ARM_FEATURE_V7) &&
1002             !arm_feature(env, ARM_FEATURE_V8)) {
1003             valid_mask &= ~SCR_SMD;
1004         }
1005     }
1006
1007     /* Clear all-context RES0 bits.  */
1008     value &= valid_mask;
1009     raw_write(env, ri, value);
1010 }
1011
1012 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1013 {
1014     ARMCPU *cpu = arm_env_get_cpu(env);
1015
1016     /* Acquire the CSSELR index from the bank corresponding to the CCSIDR
1017      * bank
1018      */
1019     uint32_t index = A32_BANKED_REG_GET(env, csselr,
1020                                         ri->secure & ARM_CP_SECSTATE_S);
1021
1022     return cpu->ccsidr[index];
1023 }
1024
1025 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1026                          uint64_t value)
1027 {
1028     raw_write(env, ri, value & 0xf);
1029 }
1030
1031 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1032 {
1033     CPUState *cs = ENV_GET_CPU(env);
1034     uint64_t ret = 0;
1035
1036     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
1037         ret |= CPSR_I;
1038     }
1039     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
1040         ret |= CPSR_F;
1041     }
1042     /* External aborts are not possible in QEMU so A bit is always clear */
1043     return ret;
1044 }
1045
1046 static const ARMCPRegInfo v7_cp_reginfo[] = {
1047     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
1048     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
1049       .access = PL1_W, .type = ARM_CP_NOP },
1050     /* Performance monitors are implementation defined in v7,
1051      * but with an ARM recommended set of registers, which we
1052      * follow (although we don't actually implement any counters)
1053      *
1054      * Performance registers fall into three categories:
1055      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
1056      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
1057      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
1058      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
1059      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
1060      */
1061     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
1062       .access = PL0_RW, .type = ARM_CP_ALIAS,
1063       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1064       .writefn = pmcntenset_write,
1065       .accessfn = pmreg_access,
1066       .raw_writefn = raw_write },
1067     { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
1068       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
1069       .access = PL0_RW, .accessfn = pmreg_access,
1070       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
1071       .writefn = pmcntenset_write, .raw_writefn = raw_write },
1072     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
1073       .access = PL0_RW,
1074       .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
1075       .accessfn = pmreg_access,
1076       .writefn = pmcntenclr_write,
1077       .type = ARM_CP_ALIAS },
1078     { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
1079       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
1080       .access = PL0_RW, .accessfn = pmreg_access,
1081       .type = ARM_CP_ALIAS,
1082       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
1083       .writefn = pmcntenclr_write },
1084     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
1085       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1086       .accessfn = pmreg_access,
1087       .writefn = pmovsr_write,
1088       .raw_writefn = raw_write },
1089     { .name = "PMOVSCLR_EL0", .state = ARM_CP_STATE_AA64,
1090       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 3,
1091       .access = PL0_RW, .accessfn = pmreg_access,
1092       .type = ARM_CP_ALIAS,
1093       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
1094       .writefn = pmovsr_write,
1095       .raw_writefn = raw_write },
1096     /* Unimplemented so WI. */
1097     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
1098       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
1099     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
1100      * We choose to RAZ/WI.
1101      */
1102     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
1103       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1104       .accessfn = pmreg_access },
1105 #ifndef CONFIG_USER_ONLY
1106     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
1107       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
1108       .readfn = pmccntr_read, .writefn = pmccntr_write32,
1109       .accessfn = pmreg_access },
1110     { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
1111       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
1112       .access = PL0_RW, .accessfn = pmreg_access,
1113       .type = ARM_CP_IO,
1114       .readfn = pmccntr_read, .writefn = pmccntr_write, },
1115 #endif
1116     { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
1117       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
1118       .writefn = pmccfiltr_write,
1119       .access = PL0_RW, .accessfn = pmreg_access,
1120       .type = ARM_CP_IO,
1121       .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
1122       .resetvalue = 0, },
1123     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
1124       .access = PL0_RW,
1125       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
1126       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
1127       .raw_writefn = raw_write },
1128     /* Unimplemented, RAZ/WI. */
1129     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
1130       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
1131       .accessfn = pmreg_access },
1132     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
1133       .access = PL0_R | PL1_RW, .accessfn = access_tpm,
1134       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1135       .resetvalue = 0,
1136       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1137     { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
1138       .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
1139       .access = PL0_R | PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1140       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
1141       .resetvalue = 0,
1142       .writefn = pmuserenr_write, .raw_writefn = raw_write },
1143     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
1144       .access = PL1_RW, .accessfn = access_tpm,
1145       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1146       .resetvalue = 0,
1147       .writefn = pmintenset_write, .raw_writefn = raw_write },
1148     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
1149       .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1150       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1151       .writefn = pmintenclr_write, },
1152     { .name = "PMINTENCLR_EL1", .state = ARM_CP_STATE_AA64,
1153       .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 2,
1154       .access = PL1_RW, .accessfn = access_tpm, .type = ARM_CP_ALIAS,
1155       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
1156       .writefn = pmintenclr_write },
1157     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
1158       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
1159       .access = PL1_RW, .writefn = vbar_write,
1160       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.vbar_s),
1161                              offsetof(CPUARMState, cp15.vbar_ns) },
1162       .resetvalue = 0 },
1163     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
1164       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
1165       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_RAW },
1166     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
1167       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
1168       .access = PL1_RW, .writefn = csselr_write, .resetvalue = 0,
1169       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.csselr_s),
1170                              offsetof(CPUARMState, cp15.csselr_ns) } },
1171     /* Auxiliary ID register: this actually has an IMPDEF value but for now
1172      * just RAZ for all cores:
1173      */
1174     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
1175       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
1176       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
1177     /* Auxiliary fault status registers: these also are IMPDEF, and we
1178      * choose to RAZ/WI for all cores.
1179      */
1180     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
1181       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
1182       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1183     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
1184       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
1185       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1186     /* MAIR can just read-as-written because we don't implement caches
1187      * and so don't need to care about memory attributes.
1188      */
1189     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
1190       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
1191       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[1]),
1192       .resetvalue = 0 },
1193     { .name = "MAIR_EL3", .state = ARM_CP_STATE_AA64,
1194       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 2, .opc2 = 0,
1195       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[3]),
1196       .resetvalue = 0 },
1197     /* For non-long-descriptor page tables these are PRRR and NMRR;
1198      * regardless they still act as reads-as-written for QEMU.
1199      */
1200      /* MAIR0/1 are defined separately from their 64-bit counterpart which
1201       * allows them to assign the correct fieldoffset based on the endianness
1202       * handled in the field definitions.
1203       */
1204     { .name = "MAIR0", .state = ARM_CP_STATE_AA32,
1205       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
1206       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair0_s),
1207                              offsetof(CPUARMState, cp15.mair0_ns) },
1208       .resetfn = arm_cp_reset_ignore },
1209     { .name = "MAIR1", .state = ARM_CP_STATE_AA32,
1210       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
1211       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.mair1_s),
1212                              offsetof(CPUARMState, cp15.mair1_ns) },
1213       .resetfn = arm_cp_reset_ignore },
1214     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
1215       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
1216       .type = ARM_CP_NO_RAW, .access = PL1_R, .readfn = isr_read },
1217     /* 32 bit ITLB invalidates */
1218     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1219       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1220     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1221       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1222     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1223       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1224     /* 32 bit DTLB invalidates */
1225     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1226       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1227     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1228       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1229     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1230       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1231     /* 32 bit TLB invalidates */
1232     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1233       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_write },
1234     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1235       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
1236     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1237       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiasid_write },
1238     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1239       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
1240     REGINFO_SENTINEL
1241 };
1242
1243 static const ARMCPRegInfo v7mp_cp_reginfo[] = {
1244     /* 32 bit TLB invalidates, Inner Shareable */
1245     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1246       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbiall_is_write },
1247     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1248       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
1249     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1250       .type = ARM_CP_NO_RAW, .access = PL1_W,
1251       .writefn = tlbiasid_is_write },
1252     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1253       .type = ARM_CP_NO_RAW, .access = PL1_W,
1254       .writefn = tlbimvaa_is_write },
1255     REGINFO_SENTINEL
1256 };
1257
1258 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1259                         uint64_t value)
1260 {
1261     value &= 1;
1262     env->teecr = value;
1263 }
1264
1265 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri,
1266                                     bool isread)
1267 {
1268     if (arm_current_el(env) == 0 && (env->teecr & 1)) {
1269         return CP_ACCESS_TRAP;
1270     }
1271     return CP_ACCESS_OK;
1272 }
1273
1274 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
1275     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
1276       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
1277       .resetvalue = 0,
1278       .writefn = teecr_write },
1279     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
1280       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
1281       .accessfn = teehbr_access, .resetvalue = 0 },
1282     REGINFO_SENTINEL
1283 };
1284
1285 static const ARMCPRegInfo v6k_cp_reginfo[] = {
1286     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
1287       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
1288       .access = PL0_RW,
1289       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[0]), .resetvalue = 0 },
1290     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
1291       .access = PL0_RW,
1292       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrurw_s),
1293                              offsetoflow32(CPUARMState, cp15.tpidrurw_ns) },
1294       .resetfn = arm_cp_reset_ignore },
1295     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
1296       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
1297       .access = PL0_R|PL1_W,
1298       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el[0]),
1299       .resetvalue = 0},
1300     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
1301       .access = PL0_R|PL1_W,
1302       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidruro_s),
1303                              offsetoflow32(CPUARMState, cp15.tpidruro_ns) },
1304       .resetfn = arm_cp_reset_ignore },
1305     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_AA64,
1306       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
1307       .access = PL1_RW,
1308       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[1]), .resetvalue = 0 },
1309     { .name = "TPIDRPRW", .opc1 = 0, .cp = 15, .crn = 13, .crm = 0, .opc2 = 4,
1310       .access = PL1_RW,
1311       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tpidrprw_s),
1312                              offsetoflow32(CPUARMState, cp15.tpidrprw_ns) },
1313       .resetvalue = 0 },
1314     REGINFO_SENTINEL
1315 };
1316
1317 #ifndef CONFIG_USER_ONLY
1318
1319 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri,
1320                                        bool isread)
1321 {
1322     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero.
1323      * Writable only at the highest implemented exception level.
1324      */
1325     int el = arm_current_el(env);
1326
1327     switch (el) {
1328     case 0:
1329         if (!extract32(env->cp15.c14_cntkctl, 0, 2)) {
1330             return CP_ACCESS_TRAP;
1331         }
1332         break;
1333     case 1:
1334         if (!isread && ri->state == ARM_CP_STATE_AA32 &&
1335             arm_is_secure_below_el3(env)) {
1336             /* Accesses from 32-bit Secure EL1 UNDEF (*not* trap to EL3!) */
1337             return CP_ACCESS_TRAP_UNCATEGORIZED;
1338         }
1339         break;
1340     case 2:
1341     case 3:
1342         break;
1343     }
1344
1345     if (!isread && el < arm_highest_el(env)) {
1346         return CP_ACCESS_TRAP_UNCATEGORIZED;
1347     }
1348
1349     return CP_ACCESS_OK;
1350 }
1351
1352 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx,
1353                                         bool isread)
1354 {
1355     unsigned int cur_el = arm_current_el(env);
1356     bool secure = arm_is_secure(env);
1357
1358     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
1359     if (cur_el == 0 &&
1360         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
1361         return CP_ACCESS_TRAP;
1362     }
1363
1364     if (arm_feature(env, ARM_FEATURE_EL2) &&
1365         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1366         !extract32(env->cp15.cnthctl_el2, 0, 1)) {
1367         return CP_ACCESS_TRAP_EL2;
1368     }
1369     return CP_ACCESS_OK;
1370 }
1371
1372 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx,
1373                                       bool isread)
1374 {
1375     unsigned int cur_el = arm_current_el(env);
1376     bool secure = arm_is_secure(env);
1377
1378     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
1379      * EL0[PV]TEN is zero.
1380      */
1381     if (cur_el == 0 &&
1382         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
1383         return CP_ACCESS_TRAP;
1384     }
1385
1386     if (arm_feature(env, ARM_FEATURE_EL2) &&
1387         timeridx == GTIMER_PHYS && !secure && cur_el < 2 &&
1388         !extract32(env->cp15.cnthctl_el2, 1, 1)) {
1389         return CP_ACCESS_TRAP_EL2;
1390     }
1391     return CP_ACCESS_OK;
1392 }
1393
1394 static CPAccessResult gt_pct_access(CPUARMState *env,
1395                                     const ARMCPRegInfo *ri,
1396                                     bool isread)
1397 {
1398     return gt_counter_access(env, GTIMER_PHYS, isread);
1399 }
1400
1401 static CPAccessResult gt_vct_access(CPUARMState *env,
1402                                     const ARMCPRegInfo *ri,
1403                                     bool isread)
1404 {
1405     return gt_counter_access(env, GTIMER_VIRT, isread);
1406 }
1407
1408 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1409                                        bool isread)
1410 {
1411     return gt_timer_access(env, GTIMER_PHYS, isread);
1412 }
1413
1414 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri,
1415                                        bool isread)
1416 {
1417     return gt_timer_access(env, GTIMER_VIRT, isread);
1418 }
1419
1420 static CPAccessResult gt_stimer_access(CPUARMState *env,
1421                                        const ARMCPRegInfo *ri,
1422                                        bool isread)
1423 {
1424     /* The AArch64 register view of the secure physical timer is
1425      * always accessible from EL3, and configurably accessible from
1426      * Secure EL1.
1427      */
1428     switch (arm_current_el(env)) {
1429     case 1:
1430         if (!arm_is_secure(env)) {
1431             return CP_ACCESS_TRAP;
1432         }
1433         if (!(env->cp15.scr_el3 & SCR_ST)) {
1434             return CP_ACCESS_TRAP_EL3;
1435         }
1436         return CP_ACCESS_OK;
1437     case 0:
1438     case 2:
1439         return CP_ACCESS_TRAP;
1440     case 3:
1441         return CP_ACCESS_OK;
1442     default:
1443         g_assert_not_reached();
1444     }
1445 }
1446
1447 static uint64_t gt_get_countervalue(CPUARMState *env)
1448 {
1449     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
1450 }
1451
1452 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
1453 {
1454     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
1455
1456     if (gt->ctl & 1) {
1457         /* Timer enabled: calculate and set current ISTATUS, irq, and
1458          * reset timer to when ISTATUS next has to change
1459          */
1460         uint64_t offset = timeridx == GTIMER_VIRT ?
1461                                       cpu->env.cp15.cntvoff_el2 : 0;
1462         uint64_t count = gt_get_countervalue(&cpu->env);
1463         /* Note that this must be unsigned 64 bit arithmetic: */
1464         int istatus = count - offset >= gt->cval;
1465         uint64_t nexttick;
1466
1467         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
1468         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1469                      (istatus && !(gt->ctl & 2)));
1470         if (istatus) {
1471             /* Next transition is when count rolls back over to zero */
1472             nexttick = UINT64_MAX;
1473         } else {
1474             /* Next transition is when we hit cval */
1475             nexttick = gt->cval + offset;
1476         }
1477         /* Note that the desired next expiry time might be beyond the
1478          * signed-64-bit range of a QEMUTimer -- in this case we just
1479          * set the timer for as far in the future as possible. When the
1480          * timer expires we will reset the timer for any remaining period.
1481          */
1482         if (nexttick > INT64_MAX / GTIMER_SCALE) {
1483             nexttick = INT64_MAX / GTIMER_SCALE;
1484         }
1485         timer_mod(cpu->gt_timer[timeridx], nexttick);
1486     } else {
1487         /* Timer disabled: ISTATUS and timer output always clear */
1488         gt->ctl &= ~4;
1489         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
1490         timer_del(cpu->gt_timer[timeridx]);
1491     }
1492 }
1493
1494 static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
1495                            int timeridx)
1496 {
1497     ARMCPU *cpu = arm_env_get_cpu(env);
1498
1499     timer_del(cpu->gt_timer[timeridx]);
1500 }
1501
1502 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1503 {
1504     return gt_get_countervalue(env);
1505 }
1506
1507 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
1508 {
1509     return gt_get_countervalue(env) - env->cp15.cntvoff_el2;
1510 }
1511
1512 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1513                           int timeridx,
1514                           uint64_t value)
1515 {
1516     env->cp15.c14_timer[timeridx].cval = value;
1517     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1518 }
1519
1520 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
1521                              int timeridx)
1522 {
1523     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1524
1525     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
1526                       (gt_get_countervalue(env) - offset));
1527 }
1528
1529 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1530                           int timeridx,
1531                           uint64_t value)
1532 {
1533     uint64_t offset = timeridx == GTIMER_VIRT ? env->cp15.cntvoff_el2 : 0;
1534
1535     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
1536                                          sextract64(value, 0, 32);
1537     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1538 }
1539
1540 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1541                          int timeridx,
1542                          uint64_t value)
1543 {
1544     ARMCPU *cpu = arm_env_get_cpu(env);
1545     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1546
1547     env->cp15.c14_timer[timeridx].ctl = deposit64(oldval, 0, 2, value);
1548     if ((oldval ^ value) & 1) {
1549         /* Enable toggled */
1550         gt_recalc_timer(cpu, timeridx);
1551     } else if ((oldval ^ value) & 2) {
1552         /* IMASK toggled: don't need to recalculate,
1553          * just set the interrupt line based on ISTATUS
1554          */
1555         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1556                      (oldval & 4) && !(value & 2));
1557     }
1558 }
1559
1560 static void gt_phys_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1561 {
1562     gt_timer_reset(env, ri, GTIMER_PHYS);
1563 }
1564
1565 static void gt_phys_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1566                                uint64_t value)
1567 {
1568     gt_cval_write(env, ri, GTIMER_PHYS, value);
1569 }
1570
1571 static uint64_t gt_phys_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1572 {
1573     return gt_tval_read(env, ri, GTIMER_PHYS);
1574 }
1575
1576 static void gt_phys_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1577                                uint64_t value)
1578 {
1579     gt_tval_write(env, ri, GTIMER_PHYS, value);
1580 }
1581
1582 static void gt_phys_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1583                               uint64_t value)
1584 {
1585     gt_ctl_write(env, ri, GTIMER_PHYS, value);
1586 }
1587
1588 static void gt_virt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1589 {
1590     gt_timer_reset(env, ri, GTIMER_VIRT);
1591 }
1592
1593 static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1594                                uint64_t value)
1595 {
1596     gt_cval_write(env, ri, GTIMER_VIRT, value);
1597 }
1598
1599 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1600 {
1601     return gt_tval_read(env, ri, GTIMER_VIRT);
1602 }
1603
1604 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1605                                uint64_t value)
1606 {
1607     gt_tval_write(env, ri, GTIMER_VIRT, value);
1608 }
1609
1610 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1611                               uint64_t value)
1612 {
1613     gt_ctl_write(env, ri, GTIMER_VIRT, value);
1614 }
1615
1616 static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri,
1617                               uint64_t value)
1618 {
1619     ARMCPU *cpu = arm_env_get_cpu(env);
1620
1621     raw_write(env, ri, value);
1622     gt_recalc_timer(cpu, GTIMER_VIRT);
1623 }
1624
1625 static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1626 {
1627     gt_timer_reset(env, ri, GTIMER_HYP);
1628 }
1629
1630 static void gt_hyp_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1631                               uint64_t value)
1632 {
1633     gt_cval_write(env, ri, GTIMER_HYP, value);
1634 }
1635
1636 static uint64_t gt_hyp_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1637 {
1638     return gt_tval_read(env, ri, GTIMER_HYP);
1639 }
1640
1641 static void gt_hyp_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1642                               uint64_t value)
1643 {
1644     gt_tval_write(env, ri, GTIMER_HYP, value);
1645 }
1646
1647 static void gt_hyp_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1648                               uint64_t value)
1649 {
1650     gt_ctl_write(env, ri, GTIMER_HYP, value);
1651 }
1652
1653 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1654 {
1655     gt_timer_reset(env, ri, GTIMER_SEC);
1656 }
1657
1658 static void gt_sec_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1659                               uint64_t value)
1660 {
1661     gt_cval_write(env, ri, GTIMER_SEC, value);
1662 }
1663
1664 static uint64_t gt_sec_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
1665 {
1666     return gt_tval_read(env, ri, GTIMER_SEC);
1667 }
1668
1669 static void gt_sec_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1670                               uint64_t value)
1671 {
1672     gt_tval_write(env, ri, GTIMER_SEC, value);
1673 }
1674
1675 static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1676                               uint64_t value)
1677 {
1678     gt_ctl_write(env, ri, GTIMER_SEC, value);
1679 }
1680
1681 void arm_gt_ptimer_cb(void *opaque)
1682 {
1683     ARMCPU *cpu = opaque;
1684
1685     gt_recalc_timer(cpu, GTIMER_PHYS);
1686 }
1687
1688 void arm_gt_vtimer_cb(void *opaque)
1689 {
1690     ARMCPU *cpu = opaque;
1691
1692     gt_recalc_timer(cpu, GTIMER_VIRT);
1693 }
1694
1695 void arm_gt_htimer_cb(void *opaque)
1696 {
1697     ARMCPU *cpu = opaque;
1698
1699     gt_recalc_timer(cpu, GTIMER_HYP);
1700 }
1701
1702 void arm_gt_stimer_cb(void *opaque)
1703 {
1704     ARMCPU *cpu = opaque;
1705
1706     gt_recalc_timer(cpu, GTIMER_SEC);
1707 }
1708
1709 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1710     /* Note that CNTFRQ is purely reads-as-written for the benefit
1711      * of software; writing it doesn't actually change the timer frequency.
1712      * Our reset value matches the fixed frequency we implement the timer at.
1713      */
1714     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1715       .type = ARM_CP_ALIAS,
1716       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1717       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1718     },
1719     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1720       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1721       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1722       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1723       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1724     },
1725     /* overall control: mostly access permissions */
1726     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1727       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1728       .access = PL1_RW,
1729       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1730       .resetvalue = 0,
1731     },
1732     /* per-timer control */
1733     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1734       .secure = ARM_CP_SECSTATE_NS,
1735       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1736       .accessfn = gt_ptimer_access,
1737       .fieldoffset = offsetoflow32(CPUARMState,
1738                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1739       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1740     },
1741     { .name = "CNTP_CTL(S)",
1742       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1743       .secure = ARM_CP_SECSTATE_S,
1744       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1745       .accessfn = gt_ptimer_access,
1746       .fieldoffset = offsetoflow32(CPUARMState,
1747                                    cp15.c14_timer[GTIMER_SEC].ctl),
1748       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1749     },
1750     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1751       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1752       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1753       .accessfn = gt_ptimer_access,
1754       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1755       .resetvalue = 0,
1756       .writefn = gt_phys_ctl_write, .raw_writefn = raw_write,
1757     },
1758     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1759       .type = ARM_CP_IO | ARM_CP_ALIAS, .access = PL1_RW | PL0_R,
1760       .accessfn = gt_vtimer_access,
1761       .fieldoffset = offsetoflow32(CPUARMState,
1762                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1763       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1764     },
1765     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1766       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1767       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1768       .accessfn = gt_vtimer_access,
1769       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1770       .resetvalue = 0,
1771       .writefn = gt_virt_ctl_write, .raw_writefn = raw_write,
1772     },
1773     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1774     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1775       .secure = ARM_CP_SECSTATE_NS,
1776       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1777       .accessfn = gt_ptimer_access,
1778       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1779     },
1780     { .name = "CNTP_TVAL(S)",
1781       .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1782       .secure = ARM_CP_SECSTATE_S,
1783       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1784       .accessfn = gt_ptimer_access,
1785       .readfn = gt_sec_tval_read, .writefn = gt_sec_tval_write,
1786     },
1787     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1788       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1789       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1790       .accessfn = gt_ptimer_access, .resetfn = gt_phys_timer_reset,
1791       .readfn = gt_phys_tval_read, .writefn = gt_phys_tval_write,
1792     },
1793     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1794       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1795       .accessfn = gt_vtimer_access,
1796       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1797     },
1798     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1799       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1800       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW | PL0_R,
1801       .accessfn = gt_vtimer_access, .resetfn = gt_virt_timer_reset,
1802       .readfn = gt_virt_tval_read, .writefn = gt_virt_tval_write,
1803     },
1804     /* The counter itself */
1805     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1806       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1807       .accessfn = gt_pct_access,
1808       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1809     },
1810     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1811       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1812       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1813       .accessfn = gt_pct_access, .readfn = gt_cnt_read,
1814     },
1815     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1816       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_RAW | ARM_CP_IO,
1817       .accessfn = gt_vct_access,
1818       .readfn = gt_virt_cnt_read, .resetfn = arm_cp_reset_ignore,
1819     },
1820     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1821       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1822       .access = PL0_R, .type = ARM_CP_NO_RAW | ARM_CP_IO,
1823       .accessfn = gt_vct_access, .readfn = gt_virt_cnt_read,
1824     },
1825     /* Comparison value, indicating when the timer goes off */
1826     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1827       .secure = ARM_CP_SECSTATE_NS,
1828       .access = PL1_RW | PL0_R,
1829       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1830       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1831       .accessfn = gt_ptimer_access,
1832       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1833     },
1834     { .name = "CNTP_CVAL(S)", .cp = 15, .crm = 14, .opc1 = 2,
1835       .secure = ARM_CP_SECSTATE_S,
1836       .access = PL1_RW | PL0_R,
1837       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1838       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1839       .accessfn = gt_ptimer_access,
1840       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1841     },
1842     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1843       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1844       .access = PL1_RW | PL0_R,
1845       .type = ARM_CP_IO,
1846       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1847       .resetvalue = 0, .accessfn = gt_ptimer_access,
1848       .writefn = gt_phys_cval_write, .raw_writefn = raw_write,
1849     },
1850     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1851       .access = PL1_RW | PL0_R,
1852       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS,
1853       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1854       .accessfn = gt_vtimer_access,
1855       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1856     },
1857     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1858       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1859       .access = PL1_RW | PL0_R,
1860       .type = ARM_CP_IO,
1861       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1862       .resetvalue = 0, .accessfn = gt_vtimer_access,
1863       .writefn = gt_virt_cval_write, .raw_writefn = raw_write,
1864     },
1865     /* Secure timer -- this is actually restricted to only EL3
1866      * and configurably Secure-EL1 via the accessfn.
1867      */
1868     { .name = "CNTPS_TVAL_EL1", .state = ARM_CP_STATE_AA64,
1869       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 0,
1870       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL1_RW,
1871       .accessfn = gt_stimer_access,
1872       .readfn = gt_sec_tval_read,
1873       .writefn = gt_sec_tval_write,
1874       .resetfn = gt_sec_timer_reset,
1875     },
1876     { .name = "CNTPS_CTL_EL1", .state = ARM_CP_STATE_AA64,
1877       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 1,
1878       .type = ARM_CP_IO, .access = PL1_RW,
1879       .accessfn = gt_stimer_access,
1880       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].ctl),
1881       .resetvalue = 0,
1882       .writefn = gt_sec_ctl_write, .raw_writefn = raw_write,
1883     },
1884     { .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
1885       .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
1886       .type = ARM_CP_IO, .access = PL1_RW,
1887       .accessfn = gt_stimer_access,
1888       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cval),
1889       .writefn = gt_sec_cval_write, .raw_writefn = raw_write,
1890     },
1891     REGINFO_SENTINEL
1892 };
1893
1894 #else
1895 /* In user-mode none of the generic timer registers are accessible,
1896  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1897  * so instead just don't register any of them.
1898  */
1899 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1900     REGINFO_SENTINEL
1901 };
1902
1903 #endif
1904
1905 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1906 {
1907     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1908         raw_write(env, ri, value);
1909     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1910         raw_write(env, ri, value & 0xfffff6ff);
1911     } else {
1912         raw_write(env, ri, value & 0xfffff1ff);
1913     }
1914 }
1915
1916 #ifndef CONFIG_USER_ONLY
1917 /* get_phys_addr() isn't present for user-mode-only targets */
1918
1919 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
1920                                  bool isread)
1921 {
1922     if (ri->opc2 & 4) {
1923         /* The ATS12NSO* operations must trap to EL3 if executed in
1924          * Secure EL1 (which can only happen if EL3 is AArch64).
1925          * They are simply UNDEF if executed from NS EL1.
1926          * They function normally from EL2 or EL3.
1927          */
1928         if (arm_current_el(env) == 1) {
1929             if (arm_is_secure_below_el3(env)) {
1930                 return CP_ACCESS_TRAP_UNCATEGORIZED_EL3;
1931             }
1932             return CP_ACCESS_TRAP_UNCATEGORIZED;
1933         }
1934     }
1935     return CP_ACCESS_OK;
1936 }
1937
1938 static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
1939                              int access_type, ARMMMUIdx mmu_idx)
1940 {
1941     hwaddr phys_addr;
1942     target_ulong page_size;
1943     int prot;
1944     uint32_t fsr;
1945     bool ret;
1946     uint64_t par64;
1947     MemTxAttrs attrs = {};
1948     ARMMMUFaultInfo fi = {};
1949
1950     ret = get_phys_addr(env, value, access_type, mmu_idx,
1951                         &phys_addr, &attrs, &prot, &page_size, &fsr, &fi);
1952     if (extended_addresses_enabled(env)) {
1953         /* fsr is a DFSR/IFSR value for the long descriptor
1954          * translation table format, but with WnR always clear.
1955          * Convert it to a 64-bit PAR.
1956          */
1957         par64 = (1 << 11); /* LPAE bit always set */
1958         if (!ret) {
1959             par64 |= phys_addr & ~0xfffULL;
1960             if (!attrs.secure) {
1961                 par64 |= (1 << 9); /* NS */
1962             }
1963             /* We don't set the ATTR or SH fields in the PAR. */
1964         } else {
1965             par64 |= 1; /* F */
1966             par64 |= (fsr & 0x3f) << 1; /* FS */
1967             /* Note that S2WLK and FSTAGE are always zero, because we don't
1968              * implement virtualization and therefore there can't be a stage 2
1969              * fault.
1970              */
1971         }
1972     } else {
1973         /* fsr is a DFSR/IFSR value for the short descriptor
1974          * translation table format (with WnR always clear).
1975          * Convert it to a 32-bit PAR.
1976          */
1977         if (!ret) {
1978             /* We do not set any attribute bits in the PAR */
1979             if (page_size == (1 << 24)
1980                 && arm_feature(env, ARM_FEATURE_V7)) {
1981                 par64 = (phys_addr & 0xff000000) | (1 << 1);
1982             } else {
1983                 par64 = phys_addr & 0xfffff000;
1984             }
1985             if (!attrs.secure) {
1986                 par64 |= (1 << 9); /* NS */
1987             }
1988         } else {
1989             par64 = ((fsr & (1 << 10)) >> 5) | ((fsr & (1 << 12)) >> 6) |
1990                     ((fsr & 0xf) << 1) | 1;
1991         }
1992     }
1993     return par64;
1994 }
1995
1996 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1997 {
1998     int access_type = ri->opc2 & 1;
1999     uint64_t par64;
2000     ARMMMUIdx mmu_idx;
2001     int el = arm_current_el(env);
2002     bool secure = arm_is_secure_below_el3(env);
2003
2004     switch (ri->opc2 & 6) {
2005     case 0:
2006         /* stage 1 current state PL1: ATS1CPR, ATS1CPW */
2007         switch (el) {
2008         case 3:
2009             mmu_idx = ARMMMUIdx_S1E3;
2010             break;
2011         case 2:
2012             mmu_idx = ARMMMUIdx_S1NSE1;
2013             break;
2014         case 1:
2015             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2016             break;
2017         default:
2018             g_assert_not_reached();
2019         }
2020         break;
2021     case 2:
2022         /* stage 1 current state PL0: ATS1CUR, ATS1CUW */
2023         switch (el) {
2024         case 3:
2025             mmu_idx = ARMMMUIdx_S1SE0;
2026             break;
2027         case 2:
2028             mmu_idx = ARMMMUIdx_S1NSE0;
2029             break;
2030         case 1:
2031             mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2032             break;
2033         default:
2034             g_assert_not_reached();
2035         }
2036         break;
2037     case 4:
2038         /* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
2039         mmu_idx = ARMMMUIdx_S12NSE1;
2040         break;
2041     case 6:
2042         /* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
2043         mmu_idx = ARMMMUIdx_S12NSE0;
2044         break;
2045     default:
2046         g_assert_not_reached();
2047     }
2048
2049     par64 = do_ats_write(env, value, access_type, mmu_idx);
2050
2051     A32_BANKED_CURRENT_REG_SET(env, par, par64);
2052 }
2053
2054 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
2055                         uint64_t value)
2056 {
2057     int access_type = ri->opc2 & 1;
2058     uint64_t par64;
2059
2060     par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
2061
2062     A32_BANKED_CURRENT_REG_SET(env, par, par64);
2063 }
2064
2065 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri,
2066                                      bool isread)
2067 {
2068     if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
2069         return CP_ACCESS_TRAP;
2070     }
2071     return CP_ACCESS_OK;
2072 }
2073
2074 static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
2075                         uint64_t value)
2076 {
2077     int access_type = ri->opc2 & 1;
2078     ARMMMUIdx mmu_idx;
2079     int secure = arm_is_secure_below_el3(env);
2080
2081     switch (ri->opc2 & 6) {
2082     case 0:
2083         switch (ri->opc1) {
2084         case 0: /* AT S1E1R, AT S1E1W */
2085             mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S1NSE1;
2086             break;
2087         case 4: /* AT S1E2R, AT S1E2W */
2088             mmu_idx = ARMMMUIdx_S1E2;
2089             break;
2090         case 6: /* AT S1E3R, AT S1E3W */
2091             mmu_idx = ARMMMUIdx_S1E3;
2092             break;
2093         default:
2094             g_assert_not_reached();
2095         }
2096         break;
2097     case 2: /* AT S1E0R, AT S1E0W */
2098         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S1NSE0;
2099         break;
2100     case 4: /* AT S12E1R, AT S12E1W */
2101         mmu_idx = secure ? ARMMMUIdx_S1SE1 : ARMMMUIdx_S12NSE1;
2102         break;
2103     case 6: /* AT S12E0R, AT S12E0W */
2104         mmu_idx = secure ? ARMMMUIdx_S1SE0 : ARMMMUIdx_S12NSE0;
2105         break;
2106     default:
2107         g_assert_not_reached();
2108     }
2109
2110     env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
2111 }
2112 #endif
2113
2114 static const ARMCPRegInfo vapa_cp_reginfo[] = {
2115     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
2116       .access = PL1_RW, .resetvalue = 0,
2117       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.par_s),
2118                              offsetoflow32(CPUARMState, cp15.par_ns) },
2119       .writefn = par_write },
2120 #ifndef CONFIG_USER_ONLY
2121     /* This underdecoding is safe because the reginfo is NO_RAW. */
2122     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
2123       .access = PL1_W, .accessfn = ats_access,
2124       .writefn = ats_write, .type = ARM_CP_NO_RAW },
2125 #endif
2126     REGINFO_SENTINEL
2127 };
2128
2129 /* Return basic MPU access permission bits.  */
2130 static uint32_t simple_mpu_ap_bits(uint32_t val)
2131 {
2132     uint32_t ret;
2133     uint32_t mask;
2134     int i;
2135     ret = 0;
2136     mask = 3;
2137     for (i = 0; i < 16; i += 2) {
2138         ret |= (val >> i) & mask;
2139         mask <<= 2;
2140     }
2141     return ret;
2142 }
2143
2144 /* Pad basic MPU access permission bits to extended format.  */
2145 static uint32_t extended_mpu_ap_bits(uint32_t val)
2146 {
2147     uint32_t ret;
2148     uint32_t mask;
2149     int i;
2150     ret = 0;
2151     mask = 3;
2152     for (i = 0; i < 16; i += 2) {
2153         ret |= (val & mask) << i;
2154         mask <<= 2;
2155     }
2156     return ret;
2157 }
2158
2159 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2160                                  uint64_t value)
2161 {
2162     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
2163 }
2164
2165 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2166 {
2167     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
2168 }
2169
2170 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
2171                                  uint64_t value)
2172 {
2173     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
2174 }
2175
2176 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
2177 {
2178     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
2179 }
2180
2181 static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
2182 {
2183     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2184
2185     if (!u32p) {
2186         return 0;
2187     }
2188
2189     u32p += env->cp15.c6_rgnr;
2190     return *u32p;
2191 }
2192
2193 static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
2194                          uint64_t value)
2195 {
2196     ARMCPU *cpu = arm_env_get_cpu(env);
2197     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2198
2199     if (!u32p) {
2200         return;
2201     }
2202
2203     u32p += env->cp15.c6_rgnr;
2204     tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
2205     *u32p = value;
2206 }
2207
2208 static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2209 {
2210     ARMCPU *cpu = arm_env_get_cpu(env);
2211     uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
2212
2213     if (!u32p) {
2214         return;
2215     }
2216
2217     memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
2218 }
2219
2220 static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2221                               uint64_t value)
2222 {
2223     ARMCPU *cpu = arm_env_get_cpu(env);
2224     uint32_t nrgs = cpu->pmsav7_dregion;
2225
2226     if (value >= nrgs) {
2227         qemu_log_mask(LOG_GUEST_ERROR,
2228                       "PMSAv7 RGNR write >= # supported regions, %" PRIu32
2229                       " > %" PRIu32 "\n", (uint32_t)value, nrgs);
2230         return;
2231     }
2232
2233     raw_write(env, ri, value);
2234 }
2235
2236 static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
2237     { .name = "DRBAR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 0,
2238       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2239       .fieldoffset = offsetof(CPUARMState, pmsav7.drbar),
2240       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2241     { .name = "DRSR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 2,
2242       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2243       .fieldoffset = offsetof(CPUARMState, pmsav7.drsr),
2244       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2245     { .name = "DRACR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 1, .opc2 = 4,
2246       .access = PL1_RW, .type = ARM_CP_NO_RAW,
2247       .fieldoffset = offsetof(CPUARMState, pmsav7.dracr),
2248       .readfn = pmsav7_read, .writefn = pmsav7_write, .resetfn = pmsav7_reset },
2249     { .name = "RGNR", .cp = 15, .crn = 6, .opc1 = 0, .crm = 2, .opc2 = 0,
2250       .access = PL1_RW,
2251       .fieldoffset = offsetof(CPUARMState, cp15.c6_rgnr),
2252       .writefn = pmsav7_rgnr_write },
2253     REGINFO_SENTINEL
2254 };
2255
2256 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
2257     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2258       .access = PL1_RW, .type = ARM_CP_ALIAS,
2259       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2260       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
2261     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2262       .access = PL1_RW, .type = ARM_CP_ALIAS,
2263       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2264       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
2265     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
2266       .access = PL1_RW,
2267       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
2268       .resetvalue = 0, },
2269     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
2270       .access = PL1_RW,
2271       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
2272       .resetvalue = 0, },
2273     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
2274       .access = PL1_RW,
2275       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
2276     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
2277       .access = PL1_RW,
2278       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
2279     /* Protection region base and size registers */
2280     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
2281       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2282       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
2283     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
2284       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2285       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
2286     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
2287       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2288       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
2289     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
2290       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2291       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
2292     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
2293       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2294       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
2295     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
2296       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2297       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
2298     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
2299       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2300       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
2301     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
2302       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
2303       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
2304     REGINFO_SENTINEL
2305 };
2306
2307 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
2308                                  uint64_t value)
2309 {
2310     TCR *tcr = raw_ptr(env, ri);
2311     int maskshift = extract32(value, 0, 3);
2312
2313     if (!arm_feature(env, ARM_FEATURE_V8)) {
2314         if (arm_feature(env, ARM_FEATURE_LPAE) && (value & TTBCR_EAE)) {
2315             /* Pre ARMv8 bits [21:19], [15:14] and [6:3] are UNK/SBZP when
2316              * using Long-desciptor translation table format */
2317             value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
2318         } else if (arm_feature(env, ARM_FEATURE_EL3)) {
2319             /* In an implementation that includes the Security Extensions
2320              * TTBCR has additional fields PD0 [4] and PD1 [5] for
2321              * Short-descriptor translation table format.
2322              */
2323             value &= TTBCR_PD1 | TTBCR_PD0 | TTBCR_N;
2324         } else {
2325             value &= TTBCR_N;
2326         }
2327     }
2328
2329     /* Update the masks corresponding to the TCR bank being written
2330      * Note that we always calculate mask and base_mask, but
2331      * they are only used for short-descriptor tables (ie if EAE is 0);
2332      * for long-descriptor tables the TCR fields are used differently
2333      * and the mask and base_mask values are meaningless.
2334      */
2335     tcr->raw_tcr = value;
2336     tcr->mask = ~(((uint32_t)0xffffffffu) >> maskshift);
2337     tcr->base_mask = ~((uint32_t)0x3fffu >> maskshift);
2338 }
2339
2340 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2341                              uint64_t value)
2342 {
2343     ARMCPU *cpu = arm_env_get_cpu(env);
2344
2345     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2346         /* With LPAE the TTBCR could result in a change of ASID
2347          * via the TTBCR.A1 bit, so do a TLB flush.
2348          */
2349         tlb_flush(CPU(cpu), 1);
2350     }
2351     vmsa_ttbcr_raw_write(env, ri, value);
2352 }
2353
2354 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
2355 {
2356     TCR *tcr = raw_ptr(env, ri);
2357
2358     /* Reset both the TCR as well as the masks corresponding to the bank of
2359      * the TCR being reset.
2360      */
2361     tcr->raw_tcr = 0;
2362     tcr->mask = 0;
2363     tcr->base_mask = 0xffffc000u;
2364 }
2365
2366 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2367                                uint64_t value)
2368 {
2369     ARMCPU *cpu = arm_env_get_cpu(env);
2370     TCR *tcr = raw_ptr(env, ri);
2371
2372     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
2373     tlb_flush(CPU(cpu), 1);
2374     tcr->raw_tcr = value;
2375 }
2376
2377 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2378                             uint64_t value)
2379 {
2380     /* 64 bit accesses to the TTBRs can change the ASID and so we
2381      * must flush the TLB.
2382      */
2383     if (cpreg_field_is_64bit(ri)) {
2384         ARMCPU *cpu = arm_env_get_cpu(env);
2385
2386         tlb_flush(CPU(cpu), 1);
2387     }
2388     raw_write(env, ri, value);
2389 }
2390
2391 static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2392                         uint64_t value)
2393 {
2394     ARMCPU *cpu = arm_env_get_cpu(env);
2395     CPUState *cs = CPU(cpu);
2396
2397     /* Accesses to VTTBR may change the VMID so we must flush the TLB.  */
2398     if (raw_read(env, ri) != value) {
2399         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2400                             ARMMMUIdx_S2NS, -1);
2401         raw_write(env, ri, value);
2402     }
2403 }
2404
2405 static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] = {
2406     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
2407       .access = PL1_RW, .type = ARM_CP_ALIAS,
2408       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dfsr_s),
2409                              offsetoflow32(CPUARMState, cp15.dfsr_ns) }, },
2410     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
2411       .access = PL1_RW, .resetvalue = 0,
2412       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
2413                              offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
2414     { .name = "DFAR", .cp = 15, .opc1 = 0, .crn = 6, .crm = 0, .opc2 = 0,
2415       .access = PL1_RW, .resetvalue = 0,
2416       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
2417                              offsetof(CPUARMState, cp15.dfar_ns) } },
2418     { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
2419       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
2420       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
2421       .resetvalue = 0, },
2422     REGINFO_SENTINEL
2423 };
2424
2425 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
2426     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
2427       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
2428       .access = PL1_RW,
2429       .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
2430     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
2431       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0,
2432       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2433       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2434                              offsetof(CPUARMState, cp15.ttbr0_ns) } },
2435     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
2436       .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1,
2437       .access = PL1_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
2438       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2439                              offsetof(CPUARMState, cp15.ttbr1_ns) } },
2440     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
2441       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2442       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
2443       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
2444       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
2445     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
2446       .access = PL1_RW, .type = ARM_CP_ALIAS, .writefn = vmsa_ttbcr_write,
2447       .raw_writefn = vmsa_ttbcr_raw_write,
2448       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.tcr_el[3]),
2449                              offsetoflow32(CPUARMState, cp15.tcr_el[1])} },
2450     REGINFO_SENTINEL
2451 };
2452
2453 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
2454                                 uint64_t value)
2455 {
2456     env->cp15.c15_ticonfig = value & 0xe7;
2457     /* The OS_TYPE bit in this register changes the reported CPUID! */
2458     env->cp15.c0_cpuid = (value & (1 << 5)) ?
2459         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
2460 }
2461
2462 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
2463                                 uint64_t value)
2464 {
2465     env->cp15.c15_threadid = value & 0xffff;
2466 }
2467
2468 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
2469                            uint64_t value)
2470 {
2471     /* Wait-for-interrupt (deprecated) */
2472     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
2473 }
2474
2475 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
2476                                   uint64_t value)
2477 {
2478     /* On OMAP there are registers indicating the max/min index of dcache lines
2479      * containing a dirty line; cache flush operations have to reset these.
2480      */
2481     env->cp15.c15_i_max = 0x000;
2482     env->cp15.c15_i_min = 0xff0;
2483 }
2484
2485 static const ARMCPRegInfo omap_cp_reginfo[] = {
2486     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
2487       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
2488       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
2489       .resetvalue = 0, },
2490     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
2491       .access = PL1_RW, .type = ARM_CP_NOP },
2492     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
2493       .access = PL1_RW,
2494       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
2495       .writefn = omap_ticonfig_write },
2496     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
2497       .access = PL1_RW,
2498       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
2499     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
2500       .access = PL1_RW, .resetvalue = 0xff0,
2501       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
2502     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
2503       .access = PL1_RW,
2504       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
2505       .writefn = omap_threadid_write },
2506     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
2507       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2508       .type = ARM_CP_NO_RAW,
2509       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
2510     /* TODO: Peripheral port remap register:
2511      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
2512      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
2513      * when MMU is off.
2514      */
2515     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
2516       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
2517       .type = ARM_CP_OVERRIDE | ARM_CP_NO_RAW,
2518       .writefn = omap_cachemaint_write },
2519     { .name = "C9", .cp = 15, .crn = 9,
2520       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
2521       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
2522     REGINFO_SENTINEL
2523 };
2524
2525 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
2526                               uint64_t value)
2527 {
2528     env->cp15.c15_cpar = value & 0x3fff;
2529 }
2530
2531 static const ARMCPRegInfo xscale_cp_reginfo[] = {
2532     { .name = "XSCALE_CPAR",
2533       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
2534       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
2535       .writefn = xscale_cpar_write, },
2536     { .name = "XSCALE_AUXCR",
2537       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
2538       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
2539       .resetvalue = 0, },
2540     /* XScale specific cache-lockdown: since we have no cache we NOP these
2541      * and hope the guest does not really rely on cache behaviour.
2542      */
2543     { .name = "XSCALE_LOCK_ICACHE_LINE",
2544       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
2545       .access = PL1_W, .type = ARM_CP_NOP },
2546     { .name = "XSCALE_UNLOCK_ICACHE",
2547       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
2548       .access = PL1_W, .type = ARM_CP_NOP },
2549     { .name = "XSCALE_DCACHE_LOCK",
2550       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
2551       .access = PL1_RW, .type = ARM_CP_NOP },
2552     { .name = "XSCALE_UNLOCK_DCACHE",
2553       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
2554       .access = PL1_W, .type = ARM_CP_NOP },
2555     REGINFO_SENTINEL
2556 };
2557
2558 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
2559     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
2560      * implementation of this implementation-defined space.
2561      * Ideally this should eventually disappear in favour of actually
2562      * implementing the correct behaviour for all cores.
2563      */
2564     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
2565       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2566       .access = PL1_RW,
2567       .type = ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE,
2568       .resetvalue = 0 },
2569     REGINFO_SENTINEL
2570 };
2571
2572 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
2573     /* Cache status: RAZ because we have no cache so it's always clean */
2574     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
2575       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2576       .resetvalue = 0 },
2577     REGINFO_SENTINEL
2578 };
2579
2580 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
2581     /* We never have a a block transfer operation in progress */
2582     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
2583       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2584       .resetvalue = 0 },
2585     /* The cache ops themselves: these all NOP for QEMU */
2586     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
2587       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2588     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
2589       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2590     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
2591       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2592     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
2593       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2594     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
2595       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2596     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
2597       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
2598     REGINFO_SENTINEL
2599 };
2600
2601 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
2602     /* The cache test-and-clean instructions always return (1 << 30)
2603      * to indicate that there are no dirty cache lines.
2604      */
2605     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
2606       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2607       .resetvalue = (1 << 30) },
2608     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
2609       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_RAW,
2610       .resetvalue = (1 << 30) },
2611     REGINFO_SENTINEL
2612 };
2613
2614 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
2615     /* Ignore ReadBuffer accesses */
2616     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
2617       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
2618       .access = PL1_RW, .resetvalue = 0,
2619       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW },
2620     REGINFO_SENTINEL
2621 };
2622
2623 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2624 {
2625     ARMCPU *cpu = arm_env_get_cpu(env);
2626     unsigned int cur_el = arm_current_el(env);
2627     bool secure = arm_is_secure(env);
2628
2629     if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2630         return env->cp15.vpidr_el2;
2631     }
2632     return raw_read(env, ri);
2633 }
2634
2635 static uint64_t mpidr_read_val(CPUARMState *env)
2636 {
2637     ARMCPU *cpu = ARM_CPU(arm_env_get_cpu(env));
2638     uint64_t mpidr = cpu->mp_affinity;
2639
2640     if (arm_feature(env, ARM_FEATURE_V7MP)) {
2641         mpidr |= (1U << 31);
2642         /* Cores which are uniprocessor (non-coherent)
2643          * but still implement the MP extensions set
2644          * bit 30. (For instance, Cortex-R5).
2645          */
2646         if (cpu->mp_is_up) {
2647             mpidr |= (1u << 30);
2648         }
2649     }
2650     return mpidr;
2651 }
2652
2653 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2654 {
2655     unsigned int cur_el = arm_current_el(env);
2656     bool secure = arm_is_secure(env);
2657
2658     if (arm_feature(env, ARM_FEATURE_EL2) && !secure && cur_el == 1) {
2659         return env->cp15.vmpidr_el2;
2660     }
2661     return mpidr_read_val(env);
2662 }
2663
2664 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
2665     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
2666       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
2667       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW },
2668     REGINFO_SENTINEL
2669 };
2670
2671 static const ARMCPRegInfo lpae_cp_reginfo[] = {
2672     /* NOP AMAIR0/1 */
2673     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
2674       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
2675       .access = PL1_RW, .type = ARM_CP_CONST,
2676       .resetvalue = 0 },
2677     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
2678     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
2679       .access = PL1_RW, .type = ARM_CP_CONST,
2680       .resetvalue = 0 },
2681     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
2682       .access = PL1_RW, .type = ARM_CP_64BIT, .resetvalue = 0,
2683       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.par_s),
2684                              offsetof(CPUARMState, cp15.par_ns)} },
2685     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
2686       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2687       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s),
2688                              offsetof(CPUARMState, cp15.ttbr0_ns) },
2689       .writefn = vmsa_ttbr_write, },
2690     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
2691       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
2692       .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s),
2693                              offsetof(CPUARMState, cp15.ttbr1_ns) },
2694       .writefn = vmsa_ttbr_write, },
2695     REGINFO_SENTINEL
2696 };
2697
2698 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2699 {
2700     return vfp_get_fpcr(env);
2701 }
2702
2703 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2704                             uint64_t value)
2705 {
2706     vfp_set_fpcr(env, value);
2707 }
2708
2709 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
2710 {
2711     return vfp_get_fpsr(env);
2712 }
2713
2714 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2715                             uint64_t value)
2716 {
2717     vfp_set_fpsr(env, value);
2718 }
2719
2720 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri,
2721                                        bool isread)
2722 {
2723     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
2724         return CP_ACCESS_TRAP;
2725     }
2726     return CP_ACCESS_OK;
2727 }
2728
2729 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
2730                             uint64_t value)
2731 {
2732     env->daif = value & PSTATE_DAIF;
2733 }
2734
2735 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
2736                                           const ARMCPRegInfo *ri,
2737                                           bool isread)
2738 {
2739     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
2740      * SCTLR_EL1.UCI is set.
2741      */
2742     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCI)) {
2743         return CP_ACCESS_TRAP;
2744     }
2745     return CP_ACCESS_OK;
2746 }
2747
2748 /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instructions
2749  * Page D4-1736 (DDI0487A.b)
2750  */
2751
2752 static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2753                                     uint64_t value)
2754 {
2755     ARMCPU *cpu = arm_env_get_cpu(env);
2756     CPUState *cs = CPU(cpu);
2757
2758     if (arm_is_secure_below_el3(env)) {
2759         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2760     } else {
2761         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2762     }
2763 }
2764
2765 static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2766                                       uint64_t value)
2767 {
2768     bool sec = arm_is_secure_below_el3(env);
2769     CPUState *other_cs;
2770
2771     CPU_FOREACH(other_cs) {
2772         if (sec) {
2773             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2774         } else {
2775             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2776                                 ARMMMUIdx_S12NSE0, -1);
2777         }
2778     }
2779 }
2780
2781 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2782                                   uint64_t value)
2783 {
2784     /* Note that the 'ALL' scope must invalidate both stage 1 and
2785      * stage 2 translations, whereas most other scopes only invalidate
2786      * stage 1 translations.
2787      */
2788     ARMCPU *cpu = arm_env_get_cpu(env);
2789     CPUState *cs = CPU(cpu);
2790
2791     if (arm_is_secure_below_el3(env)) {
2792         tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2793     } else {
2794         if (arm_feature(env, ARM_FEATURE_EL2)) {
2795             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0,
2796                                 ARMMMUIdx_S2NS, -1);
2797         } else {
2798             tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1);
2799         }
2800     }
2801 }
2802
2803 static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2804                                   uint64_t value)
2805 {
2806     ARMCPU *cpu = arm_env_get_cpu(env);
2807     CPUState *cs = CPU(cpu);
2808
2809     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1);
2810 }
2811
2812 static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2813                                   uint64_t value)
2814 {
2815     ARMCPU *cpu = arm_env_get_cpu(env);
2816     CPUState *cs = CPU(cpu);
2817
2818     tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1);
2819 }
2820
2821 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2822                                     uint64_t value)
2823 {
2824     /* Note that the 'ALL' scope must invalidate both stage 1 and
2825      * stage 2 translations, whereas most other scopes only invalidate
2826      * stage 1 translations.
2827      */
2828     bool sec = arm_is_secure_below_el3(env);
2829     bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
2830     CPUState *other_cs;
2831
2832     CPU_FOREACH(other_cs) {
2833         if (sec) {
2834             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1);
2835         } else if (has_el2) {
2836             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2837                                 ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1);
2838         } else {
2839             tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1,
2840                                 ARMMMUIdx_S12NSE0, -1);
2841         }
2842     }
2843 }
2844
2845 static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2846                                     uint64_t value)
2847 {
2848     CPUState *other_cs;
2849
2850     CPU_FOREACH(other_cs) {
2851         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1);
2852     }
2853 }
2854
2855 static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2856                                     uint64_t value)
2857 {
2858     CPUState *other_cs;
2859
2860     CPU_FOREACH(other_cs) {
2861         tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1);
2862     }
2863 }
2864
2865 static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2866                                  uint64_t value)
2867 {
2868     /* Invalidate by VA, EL1&0 (AArch64 version).
2869      * Currently handles all of VAE1, VAAE1, VAALE1 and VALE1,
2870      * since we don't support flush-for-specific-ASID-only or
2871      * flush-last-level-only.
2872      */
2873     ARMCPU *cpu = arm_env_get_cpu(env);
2874     CPUState *cs = CPU(cpu);
2875     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2876
2877     if (arm_is_secure_below_el3(env)) {
2878         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1,
2879                                  ARMMMUIdx_S1SE0, -1);
2880     } else {
2881         tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1,
2882                                  ARMMMUIdx_S12NSE0, -1);
2883     }
2884 }
2885
2886 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
2887                                  uint64_t value)
2888 {
2889     /* Invalidate by VA, EL2
2890      * Currently handles both VAE2 and VALE2, since we don't support
2891      * flush-last-level-only.
2892      */
2893     ARMCPU *cpu = arm_env_get_cpu(env);
2894     CPUState *cs = CPU(cpu);
2895     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2896
2897     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1);
2898 }
2899
2900 static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
2901                                  uint64_t value)
2902 {
2903     /* Invalidate by VA, EL3
2904      * Currently handles both VAE3 and VALE3, since we don't support
2905      * flush-last-level-only.
2906      */
2907     ARMCPU *cpu = arm_env_get_cpu(env);
2908     CPUState *cs = CPU(cpu);
2909     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2910
2911     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1);
2912 }
2913
2914 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2915                                    uint64_t value)
2916 {
2917     bool sec = arm_is_secure_below_el3(env);
2918     CPUState *other_cs;
2919     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2920
2921     CPU_FOREACH(other_cs) {
2922         if (sec) {
2923             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1,
2924                                      ARMMMUIdx_S1SE0, -1);
2925         } else {
2926             tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1,
2927                                      ARMMMUIdx_S12NSE0, -1);
2928         }
2929     }
2930 }
2931
2932 static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2933                                    uint64_t value)
2934 {
2935     CPUState *other_cs;
2936     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2937
2938     CPU_FOREACH(other_cs) {
2939         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1);
2940     }
2941 }
2942
2943 static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2944                                    uint64_t value)
2945 {
2946     CPUState *other_cs;
2947     uint64_t pageaddr = sextract64(value << 12, 0, 56);
2948
2949     CPU_FOREACH(other_cs) {
2950         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1);
2951     }
2952 }
2953
2954 static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
2955                                     uint64_t value)
2956 {
2957     /* Invalidate by IPA. This has to invalidate any structures that
2958      * contain only stage 2 translation information, but does not need
2959      * to apply to structures that contain combined stage 1 and stage 2
2960      * translation information.
2961      * This must NOP if EL2 isn't implemented or SCR_EL3.NS is zero.
2962      */
2963     ARMCPU *cpu = arm_env_get_cpu(env);
2964     CPUState *cs = CPU(cpu);
2965     uint64_t pageaddr;
2966
2967     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2968         return;
2969     }
2970
2971     pageaddr = sextract64(value << 12, 0, 48);
2972
2973     tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1);
2974 }
2975
2976 static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
2977                                       uint64_t value)
2978 {
2979     CPUState *other_cs;
2980     uint64_t pageaddr;
2981
2982     if (!arm_feature(env, ARM_FEATURE_EL2) || !(env->cp15.scr_el3 & SCR_NS)) {
2983         return;
2984     }
2985
2986     pageaddr = sextract64(value << 12, 0, 48);
2987
2988     CPU_FOREACH(other_cs) {
2989         tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1);
2990     }
2991 }
2992
2993 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,
2994                                       bool isread)
2995 {
2996     /* We don't implement EL2, so the only control on DC ZVA is the
2997      * bit in the SCTLR which can prohibit access for EL0.
2998      */
2999     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_DZE)) {
3000         return CP_ACCESS_TRAP;
3001     }
3002     return CP_ACCESS_OK;
3003 }
3004
3005 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
3006 {
3007     ARMCPU *cpu = arm_env_get_cpu(env);
3008     int dzp_bit = 1 << 4;
3009
3010     /* DZP indicates whether DC ZVA access is allowed */
3011     if (aa64_zva_access(env, NULL, false) == CP_ACCESS_OK) {
3012         dzp_bit = 0;
3013     }
3014     return cpu->dcz_blocksize | dzp_bit;
3015 }
3016
3017 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3018                                     bool isread)
3019 {
3020     if (!(env->pstate & PSTATE_SP)) {
3021         /* Access to SP_EL0 is undefined if it's being used as
3022          * the stack pointer.
3023          */
3024         return CP_ACCESS_TRAP_UNCATEGORIZED;
3025     }
3026     return CP_ACCESS_OK;
3027 }
3028
3029 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
3030 {
3031     return env->pstate & PSTATE_SP;
3032 }
3033
3034 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
3035 {
3036     update_spsel(env, val);
3037 }
3038
3039 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3040                         uint64_t value)
3041 {
3042     ARMCPU *cpu = arm_env_get_cpu(env);
3043
3044     if (raw_read(env, ri) == value) {
3045         /* Skip the TLB flush if nothing actually changed; Linux likes
3046          * to do a lot of pointless SCTLR writes.
3047          */
3048         return;
3049     }
3050
3051     raw_write(env, ri, value);
3052     /* ??? Lots of these bits are not implemented.  */
3053     /* This may enable/disable the MMU, so do a TLB flush.  */
3054     tlb_flush(CPU(cpu), 1);
3055 }
3056
3057 static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
3058                                      bool isread)
3059 {
3060     if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
3061         return CP_ACCESS_TRAP_FP_EL2;
3062     }
3063     if (env->cp15.cptr_el[3] & CPTR_TFP) {
3064         return CP_ACCESS_TRAP_FP_EL3;
3065     }
3066     return CP_ACCESS_OK;
3067 }
3068
3069 static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
3070                        uint64_t value)
3071 {
3072     env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
3073 }
3074
3075 static const ARMCPRegInfo v8_cp_reginfo[] = {
3076     /* Minimal set of EL0-visible registers. This will need to be expanded
3077      * significantly for system emulation of AArch64 CPUs.
3078      */
3079     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
3080       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
3081       .access = PL0_RW, .type = ARM_CP_NZCV },
3082     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
3083       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
3084       .type = ARM_CP_NO_RAW,
3085       .access = PL0_RW, .accessfn = aa64_daif_access,
3086       .fieldoffset = offsetof(CPUARMState, daif),
3087       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
3088     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
3089       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
3090       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
3091     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
3092       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
3093       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
3094     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
3095       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
3096       .access = PL0_R, .type = ARM_CP_NO_RAW,
3097       .readfn = aa64_dczid_read },
3098     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
3099       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
3100       .access = PL0_W, .type = ARM_CP_DC_ZVA,
3101 #ifndef CONFIG_USER_ONLY
3102       /* Avoid overhead of an access check that always passes in user-mode */
3103       .accessfn = aa64_zva_access,
3104 #endif
3105     },
3106     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
3107       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
3108       .access = PL1_R, .type = ARM_CP_CURRENTEL },
3109     /* Cache ops: all NOPs since we don't emulate caches */
3110     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
3111       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3112       .access = PL1_W, .type = ARM_CP_NOP },
3113     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
3114       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3115       .access = PL1_W, .type = ARM_CP_NOP },
3116     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
3117       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
3118       .access = PL0_W, .type = ARM_CP_NOP,
3119       .accessfn = aa64_cacheop_access },
3120     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
3121       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3122       .access = PL1_W, .type = ARM_CP_NOP },
3123     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
3124       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3125       .access = PL1_W, .type = ARM_CP_NOP },
3126     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
3127       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
3128       .access = PL0_W, .type = ARM_CP_NOP,
3129       .accessfn = aa64_cacheop_access },
3130     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
3131       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3132       .access = PL1_W, .type = ARM_CP_NOP },
3133     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
3134       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
3135       .access = PL0_W, .type = ARM_CP_NOP,
3136       .accessfn = aa64_cacheop_access },
3137     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
3138       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
3139       .access = PL0_W, .type = ARM_CP_NOP,
3140       .accessfn = aa64_cacheop_access },
3141     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
3142       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3143       .access = PL1_W, .type = ARM_CP_NOP },
3144     /* TLBI operations */
3145     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
3146       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
3147       .access = PL1_W, .type = ARM_CP_NO_RAW,
3148       .writefn = tlbi_aa64_vmalle1is_write },
3149     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
3150       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
3151       .access = PL1_W, .type = ARM_CP_NO_RAW,
3152       .writefn = tlbi_aa64_vae1is_write },
3153     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
3154       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
3155       .access = PL1_W, .type = ARM_CP_NO_RAW,
3156       .writefn = tlbi_aa64_vmalle1is_write },
3157     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
3158       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
3159       .access = PL1_W, .type = ARM_CP_NO_RAW,
3160       .writefn = tlbi_aa64_vae1is_write },
3161     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
3162       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3163       .access = PL1_W, .type = ARM_CP_NO_RAW,
3164       .writefn = tlbi_aa64_vae1is_write },
3165     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
3166       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3167       .access = PL1_W, .type = ARM_CP_NO_RAW,
3168       .writefn = tlbi_aa64_vae1is_write },
3169     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
3170       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
3171       .access = PL1_W, .type = ARM_CP_NO_RAW,
3172       .writefn = tlbi_aa64_vmalle1_write },
3173     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
3174       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
3175       .access = PL1_W, .type = ARM_CP_NO_RAW,
3176       .writefn = tlbi_aa64_vae1_write },
3177     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
3178       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
3179       .access = PL1_W, .type = ARM_CP_NO_RAW,
3180       .writefn = tlbi_aa64_vmalle1_write },
3181     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
3182       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
3183       .access = PL1_W, .type = ARM_CP_NO_RAW,
3184       .writefn = tlbi_aa64_vae1_write },
3185     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
3186       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3187       .access = PL1_W, .type = ARM_CP_NO_RAW,
3188       .writefn = tlbi_aa64_vae1_write },
3189     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
3190       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3191       .access = PL1_W, .type = ARM_CP_NO_RAW,
3192       .writefn = tlbi_aa64_vae1_write },
3193     { .name = "TLBI_IPAS2E1IS", .state = ARM_CP_STATE_AA64,
3194       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 1,
3195       .access = PL2_W, .type = ARM_CP_NO_RAW,
3196       .writefn = tlbi_aa64_ipas2e1is_write },
3197     { .name = "TLBI_IPAS2LE1IS", .state = ARM_CP_STATE_AA64,
3198       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 0, .opc2 = 5,
3199       .access = PL2_W, .type = ARM_CP_NO_RAW,
3200       .writefn = tlbi_aa64_ipas2e1is_write },
3201     { .name = "TLBI_ALLE1IS", .state = ARM_CP_STATE_AA64,
3202       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 4,
3203       .access = PL2_W, .type = ARM_CP_NO_RAW,
3204       .writefn = tlbi_aa64_alle1is_write },
3205     { .name = "TLBI_VMALLS12E1IS", .state = ARM_CP_STATE_AA64,
3206       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 6,
3207       .access = PL2_W, .type = ARM_CP_NO_RAW,
3208       .writefn = tlbi_aa64_alle1is_write },
3209     { .name = "TLBI_IPAS2E1", .state = ARM_CP_STATE_AA64,
3210       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 1,
3211       .access = PL2_W, .type = ARM_CP_NO_RAW,
3212       .writefn = tlbi_aa64_ipas2e1_write },
3213     { .name = "TLBI_IPAS2LE1", .state = ARM_CP_STATE_AA64,
3214       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 4, .opc2 = 5,
3215       .access = PL2_W, .type = ARM_CP_NO_RAW,
3216       .writefn = tlbi_aa64_ipas2e1_write },
3217     { .name = "TLBI_ALLE1", .state = ARM_CP_STATE_AA64,
3218       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 4,
3219       .access = PL2_W, .type = ARM_CP_NO_RAW,
3220       .writefn = tlbi_aa64_alle1_write },
3221     { .name = "TLBI_VMALLS12E1", .state = ARM_CP_STATE_AA64,
3222       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 6,
3223       .access = PL2_W, .type = ARM_CP_NO_RAW,
3224       .writefn = tlbi_aa64_alle1is_write },
3225 #ifndef CONFIG_USER_ONLY
3226     /* 64 bit address translation operations */
3227     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
3228       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
3229       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3230     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
3231       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
3232       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3233     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
3234       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
3235       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3236     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
3237       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
3238       .access = PL1_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3239     { .name = "AT_S12E1R", .state = ARM_CP_STATE_AA64,
3240       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 4,
3241       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3242     { .name = "AT_S12E1W", .state = ARM_CP_STATE_AA64,
3243       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 5,
3244       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3245     { .name = "AT_S12E0R", .state = ARM_CP_STATE_AA64,
3246       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 6,
3247       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3248     { .name = "AT_S12E0W", .state = ARM_CP_STATE_AA64,
3249       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 7,
3250       .access = PL2_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3251     /* AT S1E2* are elsewhere as they UNDEF from EL3 if EL2 is not present */
3252     { .name = "AT_S1E3R", .state = ARM_CP_STATE_AA64,
3253       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 0,
3254       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3255     { .name = "AT_S1E3W", .state = ARM_CP_STATE_AA64,
3256       .opc0 = 1, .opc1 = 6, .crn = 7, .crm = 8, .opc2 = 1,
3257       .access = PL3_W, .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3258     { .name = "PAR_EL1", .state = ARM_CP_STATE_AA64,
3259       .type = ARM_CP_ALIAS,
3260       .opc0 = 3, .opc1 = 0, .crn = 7, .crm = 4, .opc2 = 0,
3261       .access = PL1_RW, .resetvalue = 0,
3262       .fieldoffset = offsetof(CPUARMState, cp15.par_el[1]),
3263       .writefn = par_write },
3264 #endif
3265     /* TLB invalidate last level of translation table walk */
3266     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
3267       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_is_write },
3268     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
3269       .type = ARM_CP_NO_RAW, .access = PL1_W,
3270       .writefn = tlbimvaa_is_write },
3271     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
3272       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimva_write },
3273     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
3274       .type = ARM_CP_NO_RAW, .access = PL1_W, .writefn = tlbimvaa_write },
3275     /* 32 bit cache operations */
3276     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
3277       .type = ARM_CP_NOP, .access = PL1_W },
3278     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
3279       .type = ARM_CP_NOP, .access = PL1_W },
3280     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
3281       .type = ARM_CP_NOP, .access = PL1_W },
3282     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
3283       .type = ARM_CP_NOP, .access = PL1_W },
3284     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
3285       .type = ARM_CP_NOP, .access = PL1_W },
3286     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
3287       .type = ARM_CP_NOP, .access = PL1_W },
3288     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
3289       .type = ARM_CP_NOP, .access = PL1_W },
3290     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
3291       .type = ARM_CP_NOP, .access = PL1_W },
3292     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
3293       .type = ARM_CP_NOP, .access = PL1_W },
3294     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
3295       .type = ARM_CP_NOP, .access = PL1_W },
3296     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
3297       .type = ARM_CP_NOP, .access = PL1_W },
3298     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
3299       .type = ARM_CP_NOP, .access = PL1_W },
3300     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
3301       .type = ARM_CP_NOP, .access = PL1_W },
3302     /* MMU Domain access control / MPU write buffer control */
3303     { .name = "DACR", .cp = 15, .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
3304       .access = PL1_RW, .resetvalue = 0,
3305       .writefn = dacr_write, .raw_writefn = raw_write,
3306       .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.dacr_s),
3307                              offsetoflow32(CPUARMState, cp15.dacr_ns) } },
3308     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
3309       .type = ARM_CP_ALIAS,
3310       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
3311       .access = PL1_RW,
3312       .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
3313     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
3314       .type = ARM_CP_ALIAS,
3315       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
3316       .access = PL1_RW,
3317       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_SVC]) },
3318     /* We rely on the access checks not allowing the guest to write to the
3319      * state field when SPSel indicates that it's being used as the stack
3320      * pointer.
3321      */
3322     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
3323       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
3324       .access = PL1_RW, .accessfn = sp_el0_access,
3325       .type = ARM_CP_ALIAS,
3326       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
3327     { .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
3328       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
3329       .access = PL2_RW, .type = ARM_CP_ALIAS,
3330       .fieldoffset = offsetof(CPUARMState, sp_el[1]) },
3331     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
3332       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
3333       .type = ARM_CP_NO_RAW,
3334       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
3335     { .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
3336       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
3337       .type = ARM_CP_ALIAS,
3338       .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
3339       .access = PL2_RW, .accessfn = fpexc32_access },
3340     { .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
3341       .opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
3342       .access = PL2_RW, .resetvalue = 0,
3343       .writefn = dacr_write, .raw_writefn = raw_write,
3344       .fieldoffset = offsetof(CPUARMState, cp15.dacr32_el2) },
3345     { .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
3346       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
3347       .access = PL2_RW, .resetvalue = 0,
3348       .fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
3349     { .name = "SPSR_IRQ", .state = ARM_CP_STATE_AA64,
3350       .type = ARM_CP_ALIAS,
3351       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 0,
3352       .access = PL2_RW,
3353       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_IRQ]) },
3354     { .name = "SPSR_ABT", .state = ARM_CP_STATE_AA64,
3355       .type = ARM_CP_ALIAS,
3356       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 1,
3357       .access = PL2_RW,
3358       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_ABT]) },
3359     { .name = "SPSR_UND", .state = ARM_CP_STATE_AA64,
3360       .type = ARM_CP_ALIAS,
3361       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 2,
3362       .access = PL2_RW,
3363       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_UND]) },
3364     { .name = "SPSR_FIQ", .state = ARM_CP_STATE_AA64,
3365       .type = ARM_CP_ALIAS,
3366       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 3, .opc2 = 3,
3367       .access = PL2_RW,
3368       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
3369     { .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
3370       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
3371       .resetvalue = 0,
3372       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
3373     { .name = "SDCR", .type = ARM_CP_ALIAS,
3374       .cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
3375       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3376       .writefn = sdcr_write,
3377       .fieldoffset = offsetoflow32(CPUARMState, cp15.mdcr_el3) },
3378     REGINFO_SENTINEL
3379 };
3380
3381 /* Used to describe the behaviour of EL2 regs when EL2 does not exist.  */
3382 static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
3383     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3384       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3385       .access = PL2_RW,
3386       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3387     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3388       .type = ARM_CP_NO_RAW,
3389       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3390       .access = PL2_RW,
3391       .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
3392     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3393       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3394       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3395     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3396       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3397       .access = PL2_RW, .type = ARM_CP_CONST,
3398       .resetvalue = 0 },
3399     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3400       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3401       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3402     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3403       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3404       .access = PL2_RW, .type = ARM_CP_CONST,
3405       .resetvalue = 0 },
3406     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3407       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3408       .access = PL2_RW, .type = ARM_CP_CONST,
3409       .resetvalue = 0 },
3410     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3411       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3412       .access = PL2_RW, .type = ARM_CP_CONST,
3413       .resetvalue = 0 },
3414     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3415       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3416       .access = PL2_RW, .type = ARM_CP_CONST,
3417       .resetvalue = 0 },
3418     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3419       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3420       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3421     { .name = "VTCR_EL2", .state = ARM_CP_STATE_BOTH,
3422       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3423       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3424       .type = ARM_CP_CONST, .resetvalue = 0 },
3425     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3426       .cp = 15, .opc1 = 6, .crm = 2,
3427       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3428       .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
3429     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3430       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3431       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3432     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3433       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3434       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3435     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3436       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3437       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3438     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3439       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3440       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3441     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3442       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3443       .resetvalue = 0 },
3444     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3445       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3446       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3447     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3448       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3449       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3450     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3451       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3452       .resetvalue = 0 },
3453     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3454       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3455       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3456     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3457       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_CONST,
3458       .resetvalue = 0 },
3459     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3460       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3461       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3462     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3463       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3464       .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
3465     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3466       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3467       .access = PL2_RW, .accessfn = access_tda,
3468       .type = ARM_CP_CONST, .resetvalue = 0 },
3469     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
3470       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3471       .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
3472       .type = ARM_CP_CONST, .resetvalue = 0 },
3473     REGINFO_SENTINEL
3474 };
3475
3476 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
3477 {
3478     ARMCPU *cpu = arm_env_get_cpu(env);
3479     uint64_t valid_mask = HCR_MASK;
3480
3481     if (arm_feature(env, ARM_FEATURE_EL3)) {
3482         valid_mask &= ~HCR_HCD;
3483     } else {
3484         valid_mask &= ~HCR_TSC;
3485     }
3486
3487     /* Clear RES0 bits.  */
3488     value &= valid_mask;
3489
3490     /* These bits change the MMU setup:
3491      * HCR_VM enables stage 2 translation
3492      * HCR_PTW forbids certain page-table setups
3493      * HCR_DC Disables stage1 and enables stage2 translation
3494      */
3495     if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
3496         tlb_flush(CPU(cpu), 1);
3497     }
3498     raw_write(env, ri, value);
3499 }
3500
3501 static const ARMCPRegInfo el2_cp_reginfo[] = {
3502     { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
3503       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
3504       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
3505       .writefn = hcr_write },
3506     { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
3507       .type = ARM_CP_ALIAS,
3508       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
3509       .access = PL2_RW,
3510       .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
3511     { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
3512       .type = ARM_CP_ALIAS,
3513       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
3514       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
3515     { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
3516       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
3517       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
3518     { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
3519       .type = ARM_CP_ALIAS,
3520       .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
3521       .access = PL2_RW,
3522       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_HYP]) },
3523     { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
3524       .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
3525       .access = PL2_RW, .writefn = vbar_write,
3526       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
3527       .resetvalue = 0 },
3528     { .name = "SP_EL2", .state = ARM_CP_STATE_AA64,
3529       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 1, .opc2 = 0,
3530       .access = PL3_RW, .type = ARM_CP_ALIAS,
3531       .fieldoffset = offsetof(CPUARMState, sp_el[2]) },
3532     { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH,
3533       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2,
3534       .access = PL2_RW, .accessfn = cptr_access, .resetvalue = 0,
3535       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[2]) },
3536     { .name = "MAIR_EL2", .state = ARM_CP_STATE_BOTH,
3537       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 0,
3538       .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el[2]),
3539       .resetvalue = 0 },
3540     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3541       .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
3542       .access = PL2_RW, .type = ARM_CP_ALIAS,
3543       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
3544     { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
3545       .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
3546       .access = PL2_RW, .type = ARM_CP_CONST,
3547       .resetvalue = 0 },
3548     /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
3549     { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
3550       .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
3551       .access = PL2_RW, .type = ARM_CP_CONST,
3552       .resetvalue = 0 },
3553     { .name = "AFSR0_EL2", .state = ARM_CP_STATE_BOTH,
3554       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 0,
3555       .access = PL2_RW, .type = ARM_CP_CONST,
3556       .resetvalue = 0 },
3557     { .name = "AFSR1_EL2", .state = ARM_CP_STATE_BOTH,
3558       .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 1, .opc2 = 1,
3559       .access = PL2_RW, .type = ARM_CP_CONST,
3560       .resetvalue = 0 },
3561     { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
3562       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
3563       .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
3564       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3565       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
3566     { .name = "VTCR", .state = ARM_CP_STATE_AA32,
3567       .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3568       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3569       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3570     { .name = "VTCR_EL2", .state = ARM_CP_STATE_AA64,
3571       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,
3572       .access = PL2_RW, .type = ARM_CP_ALIAS,
3573       .fieldoffset = offsetof(CPUARMState, cp15.vtcr_el2) },
3574     { .name = "VTTBR", .state = ARM_CP_STATE_AA32,
3575       .cp = 15, .opc1 = 6, .crm = 2,
3576       .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3577       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3578       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2),
3579       .writefn = vttbr_write },
3580     { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64,
3581       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0,
3582       .access = PL2_RW, .writefn = vttbr_write,
3583       .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) },
3584     { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH,
3585       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0,
3586       .access = PL2_RW, .raw_writefn = raw_write, .writefn = sctlr_write,
3587       .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[2]) },
3588     { .name = "TPIDR_EL2", .state = ARM_CP_STATE_BOTH,
3589       .opc0 = 3, .opc1 = 4, .crn = 13, .crm = 0, .opc2 = 2,
3590       .access = PL2_RW, .resetvalue = 0,
3591       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) },
3592     { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64,
3593       .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0,
3594       .access = PL2_RW, .resetvalue = 0,
3595       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3596     { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2,
3597       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS,
3598       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) },
3599     { .name = "TLBI_ALLE2", .state = ARM_CP_STATE_AA64,
3600       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 0,
3601       .type = ARM_CP_NO_RAW, .access = PL2_W,
3602       .writefn = tlbi_aa64_alle2_write },
3603     { .name = "TLBI_VAE2", .state = ARM_CP_STATE_AA64,
3604       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 1,
3605       .type = ARM_CP_NO_RAW, .access = PL2_W,
3606       .writefn = tlbi_aa64_vae2_write },
3607     { .name = "TLBI_VALE2", .state = ARM_CP_STATE_AA64,
3608       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 7, .opc2 = 5,
3609       .access = PL2_W, .type = ARM_CP_NO_RAW,
3610       .writefn = tlbi_aa64_vae2_write },
3611     { .name = "TLBI_ALLE2IS", .state = ARM_CP_STATE_AA64,
3612       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 0,
3613       .access = PL2_W, .type = ARM_CP_NO_RAW,
3614       .writefn = tlbi_aa64_alle2is_write },
3615     { .name = "TLBI_VAE2IS", .state = ARM_CP_STATE_AA64,
3616       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 1,
3617       .type = ARM_CP_NO_RAW, .access = PL2_W,
3618       .writefn = tlbi_aa64_vae2is_write },
3619     { .name = "TLBI_VALE2IS", .state = ARM_CP_STATE_AA64,
3620       .opc0 = 1, .opc1 = 4, .crn = 8, .crm = 3, .opc2 = 5,
3621       .access = PL2_W, .type = ARM_CP_NO_RAW,
3622       .writefn = tlbi_aa64_vae2is_write },
3623 #ifndef CONFIG_USER_ONLY
3624     /* Unlike the other EL2-related AT operations, these must
3625      * UNDEF from EL3 if EL2 is not implemented, which is why we
3626      * define them here rather than with the rest of the AT ops.
3627      */
3628     { .name = "AT_S1E2R", .state = ARM_CP_STATE_AA64,
3629       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3630       .access = PL2_W, .accessfn = at_s1e2_access,
3631       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3632     { .name = "AT_S1E2W", .state = ARM_CP_STATE_AA64,
3633       .opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3634       .access = PL2_W, .accessfn = at_s1e2_access,
3635       .type = ARM_CP_NO_RAW, .writefn = ats_write64 },
3636     /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
3637      * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
3638      * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
3639      * to behave as if SCR.NS was 1.
3640      */
3641     { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
3642       .access = PL2_W,
3643       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3644     { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
3645       .access = PL2_W,
3646       .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
3647     { .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
3648       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
3649       /* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
3650        * reset values as IMPDEF. We choose to reset to 3 to comply with
3651        * both ARMv7 and ARMv8.
3652        */
3653       .access = PL2_RW, .resetvalue = 3,
3654       .fieldoffset = offsetof(CPUARMState, cp15.cnthctl_el2) },
3655     { .name = "CNTVOFF_EL2", .state = ARM_CP_STATE_AA64,
3656       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 0, .opc2 = 3,
3657       .access = PL2_RW, .type = ARM_CP_IO, .resetvalue = 0,
3658       .writefn = gt_cntvoff_write,
3659       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3660     { .name = "CNTVOFF", .cp = 15, .opc1 = 4, .crm = 14,
3661       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS | ARM_CP_IO,
3662       .writefn = gt_cntvoff_write,
3663       .fieldoffset = offsetof(CPUARMState, cp15.cntvoff_el2) },
3664     { .name = "CNTHP_CVAL_EL2", .state = ARM_CP_STATE_AA64,
3665       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 2,
3666       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3667       .type = ARM_CP_IO, .access = PL2_RW,
3668       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3669     { .name = "CNTHP_CVAL", .cp = 15, .opc1 = 6, .crm = 14,
3670       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval),
3671       .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_IO,
3672       .writefn = gt_hyp_cval_write, .raw_writefn = raw_write },
3673     { .name = "CNTHP_TVAL_EL2", .state = ARM_CP_STATE_BOTH,
3674       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 0,
3675       .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
3676       .resetfn = gt_hyp_timer_reset,
3677       .readfn = gt_hyp_tval_read, .writefn = gt_hyp_tval_write },
3678     { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
3679       .type = ARM_CP_IO,
3680       .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
3681       .access = PL2_RW,
3682       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].ctl),
3683       .resetvalue = 0,
3684       .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
3685 #endif
3686     /* The only field of MDCR_EL2 that has a defined architectural reset value
3687      * is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
3688      * don't impelment any PMU event counters, so using zero as a reset
3689      * value for MDCR_EL2 is okay
3690      */
3691     { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
3692       .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
3693       .access = PL2_RW, .resetvalue = 0,
3694       .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), },
3695     { .name = "HPFAR", .state = ARM_CP_STATE_AA32,
3696       .cp = 15, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3697       .access = PL2_RW, .accessfn = access_el3_aa32ns,
3698       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3699     { .name = "HPFAR_EL2", .state = ARM_CP_STATE_AA64,
3700       .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
3701       .access = PL2_RW,
3702       .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
3703     REGINFO_SENTINEL
3704 };
3705
3706 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
3707                                    bool isread)
3708 {
3709     /* The NSACR is RW at EL3, and RO for NS EL1 and NS EL2.
3710      * At Secure EL1 it traps to EL3.
3711      */
3712     if (arm_current_el(env) == 3) {
3713         return CP_ACCESS_OK;
3714     }
3715     if (arm_is_secure_below_el3(env)) {
3716         return CP_ACCESS_TRAP_EL3;
3717     }
3718     /* Accesses from EL1 NS and EL2 NS are UNDEF for write but allow reads. */
3719     if (isread) {
3720         return CP_ACCESS_OK;
3721     }
3722     return CP_ACCESS_TRAP_UNCATEGORIZED;
3723 }
3724
3725 static const ARMCPRegInfo el3_cp_reginfo[] = {
3726     { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
3727       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
3728       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
3729       .resetvalue = 0, .writefn = scr_write },
3730     { .name = "SCR",  .type = ARM_CP_ALIAS,
3731       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
3732       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3733       .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
3734       .writefn = scr_write },
3735     { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64,
3736       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1,
3737       .access = PL3_RW, .resetvalue = 0,
3738       .fieldoffset = offsetof(CPUARMState, cp15.sder) },
3739     { .name = "SDER",
3740       .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 1,
3741       .access = PL3_RW, .resetvalue = 0,
3742       .fieldoffset = offsetoflow32(CPUARMState, cp15.sder) },
3743     { .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
3744       .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
3745       .writefn = vbar_write, .resetvalue = 0,
3746       .fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
3747     { .name = "TTBR0_EL3", .state = ARM_CP_STATE_AA64,
3748       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 0,
3749       .access = PL3_RW, .writefn = vmsa_ttbr_write, .resetvalue = 0,
3750       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[3]) },
3751     { .name = "TCR_EL3", .state = ARM_CP_STATE_AA64,
3752       .opc0 = 3, .opc1 = 6, .crn = 2, .crm = 0, .opc2 = 2,
3753       .access = PL3_RW, .writefn = vmsa_tcr_el1_write,
3754       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
3755       .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[3]) },
3756     { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
3757       .type = ARM_CP_ALIAS,
3758       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
3759       .access = PL3_RW,
3760       .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
3761     { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
3762       .type = ARM_CP_ALIAS,
3763       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
3764       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
3765     { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
3766       .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
3767       .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
3768     { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
3769       .type = ARM_CP_ALIAS,
3770       .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
3771       .access = PL3_RW,
3772       .fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_MON]) },
3773     { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
3774       .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
3775       .access = PL3_RW, .writefn = vbar_write,
3776       .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
3777       .resetvalue = 0 },
3778     { .name = "CPTR_EL3", .state = ARM_CP_STATE_AA64,
3779       .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 2,
3780       .access = PL3_RW, .accessfn = cptr_access, .resetvalue = 0,
3781       .fieldoffset = offsetof(CPUARMState, cp15.cptr_el[3]) },
3782     { .name = "TPIDR_EL3", .state = ARM_CP_STATE_AA64,
3783       .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
3784       .access = PL3_RW, .resetvalue = 0,
3785       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
3786     { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
3787       .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
3788       .access = PL3_RW, .type = ARM_CP_CONST,
3789       .resetvalue = 0 },
3790     { .name = "AFSR0_EL3", .state = ARM_CP_STATE_BOTH,
3791       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 0,
3792       .access = PL3_RW, .type = ARM_CP_CONST,
3793       .resetvalue = 0 },
3794     { .name = "AFSR1_EL3", .state = ARM_CP_STATE_BOTH,
3795       .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 1, .opc2 = 1,
3796       .access = PL3_RW, .type = ARM_CP_CONST,
3797       .resetvalue = 0 },
3798     { .name = "TLBI_ALLE3IS", .state = ARM_CP_STATE_AA64,
3799       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 0,
3800       .access = PL3_W, .type = ARM_CP_NO_RAW,
3801       .writefn = tlbi_aa64_alle3is_write },
3802     { .name = "TLBI_VAE3IS", .state = ARM_CP_STATE_AA64,
3803       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 1,
3804       .access = PL3_W, .type = ARM_CP_NO_RAW,
3805       .writefn = tlbi_aa64_vae3is_write },
3806     { .name = "TLBI_VALE3IS", .state = ARM_CP_STATE_AA64,
3807       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 3, .opc2 = 5,
3808       .access = PL3_W, .type = ARM_CP_NO_RAW,
3809       .writefn = tlbi_aa64_vae3is_write },
3810     { .name = "TLBI_ALLE3", .state = ARM_CP_STATE_AA64,
3811       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 0,
3812       .access = PL3_W, .type = ARM_CP_NO_RAW,
3813       .writefn = tlbi_aa64_alle3_write },
3814     { .name = "TLBI_VAE3", .state = ARM_CP_STATE_AA64,
3815       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 1,
3816       .access = PL3_W, .type = ARM_CP_NO_RAW,
3817       .writefn = tlbi_aa64_vae3_write },
3818     { .name = "TLBI_VALE3", .state = ARM_CP_STATE_AA64,
3819       .opc0 = 1, .opc1 = 6, .crn = 8, .crm = 7, .opc2 = 5,
3820       .access = PL3_W, .type = ARM_CP_NO_RAW,
3821       .writefn = tlbi_aa64_vae3_write },
3822     REGINFO_SENTINEL
3823 };
3824
3825 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri,
3826                                      bool isread)
3827 {
3828     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
3829      * but the AArch32 CTR has its own reginfo struct)
3830      */
3831     if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) {
3832         return CP_ACCESS_TRAP;
3833     }
3834     return CP_ACCESS_OK;
3835 }
3836
3837 static void oslar_write(CPUARMState *env, const ARMCPRegInfo *ri,
3838                         uint64_t value)
3839 {
3840     /* Writes to OSLAR_EL1 may update the OS lock status, which can be
3841      * read via a bit in OSLSR_EL1.
3842      */
3843     int oslock;
3844
3845     if (ri->state == ARM_CP_STATE_AA32) {
3846         oslock = (value == 0xC5ACCE55);
3847     } else {
3848         oslock = value & 1;
3849     }
3850
3851     env->cp15.oslsr_el1 = deposit32(env->cp15.oslsr_el1, 1, 1, oslock);
3852 }
3853
3854 static const ARMCPRegInfo debug_cp_reginfo[] = {
3855     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
3856      * debug components. The AArch64 version of DBGDRAR is named MDRAR_EL1;
3857      * unlike DBGDRAR it is never accessible from EL0.
3858      * DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
3859      * accessor.
3860      */
3861     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
3862       .access = PL0_R, .accessfn = access_tdra,
3863       .type = ARM_CP_CONST, .resetvalue = 0 },
3864     { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
3865       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
3866       .access = PL1_R, .accessfn = access_tdra,
3867       .type = ARM_CP_CONST, .resetvalue = 0 },
3868     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
3869       .access = PL0_R, .accessfn = access_tdra,
3870       .type = ARM_CP_CONST, .resetvalue = 0 },
3871     /* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
3872     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
3873       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
3874       .access = PL1_RW, .accessfn = access_tda,
3875       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
3876       .resetvalue = 0 },
3877     /* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
3878      * We don't implement the configurable EL0 access.
3879      */
3880     { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
3881       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
3882       .type = ARM_CP_ALIAS,
3883       .access = PL1_R, .accessfn = access_tda,
3884       .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1), },
3885     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
3886       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
3887       .access = PL1_W, .type = ARM_CP_NO_RAW,
3888       .accessfn = access_tdosa,
3889       .writefn = oslar_write },
3890     { .name = "OSLSR_EL1", .state = ARM_CP_STATE_BOTH,
3891       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 4,
3892       .access = PL1_R, .resetvalue = 10,
3893       .accessfn = access_tdosa,
3894       .fieldoffset = offsetof(CPUARMState, cp15.oslsr_el1) },
3895     /* Dummy OSDLR_EL1: 32-bit Linux will read this */
3896     { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
3897       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
3898       .access = PL1_RW, .accessfn = access_tdosa,
3899       .type = ARM_CP_NOP },
3900     /* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
3901      * implement vector catch debug events yet.
3902      */
3903     { .name = "DBGVCR",
3904       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
3905       .access = PL1_RW, .accessfn = access_tda,
3906       .type = ARM_CP_NOP },
3907     REGINFO_SENTINEL
3908 };
3909
3910 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
3911     /* 64 bit access versions of the (dummy) debug registers */
3912     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
3913       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3914     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
3915       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
3916     REGINFO_SENTINEL
3917 };
3918
3919 void hw_watchpoint_update(ARMCPU *cpu, int n)
3920 {
3921     CPUARMState *env = &cpu->env;
3922     vaddr len = 0;
3923     vaddr wvr = env->cp15.dbgwvr[n];
3924     uint64_t wcr = env->cp15.dbgwcr[n];
3925     int mask;
3926     int flags = BP_CPU | BP_STOP_BEFORE_ACCESS;
3927
3928     if (env->cpu_watchpoint[n]) {
3929         cpu_watchpoint_remove_by_ref(CPU(cpu), env->cpu_watchpoint[n]);
3930         env->cpu_watchpoint[n] = NULL;
3931     }
3932
3933     if (!extract64(wcr, 0, 1)) {
3934         /* E bit clear : watchpoint disabled */
3935         return;
3936     }
3937
3938     switch (extract64(wcr, 3, 2)) {
3939     case 0:
3940         /* LSC 00 is reserved and must behave as if the wp is disabled */
3941         return;
3942     case 1:
3943         flags |= BP_MEM_READ;
3944         break;
3945     case 2:
3946         flags |= BP_MEM_WRITE;
3947         break;
3948     case 3:
3949         flags |= BP_MEM_ACCESS;
3950         break;
3951     }
3952
3953     /* Attempts to use both MASK and BAS fields simultaneously are
3954      * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case,
3955      * thus generating a watchpoint for every byte in the masked region.
3956      */
3957     mask = extract64(wcr, 24, 4);
3958     if (mask == 1 || mask == 2) {
3959         /* Reserved values of MASK; we must act as if the mask value was
3960          * some non-reserved value, or as if the watchpoint were disabled.
3961          * We choose the latter.
3962          */
3963         return;
3964     } else if (mask) {
3965         /* Watchpoint covers an aligned area up to 2GB in size */
3966         len = 1ULL << mask;
3967         /* If masked bits in WVR are not zero it's CONSTRAINED UNPREDICTABLE
3968          * whether the watchpoint fires when the unmasked bits match; we opt
3969          * to generate the exceptions.
3970          */
3971         wvr &= ~(len - 1);
3972     } else {
3973         /* Watchpoint covers bytes defined by the byte address select bits */
3974         int bas = extract64(wcr, 5, 8);
3975         int basstart;
3976
3977         if (bas == 0) {
3978             /* This must act as if the watchpoint is disabled */
3979             return;
3980         }
3981
3982         if (extract64(wvr, 2, 1)) {
3983             /* Deprecated case of an only 4-aligned address. BAS[7:4] are
3984              * ignored, and BAS[3:0] define which bytes to watch.
3985              */
3986             bas &= 0xf;
3987         }
3988         /* The BAS bits are supposed to be programmed to indicate a contiguous
3989          * range of bytes. Otherwise it is CONSTRAINED UNPREDICTABLE whether
3990          * we fire for each byte in the word/doubleword addressed by the WVR.
3991          * We choose to ignore any non-zero bits after the first range of 1s.
3992          */
3993         basstart = ctz32(bas);
3994         len = cto32(bas >> basstart);
3995         wvr += basstart;
3996     }
3997
3998     cpu_watchpoint_insert(CPU(cpu), wvr, len, flags,
3999                           &env->cpu_watchpoint[n]);
4000 }
4001
4002 void hw_watchpoint_update_all(ARMCPU *cpu)
4003 {
4004     int i;
4005     CPUARMState *env = &cpu->env;
4006
4007     /* Completely clear out existing QEMU watchpoints and our array, to
4008      * avoid possible stale entries following migration load.
4009      */
4010     cpu_watchpoint_remove_all(CPU(cpu), BP_CPU);
4011     memset(env->cpu_watchpoint, 0, sizeof(env->cpu_watchpoint));
4012
4013     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_watchpoint); i++) {
4014         hw_watchpoint_update(cpu, i);
4015     }
4016 }
4017
4018 static void dbgwvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4019                          uint64_t value)
4020 {
4021     ARMCPU *cpu = arm_env_get_cpu(env);
4022     int i = ri->crm;
4023
4024     /* Bits [63:49] are hardwired to the value of bit [48]; that is, the
4025      * register reads and behaves as if values written are sign extended.
4026      * Bits [1:0] are RES0.
4027      */
4028     value = sextract64(value, 0, 49) & ~3ULL;
4029
4030     raw_write(env, ri, value);
4031     hw_watchpoint_update(cpu, i);
4032 }
4033
4034 static void dbgwcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4035                          uint64_t value)
4036 {
4037     ARMCPU *cpu = arm_env_get_cpu(env);
4038     int i = ri->crm;
4039
4040     raw_write(env, ri, value);
4041     hw_watchpoint_update(cpu, i);
4042 }
4043
4044 void hw_breakpoint_update(ARMCPU *cpu, int n)
4045 {
4046     CPUARMState *env = &cpu->env;
4047     uint64_t bvr = env->cp15.dbgbvr[n];
4048     uint64_t bcr = env->cp15.dbgbcr[n];
4049     vaddr addr;
4050     int bt;
4051     int flags = BP_CPU;
4052
4053     if (env->cpu_breakpoint[n]) {
4054         cpu_breakpoint_remove_by_ref(CPU(cpu), env->cpu_breakpoint[n]);
4055         env->cpu_breakpoint[n] = NULL;
4056     }
4057
4058     if (!extract64(bcr, 0, 1)) {
4059         /* E bit clear : watchpoint disabled */
4060         return;
4061     }
4062
4063     bt = extract64(bcr, 20, 4);
4064
4065     switch (bt) {
4066     case 4: /* unlinked address mismatch (reserved if AArch64) */
4067     case 5: /* linked address mismatch (reserved if AArch64) */
4068         qemu_log_mask(LOG_UNIMP,
4069                       "arm: address mismatch breakpoint types not implemented");
4070         return;
4071     case 0: /* unlinked address match */
4072     case 1: /* linked address match */
4073     {
4074         /* Bits [63:49] are hardwired to the value of bit [48]; that is,
4075          * we behave as if the register was sign extended. Bits [1:0] are
4076          * RES0. The BAS field is used to allow setting breakpoints on 16
4077          * bit wide instructions; it is CONSTRAINED UNPREDICTABLE whether
4078          * a bp will fire if the addresses covered by the bp and the addresses
4079          * covered by the insn overlap but the insn doesn't start at the
4080          * start of the bp address range. We choose to require the insn and
4081          * the bp to have the same address. The constraints on writing to
4082          * BAS enforced in dbgbcr_write mean we have only four cases:
4083          *  0b0000  => no breakpoint
4084          *  0b0011  => breakpoint on addr
4085          *  0b1100  => breakpoint on addr + 2
4086          *  0b1111  => breakpoint on addr
4087          * See also figure D2-3 in the v8 ARM ARM (DDI0487A.c).
4088          */
4089         int bas = extract64(bcr, 5, 4);
4090         addr = sextract64(bvr, 0, 49) & ~3ULL;
4091         if (bas == 0) {
4092             return;
4093         }
4094         if (bas == 0xc) {
4095             addr += 2;
4096         }
4097         break;
4098     }
4099     case 2: /* unlinked context ID match */
4100     case 8: /* unlinked VMID match (reserved if no EL2) */
4101     case 10: /* unlinked context ID and VMID match (reserved if no EL2) */
4102         qemu_log_mask(LOG_UNIMP,
4103                       "arm: unlinked context breakpoint types not implemented");
4104         return;
4105     case 9: /* linked VMID match (reserved if no EL2) */
4106     case 11: /* linked context ID and VMID match (reserved if no EL2) */
4107     case 3: /* linked context ID match */
4108     default:
4109         /* We must generate no events for Linked context matches (unless
4110          * they are linked to by some other bp/wp, which is handled in
4111          * updates for the linking bp/wp). We choose to also generate no events
4112          * for reserved values.
4113          */
4114         return;
4115     }
4116
4117     cpu_breakpoint_insert(CPU(cpu), addr, flags, &env->cpu_breakpoint[n]);
4118 }
4119
4120 void hw_breakpoint_update_all(ARMCPU *cpu)
4121 {
4122     int i;
4123     CPUARMState *env = &cpu->env;
4124
4125     /* Completely clear out existing QEMU breakpoints and our array, to
4126      * avoid possible stale entries following migration load.
4127      */
4128     cpu_breakpoint_remove_all(CPU(cpu), BP_CPU);
4129     memset(env->cpu_breakpoint, 0, sizeof(env->cpu_breakpoint));
4130
4131     for (i = 0; i < ARRAY_SIZE(cpu->env.cpu_breakpoint); i++) {
4132         hw_breakpoint_update(cpu, i);
4133     }
4134 }
4135
4136 static void dbgbvr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4137                          uint64_t value)
4138 {
4139     ARMCPU *cpu = arm_env_get_cpu(env);
4140     int i = ri->crm;
4141
4142     raw_write(env, ri, value);
4143     hw_breakpoint_update(cpu, i);
4144 }
4145
4146 static void dbgbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
4147                          uint64_t value)
4148 {
4149     ARMCPU *cpu = arm_env_get_cpu(env);
4150     int i = ri->crm;
4151
4152     /* BAS[3] is a read-only copy of BAS[2], and BAS[1] a read-only
4153      * copy of BAS[0].
4154      */
4155     value = deposit64(value, 6, 1, extract64(value, 5, 1));
4156     value = deposit64(value, 8, 1, extract64(value, 7, 1));
4157
4158     raw_write(env, ri, value);
4159     hw_breakpoint_update(cpu, i);
4160 }
4161
4162 static void define_debug_regs(ARMCPU *cpu)
4163 {
4164     /* Define v7 and v8 architectural debug registers.
4165      * These are just dummy implementations for now.
4166      */
4167     int i;
4168     int wrps, brps, ctx_cmps;
4169     ARMCPRegInfo dbgdidr = {
4170         .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
4171         .access = PL0_R, .accessfn = access_tda,
4172         .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
4173     };
4174
4175     /* Note that all these register fields hold "number of Xs minus 1". */
4176     brps = extract32(cpu->dbgdidr, 24, 4);
4177     wrps = extract32(cpu->dbgdidr, 28, 4);
4178     ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
4179
4180     assert(ctx_cmps <= brps);
4181
4182     /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties
4183      * of the debug registers such as number of breakpoints;
4184      * check that if they both exist then they agree.
4185      */
4186     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
4187         assert(extract32(cpu->id_aa64dfr0, 12, 4) == brps);
4188         assert(extract32(cpu->id_aa64dfr0, 20, 4) == wrps);
4189         assert(extract32(cpu->id_aa64dfr0, 28, 4) == ctx_cmps);
4190     }
4191
4192     define_one_arm_cp_reg(cpu, &dbgdidr);
4193     define_arm_cp_regs(cpu, debug_cp_reginfo);
4194
4195     if (arm_feature(&cpu->env, ARM_FEATURE_LPAE)) {
4196         define_arm_cp_regs(cpu, debug_lpae_cp_reginfo);
4197     }
4198
4199     for (i = 0; i < brps + 1; i++) {
4200         ARMCPRegInfo dbgregs[] = {
4201             { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
4202               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
4203               .access = PL1_RW, .accessfn = access_tda,
4204               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
4205               .writefn = dbgbvr_write, .raw_writefn = raw_write
4206             },
4207             { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
4208               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
4209               .access = PL1_RW, .accessfn = access_tda,
4210               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
4211               .writefn = dbgbcr_write, .raw_writefn = raw_write
4212             },
4213             REGINFO_SENTINEL
4214         };
4215         define_arm_cp_regs(cpu, dbgregs);
4216     }
4217
4218     for (i = 0; i < wrps + 1; i++) {
4219         ARMCPRegInfo dbgregs[] = {
4220             { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
4221               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
4222               .access = PL1_RW, .accessfn = access_tda,
4223               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
4224               .writefn = dbgwvr_write, .raw_writefn = raw_write
4225             },
4226             { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
4227               .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
4228               .access = PL1_RW, .accessfn = access_tda,
4229               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
4230               .writefn = dbgwcr_write, .raw_writefn = raw_write
4231             },
4232             REGINFO_SENTINEL
4233         };
4234         define_arm_cp_regs(cpu, dbgregs);
4235     }
4236 }
4237
4238 void register_cp_regs_for_features(ARMCPU *cpu)
4239 {
4240     /* Register all the coprocessor registers based on feature bits */
4241     CPUARMState *env = &cpu->env;
4242     if (arm_feature(env, ARM_FEATURE_M)) {
4243         /* M profile has no coprocessor registers */
4244         return;
4245     }
4246
4247     define_arm_cp_regs(cpu, cp_reginfo);
4248     if (!arm_feature(env, ARM_FEATURE_V8)) {
4249         /* Must go early as it is full of wildcards that may be
4250          * overridden by later definitions.
4251          */
4252         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
4253     }
4254
4255     if (arm_feature(env, ARM_FEATURE_V6)) {
4256         /* The ID registers all have impdef reset values */
4257         ARMCPRegInfo v6_idregs[] = {
4258             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
4259               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
4260               .access = PL1_R, .type = ARM_CP_CONST,
4261               .resetvalue = cpu->id_pfr0 },
4262             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
4263               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
4264               .access = PL1_R, .type = ARM_CP_CONST,
4265               .resetvalue = cpu->id_pfr1 },
4266             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
4267               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
4268               .access = PL1_R, .type = ARM_CP_CONST,
4269               .resetvalue = cpu->id_dfr0 },
4270             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
4271               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
4272               .access = PL1_R, .type = ARM_CP_CONST,
4273               .resetvalue = cpu->id_afr0 },
4274             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
4275               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
4276               .access = PL1_R, .type = ARM_CP_CONST,
4277               .resetvalue = cpu->id_mmfr0 },
4278             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
4279               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
4280               .access = PL1_R, .type = ARM_CP_CONST,
4281               .resetvalue = cpu->id_mmfr1 },
4282             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
4283               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
4284               .access = PL1_R, .type = ARM_CP_CONST,
4285               .resetvalue = cpu->id_mmfr2 },
4286             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
4287               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
4288               .access = PL1_R, .type = ARM_CP_CONST,
4289               .resetvalue = cpu->id_mmfr3 },
4290             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
4291               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
4292               .access = PL1_R, .type = ARM_CP_CONST,
4293               .resetvalue = cpu->id_isar0 },
4294             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
4295               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
4296               .access = PL1_R, .type = ARM_CP_CONST,
4297               .resetvalue = cpu->id_isar1 },
4298             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
4299               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
4300               .access = PL1_R, .type = ARM_CP_CONST,
4301               .resetvalue = cpu->id_isar2 },
4302             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
4303               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
4304               .access = PL1_R, .type = ARM_CP_CONST,
4305               .resetvalue = cpu->id_isar3 },
4306             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
4307               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
4308               .access = PL1_R, .type = ARM_CP_CONST,
4309               .resetvalue = cpu->id_isar4 },
4310             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
4311               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
4312               .access = PL1_R, .type = ARM_CP_CONST,
4313               .resetvalue = cpu->id_isar5 },
4314             { .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
4315               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
4316               .access = PL1_R, .type = ARM_CP_CONST,
4317               .resetvalue = cpu->id_mmfr4 },
4318             /* 7 is as yet unallocated and must RAZ */
4319             { .name = "ID_ISAR7_RESERVED", .state = ARM_CP_STATE_BOTH,
4320               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
4321               .access = PL1_R, .type = ARM_CP_CONST,
4322               .resetvalue = 0 },
4323             REGINFO_SENTINEL
4324         };
4325         define_arm_cp_regs(cpu, v6_idregs);
4326         define_arm_cp_regs(cpu, v6_cp_reginfo);
4327     } else {
4328         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
4329     }
4330     if (arm_feature(env, ARM_FEATURE_V6K)) {
4331         define_arm_cp_regs(cpu, v6k_cp_reginfo);
4332     }
4333     if (arm_feature(env, ARM_FEATURE_V7MP) &&
4334         !arm_feature(env, ARM_FEATURE_MPU)) {
4335         define_arm_cp_regs(cpu, v7mp_cp_reginfo);
4336     }
4337     if (arm_feature(env, ARM_FEATURE_V7)) {
4338         /* v7 performance monitor control register: same implementor
4339          * field as main ID register, and we implement only the cycle
4340          * count register.
4341          */
4342 #ifndef CONFIG_USER_ONLY
4343         ARMCPRegInfo pmcr = {
4344             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
4345             .access = PL0_RW,
4346             .type = ARM_CP_IO | ARM_CP_ALIAS,
4347             .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
4348             .accessfn = pmreg_access, .writefn = pmcr_write,
4349             .raw_writefn = raw_write,
4350         };
4351         ARMCPRegInfo pmcr64 = {
4352             .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
4353             .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
4354             .access = PL0_RW, .accessfn = pmreg_access,
4355             .type = ARM_CP_IO,
4356             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
4357             .resetvalue = cpu->midr & 0xff000000,
4358             .writefn = pmcr_write, .raw_writefn = raw_write,
4359         };
4360         define_one_arm_cp_reg(cpu, &pmcr);
4361         define_one_arm_cp_reg(cpu, &pmcr64);
4362 #endif
4363         ARMCPRegInfo clidr = {
4364             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
4365             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
4366             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
4367         };
4368         define_one_arm_cp_reg(cpu, &clidr);
4369         define_arm_cp_regs(cpu, v7_cp_reginfo);
4370         define_debug_regs(cpu);
4371     } else {
4372         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
4373     }
4374     if (arm_feature(env, ARM_FEATURE_V8)) {
4375         /* AArch64 ID registers, which all have impdef reset values.
4376          * Note that within the ID register ranges the unused slots
4377          * must all RAZ, not UNDEF; future architecture versions may
4378          * define new registers here.
4379          */
4380         ARMCPRegInfo v8_idregs[] = {
4381             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
4382               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
4383               .access = PL1_R, .type = ARM_CP_CONST,
4384               .resetvalue = cpu->id_aa64pfr0 },
4385             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
4386               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
4387               .access = PL1_R, .type = ARM_CP_CONST,
4388               .resetvalue = cpu->id_aa64pfr1},
4389             { .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4390               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
4391               .access = PL1_R, .type = ARM_CP_CONST,
4392               .resetvalue = 0 },
4393             { .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4394               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
4395               .access = PL1_R, .type = ARM_CP_CONST,
4396               .resetvalue = 0 },
4397             { .name = "ID_AA64PFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4398               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
4399               .access = PL1_R, .type = ARM_CP_CONST,
4400               .resetvalue = 0 },
4401             { .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4402               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
4403               .access = PL1_R, .type = ARM_CP_CONST,
4404               .resetvalue = 0 },
4405             { .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4406               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
4407               .access = PL1_R, .type = ARM_CP_CONST,
4408               .resetvalue = 0 },
4409             { .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4410               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
4411               .access = PL1_R, .type = ARM_CP_CONST,
4412               .resetvalue = 0 },
4413             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
4414               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
4415               .access = PL1_R, .type = ARM_CP_CONST,
4416               /* We mask out the PMUVer field, because we don't currently
4417                * implement the PMU. Not advertising it prevents the guest
4418                * from trying to use it and getting UNDEFs on registers we
4419                * don't implement.
4420                */
4421               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
4422             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
4423               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
4424               .access = PL1_R, .type = ARM_CP_CONST,
4425               .resetvalue = cpu->id_aa64dfr1 },
4426             { .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4427               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
4428               .access = PL1_R, .type = ARM_CP_CONST,
4429               .resetvalue = 0 },
4430             { .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4431               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
4432               .access = PL1_R, .type = ARM_CP_CONST,
4433               .resetvalue = 0 },
4434             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
4435               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
4436               .access = PL1_R, .type = ARM_CP_CONST,
4437               .resetvalue = cpu->id_aa64afr0 },
4438             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
4439               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
4440               .access = PL1_R, .type = ARM_CP_CONST,
4441               .resetvalue = cpu->id_aa64afr1 },
4442             { .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4443               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
4444               .access = PL1_R, .type = ARM_CP_CONST,
4445               .resetvalue = 0 },
4446             { .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4447               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
4448               .access = PL1_R, .type = ARM_CP_CONST,
4449               .resetvalue = 0 },
4450             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
4451               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
4452               .access = PL1_R, .type = ARM_CP_CONST,
4453               .resetvalue = cpu->id_aa64isar0 },
4454             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
4455               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
4456               .access = PL1_R, .type = ARM_CP_CONST,
4457               .resetvalue = cpu->id_aa64isar1 },
4458             { .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4459               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
4460               .access = PL1_R, .type = ARM_CP_CONST,
4461               .resetvalue = 0 },
4462             { .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4463               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
4464               .access = PL1_R, .type = ARM_CP_CONST,
4465               .resetvalue = 0 },
4466             { .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4467               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
4468               .access = PL1_R, .type = ARM_CP_CONST,
4469               .resetvalue = 0 },
4470             { .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4471               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
4472               .access = PL1_R, .type = ARM_CP_CONST,
4473               .resetvalue = 0 },
4474             { .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4475               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
4476               .access = PL1_R, .type = ARM_CP_CONST,
4477               .resetvalue = 0 },
4478             { .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4479               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
4480               .access = PL1_R, .type = ARM_CP_CONST,
4481               .resetvalue = 0 },
4482             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
4483               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
4484               .access = PL1_R, .type = ARM_CP_CONST,
4485               .resetvalue = cpu->id_aa64mmfr0 },
4486             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
4487               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
4488               .access = PL1_R, .type = ARM_CP_CONST,
4489               .resetvalue = cpu->id_aa64mmfr1 },
4490             { .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4491               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
4492               .access = PL1_R, .type = ARM_CP_CONST,
4493               .resetvalue = 0 },
4494             { .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4495               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
4496               .access = PL1_R, .type = ARM_CP_CONST,
4497               .resetvalue = 0 },
4498             { .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4499               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
4500               .access = PL1_R, .type = ARM_CP_CONST,
4501               .resetvalue = 0 },
4502             { .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4503               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
4504               .access = PL1_R, .type = ARM_CP_CONST,
4505               .resetvalue = 0 },
4506             { .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4507               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
4508               .access = PL1_R, .type = ARM_CP_CONST,
4509               .resetvalue = 0 },
4510             { .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4511               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
4512               .access = PL1_R, .type = ARM_CP_CONST,
4513               .resetvalue = 0 },
4514             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
4515               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
4516               .access = PL1_R, .type = ARM_CP_CONST,
4517               .resetvalue = cpu->mvfr0 },
4518             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
4519               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
4520               .access = PL1_R, .type = ARM_CP_CONST,
4521               .resetvalue = cpu->mvfr1 },
4522             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
4523               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
4524               .access = PL1_R, .type = ARM_CP_CONST,
4525               .resetvalue = cpu->mvfr2 },
4526             { .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4527               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
4528               .access = PL1_R, .type = ARM_CP_CONST,
4529               .resetvalue = 0 },
4530             { .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4531               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
4532               .access = PL1_R, .type = ARM_CP_CONST,
4533               .resetvalue = 0 },
4534             { .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4535               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
4536               .access = PL1_R, .type = ARM_CP_CONST,
4537               .resetvalue = 0 },
4538             { .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4539               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
4540               .access = PL1_R, .type = ARM_CP_CONST,
4541               .resetvalue = 0 },
4542             { .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
4543               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
4544               .access = PL1_R, .type = ARM_CP_CONST,
4545               .resetvalue = 0 },
4546             { .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
4547               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
4548               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4549               .resetvalue = cpu->pmceid0 },
4550             { .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
4551               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
4552               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4553               .resetvalue = cpu->pmceid0 },
4554             { .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
4555               .cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
4556               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4557               .resetvalue = cpu->pmceid1 },
4558             { .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
4559               .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
4560               .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
4561               .resetvalue = cpu->pmceid1 },
4562             REGINFO_SENTINEL
4563         };
4564         /* RVBAR_EL1 is only implemented if EL1 is the highest EL */
4565         if (!arm_feature(env, ARM_FEATURE_EL3) &&
4566             !arm_feature(env, ARM_FEATURE_EL2)) {
4567             ARMCPRegInfo rvbar = {
4568                 .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
4569                 .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
4570                 .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
4571             };
4572             define_one_arm_cp_reg(cpu, &rvbar);
4573         }
4574         define_arm_cp_regs(cpu, v8_idregs);
4575         define_arm_cp_regs(cpu, v8_cp_reginfo);
4576     }
4577     if (arm_feature(env, ARM_FEATURE_EL2)) {
4578         uint64_t vmpidr_def = mpidr_read_val(env);
4579         ARMCPRegInfo vpidr_regs[] = {
4580             { .name = "VPIDR", .state = ARM_CP_STATE_AA32,
4581               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4582               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4583               .resetvalue = cpu->midr,
4584               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4585             { .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
4586               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4587               .access = PL2_RW, .resetvalue = cpu->midr,
4588               .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4589             { .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
4590               .cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4591               .access = PL2_RW, .accessfn = access_el3_aa32ns,
4592               .resetvalue = vmpidr_def,
4593               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4594             { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
4595               .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4596               .access = PL2_RW,
4597               .resetvalue = vmpidr_def,
4598               .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
4599             REGINFO_SENTINEL
4600         };
4601         define_arm_cp_regs(cpu, vpidr_regs);
4602         define_arm_cp_regs(cpu, el2_cp_reginfo);
4603         /* RVBAR_EL2 is only implemented if EL2 is the highest EL */
4604         if (!arm_feature(env, ARM_FEATURE_EL3)) {
4605             ARMCPRegInfo rvbar = {
4606                 .name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
4607                 .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
4608                 .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
4609             };
4610             define_one_arm_cp_reg(cpu, &rvbar);
4611         }
4612     } else {
4613         /* If EL2 is missing but higher ELs are enabled, we need to
4614          * register the no_el2 reginfos.
4615          */
4616         if (arm_feature(env, ARM_FEATURE_EL3)) {
4617             /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
4618              * of MIDR_EL1 and MPIDR_EL1.
4619              */
4620             ARMCPRegInfo vpidr_regs[] = {
4621                 { .name = "VPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4622                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
4623                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4624                   .type = ARM_CP_CONST, .resetvalue = cpu->midr,
4625                   .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
4626                 { .name = "VMPIDR_EL2", .state = ARM_CP_STATE_BOTH,
4627                   .opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
4628                   .access = PL2_RW, .accessfn = access_el3_aa32ns_aa64any,
4629                   .type = ARM_CP_NO_RAW,
4630                   .writefn = arm_cp_write_ignore, .readfn = mpidr_read },
4631                 REGINFO_SENTINEL
4632             };
4633             define_arm_cp_regs(cpu, vpidr_regs);
4634             define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
4635         }
4636     }
4637     if (arm_feature(env, ARM_FEATURE_EL3)) {
4638         define_arm_cp_regs(cpu, el3_cp_reginfo);
4639         ARMCPRegInfo el3_regs[] = {
4640             { .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
4641               .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
4642               .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
4643             { .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
4644               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
4645               .access = PL3_RW,
4646               .raw_writefn = raw_write, .writefn = sctlr_write,
4647               .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
4648               .resetvalue = cpu->reset_sctlr },
4649             REGINFO_SENTINEL
4650         };
4651
4652         define_arm_cp_regs(cpu, el3_regs);
4653     }
4654     /* The behaviour of NSACR is sufficiently various that we don't
4655      * try to describe it in a single reginfo:
4656      *  if EL3 is 64 bit, then trap to EL3 from S EL1,
4657      *     reads as constant 0xc00 from NS EL1 and NS EL2
4658      *  if EL3 is 32 bit, then RW at EL3, RO at NS EL1 and NS EL2
4659      *  if v7 without EL3, register doesn't exist
4660      *  if v8 without EL3, reads as constant 0xc00 from NS EL1 and NS EL2
4661      */
4662     if (arm_feature(env, ARM_FEATURE_EL3)) {
4663         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4664             ARMCPRegInfo nsacr = {
4665                 .name = "NSACR", .type = ARM_CP_CONST,
4666                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4667                 .access = PL1_RW, .accessfn = nsacr_access,
4668                 .resetvalue = 0xc00
4669             };
4670             define_one_arm_cp_reg(cpu, &nsacr);
4671         } else {
4672             ARMCPRegInfo nsacr = {
4673                 .name = "NSACR",
4674                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4675                 .access = PL3_RW | PL1_R,
4676                 .resetvalue = 0,
4677                 .fieldoffset = offsetof(CPUARMState, cp15.nsacr)
4678             };
4679             define_one_arm_cp_reg(cpu, &nsacr);
4680         }
4681     } else {
4682         if (arm_feature(env, ARM_FEATURE_V8)) {
4683             ARMCPRegInfo nsacr = {
4684                 .name = "NSACR", .type = ARM_CP_CONST,
4685                 .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 2,
4686                 .access = PL1_R,
4687                 .resetvalue = 0xc00
4688             };
4689             define_one_arm_cp_reg(cpu, &nsacr);
4690         }
4691     }
4692
4693     if (arm_feature(env, ARM_FEATURE_MPU)) {
4694         if (arm_feature(env, ARM_FEATURE_V6)) {
4695             /* PMSAv6 not implemented */
4696             assert(arm_feature(env, ARM_FEATURE_V7));
4697             define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4698             define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
4699         } else {
4700             define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
4701         }
4702     } else {
4703         define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
4704         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
4705     }
4706     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
4707         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
4708     }
4709     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
4710         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
4711     }
4712     if (arm_feature(env, ARM_FEATURE_VAPA)) {
4713         define_arm_cp_regs(cpu, vapa_cp_reginfo);
4714     }
4715     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
4716         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
4717     }
4718     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
4719         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
4720     }
4721     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
4722         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
4723     }
4724     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
4725         define_arm_cp_regs(cpu, omap_cp_reginfo);
4726     }
4727     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
4728         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
4729     }
4730     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4731         define_arm_cp_regs(cpu, xscale_cp_reginfo);
4732     }
4733     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
4734         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
4735     }
4736     if (arm_feature(env, ARM_FEATURE_LPAE)) {
4737         define_arm_cp_regs(cpu, lpae_cp_reginfo);
4738     }
4739     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
4740      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
4741      * be read-only (ie write causes UNDEF exception).
4742      */
4743     {
4744         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
4745             /* Pre-v8 MIDR space.
4746              * Note that the MIDR isn't a simple constant register because
4747              * of the TI925 behaviour where writes to another register can
4748              * cause the MIDR value to change.
4749              *
4750              * Unimplemented registers in the c15 0 0 0 space default to
4751              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
4752              * and friends override accordingly.
4753              */
4754             { .name = "MIDR",
4755               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
4756               .access = PL1_R, .resetvalue = cpu->midr,
4757               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
4758               .readfn = midr_read,
4759               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4760               .type = ARM_CP_OVERRIDE },
4761             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
4762             { .name = "DUMMY",
4763               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
4764               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4765             { .name = "DUMMY",
4766               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
4767               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4768             { .name = "DUMMY",
4769               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
4770               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4771             { .name = "DUMMY",
4772               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
4773               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4774             { .name = "DUMMY",
4775               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
4776               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4777             REGINFO_SENTINEL
4778         };
4779         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
4780             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
4781               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
4782               .access = PL1_R, .type = ARM_CP_NO_RAW, .resetvalue = cpu->midr,
4783               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
4784               .readfn = midr_read },
4785             /* crn = 0 op1 = 0 crm = 0 op2 = 4,7 : AArch32 aliases of MIDR */
4786             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4787               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4788               .access = PL1_R, .resetvalue = cpu->midr },
4789             { .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST,
4790               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 7,
4791               .access = PL1_R, .resetvalue = cpu->midr },
4792             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
4793               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
4794               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->revidr },
4795             REGINFO_SENTINEL
4796         };
4797         ARMCPRegInfo id_cp_reginfo[] = {
4798             /* These are common to v8 and pre-v8 */
4799             { .name = "CTR",
4800               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
4801               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4802             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
4803               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
4804               .access = PL0_R, .accessfn = ctr_el0_access,
4805               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
4806             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
4807             { .name = "TCMTR",
4808               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
4809               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
4810             REGINFO_SENTINEL
4811         };
4812         /* TLBTR is specific to VMSA */
4813         ARMCPRegInfo id_tlbtr_reginfo = {
4814               .name = "TLBTR",
4815               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
4816               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0,
4817         };
4818         /* MPUIR is specific to PMSA V6+ */
4819         ARMCPRegInfo id_mpuir_reginfo = {
4820               .name = "MPUIR",
4821               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4,
4822               .access = PL1_R, .type = ARM_CP_CONST,
4823               .resetvalue = cpu->pmsav7_dregion << 8
4824         };
4825         ARMCPRegInfo crn0_wi_reginfo = {
4826             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
4827             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
4828             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
4829         };
4830         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
4831             arm_feature(env, ARM_FEATURE_STRONGARM)) {
4832             ARMCPRegInfo *r;
4833             /* Register the blanket "writes ignored" value first to cover the
4834              * whole space. Then update the specific ID registers to allow write
4835              * access, so that they ignore writes rather than causing them to
4836              * UNDEF.
4837              */
4838             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
4839             for (r = id_pre_v8_midr_cp_reginfo;
4840                  r->type != ARM_CP_SENTINEL; r++) {
4841                 r->access = PL1_RW;
4842             }
4843             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
4844                 r->access = PL1_RW;
4845             }
4846             id_tlbtr_reginfo.access = PL1_RW;
4847             id_tlbtr_reginfo.access = PL1_RW;
4848         }
4849         if (arm_feature(env, ARM_FEATURE_V8)) {
4850             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
4851         } else {
4852             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
4853         }
4854         define_arm_cp_regs(cpu, id_cp_reginfo);
4855         if (!arm_feature(env, ARM_FEATURE_MPU)) {
4856             define_one_arm_cp_reg(cpu, &id_tlbtr_reginfo);
4857         } else if (arm_feature(env, ARM_FEATURE_V7)) {
4858             define_one_arm_cp_reg(cpu, &id_mpuir_reginfo);
4859         }
4860     }
4861
4862     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
4863         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
4864     }
4865
4866     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
4867         ARMCPRegInfo auxcr_reginfo[] = {
4868             { .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
4869               .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
4870               .access = PL1_RW, .type = ARM_CP_CONST,
4871               .resetvalue = cpu->reset_auxcr },
4872             { .name = "ACTLR_EL2", .state = ARM_CP_STATE_BOTH,
4873               .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 1,
4874               .access = PL2_RW, .type = ARM_CP_CONST,
4875               .resetvalue = 0 },
4876             { .name = "ACTLR_EL3", .state = ARM_CP_STATE_AA64,
4877               .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 1,
4878               .access = PL3_RW, .type = ARM_CP_CONST,
4879               .resetvalue = 0 },
4880             REGINFO_SENTINEL
4881         };
4882         define_arm_cp_regs(cpu, auxcr_reginfo);
4883     }
4884
4885     if (arm_feature(env, ARM_FEATURE_CBAR)) {
4886         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4887             /* 32 bit view is [31:18] 0...0 [43:32]. */
4888             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
4889                 | extract64(cpu->reset_cbar, 32, 12);
4890             ARMCPRegInfo cbar_reginfo[] = {
4891                 { .name = "CBAR",
4892                   .type = ARM_CP_CONST,
4893                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4894                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
4895                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
4896                   .type = ARM_CP_CONST,
4897                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
4898                   .access = PL1_R, .resetvalue = cbar32 },
4899                 REGINFO_SENTINEL
4900             };
4901             /* We don't implement a r/w 64 bit CBAR currently */
4902             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
4903             define_arm_cp_regs(cpu, cbar_reginfo);
4904         } else {
4905             ARMCPRegInfo cbar = {
4906                 .name = "CBAR",
4907                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
4908                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
4909                 .fieldoffset = offsetof(CPUARMState,
4910                                         cp15.c15_config_base_address)
4911             };
4912             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
4913                 cbar.access = PL1_R;
4914                 cbar.fieldoffset = 0;
4915                 cbar.type = ARM_CP_CONST;
4916             }
4917             define_one_arm_cp_reg(cpu, &cbar);
4918         }
4919     }
4920
4921     /* Generic registers whose values depend on the implementation */
4922     {
4923         ARMCPRegInfo sctlr = {
4924             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
4925             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
4926             .access = PL1_RW,
4927             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
4928                                    offsetof(CPUARMState, cp15.sctlr_ns) },
4929             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
4930             .raw_writefn = raw_write,
4931         };
4932         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
4933             /* Normally we would always end the TB on an SCTLR write, but Linux
4934              * arch/arm/mach-pxa/sleep.S expects two instructions following
4935              * an MMU enable to execute from cache.  Imitate this behaviour.
4936              */
4937             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
4938         }
4939         define_one_arm_cp_reg(cpu, &sctlr);
4940     }
4941 }
4942
4943 ARMCPU *cpu_arm_init(const char *cpu_model)
4944 {
4945     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
4946 }
4947
4948 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
4949 {
4950     CPUState *cs = CPU(cpu);
4951     CPUARMState *env = &cpu->env;
4952
4953     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
4954         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
4955                                  aarch64_fpu_gdb_set_reg,
4956                                  34, "aarch64-fpu.xml", 0);
4957     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
4958         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4959                                  51, "arm-neon.xml", 0);
4960     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
4961         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4962                                  35, "arm-vfp3.xml", 0);
4963     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
4964         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
4965                                  19, "arm-vfp.xml", 0);
4966     }
4967 }
4968
4969 /* Sort alphabetically by type name, except for "any". */
4970 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
4971 {
4972     ObjectClass *class_a = (ObjectClass *)a;
4973     ObjectClass *class_b = (ObjectClass *)b;
4974     const char *name_a, *name_b;
4975
4976     name_a = object_class_get_name(class_a);
4977     name_b = object_class_get_name(class_b);
4978     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
4979         return 1;
4980     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
4981         return -1;
4982     } else {
4983         return strcmp(name_a, name_b);
4984     }
4985 }
4986
4987 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
4988 {
4989     ObjectClass *oc = data;
4990     CPUListState *s = user_data;
4991     const char *typename;
4992     char *name;
4993
4994     typename = object_class_get_name(oc);
4995     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
4996     (*s->cpu_fprintf)(s->file, "  %s\n",
4997                       name);
4998     g_free(name);
4999 }
5000
5001 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
5002 {
5003     CPUListState s = {
5004         .file = f,
5005         .cpu_fprintf = cpu_fprintf,
5006     };
5007     GSList *list;
5008
5009     list = object_class_get_list(TYPE_ARM_CPU, false);
5010     list = g_slist_sort(list, arm_cpu_list_compare);
5011     (*cpu_fprintf)(f, "Available CPUs:\n");
5012     g_slist_foreach(list, arm_cpu_list_entry, &s);
5013     g_slist_free(list);
5014 #ifdef CONFIG_KVM
5015     /* The 'host' CPU type is dynamically registered only if KVM is
5016      * enabled, so we have to special-case it here:
5017      */
5018     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
5019 #endif
5020 }
5021
5022 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
5023 {
5024     ObjectClass *oc = data;
5025     CpuDefinitionInfoList **cpu_list = user_data;
5026     CpuDefinitionInfoList *entry;
5027     CpuDefinitionInfo *info;
5028     const char *typename;
5029
5030     typename = object_class_get_name(oc);
5031     info = g_malloc0(sizeof(*info));
5032     info->name = g_strndup(typename,
5033                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
5034
5035     entry = g_malloc0(sizeof(*entry));
5036     entry->value = info;
5037     entry->next = *cpu_list;
5038     *cpu_list = entry;
5039 }
5040
5041 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
5042 {
5043     CpuDefinitionInfoList *cpu_list = NULL;
5044     GSList *list;
5045
5046     list = object_class_get_list(TYPE_ARM_CPU, false);
5047     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
5048     g_slist_free(list);
5049
5050     return cpu_list;
5051 }
5052
5053 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
5054                                    void *opaque, int state, int secstate,
5055                                    int crm, int opc1, int opc2)
5056 {
5057     /* Private utility function for define_one_arm_cp_reg_with_opaque():
5058      * add a single reginfo struct to the hash table.
5059      */
5060     uint32_t *key = g_new(uint32_t, 1);
5061     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
5062     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
5063     int ns = (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
5064
5065     /* Reset the secure state to the specific incoming state.  This is
5066      * necessary as the register may have been defined with both states.
5067      */
5068     r2->secure = secstate;
5069
5070     if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5071         /* Register is banked (using both entries in array).
5072          * Overwriting fieldoffset as the array is only used to define
5073          * banked registers but later only fieldoffset is used.
5074          */
5075         r2->fieldoffset = r->bank_fieldoffsets[ns];
5076     }
5077
5078     if (state == ARM_CP_STATE_AA32) {
5079         if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) {
5080             /* If the register is banked then we don't need to migrate or
5081              * reset the 32-bit instance in certain cases:
5082              *
5083              * 1) If the register has both 32-bit and 64-bit instances then we
5084              *    can count on the 64-bit instance taking care of the
5085              *    non-secure bank.
5086              * 2) If ARMv8 is enabled then we can count on a 64-bit version
5087              *    taking care of the secure bank.  This requires that separate
5088              *    32 and 64-bit definitions are provided.
5089              */
5090             if ((r->state == ARM_CP_STATE_BOTH && ns) ||
5091                 (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) {
5092                 r2->type |= ARM_CP_ALIAS;
5093             }
5094         } else if ((secstate != r->secure) && !ns) {
5095             /* The register is not banked so we only want to allow migration of
5096              * the non-secure instance.
5097              */
5098             r2->type |= ARM_CP_ALIAS;
5099         }
5100
5101         if (r->state == ARM_CP_STATE_BOTH) {
5102             /* We assume it is a cp15 register if the .cp field is left unset.
5103              */
5104             if (r2->cp == 0) {
5105                 r2->cp = 15;
5106             }
5107
5108 #ifdef HOST_WORDS_BIGENDIAN
5109             if (r2->fieldoffset) {
5110                 r2->fieldoffset += sizeof(uint32_t);
5111             }
5112 #endif
5113         }
5114     }
5115     if (state == ARM_CP_STATE_AA64) {
5116         /* To allow abbreviation of ARMCPRegInfo
5117          * definitions, we treat cp == 0 as equivalent to
5118          * the value for "standard guest-visible sysreg".
5119          * STATE_BOTH definitions are also always "standard
5120          * sysreg" in their AArch64 view (the .cp value may
5121          * be non-zero for the benefit of the AArch32 view).
5122          */
5123         if (r->cp == 0 || r->state == ARM_CP_STATE_BOTH) {
5124             r2->cp = CP_REG_ARM64_SYSREG_CP;
5125         }
5126         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
5127                                   r2->opc0, opc1, opc2);
5128     } else {
5129         *key = ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
5130     }
5131     if (opaque) {
5132         r2->opaque = opaque;
5133     }
5134     /* reginfo passed to helpers is correct for the actual access,
5135      * and is never ARM_CP_STATE_BOTH:
5136      */
5137     r2->state = state;
5138     /* Make sure reginfo passed to helpers for wildcarded regs
5139      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
5140      */
5141     r2->crm = crm;
5142     r2->opc1 = opc1;
5143     r2->opc2 = opc2;
5144     /* By convention, for wildcarded registers only the first
5145      * entry is used for migration; the others are marked as
5146      * ALIAS so we don't try to transfer the register
5147      * multiple times. Special registers (ie NOP/WFI) are
5148      * never migratable and not even raw-accessible.
5149      */
5150     if ((r->type & ARM_CP_SPECIAL)) {
5151         r2->type |= ARM_CP_NO_RAW;
5152     }
5153     if (((r->crm == CP_ANY) && crm != 0) ||
5154         ((r->opc1 == CP_ANY) && opc1 != 0) ||
5155         ((r->opc2 == CP_ANY) && opc2 != 0)) {
5156         r2->type |= ARM_CP_ALIAS;
5157     }
5158
5159     /* Check that raw accesses are either forbidden or handled. Note that
5160      * we can't assert this earlier because the setup of fieldoffset for
5161      * banked registers has to be done first.
5162      */
5163     if (!(r2->type & ARM_CP_NO_RAW)) {
5164         assert(!raw_accessors_invalid(r2));
5165     }
5166
5167     /* Overriding of an existing definition must be explicitly
5168      * requested.
5169      */
5170     if (!(r->type & ARM_CP_OVERRIDE)) {
5171         ARMCPRegInfo *oldreg;
5172         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
5173         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
5174             fprintf(stderr, "Register redefined: cp=%d %d bit "
5175                     "crn=%d crm=%d opc1=%d opc2=%d, "
5176                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
5177                     r2->crn, r2->crm, r2->opc1, r2->opc2,
5178                     oldreg->name, r2->name);
5179             g_assert_not_reached();
5180         }
5181     }
5182     g_hash_table_insert(cpu->cp_regs, key, r2);
5183 }
5184
5185
5186 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
5187                                        const ARMCPRegInfo *r, void *opaque)
5188 {
5189     /* Define implementations of coprocessor registers.
5190      * We store these in a hashtable because typically
5191      * there are less than 150 registers in a space which
5192      * is 16*16*16*8*8 = 262144 in size.
5193      * Wildcarding is supported for the crm, opc1 and opc2 fields.
5194      * If a register is defined twice then the second definition is
5195      * used, so this can be used to define some generic registers and
5196      * then override them with implementation specific variations.
5197      * At least one of the original and the second definition should
5198      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
5199      * against accidental use.
5200      *
5201      * The state field defines whether the register is to be
5202      * visible in the AArch32 or AArch64 execution state. If the
5203      * state is set to ARM_CP_STATE_BOTH then we synthesise a
5204      * reginfo structure for the AArch32 view, which sees the lower
5205      * 32 bits of the 64 bit register.
5206      *
5207      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
5208      * be wildcarded. AArch64 registers are always considered to be 64
5209      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
5210      * the register, if any.
5211      */
5212     int crm, opc1, opc2, state;
5213     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
5214     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
5215     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
5216     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
5217     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
5218     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
5219     /* 64 bit registers have only CRm and Opc1 fields */
5220     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
5221     /* op0 only exists in the AArch64 encodings */
5222     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
5223     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
5224     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
5225     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
5226      * encodes a minimum access level for the register. We roll this
5227      * runtime check into our general permission check code, so check
5228      * here that the reginfo's specified permissions are strict enough
5229      * to encompass the generic architectural permission check.
5230      */
5231     if (r->state != ARM_CP_STATE_AA32) {
5232         int mask = 0;
5233         switch (r->opc1) {
5234         case 0: case 1: case 2:
5235             /* min_EL EL1 */
5236             mask = PL1_RW;
5237             break;
5238         case 3:
5239             /* min_EL EL0 */
5240             mask = PL0_RW;
5241             break;
5242         case 4:
5243             /* min_EL EL2 */
5244             mask = PL2_RW;
5245             break;
5246         case 5:
5247             /* unallocated encoding, so not possible */
5248             assert(false);
5249             break;
5250         case 6:
5251             /* min_EL EL3 */
5252             mask = PL3_RW;
5253             break;
5254         case 7:
5255             /* min_EL EL1, secure mode only (we don't check the latter) */
5256             mask = PL1_RW;
5257             break;
5258         default:
5259             /* broken reginfo with out-of-range opc1 */
5260             assert(false);
5261             break;
5262         }
5263         /* assert our permissions are not too lax (stricter is fine) */
5264         assert((r->access & ~mask) == 0);
5265     }
5266
5267     /* Check that the register definition has enough info to handle
5268      * reads and writes if they are permitted.
5269      */
5270     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
5271         if (r->access & PL3_R) {
5272             assert((r->fieldoffset ||
5273                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5274                    r->readfn);
5275         }
5276         if (r->access & PL3_W) {
5277             assert((r->fieldoffset ||
5278                    (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) ||
5279                    r->writefn);
5280         }
5281     }
5282     /* Bad type field probably means missing sentinel at end of reg list */
5283     assert(cptype_valid(r->type));
5284     for (crm = crmmin; crm <= crmmax; crm++) {
5285         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
5286             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
5287                 for (state = ARM_CP_STATE_AA32;
5288                      state <= ARM_CP_STATE_AA64; state++) {
5289                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
5290                         continue;
5291                     }
5292                     if (state == ARM_CP_STATE_AA32) {
5293                         /* Under AArch32 CP registers can be common
5294                          * (same for secure and non-secure world) or banked.
5295                          */
5296                         switch (r->secure) {
5297                         case ARM_CP_SECSTATE_S:
5298                         case ARM_CP_SECSTATE_NS:
5299                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5300                                                    r->secure, crm, opc1, opc2);
5301                             break;
5302                         default:
5303                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5304                                                    ARM_CP_SECSTATE_S,
5305                                                    crm, opc1, opc2);
5306                             add_cpreg_to_hashtable(cpu, r, opaque, state,
5307                                                    ARM_CP_SECSTATE_NS,
5308                                                    crm, opc1, opc2);
5309                             break;
5310                         }
5311                     } else {
5312                         /* AArch64 registers get mapped to non-secure instance
5313                          * of AArch32 */
5314                         add_cpreg_to_hashtable(cpu, r, opaque, state,
5315                                                ARM_CP_SECSTATE_NS,
5316                                                crm, opc1, opc2);
5317                     }
5318                 }
5319             }
5320         }
5321     }
5322 }
5323
5324 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
5325                                     const ARMCPRegInfo *regs, void *opaque)
5326 {
5327     /* Define a whole list of registers */
5328     const ARMCPRegInfo *r;
5329     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
5330         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
5331     }
5332 }
5333
5334 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
5335 {
5336     return g_hash_table_lookup(cpregs, &encoded_cp);
5337 }
5338
5339 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
5340                          uint64_t value)
5341 {
5342     /* Helper coprocessor write function for write-ignore registers */
5343 }
5344
5345 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
5346 {
5347     /* Helper coprocessor write function for read-as-zero registers */
5348     return 0;
5349 }
5350
5351 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
5352 {
5353     /* Helper coprocessor reset function for do-nothing-on-reset registers */
5354 }
5355
5356 static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
5357 {
5358     /* Return true if it is not valid for us to switch to
5359      * this CPU mode (ie all the UNPREDICTABLE cases in
5360      * the ARM ARM CPSRWriteByInstr pseudocode).
5361      */
5362
5363     /* Changes to or from Hyp via MSR and CPS are illegal. */
5364     if (write_type == CPSRWriteByInstr &&
5365         ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
5366          mode == ARM_CPU_MODE_HYP)) {
5367         return 1;
5368     }
5369
5370     switch (mode) {
5371     case ARM_CPU_MODE_USR:
5372         return 0;
5373     case ARM_CPU_MODE_SYS:
5374     case ARM_CPU_MODE_SVC:
5375     case ARM_CPU_MODE_ABT:
5376     case ARM_CPU_MODE_UND:
5377     case ARM_CPU_MODE_IRQ:
5378     case ARM_CPU_MODE_FIQ:
5379         /* Note that we don't implement the IMPDEF NSACR.RFR which in v7
5380          * allows FIQ mode to be Secure-only. (In v8 this doesn't exist.)
5381          */
5382         /* If HCR.TGE is set then changes from Monitor to NS PL1 via MSR
5383          * and CPS are treated as illegal mode changes.
5384          */
5385         if (write_type == CPSRWriteByInstr &&
5386             (env->cp15.hcr_el2 & HCR_TGE) &&
5387             (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
5388             !arm_is_secure_below_el3(env)) {
5389             return 1;
5390         }
5391         return 0;
5392     case ARM_CPU_MODE_HYP:
5393         return !arm_feature(env, ARM_FEATURE_EL2)
5394             || arm_current_el(env) < 2 || arm_is_secure(env);
5395     case ARM_CPU_MODE_MON:
5396         return arm_current_el(env) < 3;
5397     default:
5398         return 1;
5399     }
5400 }
5401
5402 uint32_t cpsr_read(CPUARMState *env)
5403 {
5404     int ZF;
5405     ZF = (env->ZF == 0);
5406     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
5407         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
5408         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
5409         | ((env->condexec_bits & 0xfc) << 8)
5410         | (env->GE << 16) | (env->daif & CPSR_AIF);
5411 }
5412
5413 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask,
5414                 CPSRWriteType write_type)
5415 {
5416     uint32_t changed_daif;
5417
5418     if (mask & CPSR_NZCV) {
5419         env->ZF = (~val) & CPSR_Z;
5420         env->NF = val;
5421         env->CF = (val >> 29) & 1;
5422         env->VF = (val << 3) & 0x80000000;
5423     }
5424     if (mask & CPSR_Q)
5425         env->QF = ((val & CPSR_Q) != 0);
5426     if (mask & CPSR_T)
5427         env->thumb = ((val & CPSR_T) != 0);
5428     if (mask & CPSR_IT_0_1) {
5429         env->condexec_bits &= ~3;
5430         env->condexec_bits |= (val >> 25) & 3;
5431     }
5432     if (mask & CPSR_IT_2_7) {
5433         env->condexec_bits &= 3;
5434         env->condexec_bits |= (val >> 8) & 0xfc;
5435     }
5436     if (mask & CPSR_GE) {
5437         env->GE = (val >> 16) & 0xf;
5438     }
5439
5440     /* In a V7 implementation that includes the security extensions but does
5441      * not include Virtualization Extensions the SCR.FW and SCR.AW bits control
5442      * whether non-secure software is allowed to change the CPSR_F and CPSR_A
5443      * bits respectively.
5444      *
5445      * In a V8 implementation, it is permitted for privileged software to
5446      * change the CPSR A/F bits regardless of the SCR.AW/FW bits.
5447      */
5448     if (write_type != CPSRWriteRaw && !arm_feature(env, ARM_FEATURE_V8) &&
5449         arm_feature(env, ARM_FEATURE_EL3) &&
5450         !arm_feature(env, ARM_FEATURE_EL2) &&
5451         !arm_is_secure(env)) {
5452
5453         changed_daif = (env->daif ^ val) & mask;
5454
5455         if (changed_daif & CPSR_A) {
5456             /* Check to see if we are allowed to change the masking of async
5457              * abort exceptions from a non-secure state.
5458              */
5459             if (!(env->cp15.scr_el3 & SCR_AW)) {
5460                 qemu_log_mask(LOG_GUEST_ERROR,
5461                               "Ignoring attempt to switch CPSR_A flag from "
5462                               "non-secure world with SCR.AW bit clear\n");
5463                 mask &= ~CPSR_A;
5464             }
5465         }
5466
5467         if (changed_daif & CPSR_F) {
5468             /* Check to see if we are allowed to change the masking of FIQ
5469              * exceptions from a non-secure state.
5470              */
5471             if (!(env->cp15.scr_el3 & SCR_FW)) {
5472                 qemu_log_mask(LOG_GUEST_ERROR,
5473                               "Ignoring attempt to switch CPSR_F flag from "
5474                               "non-secure world with SCR.FW bit clear\n");
5475                 mask &= ~CPSR_F;
5476             }
5477
5478             /* Check whether non-maskable FIQ (NMFI) support is enabled.
5479              * If this bit is set software is not allowed to mask
5480              * FIQs, but is allowed to set CPSR_F to 0.
5481              */
5482             if ((A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_NMFI) &&
5483                 (val & CPSR_F)) {
5484                 qemu_log_mask(LOG_GUEST_ERROR,
5485                               "Ignoring attempt to enable CPSR_F flag "
5486                               "(non-maskable FIQ [NMFI] support enabled)\n");
5487                 mask &= ~CPSR_F;
5488             }
5489         }
5490     }
5491
5492     env->daif &= ~(CPSR_AIF & mask);
5493     env->daif |= val & CPSR_AIF & mask;
5494
5495     if (write_type != CPSRWriteRaw &&
5496         ((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
5497         if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR) {
5498             /* Note that we can only get here in USR mode if this is a
5499              * gdb stub write; for this case we follow the architectural
5500              * behaviour for guest writes in USR mode of ignoring an attempt
5501              * to switch mode. (Those are caught by translate.c for writes
5502              * triggered by guest instructions.)
5503              */
5504             mask &= ~CPSR_M;
5505         } else if (bad_mode_switch(env, val & CPSR_M, write_type)) {
5506             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
5507              * v7, and has defined behaviour in v8:
5508              *  + leave CPSR.M untouched
5509              *  + allow changes to the other CPSR fields
5510              *  + set PSTATE.IL
5511              * For user changes via the GDB stub, we don't set PSTATE.IL,
5512              * as this would be unnecessarily harsh for a user error.
5513              */
5514             mask &= ~CPSR_M;
5515             if (write_type != CPSRWriteByGDBStub &&
5516                 arm_feature(env, ARM_FEATURE_V8)) {
5517                 mask |= CPSR_IL;
5518                 val |= CPSR_IL;
5519             }
5520         } else {
5521             switch_mode(env, val & CPSR_M);
5522         }
5523     }
5524     mask &= ~CACHED_CPSR_BITS;
5525     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
5526 }
5527
5528 /* Sign/zero extend */
5529 uint32_t HELPER(sxtb16)(uint32_t x)
5530 {
5531     uint32_t res;
5532     res = (uint16_t)(int8_t)x;
5533     res |= (uint32_t)(int8_t)(x >> 16) << 16;
5534     return res;
5535 }
5536
5537 uint32_t HELPER(uxtb16)(uint32_t x)
5538 {
5539     uint32_t res;
5540     res = (uint16_t)(uint8_t)x;
5541     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
5542     return res;
5543 }
5544
5545 uint32_t HELPER(clz)(uint32_t x)
5546 {
5547     return clz32(x);
5548 }
5549
5550 int32_t HELPER(sdiv)(int32_t num, int32_t den)
5551 {
5552     if (den == 0)
5553       return 0;
5554     if (num == INT_MIN && den == -1)
5555       return INT_MIN;
5556     return num / den;
5557 }
5558
5559 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
5560 {
5561     if (den == 0)
5562       return 0;
5563     return num / den;
5564 }
5565
5566 uint32_t HELPER(rbit)(uint32_t x)
5567 {
5568     return revbit32(x);
5569 }
5570
5571 #if defined(CONFIG_USER_ONLY)
5572
5573 /* These should probably raise undefined insn exceptions.  */
5574 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
5575 {
5576     ARMCPU *cpu = arm_env_get_cpu(env);
5577
5578     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
5579 }
5580
5581 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
5582 {
5583     ARMCPU *cpu = arm_env_get_cpu(env);
5584
5585     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
5586     return 0;
5587 }
5588
5589 void switch_mode(CPUARMState *env, int mode)
5590 {
5591     ARMCPU *cpu = arm_env_get_cpu(env);
5592
5593     if (mode != ARM_CPU_MODE_USR) {
5594         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
5595     }
5596 }
5597
5598 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5599                                  uint32_t cur_el, bool secure)
5600 {
5601     return 1;
5602 }
5603
5604 void aarch64_sync_64_to_32(CPUARMState *env)
5605 {
5606     g_assert_not_reached();
5607 }
5608
5609 #else
5610
5611 void switch_mode(CPUARMState *env, int mode)
5612 {
5613     int old_mode;
5614     int i;
5615
5616     old_mode = env->uncached_cpsr & CPSR_M;
5617     if (mode == old_mode)
5618         return;
5619
5620     if (old_mode == ARM_CPU_MODE_FIQ) {
5621         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
5622         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
5623     } else if (mode == ARM_CPU_MODE_FIQ) {
5624         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
5625         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
5626     }
5627
5628     i = bank_number(old_mode);
5629     env->banked_r13[i] = env->regs[13];
5630     env->banked_r14[i] = env->regs[14];
5631     env->banked_spsr[i] = env->spsr;
5632
5633     i = bank_number(mode);
5634     env->regs[13] = env->banked_r13[i];
5635     env->regs[14] = env->banked_r14[i];
5636     env->spsr = env->banked_spsr[i];
5637 }
5638
5639 /* Physical Interrupt Target EL Lookup Table
5640  *
5641  * [ From ARM ARM section G1.13.4 (Table G1-15) ]
5642  *
5643  * The below multi-dimensional table is used for looking up the target
5644  * exception level given numerous condition criteria.  Specifically, the
5645  * target EL is based on SCR and HCR routing controls as well as the
5646  * currently executing EL and secure state.
5647  *
5648  *    Dimensions:
5649  *    target_el_table[2][2][2][2][2][4]
5650  *                    |  |  |  |  |  +--- Current EL
5651  *                    |  |  |  |  +------ Non-secure(0)/Secure(1)
5652  *                    |  |  |  +--------- HCR mask override
5653  *                    |  |  +------------ SCR exec state control
5654  *                    |  +--------------- SCR mask override
5655  *                    +------------------ 32-bit(0)/64-bit(1) EL3
5656  *
5657  *    The table values are as such:
5658  *    0-3 = EL0-EL3
5659  *     -1 = Cannot occur
5660  *
5661  * The ARM ARM target EL table includes entries indicating that an "exception
5662  * is not taken".  The two cases where this is applicable are:
5663  *    1) An exception is taken from EL3 but the SCR does not have the exception
5664  *    routed to EL3.
5665  *    2) An exception is taken from EL2 but the HCR does not have the exception
5666  *    routed to EL2.
5667  * In these two cases, the below table contain a target of EL1.  This value is
5668  * returned as it is expected that the consumer of the table data will check
5669  * for "target EL >= current EL" to ensure the exception is not taken.
5670  *
5671  *            SCR     HCR
5672  *         64  EA     AMO                 From
5673  *        BIT IRQ     IMO      Non-secure         Secure
5674  *        EL3 FIQ  RW FMO   EL0 EL1 EL2 EL3   EL0 EL1 EL2 EL3
5675  */
5676 static const int8_t target_el_table[2][2][2][2][2][4] = {
5677     {{{{/* 0   0   0   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5678        {/* 0   0   0   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},
5679       {{/* 0   0   1   0 */{ 1,  1,  2, -1 },{ 3, -1, -1,  3 },},
5680        {/* 0   0   1   1 */{ 2,  2,  2, -1 },{ 3, -1, -1,  3 },},},},
5681      {{{/* 0   1   0   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5682        {/* 0   1   0   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},
5683       {{/* 0   1   1   0 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},
5684        {/* 0   1   1   1 */{ 3,  3,  3, -1 },{ 3, -1, -1,  3 },},},},},
5685     {{{{/* 1   0   0   0 */{ 1,  1,  2, -1 },{ 1,  1, -1,  1 },},
5686        {/* 1   0   0   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},
5687       {{/* 1   0   1   0 */{ 1,  1,  1, -1 },{ 1,  1, -1,  1 },},
5688        {/* 1   0   1   1 */{ 2,  2,  2, -1 },{ 1,  1, -1,  1 },},},},
5689      {{{/* 1   1   0   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5690        {/* 1   1   0   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},
5691       {{/* 1   1   1   0 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},
5692        {/* 1   1   1   1 */{ 3,  3,  3, -1 },{ 3,  3, -1,  3 },},},},},
5693 };
5694
5695 /*
5696  * Determine the target EL for physical exceptions
5697  */
5698 uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
5699                                  uint32_t cur_el, bool secure)
5700 {
5701     CPUARMState *env = cs->env_ptr;
5702     int rw;
5703     int scr;
5704     int hcr;
5705     int target_el;
5706     /* Is the highest EL AArch64? */
5707     int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
5708
5709     if (arm_feature(env, ARM_FEATURE_EL3)) {
5710         rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
5711     } else {
5712         /* Either EL2 is the highest EL (and so the EL2 register width
5713          * is given by is64); or there is no EL2 or EL3, in which case
5714          * the value of 'rw' does not affect the table lookup anyway.
5715          */
5716         rw = is64;
5717     }
5718
5719     switch (excp_idx) {
5720     case EXCP_IRQ:
5721         scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
5722         hcr = ((env->cp15.hcr_el2 & HCR_IMO) == HCR_IMO);
5723         break;
5724     case EXCP_FIQ:
5725         scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
5726         hcr = ((env->cp15.hcr_el2 & HCR_FMO) == HCR_FMO);
5727         break;
5728     default:
5729         scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
5730         hcr = ((env->cp15.hcr_el2 & HCR_AMO) == HCR_AMO);
5731         break;
5732     };
5733
5734     /* If HCR.TGE is set then HCR is treated as being 1 */
5735     hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
5736
5737     /* Perform a table-lookup for the target EL given the current state */
5738     target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
5739
5740     assert(target_el > 0);
5741
5742     return target_el;
5743 }
5744
5745 static void v7m_push(CPUARMState *env, uint32_t val)
5746 {
5747     CPUState *cs = CPU(arm_env_get_cpu(env));
5748
5749     env->regs[13] -= 4;
5750     stl_phys(cs->as, env->regs[13], val);
5751 }
5752
5753 static uint32_t v7m_pop(CPUARMState *env)
5754 {
5755     CPUState *cs = CPU(arm_env_get_cpu(env));
5756     uint32_t val;
5757
5758     val = ldl_phys(cs->as, env->regs[13]);
5759     env->regs[13] += 4;
5760     return val;
5761 }
5762
5763 /* Switch to V7M main or process stack pointer.  */
5764 static void switch_v7m_sp(CPUARMState *env, int process)
5765 {
5766     uint32_t tmp;
5767     if (env->v7m.current_sp != process) {
5768         tmp = env->v7m.other_sp;
5769         env->v7m.other_sp = env->regs[13];
5770         env->regs[13] = tmp;
5771         env->v7m.current_sp = process;
5772     }
5773 }
5774
5775 static void do_v7m_exception_exit(CPUARMState *env)
5776 {
5777     uint32_t type;
5778     uint32_t xpsr;
5779
5780     type = env->regs[15];
5781     if (env->v7m.exception != 0)
5782         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
5783
5784     /* Switch to the target stack.  */
5785     switch_v7m_sp(env, (type & 4) != 0);
5786     /* Pop registers.  */
5787     env->regs[0] = v7m_pop(env);
5788     env->regs[1] = v7m_pop(env);
5789     env->regs[2] = v7m_pop(env);
5790     env->regs[3] = v7m_pop(env);
5791     env->regs[12] = v7m_pop(env);
5792     env->regs[14] = v7m_pop(env);
5793     env->regs[15] = v7m_pop(env);
5794     if (env->regs[15] & 1) {
5795         qemu_log_mask(LOG_GUEST_ERROR,
5796                       "M profile return from interrupt with misaligned "
5797                       "PC is UNPREDICTABLE\n");
5798         /* Actual hardware seems to ignore the lsbit, and there are several
5799          * RTOSes out there which incorrectly assume the r15 in the stack
5800          * frame should be a Thumb-style "lsbit indicates ARM/Thumb" value.
5801          */
5802         env->regs[15] &= ~1U;
5803     }
5804     xpsr = v7m_pop(env);
5805     xpsr_write(env, xpsr, 0xfffffdff);
5806     /* Undo stack alignment.  */
5807     if (xpsr & 0x200)
5808         env->regs[13] |= 4;
5809     /* ??? The exception return type specifies Thread/Handler mode.  However
5810        this is also implied by the xPSR value. Not sure what to do
5811        if there is a mismatch.  */
5812     /* ??? Likewise for mismatches between the CONTROL register and the stack
5813        pointer.  */
5814 }
5815
5816 void arm_v7m_cpu_do_interrupt(CPUState *cs)
5817 {
5818     ARMCPU *cpu = ARM_CPU(cs);
5819     CPUARMState *env = &cpu->env;
5820     uint32_t xpsr = xpsr_read(env);
5821     uint32_t lr;
5822     uint32_t addr;
5823
5824     arm_log_exception(cs->exception_index);
5825
5826     lr = 0xfffffff1;
5827     if (env->v7m.current_sp)
5828         lr |= 4;
5829     if (env->v7m.exception == 0)
5830         lr |= 8;
5831
5832     /* For exceptions we just mark as pending on the NVIC, and let that
5833        handle it.  */
5834     /* TODO: Need to escalate if the current priority is higher than the
5835        one we're raising.  */
5836     switch (cs->exception_index) {
5837     case EXCP_UDEF:
5838         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
5839         return;
5840     case EXCP_SWI:
5841         /* The PC already points to the next instruction.  */
5842         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
5843         return;
5844     case EXCP_PREFETCH_ABORT:
5845     case EXCP_DATA_ABORT:
5846         /* TODO: if we implemented the MPU registers, this is where we
5847          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
5848          */
5849         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
5850         return;
5851     case EXCP_BKPT:
5852         if (semihosting_enabled()) {
5853             int nr;
5854             nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff;
5855             if (nr == 0xab) {
5856                 env->regs[15] += 2;
5857                 qemu_log_mask(CPU_LOG_INT,
5858                               "...handling as semihosting call 0x%x\n",
5859                               env->regs[0]);
5860                 env->regs[0] = do_arm_semihosting(env);
5861                 return;
5862             }
5863         }
5864         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
5865         return;
5866     case EXCP_IRQ:
5867         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
5868         break;
5869     case EXCP_EXCEPTION_EXIT:
5870         do_v7m_exception_exit(env);
5871         return;
5872     default:
5873         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
5874         return; /* Never happens.  Keep compiler happy.  */
5875     }
5876
5877     /* Align stack pointer.  */
5878     /* ??? Should only do this if Configuration Control Register
5879        STACKALIGN bit is set.  */
5880     if (env->regs[13] & 4) {
5881         env->regs[13] -= 4;
5882         xpsr |= 0x200;
5883     }
5884     /* Switch to the handler mode.  */
5885     v7m_push(env, xpsr);
5886     v7m_push(env, env->regs[15]);
5887     v7m_push(env, env->regs[14]);
5888     v7m_push(env, env->regs[12]);
5889     v7m_push(env, env->regs[3]);
5890     v7m_push(env, env->regs[2]);
5891     v7m_push(env, env->regs[1]);
5892     v7m_push(env, env->regs[0]);
5893     switch_v7m_sp(env, 0);
5894     /* Clear IT bits */
5895     env->condexec_bits = 0;
5896     env->regs[14] = lr;
5897     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
5898     env->regs[15] = addr & 0xfffffffe;
5899     env->thumb = addr & 1;
5900 }
5901
5902 /* Function used to synchronize QEMU's AArch64 register set with AArch32
5903  * register set.  This is necessary when switching between AArch32 and AArch64
5904  * execution state.
5905  */
5906 void aarch64_sync_32_to_64(CPUARMState *env)
5907 {
5908     int i;
5909     uint32_t mode = env->uncached_cpsr & CPSR_M;
5910
5911     /* We can blanket copy R[0:7] to X[0:7] */
5912     for (i = 0; i < 8; i++) {
5913         env->xregs[i] = env->regs[i];
5914     }
5915
5916     /* Unless we are in FIQ mode, x8-x12 come from the user registers r8-r12.
5917      * Otherwise, they come from the banked user regs.
5918      */
5919     if (mode == ARM_CPU_MODE_FIQ) {
5920         for (i = 8; i < 13; i++) {
5921             env->xregs[i] = env->usr_regs[i - 8];
5922         }
5923     } else {
5924         for (i = 8; i < 13; i++) {
5925             env->xregs[i] = env->regs[i];
5926         }
5927     }
5928
5929     /* Registers x13-x23 are the various mode SP and FP registers. Registers
5930      * r13 and r14 are only copied if we are in that mode, otherwise we copy
5931      * from the mode banked register.
5932      */
5933     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
5934         env->xregs[13] = env->regs[13];
5935         env->xregs[14] = env->regs[14];
5936     } else {
5937         env->xregs[13] = env->banked_r13[bank_number(ARM_CPU_MODE_USR)];
5938         /* HYP is an exception in that it is copied from r14 */
5939         if (mode == ARM_CPU_MODE_HYP) {
5940             env->xregs[14] = env->regs[14];
5941         } else {
5942             env->xregs[14] = env->banked_r14[bank_number(ARM_CPU_MODE_USR)];
5943         }
5944     }
5945
5946     if (mode == ARM_CPU_MODE_HYP) {
5947         env->xregs[15] = env->regs[13];
5948     } else {
5949         env->xregs[15] = env->banked_r13[bank_number(ARM_CPU_MODE_HYP)];
5950     }
5951
5952     if (mode == ARM_CPU_MODE_IRQ) {
5953         env->xregs[16] = env->regs[14];
5954         env->xregs[17] = env->regs[13];
5955     } else {
5956         env->xregs[16] = env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)];
5957         env->xregs[17] = env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)];
5958     }
5959
5960     if (mode == ARM_CPU_MODE_SVC) {
5961         env->xregs[18] = env->regs[14];
5962         env->xregs[19] = env->regs[13];
5963     } else {
5964         env->xregs[18] = env->banked_r14[bank_number(ARM_CPU_MODE_SVC)];
5965         env->xregs[19] = env->banked_r13[bank_number(ARM_CPU_MODE_SVC)];
5966     }
5967
5968     if (mode == ARM_CPU_MODE_ABT) {
5969         env->xregs[20] = env->regs[14];
5970         env->xregs[21] = env->regs[13];
5971     } else {
5972         env->xregs[20] = env->banked_r14[bank_number(ARM_CPU_MODE_ABT)];
5973         env->xregs[21] = env->banked_r13[bank_number(ARM_CPU_MODE_ABT)];
5974     }
5975
5976     if (mode == ARM_CPU_MODE_UND) {
5977         env->xregs[22] = env->regs[14];
5978         env->xregs[23] = env->regs[13];
5979     } else {
5980         env->xregs[22] = env->banked_r14[bank_number(ARM_CPU_MODE_UND)];
5981         env->xregs[23] = env->banked_r13[bank_number(ARM_CPU_MODE_UND)];
5982     }
5983
5984     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
5985      * mode, then we can copy from r8-r14.  Otherwise, we copy from the
5986      * FIQ bank for r8-r14.
5987      */
5988     if (mode == ARM_CPU_MODE_FIQ) {
5989         for (i = 24; i < 31; i++) {
5990             env->xregs[i] = env->regs[i - 16];   /* X[24:30] <- R[8:14] */
5991         }
5992     } else {
5993         for (i = 24; i < 29; i++) {
5994             env->xregs[i] = env->fiq_regs[i - 24];
5995         }
5996         env->xregs[29] = env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)];
5997         env->xregs[30] = env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)];
5998     }
5999
6000     env->pc = env->regs[15];
6001 }
6002
6003 /* Function used to synchronize QEMU's AArch32 register set with AArch64
6004  * register set.  This is necessary when switching between AArch32 and AArch64
6005  * execution state.
6006  */
6007 void aarch64_sync_64_to_32(CPUARMState *env)
6008 {
6009     int i;
6010     uint32_t mode = env->uncached_cpsr & CPSR_M;
6011
6012     /* We can blanket copy X[0:7] to R[0:7] */
6013     for (i = 0; i < 8; i++) {
6014         env->regs[i] = env->xregs[i];
6015     }
6016
6017     /* Unless we are in FIQ mode, r8-r12 come from the user registers x8-x12.
6018      * Otherwise, we copy x8-x12 into the banked user regs.
6019      */
6020     if (mode == ARM_CPU_MODE_FIQ) {
6021         for (i = 8; i < 13; i++) {
6022             env->usr_regs[i - 8] = env->xregs[i];
6023         }
6024     } else {
6025         for (i = 8; i < 13; i++) {
6026             env->regs[i] = env->xregs[i];
6027         }
6028     }
6029
6030     /* Registers r13 & r14 depend on the current mode.
6031      * If we are in a given mode, we copy the corresponding x registers to r13
6032      * and r14.  Otherwise, we copy the x register to the banked r13 and r14
6033      * for the mode.
6034      */
6035     if (mode == ARM_CPU_MODE_USR || mode == ARM_CPU_MODE_SYS) {
6036         env->regs[13] = env->xregs[13];
6037         env->regs[14] = env->xregs[14];
6038     } else {
6039         env->banked_r13[bank_number(ARM_CPU_MODE_USR)] = env->xregs[13];
6040
6041         /* HYP is an exception in that it does not have its own banked r14 but
6042          * shares the USR r14
6043          */
6044         if (mode == ARM_CPU_MODE_HYP) {
6045             env->regs[14] = env->xregs[14];
6046         } else {
6047             env->banked_r14[bank_number(ARM_CPU_MODE_USR)] = env->xregs[14];
6048         }
6049     }
6050
6051     if (mode == ARM_CPU_MODE_HYP) {
6052         env->regs[13] = env->xregs[15];
6053     } else {
6054         env->banked_r13[bank_number(ARM_CPU_MODE_HYP)] = env->xregs[15];
6055     }
6056
6057     if (mode == ARM_CPU_MODE_IRQ) {
6058         env->regs[14] = env->xregs[16];
6059         env->regs[13] = env->xregs[17];
6060     } else {
6061         env->banked_r14[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[16];
6062         env->banked_r13[bank_number(ARM_CPU_MODE_IRQ)] = env->xregs[17];
6063     }
6064
6065     if (mode == ARM_CPU_MODE_SVC) {
6066         env->regs[14] = env->xregs[18];
6067         env->regs[13] = env->xregs[19];
6068     } else {
6069         env->banked_r14[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[18];
6070         env->banked_r13[bank_number(ARM_CPU_MODE_SVC)] = env->xregs[19];
6071     }
6072
6073     if (mode == ARM_CPU_MODE_ABT) {
6074         env->regs[14] = env->xregs[20];
6075         env->regs[13] = env->xregs[21];
6076     } else {
6077         env->banked_r14[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[20];
6078         env->banked_r13[bank_number(ARM_CPU_MODE_ABT)] = env->xregs[21];
6079     }
6080
6081     if (mode == ARM_CPU_MODE_UND) {
6082         env->regs[14] = env->xregs[22];
6083         env->regs[13] = env->xregs[23];
6084     } else {
6085         env->banked_r14[bank_number(ARM_CPU_MODE_UND)] = env->xregs[22];
6086         env->banked_r13[bank_number(ARM_CPU_MODE_UND)] = env->xregs[23];
6087     }
6088
6089     /* Registers x24-x30 are mapped to r8-r14 in FIQ mode.  If we are in FIQ
6090      * mode, then we can copy to r8-r14.  Otherwise, we copy to the
6091      * FIQ bank for r8-r14.
6092      */
6093     if (mode == ARM_CPU_MODE_FIQ) {
6094         for (i = 24; i < 31; i++) {
6095             env->regs[i - 16] = env->xregs[i];   /* X[24:30] -> R[8:14] */
6096         }
6097     } else {
6098         for (i = 24; i < 29; i++) {
6099             env->fiq_regs[i - 24] = env->xregs[i];
6100         }
6101         env->banked_r13[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[29];
6102         env->banked_r14[bank_number(ARM_CPU_MODE_FIQ)] = env->xregs[30];
6103     }
6104
6105     env->regs[15] = env->pc;
6106 }
6107
6108 static void arm_cpu_do_interrupt_aarch32(CPUState *cs)
6109 {
6110     ARMCPU *cpu = ARM_CPU(cs);
6111     CPUARMState *env = &cpu->env;
6112     uint32_t addr;
6113     uint32_t mask;
6114     int new_mode;
6115     uint32_t offset;
6116     uint32_t moe;
6117
6118     /* If this is a debug exception we must update the DBGDSCR.MOE bits */
6119     switch (env->exception.syndrome >> ARM_EL_EC_SHIFT) {
6120     case EC_BREAKPOINT:
6121     case EC_BREAKPOINT_SAME_EL:
6122         moe = 1;
6123         break;
6124     case EC_WATCHPOINT:
6125     case EC_WATCHPOINT_SAME_EL:
6126         moe = 10;
6127         break;
6128     case EC_AA32_BKPT:
6129         moe = 3;
6130         break;
6131     case EC_VECTORCATCH:
6132         moe = 5;
6133         break;
6134     default:
6135         moe = 0;
6136         break;
6137     }
6138
6139     if (moe) {
6140         env->cp15.mdscr_el1 = deposit64(env->cp15.mdscr_el1, 2, 4, moe);
6141     }
6142
6143     /* TODO: Vectored interrupt controller.  */
6144     switch (cs->exception_index) {
6145     case EXCP_UDEF:
6146         new_mode = ARM_CPU_MODE_UND;
6147         addr = 0x04;
6148         mask = CPSR_I;
6149         if (env->thumb)
6150             offset = 2;
6151         else
6152             offset = 4;
6153         break;
6154     case EXCP_SWI:
6155         new_mode = ARM_CPU_MODE_SVC;
6156         addr = 0x08;
6157         mask = CPSR_I;
6158         /* The PC already points to the next instruction.  */
6159         offset = 0;
6160         break;
6161     case EXCP_BKPT:
6162         env->exception.fsr = 2;
6163         /* Fall through to prefetch abort.  */
6164     case EXCP_PREFETCH_ABORT:
6165         A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
6166         A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
6167         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
6168                       env->exception.fsr, (uint32_t)env->exception.vaddress);
6169         new_mode = ARM_CPU_MODE_ABT;
6170         addr = 0x0c;
6171         mask = CPSR_A | CPSR_I;
6172         offset = 4;
6173         break;
6174     case EXCP_DATA_ABORT:
6175         A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
6176         A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
6177         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
6178                       env->exception.fsr,
6179                       (uint32_t)env->exception.vaddress);
6180         new_mode = ARM_CPU_MODE_ABT;
6181         addr = 0x10;
6182         mask = CPSR_A | CPSR_I;
6183         offset = 8;
6184         break;
6185     case EXCP_IRQ:
6186         new_mode = ARM_CPU_MODE_IRQ;
6187         addr = 0x18;
6188         /* Disable IRQ and imprecise data aborts.  */
6189         mask = CPSR_A | CPSR_I;
6190         offset = 4;
6191         if (env->cp15.scr_el3 & SCR_IRQ) {
6192             /* IRQ routed to monitor mode */
6193             new_mode = ARM_CPU_MODE_MON;
6194             mask |= CPSR_F;
6195         }
6196         break;
6197     case EXCP_FIQ:
6198         new_mode = ARM_CPU_MODE_FIQ;
6199         addr = 0x1c;
6200         /* Disable FIQ, IRQ and imprecise data aborts.  */
6201         mask = CPSR_A | CPSR_I | CPSR_F;
6202         if (env->cp15.scr_el3 & SCR_FIQ) {
6203             /* FIQ routed to monitor mode */
6204             new_mode = ARM_CPU_MODE_MON;
6205         }
6206         offset = 4;
6207         break;
6208     case EXCP_SMC:
6209         new_mode = ARM_CPU_MODE_MON;
6210         addr = 0x08;
6211         mask = CPSR_A | CPSR_I | CPSR_F;
6212         offset = 0;
6213         break;
6214     default:
6215         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6216         return; /* Never happens.  Keep compiler happy.  */
6217     }
6218
6219     if (new_mode == ARM_CPU_MODE_MON) {
6220         addr += env->cp15.mvbar;
6221     } else if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
6222         /* High vectors. When enabled, base address cannot be remapped. */
6223         addr += 0xffff0000;
6224     } else {
6225         /* ARM v7 architectures provide a vector base address register to remap
6226          * the interrupt vector table.
6227          * This register is only followed in non-monitor mode, and is banked.
6228          * Note: only bits 31:5 are valid.
6229          */
6230         addr += A32_BANKED_CURRENT_REG_GET(env, vbar);
6231     }
6232
6233     if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON) {
6234         env->cp15.scr_el3 &= ~SCR_NS;
6235     }
6236
6237     switch_mode (env, new_mode);
6238     /* For exceptions taken to AArch32 we must clear the SS bit in both
6239      * PSTATE and in the old-state value we save to SPSR_<mode>, so zero it now.
6240      */
6241     env->uncached_cpsr &= ~PSTATE_SS;
6242     env->spsr = cpsr_read(env);
6243     /* Clear IT bits.  */
6244     env->condexec_bits = 0;
6245     /* Switch to the new mode, and to the correct instruction set.  */
6246     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
6247     /* Set new mode endianness */
6248     env->uncached_cpsr &= ~CPSR_E;
6249     if (env->cp15.sctlr_el[arm_current_el(env)] & SCTLR_EE) {
6250         env->uncached_cpsr |= ~CPSR_E;
6251     }
6252     env->daif |= mask;
6253     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
6254      * and we should just guard the thumb mode on V4 */
6255     if (arm_feature(env, ARM_FEATURE_V4T)) {
6256         env->thumb = (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_TE) != 0;
6257     }
6258     env->regs[14] = env->regs[15] + offset;
6259     env->regs[15] = addr;
6260 }
6261
6262 /* Handle exception entry to a target EL which is using AArch64 */
6263 static void arm_cpu_do_interrupt_aarch64(CPUState *cs)
6264 {
6265     ARMCPU *cpu = ARM_CPU(cs);
6266     CPUARMState *env = &cpu->env;
6267     unsigned int new_el = env->exception.target_el;
6268     target_ulong addr = env->cp15.vbar_el[new_el];
6269     unsigned int new_mode = aarch64_pstate_mode(new_el, true);
6270
6271     if (arm_current_el(env) < new_el) {
6272         /* Entry vector offset depends on whether the implemented EL
6273          * immediately lower than the target level is using AArch32 or AArch64
6274          */
6275         bool is_aa64;
6276
6277         switch (new_el) {
6278         case 3:
6279             is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
6280             break;
6281         case 2:
6282             is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
6283             break;
6284         case 1:
6285             is_aa64 = is_a64(env);
6286             break;
6287         default:
6288             g_assert_not_reached();
6289         }
6290
6291         if (is_aa64) {
6292             addr += 0x400;
6293         } else {
6294             addr += 0x600;
6295         }
6296     } else if (pstate_read(env) & PSTATE_SP) {
6297         addr += 0x200;
6298     }
6299
6300     switch (cs->exception_index) {
6301     case EXCP_PREFETCH_ABORT:
6302     case EXCP_DATA_ABORT:
6303         env->cp15.far_el[new_el] = env->exception.vaddress;
6304         qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
6305                       env->cp15.far_el[new_el]);
6306         /* fall through */
6307     case EXCP_BKPT:
6308     case EXCP_UDEF:
6309     case EXCP_SWI:
6310     case EXCP_HVC:
6311     case EXCP_HYP_TRAP:
6312     case EXCP_SMC:
6313         env->cp15.esr_el[new_el] = env->exception.syndrome;
6314         break;
6315     case EXCP_IRQ:
6316     case EXCP_VIRQ:
6317         addr += 0x80;
6318         break;
6319     case EXCP_FIQ:
6320     case EXCP_VFIQ:
6321         addr += 0x100;
6322         break;
6323     case EXCP_SEMIHOST:
6324         qemu_log_mask(CPU_LOG_INT,
6325                       "...handling as semihosting call 0x%" PRIx64 "\n",
6326                       env->xregs[0]);
6327         env->xregs[0] = do_arm_semihosting(env);
6328         return;
6329     default:
6330         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
6331     }
6332
6333     if (is_a64(env)) {
6334         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
6335         aarch64_save_sp(env, arm_current_el(env));
6336         env->elr_el[new_el] = env->pc;
6337     } else {
6338         env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
6339         if (!env->thumb) {
6340             env->cp15.esr_el[new_el] |= 1 << 25;
6341         }
6342         env->elr_el[new_el] = env->regs[15];
6343
6344         aarch64_sync_32_to_64(env);
6345
6346         env->condexec_bits = 0;
6347     }
6348     qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
6349                   env->elr_el[new_el]);
6350
6351     pstate_write(env, PSTATE_DAIF | new_mode);
6352     env->aarch64 = 1;
6353     aarch64_restore_sp(env, new_el);
6354
6355     env->pc = addr;
6356
6357     qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n",
6358                   new_el, env->pc, pstate_read(env));
6359 }
6360
6361 static inline bool check_for_semihosting(CPUState *cs)
6362 {
6363     /* Check whether this exception is a semihosting call; if so
6364      * then handle it and return true; otherwise return false.
6365      */
6366     ARMCPU *cpu = ARM_CPU(cs);
6367     CPUARMState *env = &cpu->env;
6368
6369     if (is_a64(env)) {
6370         if (cs->exception_index == EXCP_SEMIHOST) {
6371             /* This is always the 64-bit semihosting exception.
6372              * The "is this usermode" and "is semihosting enabled"
6373              * checks have been done at translate time.
6374              */
6375             qemu_log_mask(CPU_LOG_INT,
6376                           "...handling as semihosting call 0x%" PRIx64 "\n",
6377                           env->xregs[0]);
6378             env->xregs[0] = do_arm_semihosting(env);
6379             return true;
6380         }
6381         return false;
6382     } else {
6383         uint32_t imm;
6384
6385         /* Only intercept calls from privileged modes, to provide some
6386          * semblance of security.
6387          */
6388         if (!semihosting_enabled() ||
6389             ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR)) {
6390             return false;
6391         }
6392
6393         switch (cs->exception_index) {
6394         case EXCP_SWI:
6395             /* Check for semihosting interrupt.  */
6396             if (env->thumb) {
6397                 imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env))
6398                     & 0xff;
6399                 if (imm == 0xab) {
6400                     break;
6401                 }
6402             } else {
6403                 imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env))
6404                     & 0xffffff;
6405                 if (imm == 0x123456) {
6406                     break;
6407                 }
6408             }
6409             return false;
6410         case EXCP_BKPT:
6411             /* See if this is a semihosting syscall.  */
6412             if (env->thumb) {
6413                 imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env))
6414                     & 0xff;
6415                 if (imm == 0xab) {
6416                     env->regs[15] += 2;
6417                     break;
6418                 }
6419             }
6420             return false;
6421         default:
6422             return false;
6423         }
6424
6425         qemu_log_mask(CPU_LOG_INT,
6426                       "...handling as semihosting call 0x%x\n",
6427                       env->regs[0]);
6428         env->regs[0] = do_arm_semihosting(env);
6429         return true;
6430     }
6431 }
6432
6433 /* Handle a CPU exception for A and R profile CPUs.
6434  * Do any appropriate logging, handle PSCI calls, and then hand off
6435  * to the AArch64-entry or AArch32-entry function depending on the
6436  * target exception level's register width.
6437  */
6438 void arm_cpu_do_interrupt(CPUState *cs)
6439 {
6440     ARMCPU *cpu = ARM_CPU(cs);
6441     CPUARMState *env = &cpu->env;
6442     unsigned int new_el = env->exception.target_el;
6443
6444     assert(!IS_M(env));
6445
6446     arm_log_exception(cs->exception_index);
6447     qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
6448                   new_el);
6449     if (qemu_loglevel_mask(CPU_LOG_INT)
6450         && !excp_is_internal(cs->exception_index)) {
6451         qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n",
6452                       env->exception.syndrome >> ARM_EL_EC_SHIFT,
6453                       env->exception.syndrome);
6454     }
6455
6456     if (arm_is_psci_call(cpu, cs->exception_index)) {
6457         arm_handle_psci_call(cpu);
6458         qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
6459         return;
6460     }
6461
6462     /* Semihosting semantics depend on the register width of the
6463      * code that caused the exception, not the target exception level,
6464      * so must be handled here.
6465      */
6466     if (check_for_semihosting(cs)) {
6467         return;
6468     }
6469
6470     assert(!excp_is_internal(cs->exception_index));
6471     if (arm_el_is_aa64(env, new_el)) {
6472         arm_cpu_do_interrupt_aarch64(cs);
6473     } else {
6474         arm_cpu_do_interrupt_aarch32(cs);
6475     }
6476
6477     if (!kvm_enabled()) {
6478         cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
6479     }
6480 }
6481
6482 /* Return the exception level which controls this address translation regime */
6483 static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
6484 {
6485     switch (mmu_idx) {
6486     case ARMMMUIdx_S2NS:
6487     case ARMMMUIdx_S1E2:
6488         return 2;
6489     case ARMMMUIdx_S1E3:
6490         return 3;
6491     case ARMMMUIdx_S1SE0:
6492         return arm_el_is_aa64(env, 3) ? 1 : 3;
6493     case ARMMMUIdx_S1SE1:
6494     case ARMMMUIdx_S1NSE0:
6495     case ARMMMUIdx_S1NSE1:
6496         return 1;
6497     default:
6498         g_assert_not_reached();
6499     }
6500 }
6501
6502 /* Return true if this address translation regime is secure */
6503 static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
6504 {
6505     switch (mmu_idx) {
6506     case ARMMMUIdx_S12NSE0:
6507     case ARMMMUIdx_S12NSE1:
6508     case ARMMMUIdx_S1NSE0:
6509     case ARMMMUIdx_S1NSE1:
6510     case ARMMMUIdx_S1E2:
6511     case ARMMMUIdx_S2NS:
6512         return false;
6513     case ARMMMUIdx_S1E3:
6514     case ARMMMUIdx_S1SE0:
6515     case ARMMMUIdx_S1SE1:
6516         return true;
6517     default:
6518         g_assert_not_reached();
6519     }
6520 }
6521
6522 /* Return the SCTLR value which controls this address translation regime */
6523 static inline uint32_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx)
6524 {
6525     return env->cp15.sctlr_el[regime_el(env, mmu_idx)];
6526 }
6527
6528 /* Return true if the specified stage of address translation is disabled */
6529 static inline bool regime_translation_disabled(CPUARMState *env,
6530                                                ARMMMUIdx mmu_idx)
6531 {
6532     if (mmu_idx == ARMMMUIdx_S2NS) {
6533         return (env->cp15.hcr_el2 & HCR_VM) == 0;
6534     }
6535     return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
6536 }
6537
6538 static inline bool regime_translation_big_endian(CPUARMState *env,
6539                                                  ARMMMUIdx mmu_idx)
6540 {
6541     return (regime_sctlr(env, mmu_idx) & SCTLR_EE) != 0;
6542 }
6543
6544 /* Return the TCR controlling this translation regime */
6545 static inline TCR *regime_tcr(CPUARMState *env, ARMMMUIdx mmu_idx)
6546 {
6547     if (mmu_idx == ARMMMUIdx_S2NS) {
6548         return &env->cp15.vtcr_el2;
6549     }
6550     return &env->cp15.tcr_el[regime_el(env, mmu_idx)];
6551 }
6552
6553 /* Return the TTBR associated with this translation regime */
6554 static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
6555                                    int ttbrn)
6556 {
6557     if (mmu_idx == ARMMMUIdx_S2NS) {
6558         return env->cp15.vttbr_el2;
6559     }
6560     if (ttbrn == 0) {
6561         return env->cp15.ttbr0_el[regime_el(env, mmu_idx)];
6562     } else {
6563         return env->cp15.ttbr1_el[regime_el(env, mmu_idx)];
6564     }
6565 }
6566
6567 /* Return true if the translation regime is using LPAE format page tables */
6568 static inline bool regime_using_lpae_format(CPUARMState *env,
6569                                             ARMMMUIdx mmu_idx)
6570 {
6571     int el = regime_el(env, mmu_idx);
6572     if (el == 2 || arm_el_is_aa64(env, el)) {
6573         return true;
6574     }
6575     if (arm_feature(env, ARM_FEATURE_LPAE)
6576         && (regime_tcr(env, mmu_idx)->raw_tcr & TTBCR_EAE)) {
6577         return true;
6578     }
6579     return false;
6580 }
6581
6582 /* Returns true if the stage 1 translation regime is using LPAE format page
6583  * tables. Used when raising alignment exceptions, whose FSR changes depending
6584  * on whether the long or short descriptor format is in use. */
6585 bool arm_s1_regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mmu_idx)
6586 {
6587     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
6588         mmu_idx += ARMMMUIdx_S1NSE0;
6589     }
6590
6591     return regime_using_lpae_format(env, mmu_idx);
6592 }
6593
6594 static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
6595 {
6596     switch (mmu_idx) {
6597     case ARMMMUIdx_S1SE0:
6598     case ARMMMUIdx_S1NSE0:
6599         return true;
6600     default:
6601         return false;
6602     case ARMMMUIdx_S12NSE0:
6603     case ARMMMUIdx_S12NSE1:
6604         g_assert_not_reached();
6605     }
6606 }
6607
6608 /* Translate section/page access permissions to page
6609  * R/W protection flags
6610  *
6611  * @env:         CPUARMState
6612  * @mmu_idx:     MMU index indicating required translation regime
6613  * @ap:          The 3-bit access permissions (AP[2:0])
6614  * @domain_prot: The 2-bit domain access permissions
6615  */
6616 static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx,
6617                                 int ap, int domain_prot)
6618 {
6619     bool is_user = regime_is_user(env, mmu_idx);
6620
6621     if (domain_prot == 3) {
6622         return PAGE_READ | PAGE_WRITE;
6623     }
6624
6625     switch (ap) {
6626     case 0:
6627         if (arm_feature(env, ARM_FEATURE_V7)) {
6628             return 0;
6629         }
6630         switch (regime_sctlr(env, mmu_idx) & (SCTLR_S | SCTLR_R)) {
6631         case SCTLR_S:
6632             return is_user ? 0 : PAGE_READ;
6633         case SCTLR_R:
6634             return PAGE_READ;
6635         default:
6636             return 0;
6637         }
6638     case 1:
6639         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6640     case 2:
6641         if (is_user) {
6642             return PAGE_READ;
6643         } else {
6644             return PAGE_READ | PAGE_WRITE;
6645         }
6646     case 3:
6647         return PAGE_READ | PAGE_WRITE;
6648     case 4: /* Reserved.  */
6649         return 0;
6650     case 5:
6651         return is_user ? 0 : PAGE_READ;
6652     case 6:
6653         return PAGE_READ;
6654     case 7:
6655         if (!arm_feature(env, ARM_FEATURE_V6K)) {
6656             return 0;
6657         }
6658         return PAGE_READ;
6659     default:
6660         g_assert_not_reached();
6661     }
6662 }
6663
6664 /* Translate section/page access permissions to page
6665  * R/W protection flags.
6666  *
6667  * @ap:      The 2-bit simple AP (AP[2:1])
6668  * @is_user: TRUE if accessing from PL0
6669  */
6670 static inline int simple_ap_to_rw_prot_is_user(int ap, bool is_user)
6671 {
6672     switch (ap) {
6673     case 0:
6674         return is_user ? 0 : PAGE_READ | PAGE_WRITE;
6675     case 1:
6676         return PAGE_READ | PAGE_WRITE;
6677     case 2:
6678         return is_user ? 0 : PAGE_READ;
6679     case 3:
6680         return PAGE_READ;
6681     default:
6682         g_assert_not_reached();
6683     }
6684 }
6685
6686 static inline int
6687 simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap)
6688 {
6689     return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx));
6690 }
6691
6692 /* Translate S2 section/page access permissions to protection flags
6693  *
6694  * @env:     CPUARMState
6695  * @s2ap:    The 2-bit stage2 access permissions (S2AP)
6696  * @xn:      XN (execute-never) bit
6697  */
6698 static int get_S2prot(CPUARMState *env, int s2ap, int xn)
6699 {
6700     int prot = 0;
6701
6702     if (s2ap & 1) {
6703         prot |= PAGE_READ;
6704     }
6705     if (s2ap & 2) {
6706         prot |= PAGE_WRITE;
6707     }
6708     if (!xn) {
6709         prot |= PAGE_EXEC;
6710     }
6711     return prot;
6712 }
6713
6714 /* Translate section/page access permissions to protection flags
6715  *
6716  * @env:     CPUARMState
6717  * @mmu_idx: MMU index indicating required translation regime
6718  * @is_aa64: TRUE if AArch64
6719  * @ap:      The 2-bit simple AP (AP[2:1])
6720  * @ns:      NS (non-secure) bit
6721  * @xn:      XN (execute-never) bit
6722  * @pxn:     PXN (privileged execute-never) bit
6723  */
6724 static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu_idx, bool is_aa64,
6725                       int ap, int ns, int xn, int pxn)
6726 {
6727     bool is_user = regime_is_user(env, mmu_idx);
6728     int prot_rw, user_rw;
6729     bool have_wxn;
6730     int wxn = 0;
6731
6732     assert(mmu_idx != ARMMMUIdx_S2NS);
6733
6734     user_rw = simple_ap_to_rw_prot_is_user(ap, true);
6735     if (is_user) {
6736         prot_rw = user_rw;
6737     } else {
6738         prot_rw = simple_ap_to_rw_prot_is_user(ap, false);
6739     }
6740
6741     if (ns && arm_is_secure(env) && (env->cp15.scr_el3 & SCR_SIF)) {
6742         return prot_rw;
6743     }
6744
6745     /* TODO have_wxn should be replaced with
6746      *   ARM_FEATURE_V8 || (ARM_FEATURE_V7 && ARM_FEATURE_EL2)
6747      * when ARM_FEATURE_EL2 starts getting set. For now we assume all LPAE
6748      * compatible processors have EL2, which is required for [U]WXN.
6749      */
6750     have_wxn = arm_feature(env, ARM_FEATURE_LPAE);
6751
6752     if (have_wxn) {
6753         wxn = regime_sctlr(env, mmu_idx) & SCTLR_WXN;
6754     }
6755
6756     if (is_aa64) {
6757         switch (regime_el(env, mmu_idx)) {
6758         case 1:
6759             if (!is_user) {
6760                 xn = pxn || (user_rw & PAGE_WRITE);
6761             }
6762             break;
6763         case 2:
6764         case 3:
6765             break;
6766         }
6767     } else if (arm_feature(env, ARM_FEATURE_V7)) {
6768         switch (regime_el(env, mmu_idx)) {
6769         case 1:
6770         case 3:
6771             if (is_user) {
6772                 xn = xn || !(user_rw & PAGE_READ);
6773             } else {
6774                 int uwxn = 0;
6775                 if (have_wxn) {
6776                     uwxn = regime_sctlr(env, mmu_idx) & SCTLR_UWXN;
6777                 }
6778                 xn = xn || !(prot_rw & PAGE_READ) || pxn ||
6779                      (uwxn && (user_rw & PAGE_WRITE));
6780             }
6781             break;
6782         case 2:
6783             break;
6784         }
6785     } else {
6786         xn = wxn = 0;
6787     }
6788
6789     if (xn || (wxn && (prot_rw & PAGE_WRITE))) {
6790         return prot_rw;
6791     }
6792     return prot_rw | PAGE_EXEC;
6793 }
6794
6795 static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx,
6796                                      uint32_t *table, uint32_t address)
6797 {
6798     /* Note that we can only get here for an AArch32 PL0/PL1 lookup */
6799     TCR *tcr = regime_tcr(env, mmu_idx);
6800
6801     if (address & tcr->mask) {
6802         if (tcr->raw_tcr & TTBCR_PD1) {
6803             /* Translation table walk disabled for TTBR1 */
6804             return false;
6805         }
6806         *table = regime_ttbr(env, mmu_idx, 1) & 0xffffc000;
6807     } else {
6808         if (tcr->raw_tcr & TTBCR_PD0) {
6809             /* Translation table walk disabled for TTBR0 */
6810             return false;
6811         }
6812         *table = regime_ttbr(env, mmu_idx, 0) & tcr->base_mask;
6813     }
6814     *table |= (address >> 18) & 0x3ffc;
6815     return true;
6816 }
6817
6818 /* Translate a S1 pagetable walk through S2 if needed.  */
6819 static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
6820                                hwaddr addr, MemTxAttrs txattrs,
6821                                uint32_t *fsr,
6822                                ARMMMUFaultInfo *fi)
6823 {
6824     if ((mmu_idx == ARMMMUIdx_S1NSE0 || mmu_idx == ARMMMUIdx_S1NSE1) &&
6825         !regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
6826         target_ulong s2size;
6827         hwaddr s2pa;
6828         int s2prot;
6829         int ret;
6830
6831         ret = get_phys_addr_lpae(env, addr, 0, ARMMMUIdx_S2NS, &s2pa,
6832                                  &txattrs, &s2prot, &s2size, fsr, fi);
6833         if (ret) {
6834             fi->s2addr = addr;
6835             fi->stage2 = true;
6836             fi->s1ptw = true;
6837             return ~0;
6838         }
6839         addr = s2pa;
6840     }
6841     return addr;
6842 }
6843
6844 /* All loads done in the course of a page table walk go through here.
6845  * TODO: rather than ignoring errors from physical memory reads (which
6846  * are external aborts in ARM terminology) we should propagate this
6847  * error out so that we can turn it into a Data Abort if this walk
6848  * was being done for a CPU load/store or an address translation instruction
6849  * (but not if it was for a debug access).
6850  */
6851 static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6852                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6853                             ARMMMUFaultInfo *fi)
6854 {
6855     ARMCPU *cpu = ARM_CPU(cs);
6856     CPUARMState *env = &cpu->env;
6857     MemTxAttrs attrs = {};
6858     AddressSpace *as;
6859
6860     attrs.secure = is_secure;
6861     as = arm_addressspace(cs, attrs);
6862     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6863     if (fi->s1ptw) {
6864         return 0;
6865     }
6866     if (regime_translation_big_endian(env, mmu_idx)) {
6867         return address_space_ldl_be(as, addr, attrs, NULL);
6868     } else {
6869         return address_space_ldl_le(as, addr, attrs, NULL);
6870     }
6871 }
6872
6873 static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
6874                             ARMMMUIdx mmu_idx, uint32_t *fsr,
6875                             ARMMMUFaultInfo *fi)
6876 {
6877     ARMCPU *cpu = ARM_CPU(cs);
6878     CPUARMState *env = &cpu->env;
6879     MemTxAttrs attrs = {};
6880     AddressSpace *as;
6881
6882     attrs.secure = is_secure;
6883     as = arm_addressspace(cs, attrs);
6884     addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
6885     if (fi->s1ptw) {
6886         return 0;
6887     }
6888     if (regime_translation_big_endian(env, mmu_idx)) {
6889         return address_space_ldq_be(as, addr, attrs, NULL);
6890     } else {
6891         return address_space_ldq_le(as, addr, attrs, NULL);
6892     }
6893 }
6894
6895 static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
6896                              int access_type, ARMMMUIdx mmu_idx,
6897                              hwaddr *phys_ptr, int *prot,
6898                              target_ulong *page_size, uint32_t *fsr,
6899                              ARMMMUFaultInfo *fi)
6900 {
6901     CPUState *cs = CPU(arm_env_get_cpu(env));
6902     int code;
6903     uint32_t table;
6904     uint32_t desc;
6905     int type;
6906     int ap;
6907     int domain = 0;
6908     int domain_prot;
6909     hwaddr phys_addr;
6910     uint32_t dacr;
6911
6912     /* Pagetable walk.  */
6913     /* Lookup l1 descriptor.  */
6914     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
6915         /* Section translation fault if page walk is disabled by PD0 or PD1 */
6916         code = 5;
6917         goto do_fault;
6918     }
6919     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6920                        mmu_idx, fsr, fi);
6921     type = (desc & 3);
6922     domain = (desc >> 5) & 0x0f;
6923     if (regime_el(env, mmu_idx) == 1) {
6924         dacr = env->cp15.dacr_ns;
6925     } else {
6926         dacr = env->cp15.dacr_s;
6927     }
6928     domain_prot = (dacr >> (domain * 2)) & 3;
6929     if (type == 0) {
6930         /* Section translation fault.  */
6931         code = 5;
6932         goto do_fault;
6933     }
6934     if (domain_prot == 0 || domain_prot == 2) {
6935         if (type == 2)
6936             code = 9; /* Section domain fault.  */
6937         else
6938             code = 11; /* Page domain fault.  */
6939         goto do_fault;
6940     }
6941     if (type == 2) {
6942         /* 1Mb section.  */
6943         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
6944         ap = (desc >> 10) & 3;
6945         code = 13;
6946         *page_size = 1024 * 1024;
6947     } else {
6948         /* Lookup l2 entry.  */
6949         if (type == 1) {
6950             /* Coarse pagetable.  */
6951             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
6952         } else {
6953             /* Fine pagetable.  */
6954             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
6955         }
6956         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
6957                            mmu_idx, fsr, fi);
6958         switch (desc & 3) {
6959         case 0: /* Page translation fault.  */
6960             code = 7;
6961             goto do_fault;
6962         case 1: /* 64k page.  */
6963             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
6964             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
6965             *page_size = 0x10000;
6966             break;
6967         case 2: /* 4k page.  */
6968             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6969             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
6970             *page_size = 0x1000;
6971             break;
6972         case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
6973             if (type == 1) {
6974                 /* ARMv6/XScale extended small page format */
6975                 if (arm_feature(env, ARM_FEATURE_XSCALE)
6976                     || arm_feature(env, ARM_FEATURE_V6)) {
6977                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
6978                     *page_size = 0x1000;
6979                 } else {
6980                     /* UNPREDICTABLE in ARMv5; we choose to take a
6981                      * page translation fault.
6982                      */
6983                     code = 7;
6984                     goto do_fault;
6985                 }
6986             } else {
6987                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
6988                 *page_size = 0x400;
6989             }
6990             ap = (desc >> 4) & 3;
6991             break;
6992         default:
6993             /* Never happens, but compiler isn't smart enough to tell.  */
6994             abort();
6995         }
6996         code = 15;
6997     }
6998     *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
6999     *prot |= *prot ? PAGE_EXEC : 0;
7000     if (!(*prot & (1 << access_type))) {
7001         /* Access permission fault.  */
7002         goto do_fault;
7003     }
7004     *phys_ptr = phys_addr;
7005     return false;
7006 do_fault:
7007     *fsr = code | (domain << 4);
7008     return true;
7009 }
7010
7011 static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
7012                              int access_type, ARMMMUIdx mmu_idx,
7013                              hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7014                              target_ulong *page_size, uint32_t *fsr,
7015                              ARMMMUFaultInfo *fi)
7016 {
7017     CPUState *cs = CPU(arm_env_get_cpu(env));
7018     int code;
7019     uint32_t table;
7020     uint32_t desc;
7021     uint32_t xn;
7022     uint32_t pxn = 0;
7023     int type;
7024     int ap;
7025     int domain = 0;
7026     int domain_prot;
7027     hwaddr phys_addr;
7028     uint32_t dacr;
7029     bool ns;
7030
7031     /* Pagetable walk.  */
7032     /* Lookup l1 descriptor.  */
7033     if (!get_level1_table_address(env, mmu_idx, &table, address)) {
7034         /* Section translation fault if page walk is disabled by PD0 or PD1 */
7035         code = 5;
7036         goto do_fault;
7037     }
7038     desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7039                        mmu_idx, fsr, fi);
7040     type = (desc & 3);
7041     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
7042         /* Section translation fault, or attempt to use the encoding
7043          * which is Reserved on implementations without PXN.
7044          */
7045         code = 5;
7046         goto do_fault;
7047     }
7048     if ((type == 1) || !(desc & (1 << 18))) {
7049         /* Page or Section.  */
7050         domain = (desc >> 5) & 0x0f;
7051     }
7052     if (regime_el(env, mmu_idx) == 1) {
7053         dacr = env->cp15.dacr_ns;
7054     } else {
7055         dacr = env->cp15.dacr_s;
7056     }
7057     domain_prot = (dacr >> (domain * 2)) & 3;
7058     if (domain_prot == 0 || domain_prot == 2) {
7059         if (type != 1) {
7060             code = 9; /* Section domain fault.  */
7061         } else {
7062             code = 11; /* Page domain fault.  */
7063         }
7064         goto do_fault;
7065     }
7066     if (type != 1) {
7067         if (desc & (1 << 18)) {
7068             /* Supersection.  */
7069             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
7070             phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
7071             phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
7072             *page_size = 0x1000000;
7073         } else {
7074             /* Section.  */
7075             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
7076             *page_size = 0x100000;
7077         }
7078         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
7079         xn = desc & (1 << 4);
7080         pxn = desc & 1;
7081         code = 13;
7082         ns = extract32(desc, 19, 1);
7083     } else {
7084         if (arm_feature(env, ARM_FEATURE_PXN)) {
7085             pxn = (desc >> 2) & 1;
7086         }
7087         ns = extract32(desc, 3, 1);
7088         /* Lookup l2 entry.  */
7089         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
7090         desc = arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx),
7091                            mmu_idx, fsr, fi);
7092         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
7093         switch (desc & 3) {
7094         case 0: /* Page translation fault.  */
7095             code = 7;
7096             goto do_fault;
7097         case 1: /* 64k page.  */
7098             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
7099             xn = desc & (1 << 15);
7100             *page_size = 0x10000;
7101             break;
7102         case 2: case 3: /* 4k page.  */
7103             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
7104             xn = desc & 1;
7105             *page_size = 0x1000;
7106             break;
7107         default:
7108             /* Never happens, but compiler isn't smart enough to tell.  */
7109             abort();
7110         }
7111         code = 15;
7112     }
7113     if (domain_prot == 3) {
7114         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7115     } else {
7116         if (pxn && !regime_is_user(env, mmu_idx)) {
7117             xn = 1;
7118         }
7119         if (xn && access_type == 2)
7120             goto do_fault;
7121
7122         if (arm_feature(env, ARM_FEATURE_V6K) &&
7123                 (regime_sctlr(env, mmu_idx) & SCTLR_AFE)) {
7124             /* The simplified model uses AP[0] as an access control bit.  */
7125             if ((ap & 1) == 0) {
7126                 /* Access flag fault.  */
7127                 code = (code == 15) ? 6 : 3;
7128                 goto do_fault;
7129             }
7130             *prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
7131         } else {
7132             *prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
7133         }
7134         if (*prot && !xn) {
7135             *prot |= PAGE_EXEC;
7136         }
7137         if (!(*prot & (1 << access_type))) {
7138             /* Access permission fault.  */
7139             goto do_fault;
7140         }
7141     }
7142     if (ns) {
7143         /* The NS bit will (as required by the architecture) have no effect if
7144          * the CPU doesn't support TZ or this is a non-secure translation
7145          * regime, because the attribute will already be non-secure.
7146          */
7147         attrs->secure = false;
7148     }
7149     *phys_ptr = phys_addr;
7150     return false;
7151 do_fault:
7152     *fsr = code | (domain << 4);
7153     return true;
7154 }
7155
7156 /* Fault type for long-descriptor MMU fault reporting; this corresponds
7157  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
7158  */
7159 typedef enum {
7160     translation_fault = 1,
7161     access_fault = 2,
7162     permission_fault = 3,
7163 } MMUFaultType;
7164
7165 /*
7166  * check_s2_mmu_setup
7167  * @cpu:        ARMCPU
7168  * @is_aa64:    True if the translation regime is in AArch64 state
7169  * @startlevel: Suggested starting level
7170  * @inputsize:  Bitsize of IPAs
7171  * @stride:     Page-table stride (See the ARM ARM)
7172  *
7173  * Returns true if the suggested S2 translation parameters are OK and
7174  * false otherwise.
7175  */
7176 static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
7177                                int inputsize, int stride)
7178 {
7179     const int grainsize = stride + 3;
7180     int startsizecheck;
7181
7182     /* Negative levels are never allowed.  */
7183     if (level < 0) {
7184         return false;
7185     }
7186
7187     startsizecheck = inputsize - ((3 - level) * stride + grainsize);
7188     if (startsizecheck < 1 || startsizecheck > stride + 4) {
7189         return false;
7190     }
7191
7192     if (is_aa64) {
7193         CPUARMState *env = &cpu->env;
7194         unsigned int pamax = arm_pamax(cpu);
7195
7196         switch (stride) {
7197         case 13: /* 64KB Pages.  */
7198             if (level == 0 || (level == 1 && pamax <= 42)) {
7199                 return false;
7200             }
7201             break;
7202         case 11: /* 16KB Pages.  */
7203             if (level == 0 || (level == 1 && pamax <= 40)) {
7204                 return false;
7205             }
7206             break;
7207         case 9: /* 4KB Pages.  */
7208             if (level == 0 && pamax <= 42) {
7209                 return false;
7210             }
7211             break;
7212         default:
7213             g_assert_not_reached();
7214         }
7215
7216         /* Inputsize checks.  */
7217         if (inputsize > pamax &&
7218             (arm_el_is_aa64(env, 1) || inputsize > 40)) {
7219             /* This is CONSTRAINED UNPREDICTABLE and we choose to fault.  */
7220             return false;
7221         }
7222     } else {
7223         /* AArch32 only supports 4KB pages. Assert on that.  */
7224         assert(stride == 9);
7225
7226         if (level == 0) {
7227             return false;
7228         }
7229     }
7230     return true;
7231 }
7232
7233 static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
7234                                int access_type, ARMMMUIdx mmu_idx,
7235                                hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
7236                                target_ulong *page_size_ptr, uint32_t *fsr,
7237                                ARMMMUFaultInfo *fi)
7238 {
7239     ARMCPU *cpu = arm_env_get_cpu(env);
7240     CPUState *cs = CPU(cpu);
7241     /* Read an LPAE long-descriptor translation table. */
7242     MMUFaultType fault_type = translation_fault;
7243     uint32_t level;
7244     uint32_t epd = 0;
7245     int32_t t0sz, t1sz;
7246     uint32_t tg;
7247     uint64_t ttbr;
7248     int ttbr_select;
7249     hwaddr descaddr, descmask;
7250     uint32_t tableattrs;
7251     target_ulong page_size;
7252     uint32_t attrs;
7253     int32_t stride = 9;
7254     int32_t va_size;
7255     int inputsize;
7256     int32_t tbi = 0;
7257     TCR *tcr = regime_tcr(env, mmu_idx);
7258     int ap, ns, xn, pxn;
7259     uint32_t el = regime_el(env, mmu_idx);
7260     bool ttbr1_valid = true;
7261     uint64_t descaddrmask;
7262
7263     /* TODO:
7264      * This code does not handle the different format TCR for VTCR_EL2.
7265      * This code also does not support shareability levels.
7266      * Attribute and permission bit handling should also be checked when adding
7267      * support for those page table walks.
7268      */
7269     if (arm_el_is_aa64(env, el)) {
7270         level = 0;
7271         va_size = 64;
7272         if (el > 1) {
7273             if (mmu_idx != ARMMMUIdx_S2NS) {
7274                 tbi = extract64(tcr->raw_tcr, 20, 1);
7275             }
7276         } else {
7277             if (extract64(address, 55, 1)) {
7278                 tbi = extract64(tcr->raw_tcr, 38, 1);
7279             } else {
7280                 tbi = extract64(tcr->raw_tcr, 37, 1);
7281             }
7282         }
7283         tbi *= 8;
7284
7285         /* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
7286          * invalid.
7287          */
7288         if (el > 1) {
7289             ttbr1_valid = false;
7290         }
7291     } else {
7292         level = 1;
7293         va_size = 32;
7294         /* There is no TTBR1 for EL2 */
7295         if (el == 2) {
7296             ttbr1_valid = false;
7297         }
7298     }
7299
7300     /* Determine whether this address is in the region controlled by
7301      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
7302      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
7303      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
7304      */
7305     if (va_size == 64) {
7306         /* AArch64 translation.  */
7307         t0sz = extract32(tcr->raw_tcr, 0, 6);
7308         t0sz = MIN(t0sz, 39);
7309         t0sz = MAX(t0sz, 16);
7310     } else if (mmu_idx != ARMMMUIdx_S2NS) {
7311         /* AArch32 stage 1 translation.  */
7312         t0sz = extract32(tcr->raw_tcr, 0, 3);
7313     } else {
7314         /* AArch32 stage 2 translation.  */
7315         bool sext = extract32(tcr->raw_tcr, 4, 1);
7316         bool sign = extract32(tcr->raw_tcr, 3, 1);
7317         t0sz = sextract32(tcr->raw_tcr, 0, 4);
7318
7319         /* If the sign-extend bit is not the same as t0sz[3], the result
7320          * is unpredictable. Flag this as a guest error.  */
7321         if (sign != sext) {
7322             qemu_log_mask(LOG_GUEST_ERROR,
7323                           "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
7324         }
7325     }
7326     t1sz = extract32(tcr->raw_tcr, 16, 6);
7327     if (va_size == 64) {
7328         t1sz = MIN(t1sz, 39);
7329         t1sz = MAX(t1sz, 16);
7330     }
7331     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
7332         /* there is a ttbr0 region and we are in it (high bits all zero) */
7333         ttbr_select = 0;
7334     } else if (ttbr1_valid && t1sz &&
7335                !extract64(~address, va_size - t1sz, t1sz - tbi)) {
7336         /* there is a ttbr1 region and we are in it (high bits all one) */
7337         ttbr_select = 1;
7338     } else if (!t0sz) {
7339         /* ttbr0 region is "everything not in the ttbr1 region" */
7340         ttbr_select = 0;
7341     } else if (!t1sz && ttbr1_valid) {
7342         /* ttbr1 region is "everything not in the ttbr0 region" */
7343         ttbr_select = 1;
7344     } else {
7345         /* in the gap between the two regions, this is a Translation fault */
7346         fault_type = translation_fault;
7347         goto do_fault;
7348     }
7349
7350     /* Note that QEMU ignores shareability and cacheability attributes,
7351      * so we don't need to do anything with the SH, ORGN, IRGN fields
7352      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
7353      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
7354      * implement any ASID-like capability so we can ignore it (instead
7355      * we will always flush the TLB any time the ASID is changed).
7356      */
7357     if (ttbr_select == 0) {
7358         ttbr = regime_ttbr(env, mmu_idx, 0);
7359         if (el < 2) {
7360             epd = extract32(tcr->raw_tcr, 7, 1);
7361         }
7362         inputsize = va_size - t0sz;
7363
7364         tg = extract32(tcr->raw_tcr, 14, 2);
7365         if (tg == 1) { /* 64KB pages */
7366             stride = 13;
7367         }
7368         if (tg == 2) { /* 16KB pages */
7369             stride = 11;
7370         }
7371     } else {
7372         /* We should only be here if TTBR1 is valid */
7373         assert(ttbr1_valid);
7374
7375         ttbr = regime_ttbr(env, mmu_idx, 1);
7376         epd = extract32(tcr->raw_tcr, 23, 1);
7377         inputsize = va_size - t1sz;
7378
7379         tg = extract32(tcr->raw_tcr, 30, 2);
7380         if (tg == 3)  { /* 64KB pages */
7381             stride = 13;
7382         }
7383         if (tg == 1) { /* 16KB pages */
7384             stride = 11;
7385         }
7386     }
7387
7388     /* Here we should have set up all the parameters for the translation:
7389      * va_size, inputsize, ttbr, epd, stride, tbi
7390      */
7391
7392     if (epd) {
7393         /* Translation table walk disabled => Translation fault on TLB miss
7394          * Note: This is always 0 on 64-bit EL2 and EL3.
7395          */
7396         goto do_fault;
7397     }
7398
7399     if (mmu_idx != ARMMMUIdx_S2NS) {
7400         /* The starting level depends on the virtual address size (which can
7401          * be up to 48 bits) and the translation granule size. It indicates
7402          * the number of strides (stride bits at a time) needed to
7403          * consume the bits of the input address. In the pseudocode this is:
7404          *  level = 4 - RoundUp((inputsize - grainsize) / stride)
7405          * where their 'inputsize' is our 'inputsize', 'grainsize' is
7406          * our 'stride + 3' and 'stride' is our 'stride'.
7407          * Applying the usual "rounded up m/n is (m+n-1)/n" and simplifying:
7408          * = 4 - (inputsize - stride - 3 + stride - 1) / stride
7409          * = 4 - (inputsize - 4) / stride;
7410          */
7411         level = 4 - (inputsize - 4) / stride;
7412     } else {
7413         /* For stage 2 translations the starting level is specified by the
7414          * VTCR_EL2.SL0 field (whose interpretation depends on the page size)
7415          */
7416         uint32_t sl0 = extract32(tcr->raw_tcr, 6, 2);
7417         uint32_t startlevel;
7418         bool ok;
7419
7420         if (va_size == 32 || stride == 9) {
7421             /* AArch32 or 4KB pages */
7422             startlevel = 2 - sl0;
7423         } else {
7424             /* 16KB or 64KB pages */
7425             startlevel = 3 - sl0;
7426         }
7427
7428         /* Check that the starting level is valid. */
7429         ok = check_s2_mmu_setup(cpu, va_size == 64, startlevel,
7430                                 inputsize, stride);
7431         if (!ok) {
7432             fault_type = translation_fault;
7433             goto do_fault;
7434         }
7435         level = startlevel;
7436     }
7437
7438     /* Clear the vaddr bits which aren't part of the within-region address,
7439      * so that we don't have to special case things when calculating the
7440      * first descriptor address.
7441      */
7442     if (va_size != inputsize) {
7443         address &= (1ULL << inputsize) - 1;
7444     }
7445
7446     descmask = (1ULL << (stride + 3)) - 1;
7447
7448     /* Now we can extract the actual base address from the TTBR */
7449     descaddr = extract64(ttbr, 0, 48);
7450     descaddr &= ~((1ULL << (inputsize - (stride * (4 - level)))) - 1);
7451
7452     /* The address field in the descriptor goes up to bit 39 for ARMv7
7453      * but up to bit 47 for ARMv8.
7454      */
7455     if (arm_feature(env, ARM_FEATURE_V8)) {
7456         descaddrmask = 0xfffffffff000ULL;
7457     } else {
7458         descaddrmask = 0xfffffff000ULL;
7459     }
7460
7461     /* Secure accesses start with the page table in secure memory and
7462      * can be downgraded to non-secure at any step. Non-secure accesses
7463      * remain non-secure. We implement this by just ORing in the NSTable/NS
7464      * bits at each step.
7465      */
7466     tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
7467     for (;;) {
7468         uint64_t descriptor;
7469         bool nstable;
7470
7471         descaddr |= (address >> (stride * (4 - level))) & descmask;
7472         descaddr &= ~7ULL;
7473         nstable = extract32(tableattrs, 4, 1);
7474         descriptor = arm_ldq_ptw(cs, descaddr, !nstable, mmu_idx, fsr, fi);
7475         if (fi->s1ptw) {
7476             goto do_fault;
7477         }
7478
7479         if (!(descriptor & 1) ||
7480             (!(descriptor & 2) && (level == 3))) {
7481             /* Invalid, or the Reserved level 3 encoding */
7482             goto do_fault;
7483         }
7484         descaddr = descriptor & descaddrmask;
7485
7486         if ((descriptor & 2) && (level < 3)) {
7487             /* Table entry. The top five bits are attributes which  may
7488              * propagate down through lower levels of the table (and
7489              * which are all arranged so that 0 means "no effect", so
7490              * we can gather them up by ORing in the bits at each level).
7491              */
7492             tableattrs |= extract64(descriptor, 59, 5);
7493             level++;
7494             continue;
7495         }
7496         /* Block entry at level 1 or 2, or page entry at level 3.
7497          * These are basically the same thing, although the number
7498          * of bits we pull in from the vaddr varies.
7499          */
7500         page_size = (1ULL << ((stride * (4 - level)) + 3));
7501         descaddr |= (address & (page_size - 1));
7502         /* Extract attributes from the descriptor */
7503         attrs = extract64(descriptor, 2, 10)
7504             | (extract64(descriptor, 52, 12) << 10);
7505
7506         if (mmu_idx == ARMMMUIdx_S2NS) {
7507             /* Stage 2 table descriptors do not include any attribute fields */
7508             break;
7509         }
7510         /* Merge in attributes from table descriptors */
7511         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
7512         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
7513         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
7514          * means "force PL1 access only", which means forcing AP[1] to 0.
7515          */
7516         if (extract32(tableattrs, 2, 1)) {
7517             attrs &= ~(1 << 4);
7518         }
7519         attrs |= nstable << 3; /* NS */
7520         break;
7521     }
7522     /* Here descaddr is the final physical address, and attributes
7523      * are all in attrs.
7524      */
7525     fault_type = access_fault;
7526     if ((attrs & (1 << 8)) == 0) {
7527         /* Access flag */
7528         goto do_fault;
7529     }
7530
7531     ap = extract32(attrs, 4, 2);
7532     xn = extract32(attrs, 12, 1);
7533
7534     if (mmu_idx == ARMMMUIdx_S2NS) {
7535         ns = true;
7536         *prot = get_S2prot(env, ap, xn);
7537     } else {
7538         ns = extract32(attrs, 3, 1);
7539         pxn = extract32(attrs, 11, 1);
7540         *prot = get_S1prot(env, mmu_idx, va_size == 64, ap, ns, xn, pxn);
7541     }
7542
7543     fault_type = permission_fault;
7544     if (!(*prot & (1 << access_type))) {
7545         goto do_fault;
7546     }
7547
7548     if (ns) {
7549         /* The NS bit will (as required by the architecture) have no effect if
7550          * the CPU doesn't support TZ or this is a non-secure translation
7551          * regime, because the attribute will already be non-secure.
7552          */
7553         txattrs->secure = false;
7554     }
7555     *phys_ptr = descaddr;
7556     *page_size_ptr = page_size;
7557     return false;
7558
7559 do_fault:
7560     /* Long-descriptor format IFSR/DFSR value */
7561     *fsr = (1 << 9) | (fault_type << 2) | level;
7562     /* Tag the error as S2 for failed S1 PTW at S2 or ordinary S2.  */
7563     fi->stage2 = fi->s1ptw || (mmu_idx == ARMMMUIdx_S2NS);
7564     return true;
7565 }
7566
7567 static inline void get_phys_addr_pmsav7_default(CPUARMState *env,
7568                                                 ARMMMUIdx mmu_idx,
7569                                                 int32_t address, int *prot)
7570 {
7571     *prot = PAGE_READ | PAGE_WRITE;
7572     switch (address) {
7573     case 0xF0000000 ... 0xFFFFFFFF:
7574         if (regime_sctlr(env, mmu_idx) & SCTLR_V) { /* hivecs execing is ok */
7575             *prot |= PAGE_EXEC;
7576         }
7577         break;
7578     case 0x00000000 ... 0x7FFFFFFF:
7579         *prot |= PAGE_EXEC;
7580         break;
7581     }
7582
7583 }
7584
7585 static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
7586                                  int access_type, ARMMMUIdx mmu_idx,
7587                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7588 {
7589     ARMCPU *cpu = arm_env_get_cpu(env);
7590     int n;
7591     bool is_user = regime_is_user(env, mmu_idx);
7592
7593     *phys_ptr = address;
7594     *prot = 0;
7595
7596     if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
7597         get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7598     } else { /* MPU enabled */
7599         for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
7600             /* region search */
7601             uint32_t base = env->pmsav7.drbar[n];
7602             uint32_t rsize = extract32(env->pmsav7.drsr[n], 1, 5);
7603             uint32_t rmask;
7604             bool srdis = false;
7605
7606             if (!(env->pmsav7.drsr[n] & 0x1)) {
7607                 continue;
7608             }
7609
7610             if (!rsize) {
7611                 qemu_log_mask(LOG_GUEST_ERROR, "DRSR.Rsize field can not be 0");
7612                 continue;
7613             }
7614             rsize++;
7615             rmask = (1ull << rsize) - 1;
7616
7617             if (base & rmask) {
7618                 qemu_log_mask(LOG_GUEST_ERROR, "DRBAR %" PRIx32 " misaligned "
7619                               "to DRSR region size, mask = %" PRIx32,
7620                               base, rmask);
7621                 continue;
7622             }
7623
7624             if (address < base || address > base + rmask) {
7625                 continue;
7626             }
7627
7628             /* Region matched */
7629
7630             if (rsize >= 8) { /* no subregions for regions < 256 bytes */
7631                 int i, snd;
7632                 uint32_t srdis_mask;
7633
7634                 rsize -= 3; /* sub region size (power of 2) */
7635                 snd = ((address - base) >> rsize) & 0x7;
7636                 srdis = extract32(env->pmsav7.drsr[n], snd + 8, 1);
7637
7638                 srdis_mask = srdis ? 0x3 : 0x0;
7639                 for (i = 2; i <= 8 && rsize < TARGET_PAGE_BITS; i *= 2) {
7640                     /* This will check in groups of 2, 4 and then 8, whether
7641                      * the subregion bits are consistent. rsize is incremented
7642                      * back up to give the region size, considering consistent
7643                      * adjacent subregions as one region. Stop testing if rsize
7644                      * is already big enough for an entire QEMU page.
7645                      */
7646                     int snd_rounded = snd & ~(i - 1);
7647                     uint32_t srdis_multi = extract32(env->pmsav7.drsr[n],
7648                                                      snd_rounded + 8, i);
7649                     if (srdis_mask ^ srdis_multi) {
7650                         break;
7651                     }
7652                     srdis_mask = (srdis_mask << i) | srdis_mask;
7653                     rsize++;
7654                 }
7655             }
7656             if (rsize < TARGET_PAGE_BITS) {
7657                 qemu_log_mask(LOG_UNIMP, "No support for MPU (sub)region"
7658                               "alignment of %" PRIu32 " bits. Minimum is %d\n",
7659                               rsize, TARGET_PAGE_BITS);
7660                 continue;
7661             }
7662             if (srdis) {
7663                 continue;
7664             }
7665             break;
7666         }
7667
7668         if (n == -1) { /* no hits */
7669             if (cpu->pmsav7_dregion &&
7670                 (is_user || !(regime_sctlr(env, mmu_idx) & SCTLR_BR))) {
7671                 /* background fault */
7672                 *fsr = 0;
7673                 return true;
7674             }
7675             get_phys_addr_pmsav7_default(env, mmu_idx, address, prot);
7676         } else { /* a MPU hit! */
7677             uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
7678
7679             if (is_user) { /* User mode AP bit decoding */
7680                 switch (ap) {
7681                 case 0:
7682                 case 1:
7683                 case 5:
7684                     break; /* no access */
7685                 case 3:
7686                     *prot |= PAGE_WRITE;
7687                     /* fall through */
7688                 case 2:
7689                 case 6:
7690                     *prot |= PAGE_READ | PAGE_EXEC;
7691                     break;
7692                 default:
7693                     qemu_log_mask(LOG_GUEST_ERROR,
7694                                   "Bad value for AP bits in DRACR %"
7695                                   PRIx32 "\n", ap);
7696                 }
7697             } else { /* Priv. mode AP bits decoding */
7698                 switch (ap) {
7699                 case 0:
7700                     break; /* no access */
7701                 case 1:
7702                 case 2:
7703                 case 3:
7704                     *prot |= PAGE_WRITE;
7705                     /* fall through */
7706                 case 5:
7707                 case 6:
7708                     *prot |= PAGE_READ | PAGE_EXEC;
7709                     break;
7710                 default:
7711                     qemu_log_mask(LOG_GUEST_ERROR,
7712                                   "Bad value for AP bits in DRACR %"
7713                                   PRIx32 "\n", ap);
7714                 }
7715             }
7716
7717             /* execute never */
7718             if (env->pmsav7.dracr[n] & (1 << 12)) {
7719                 *prot &= ~PAGE_EXEC;
7720             }
7721         }
7722     }
7723
7724     *fsr = 0x00d; /* Permission fault */
7725     return !(*prot & (1 << access_type));
7726 }
7727
7728 static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
7729                                  int access_type, ARMMMUIdx mmu_idx,
7730                                  hwaddr *phys_ptr, int *prot, uint32_t *fsr)
7731 {
7732     int n;
7733     uint32_t mask;
7734     uint32_t base;
7735     bool is_user = regime_is_user(env, mmu_idx);
7736
7737     *phys_ptr = address;
7738     for (n = 7; n >= 0; n--) {
7739         base = env->cp15.c6_region[n];
7740         if ((base & 1) == 0) {
7741             continue;
7742         }
7743         mask = 1 << ((base >> 1) & 0x1f);
7744         /* Keep this shift separate from the above to avoid an
7745            (undefined) << 32.  */
7746         mask = (mask << 1) - 1;
7747         if (((base ^ address) & ~mask) == 0) {
7748             break;
7749         }
7750     }
7751     if (n < 0) {
7752         *fsr = 2;
7753         return true;
7754     }
7755
7756     if (access_type == 2) {
7757         mask = env->cp15.pmsav5_insn_ap;
7758     } else {
7759         mask = env->cp15.pmsav5_data_ap;
7760     }
7761     mask = (mask >> (n * 4)) & 0xf;
7762     switch (mask) {
7763     case 0:
7764         *fsr = 1;
7765         return true;
7766     case 1:
7767         if (is_user) {
7768             *fsr = 1;
7769             return true;
7770         }
7771         *prot = PAGE_READ | PAGE_WRITE;
7772         break;
7773     case 2:
7774         *prot = PAGE_READ;
7775         if (!is_user) {
7776             *prot |= PAGE_WRITE;
7777         }
7778         break;
7779     case 3:
7780         *prot = PAGE_READ | PAGE_WRITE;
7781         break;
7782     case 5:
7783         if (is_user) {
7784             *fsr = 1;
7785             return true;
7786         }
7787         *prot = PAGE_READ;
7788         break;
7789     case 6:
7790         *prot = PAGE_READ;
7791         break;
7792     default:
7793         /* Bad permission.  */
7794         *fsr = 1;
7795         return true;
7796     }
7797     *prot |= PAGE_EXEC;
7798     return false;
7799 }
7800
7801 /* get_phys_addr - get the physical address for this virtual address
7802  *
7803  * Find the physical address corresponding to the given virtual address,
7804  * by doing a translation table walk on MMU based systems or using the
7805  * MPU state on MPU based systems.
7806  *
7807  * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
7808  * prot and page_size may not be filled in, and the populated fsr value provides
7809  * information on why the translation aborted, in the format of a
7810  * DFSR/IFSR fault register, with the following caveats:
7811  *  * we honour the short vs long DFSR format differences.
7812  *  * the WnR bit is never set (the caller must do this).
7813  *  * for PSMAv5 based systems we don't bother to return a full FSR format
7814  *    value.
7815  *
7816  * @env: CPUARMState
7817  * @address: virtual address to get physical address for
7818  * @access_type: 0 for read, 1 for write, 2 for execute
7819  * @mmu_idx: MMU index indicating required translation regime
7820  * @phys_ptr: set to the physical address corresponding to the virtual address
7821  * @attrs: set to the memory transaction attributes to use
7822  * @prot: set to the permissions for the page containing phys_ptr
7823  * @page_size: set to the size of the page containing phys_ptr
7824  * @fsr: set to the DFSR/IFSR value on failure
7825  */
7826 static bool get_phys_addr(CPUARMState *env, target_ulong address,
7827                           int access_type, ARMMMUIdx mmu_idx,
7828                           hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot,
7829                           target_ulong *page_size, uint32_t *fsr,
7830                           ARMMMUFaultInfo *fi)
7831 {
7832     if (mmu_idx == ARMMMUIdx_S12NSE0 || mmu_idx == ARMMMUIdx_S12NSE1) {
7833         /* Call ourselves recursively to do the stage 1 and then stage 2
7834          * translations.
7835          */
7836         if (arm_feature(env, ARM_FEATURE_EL2)) {
7837             hwaddr ipa;
7838             int s2_prot;
7839             int ret;
7840
7841             ret = get_phys_addr(env, address, access_type,
7842                                 mmu_idx + ARMMMUIdx_S1NSE0, &ipa, attrs,
7843                                 prot, page_size, fsr, fi);
7844
7845             /* If S1 fails or S2 is disabled, return early.  */
7846             if (ret || regime_translation_disabled(env, ARMMMUIdx_S2NS)) {
7847                 *phys_ptr = ipa;
7848                 return ret;
7849             }
7850
7851             /* S1 is done. Now do S2 translation.  */
7852             ret = get_phys_addr_lpae(env, ipa, access_type, ARMMMUIdx_S2NS,
7853                                      phys_ptr, attrs, &s2_prot,
7854                                      page_size, fsr, fi);
7855             fi->s2addr = ipa;
7856             /* Combine the S1 and S2 perms.  */
7857             *prot &= s2_prot;
7858             return ret;
7859         } else {
7860             /*
7861              * For non-EL2 CPUs a stage1+stage2 translation is just stage 1.
7862              */
7863             mmu_idx += ARMMMUIdx_S1NSE0;
7864         }
7865     }
7866
7867     /* The page table entries may downgrade secure to non-secure, but
7868      * cannot upgrade an non-secure translation regime's attributes
7869      * to secure.
7870      */
7871     attrs->secure = regime_is_secure(env, mmu_idx);
7872     attrs->user = regime_is_user(env, mmu_idx);
7873
7874     /* Fast Context Switch Extension. This doesn't exist at all in v8.
7875      * In v7 and earlier it affects all stage 1 translations.
7876      */
7877     if (address < 0x02000000 && mmu_idx != ARMMMUIdx_S2NS
7878         && !arm_feature(env, ARM_FEATURE_V8)) {
7879         if (regime_el(env, mmu_idx) == 3) {
7880             address += env->cp15.fcseidr_s;
7881         } else {
7882             address += env->cp15.fcseidr_ns;
7883         }
7884     }
7885
7886     /* pmsav7 has special handling for when MPU is disabled so call it before
7887      * the common MMU/MPU disabled check below.
7888      */
7889     if (arm_feature(env, ARM_FEATURE_MPU) &&
7890         arm_feature(env, ARM_FEATURE_V7)) {
7891         *page_size = TARGET_PAGE_SIZE;
7892         return get_phys_addr_pmsav7(env, address, access_type, mmu_idx,
7893                                     phys_ptr, prot, fsr);
7894     }
7895
7896     if (regime_translation_disabled(env, mmu_idx)) {
7897         /* MMU/MPU disabled.  */
7898         *phys_ptr = address;
7899         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
7900         *page_size = TARGET_PAGE_SIZE;
7901         return 0;
7902     }
7903
7904     if (arm_feature(env, ARM_FEATURE_MPU)) {
7905         /* Pre-v7 MPU */
7906         *page_size = TARGET_PAGE_SIZE;
7907         return get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
7908                                     phys_ptr, prot, fsr);
7909     }
7910
7911     if (regime_using_lpae_format(env, mmu_idx)) {
7912         return get_phys_addr_lpae(env, address, access_type, mmu_idx, phys_ptr,
7913                                   attrs, prot, page_size, fsr, fi);
7914     } else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
7915         return get_phys_addr_v6(env, address, access_type, mmu_idx, phys_ptr,
7916                                 attrs, prot, page_size, fsr, fi);
7917     } else {
7918         return get_phys_addr_v5(env, address, access_type, mmu_idx, phys_ptr,
7919                                 prot, page_size, fsr, fi);
7920     }
7921 }
7922
7923 /* Walk the page table and (if the mapping exists) add the page
7924  * to the TLB. Return false on success, or true on failure. Populate
7925  * fsr with ARM DFSR/IFSR fault register format value on failure.
7926  */
7927 bool arm_tlb_fill(CPUState *cs, vaddr address,
7928                   int access_type, int mmu_idx, uint32_t *fsr,
7929                   ARMMMUFaultInfo *fi)
7930 {
7931     ARMCPU *cpu = ARM_CPU(cs);
7932     CPUARMState *env = &cpu->env;
7933     hwaddr phys_addr;
7934     target_ulong page_size;
7935     int prot;
7936     int ret;
7937     MemTxAttrs attrs = {};
7938
7939     ret = get_phys_addr(env, address, access_type, mmu_idx, &phys_addr,
7940                         &attrs, &prot, &page_size, fsr, fi);
7941     if (!ret) {
7942         /* Map a single [sub]page.  */
7943         phys_addr &= TARGET_PAGE_MASK;
7944         address &= TARGET_PAGE_MASK;
7945         tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
7946                                 prot, mmu_idx, page_size);
7947         return 0;
7948     }
7949
7950     return ret;
7951 }
7952
7953 hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
7954                                          MemTxAttrs *attrs)
7955 {
7956     ARMCPU *cpu = ARM_CPU(cs);
7957     CPUARMState *env = &cpu->env;
7958     hwaddr phys_addr;
7959     target_ulong page_size;
7960     int prot;
7961     bool ret;
7962     uint32_t fsr;
7963     ARMMMUFaultInfo fi = {};
7964
7965     *attrs = (MemTxAttrs) {};
7966
7967     ret = get_phys_addr(env, addr, 0, cpu_mmu_index(env, false), &phys_addr,
7968                         attrs, &prot, &page_size, &fsr, &fi);
7969
7970     if (ret) {
7971         return -1;
7972     }
7973     return phys_addr;
7974 }
7975
7976 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
7977 {
7978     ARMCPU *cpu = arm_env_get_cpu(env);
7979
7980     switch (reg) {
7981     case 0: /* APSR */
7982         return xpsr_read(env) & 0xf8000000;
7983     case 1: /* IAPSR */
7984         return xpsr_read(env) & 0xf80001ff;
7985     case 2: /* EAPSR */
7986         return xpsr_read(env) & 0xff00fc00;
7987     case 3: /* xPSR */
7988         return xpsr_read(env) & 0xff00fdff;
7989     case 5: /* IPSR */
7990         return xpsr_read(env) & 0x000001ff;
7991     case 6: /* EPSR */
7992         return xpsr_read(env) & 0x0700fc00;
7993     case 7: /* IEPSR */
7994         return xpsr_read(env) & 0x0700edff;
7995     case 8: /* MSP */
7996         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
7997     case 9: /* PSP */
7998         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
7999     case 16: /* PRIMASK */
8000         return (env->daif & PSTATE_I) != 0;
8001     case 17: /* BASEPRI */
8002     case 18: /* BASEPRI_MAX */
8003         return env->v7m.basepri;
8004     case 19: /* FAULTMASK */
8005         return (env->daif & PSTATE_F) != 0;
8006     case 20: /* CONTROL */
8007         return env->v7m.control;
8008     default:
8009         /* ??? For debugging only.  */
8010         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
8011         return 0;
8012     }
8013 }
8014
8015 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
8016 {
8017     ARMCPU *cpu = arm_env_get_cpu(env);
8018
8019     switch (reg) {
8020     case 0: /* APSR */
8021         xpsr_write(env, val, 0xf8000000);
8022         break;
8023     case 1: /* IAPSR */
8024         xpsr_write(env, val, 0xf8000000);
8025         break;
8026     case 2: /* EAPSR */
8027         xpsr_write(env, val, 0xfe00fc00);
8028         break;
8029     case 3: /* xPSR */
8030         xpsr_write(env, val, 0xfe00fc00);
8031         break;
8032     case 5: /* IPSR */
8033         /* IPSR bits are readonly.  */
8034         break;
8035     case 6: /* EPSR */
8036         xpsr_write(env, val, 0x0600fc00);
8037         break;
8038     case 7: /* IEPSR */
8039         xpsr_write(env, val, 0x0600fc00);
8040         break;
8041     case 8: /* MSP */
8042         if (env->v7m.current_sp)
8043             env->v7m.other_sp = val;
8044         else
8045             env->regs[13] = val;
8046         break;
8047     case 9: /* PSP */
8048         if (env->v7m.current_sp)
8049             env->regs[13] = val;
8050         else
8051             env->v7m.other_sp = val;
8052         break;
8053     case 16: /* PRIMASK */
8054         if (val & 1) {
8055             env->daif |= PSTATE_I;
8056         } else {
8057             env->daif &= ~PSTATE_I;
8058         }
8059         break;
8060     case 17: /* BASEPRI */
8061         env->v7m.basepri = val & 0xff;
8062         break;
8063     case 18: /* BASEPRI_MAX */
8064         val &= 0xff;
8065         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
8066             env->v7m.basepri = val;
8067         break;
8068     case 19: /* FAULTMASK */
8069         if (val & 1) {
8070             env->daif |= PSTATE_F;
8071         } else {
8072             env->daif &= ~PSTATE_F;
8073         }
8074         break;
8075     case 20: /* CONTROL */
8076         env->v7m.control = val & 3;
8077         switch_v7m_sp(env, (val & 2) != 0);
8078         break;
8079     default:
8080         /* ??? For debugging only.  */
8081         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
8082         return;
8083     }
8084 }
8085
8086 #endif
8087
8088 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
8089 {
8090     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
8091      * Note that we do not implement the (architecturally mandated)
8092      * alignment fault for attempts to use this on Device memory
8093      * (which matches the usual QEMU behaviour of not implementing either
8094      * alignment faults or any memory attribute handling).
8095      */
8096
8097     ARMCPU *cpu = arm_env_get_cpu(env);
8098     uint64_t blocklen = 4 << cpu->dcz_blocksize;
8099     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
8100
8101 #ifndef CONFIG_USER_ONLY
8102     {
8103         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
8104          * the block size so we might have to do more than one TLB lookup.
8105          * We know that in fact for any v8 CPU the page size is at least 4K
8106          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
8107          * 1K as an artefact of legacy v5 subpage support being present in the
8108          * same QEMU executable.
8109          */
8110         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
8111         void *hostaddr[maxidx];
8112         int try, i;
8113         unsigned mmu_idx = cpu_mmu_index(env, false);
8114         TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
8115
8116         for (try = 0; try < 2; try++) {
8117
8118             for (i = 0; i < maxidx; i++) {
8119                 hostaddr[i] = tlb_vaddr_to_host(env,
8120                                                 vaddr + TARGET_PAGE_SIZE * i,
8121                                                 1, mmu_idx);
8122                 if (!hostaddr[i]) {
8123                     break;
8124                 }
8125             }
8126             if (i == maxidx) {
8127                 /* If it's all in the TLB it's fair game for just writing to;
8128                  * we know we don't need to update dirty status, etc.
8129                  */
8130                 for (i = 0; i < maxidx - 1; i++) {
8131                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
8132                 }
8133                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
8134                 return;
8135             }
8136             /* OK, try a store and see if we can populate the tlb. This
8137              * might cause an exception if the memory isn't writable,
8138              * in which case we will longjmp out of here. We must for
8139              * this purpose use the actual register value passed to us
8140              * so that we get the fault address right.
8141              */
8142             helper_ret_stb_mmu(env, vaddr_in, 0, oi, GETRA());
8143             /* Now we can populate the other TLB entries, if any */
8144             for (i = 0; i < maxidx; i++) {
8145                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
8146                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
8147                     helper_ret_stb_mmu(env, va, 0, oi, GETRA());
8148                 }
8149             }
8150         }
8151
8152         /* Slow path (probably attempt to do this to an I/O device or
8153          * similar, or clearing of a block of code we have translations
8154          * cached for). Just do a series of byte writes as the architecture
8155          * demands. It's not worth trying to use a cpu_physical_memory_map(),
8156          * memset(), unmap() sequence here because:
8157          *  + we'd need to account for the blocksize being larger than a page
8158          *  + the direct-RAM access case is almost always going to be dealt
8159          *    with in the fastpath code above, so there's no speed benefit
8160          *  + we would have to deal with the map returning NULL because the
8161          *    bounce buffer was in use
8162          */
8163         for (i = 0; i < blocklen; i++) {
8164             helper_ret_stb_mmu(env, vaddr + i, 0, oi, GETRA());
8165         }
8166     }
8167 #else
8168     memset(g2h(vaddr), 0, blocklen);
8169 #endif
8170 }
8171
8172 /* Note that signed overflow is undefined in C.  The following routines are
8173    careful to use unsigned types where modulo arithmetic is required.
8174    Failure to do so _will_ break on newer gcc.  */
8175
8176 /* Signed saturating arithmetic.  */
8177
8178 /* Perform 16-bit signed saturating addition.  */
8179 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
8180 {
8181     uint16_t res;
8182
8183     res = a + b;
8184     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
8185         if (a & 0x8000)
8186             res = 0x8000;
8187         else
8188             res = 0x7fff;
8189     }
8190     return res;
8191 }
8192
8193 /* Perform 8-bit signed saturating addition.  */
8194 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
8195 {
8196     uint8_t res;
8197
8198     res = a + b;
8199     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
8200         if (a & 0x80)
8201             res = 0x80;
8202         else
8203             res = 0x7f;
8204     }
8205     return res;
8206 }
8207
8208 /* Perform 16-bit signed saturating subtraction.  */
8209 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
8210 {
8211     uint16_t res;
8212
8213     res = a - b;
8214     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
8215         if (a & 0x8000)
8216             res = 0x8000;
8217         else
8218             res = 0x7fff;
8219     }
8220     return res;
8221 }
8222
8223 /* Perform 8-bit signed saturating subtraction.  */
8224 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
8225 {
8226     uint8_t res;
8227
8228     res = a - b;
8229     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
8230         if (a & 0x80)
8231             res = 0x80;
8232         else
8233             res = 0x7f;
8234     }
8235     return res;
8236 }
8237
8238 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
8239 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
8240 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
8241 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
8242 #define PFX q
8243
8244 #include "op_addsub.h"
8245
8246 /* Unsigned saturating arithmetic.  */
8247 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
8248 {
8249     uint16_t res;
8250     res = a + b;
8251     if (res < a)
8252         res = 0xffff;
8253     return res;
8254 }
8255
8256 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
8257 {
8258     if (a > b)
8259         return a - b;
8260     else
8261         return 0;
8262 }
8263
8264 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
8265 {
8266     uint8_t res;
8267     res = a + b;
8268     if (res < a)
8269         res = 0xff;
8270     return res;
8271 }
8272
8273 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
8274 {
8275     if (a > b)
8276         return a - b;
8277     else
8278         return 0;
8279 }
8280
8281 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
8282 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
8283 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
8284 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
8285 #define PFX uq
8286
8287 #include "op_addsub.h"
8288
8289 /* Signed modulo arithmetic.  */
8290 #define SARITH16(a, b, n, op) do { \
8291     int32_t sum; \
8292     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
8293     RESULT(sum, n, 16); \
8294     if (sum >= 0) \
8295         ge |= 3 << (n * 2); \
8296     } while(0)
8297
8298 #define SARITH8(a, b, n, op) do { \
8299     int32_t sum; \
8300     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
8301     RESULT(sum, n, 8); \
8302     if (sum >= 0) \
8303         ge |= 1 << n; \
8304     } while(0)
8305
8306
8307 #define ADD16(a, b, n) SARITH16(a, b, n, +)
8308 #define SUB16(a, b, n) SARITH16(a, b, n, -)
8309 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
8310 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
8311 #define PFX s
8312 #define ARITH_GE
8313
8314 #include "op_addsub.h"
8315
8316 /* Unsigned modulo arithmetic.  */
8317 #define ADD16(a, b, n) do { \
8318     uint32_t sum; \
8319     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
8320     RESULT(sum, n, 16); \
8321     if ((sum >> 16) == 1) \
8322         ge |= 3 << (n * 2); \
8323     } while(0)
8324
8325 #define ADD8(a, b, n) do { \
8326     uint32_t sum; \
8327     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
8328     RESULT(sum, n, 8); \
8329     if ((sum >> 8) == 1) \
8330         ge |= 1 << n; \
8331     } while(0)
8332
8333 #define SUB16(a, b, n) do { \
8334     uint32_t sum; \
8335     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
8336     RESULT(sum, n, 16); \
8337     if ((sum >> 16) == 0) \
8338         ge |= 3 << (n * 2); \
8339     } while(0)
8340
8341 #define SUB8(a, b, n) do { \
8342     uint32_t sum; \
8343     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
8344     RESULT(sum, n, 8); \
8345     if ((sum >> 8) == 0) \
8346         ge |= 1 << n; \
8347     } while(0)
8348
8349 #define PFX u
8350 #define ARITH_GE
8351
8352 #include "op_addsub.h"
8353
8354 /* Halved signed arithmetic.  */
8355 #define ADD16(a, b, n) \
8356   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
8357 #define SUB16(a, b, n) \
8358   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
8359 #define ADD8(a, b, n) \
8360   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
8361 #define SUB8(a, b, n) \
8362   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
8363 #define PFX sh
8364
8365 #include "op_addsub.h"
8366
8367 /* Halved unsigned arithmetic.  */
8368 #define ADD16(a, b, n) \
8369   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8370 #define SUB16(a, b, n) \
8371   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
8372 #define ADD8(a, b, n) \
8373   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8374 #define SUB8(a, b, n) \
8375   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
8376 #define PFX uh
8377
8378 #include "op_addsub.h"
8379
8380 static inline uint8_t do_usad(uint8_t a, uint8_t b)
8381 {
8382     if (a > b)
8383         return a - b;
8384     else
8385         return b - a;
8386 }
8387
8388 /* Unsigned sum of absolute byte differences.  */
8389 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
8390 {
8391     uint32_t sum;
8392     sum = do_usad(a, b);
8393     sum += do_usad(a >> 8, b >> 8);
8394     sum += do_usad(a >> 16, b >>16);
8395     sum += do_usad(a >> 24, b >> 24);
8396     return sum;
8397 }
8398
8399 /* For ARMv6 SEL instruction.  */
8400 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
8401 {
8402     uint32_t mask;
8403
8404     mask = 0;
8405     if (flags & 1)
8406         mask |= 0xff;
8407     if (flags & 2)
8408         mask |= 0xff00;
8409     if (flags & 4)
8410         mask |= 0xff0000;
8411     if (flags & 8)
8412         mask |= 0xff000000;
8413     return (a & mask) | (b & ~mask);
8414 }
8415
8416 /* VFP support.  We follow the convention used for VFP instructions:
8417    Single precision routines have a "s" suffix, double precision a
8418    "d" suffix.  */
8419
8420 /* Convert host exception flags to vfp form.  */
8421 static inline int vfp_exceptbits_from_host(int host_bits)
8422 {
8423     int target_bits = 0;
8424
8425     if (host_bits & float_flag_invalid)
8426         target_bits |= 1;
8427     if (host_bits & float_flag_divbyzero)
8428         target_bits |= 2;
8429     if (host_bits & float_flag_overflow)
8430         target_bits |= 4;
8431     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
8432         target_bits |= 8;
8433     if (host_bits & float_flag_inexact)
8434         target_bits |= 0x10;
8435     if (host_bits & float_flag_input_denormal)
8436         target_bits |= 0x80;
8437     return target_bits;
8438 }
8439
8440 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
8441 {
8442     int i;
8443     uint32_t fpscr;
8444
8445     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
8446             | (env->vfp.vec_len << 16)
8447             | (env->vfp.vec_stride << 20);
8448     i = get_float_exception_flags(&env->vfp.fp_status);
8449     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
8450     fpscr |= vfp_exceptbits_from_host(i);
8451     return fpscr;
8452 }
8453
8454 uint32_t vfp_get_fpscr(CPUARMState *env)
8455 {
8456     return HELPER(vfp_get_fpscr)(env);
8457 }
8458
8459 /* Convert vfp exception flags to target form.  */
8460 static inline int vfp_exceptbits_to_host(int target_bits)
8461 {
8462     int host_bits = 0;
8463
8464     if (target_bits & 1)
8465         host_bits |= float_flag_invalid;
8466     if (target_bits & 2)
8467         host_bits |= float_flag_divbyzero;
8468     if (target_bits & 4)
8469         host_bits |= float_flag_overflow;
8470     if (target_bits & 8)
8471         host_bits |= float_flag_underflow;
8472     if (target_bits & 0x10)
8473         host_bits |= float_flag_inexact;
8474     if (target_bits & 0x80)
8475         host_bits |= float_flag_input_denormal;
8476     return host_bits;
8477 }
8478
8479 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
8480 {
8481     int i;
8482     uint32_t changed;
8483
8484     changed = env->vfp.xregs[ARM_VFP_FPSCR];
8485     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
8486     env->vfp.vec_len = (val >> 16) & 7;
8487     env->vfp.vec_stride = (val >> 20) & 3;
8488
8489     changed ^= val;
8490     if (changed & (3 << 22)) {
8491         i = (val >> 22) & 3;
8492         switch (i) {
8493         case FPROUNDING_TIEEVEN:
8494             i = float_round_nearest_even;
8495             break;
8496         case FPROUNDING_POSINF:
8497             i = float_round_up;
8498             break;
8499         case FPROUNDING_NEGINF:
8500             i = float_round_down;
8501             break;
8502         case FPROUNDING_ZERO:
8503             i = float_round_to_zero;
8504             break;
8505         }
8506         set_float_rounding_mode(i, &env->vfp.fp_status);
8507     }
8508     if (changed & (1 << 24)) {
8509         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8510         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
8511     }
8512     if (changed & (1 << 25))
8513         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
8514
8515     i = vfp_exceptbits_to_host(val);
8516     set_float_exception_flags(i, &env->vfp.fp_status);
8517     set_float_exception_flags(0, &env->vfp.standard_fp_status);
8518 }
8519
8520 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
8521 {
8522     HELPER(vfp_set_fpscr)(env, val);
8523 }
8524
8525 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
8526
8527 #define VFP_BINOP(name) \
8528 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
8529 { \
8530     float_status *fpst = fpstp; \
8531     return float32_ ## name(a, b, fpst); \
8532 } \
8533 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
8534 { \
8535     float_status *fpst = fpstp; \
8536     return float64_ ## name(a, b, fpst); \
8537 }
8538 VFP_BINOP(add)
8539 VFP_BINOP(sub)
8540 VFP_BINOP(mul)
8541 VFP_BINOP(div)
8542 VFP_BINOP(min)
8543 VFP_BINOP(max)
8544 VFP_BINOP(minnum)
8545 VFP_BINOP(maxnum)
8546 #undef VFP_BINOP
8547
8548 float32 VFP_HELPER(neg, s)(float32 a)
8549 {
8550     return float32_chs(a);
8551 }
8552
8553 float64 VFP_HELPER(neg, d)(float64 a)
8554 {
8555     return float64_chs(a);
8556 }
8557
8558 float32 VFP_HELPER(abs, s)(float32 a)
8559 {
8560     return float32_abs(a);
8561 }
8562
8563 float64 VFP_HELPER(abs, d)(float64 a)
8564 {
8565     return float64_abs(a);
8566 }
8567
8568 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
8569 {
8570     return float32_sqrt(a, &env->vfp.fp_status);
8571 }
8572
8573 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
8574 {
8575     return float64_sqrt(a, &env->vfp.fp_status);
8576 }
8577
8578 /* XXX: check quiet/signaling case */
8579 #define DO_VFP_cmp(p, type) \
8580 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
8581 { \
8582     uint32_t flags; \
8583     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
8584     case 0: flags = 0x6; break; \
8585     case -1: flags = 0x8; break; \
8586     case 1: flags = 0x2; break; \
8587     default: case 2: flags = 0x3; break; \
8588     } \
8589     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8590         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8591 } \
8592 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
8593 { \
8594     uint32_t flags; \
8595     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
8596     case 0: flags = 0x6; break; \
8597     case -1: flags = 0x8; break; \
8598     case 1: flags = 0x2; break; \
8599     default: case 2: flags = 0x3; break; \
8600     } \
8601     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
8602         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
8603 }
8604 DO_VFP_cmp(s, float32)
8605 DO_VFP_cmp(d, float64)
8606 #undef DO_VFP_cmp
8607
8608 /* Integer to float and float to integer conversions */
8609
8610 #define CONV_ITOF(name, fsz, sign) \
8611     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
8612 { \
8613     float_status *fpst = fpstp; \
8614     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
8615 }
8616
8617 #define CONV_FTOI(name, fsz, sign, round) \
8618 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
8619 { \
8620     float_status *fpst = fpstp; \
8621     if (float##fsz##_is_any_nan(x)) { \
8622         float_raise(float_flag_invalid, fpst); \
8623         return 0; \
8624     } \
8625     return float##fsz##_to_##sign##int32##round(x, fpst); \
8626 }
8627
8628 #define FLOAT_CONVS(name, p, fsz, sign) \
8629 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
8630 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
8631 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
8632
8633 FLOAT_CONVS(si, s, 32, )
8634 FLOAT_CONVS(si, d, 64, )
8635 FLOAT_CONVS(ui, s, 32, u)
8636 FLOAT_CONVS(ui, d, 64, u)
8637
8638 #undef CONV_ITOF
8639 #undef CONV_FTOI
8640 #undef FLOAT_CONVS
8641
8642 /* floating point conversion */
8643 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
8644 {
8645     float64 r = float32_to_float64(x, &env->vfp.fp_status);
8646     /* ARM requires that S<->D conversion of any kind of NaN generates
8647      * a quiet NaN by forcing the most significant frac bit to 1.
8648      */
8649     return float64_maybe_silence_nan(r);
8650 }
8651
8652 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
8653 {
8654     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
8655     /* ARM requires that S<->D conversion of any kind of NaN generates
8656      * a quiet NaN by forcing the most significant frac bit to 1.
8657      */
8658     return float32_maybe_silence_nan(r);
8659 }
8660
8661 /* VFP3 fixed point conversion.  */
8662 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
8663 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
8664                                      void *fpstp) \
8665 { \
8666     float_status *fpst = fpstp; \
8667     float##fsz tmp; \
8668     tmp = itype##_to_##float##fsz(x, fpst); \
8669     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
8670 }
8671
8672 /* Notice that we want only input-denormal exception flags from the
8673  * scalbn operation: the other possible flags (overflow+inexact if
8674  * we overflow to infinity, output-denormal) aren't correct for the
8675  * complete scale-and-convert operation.
8676  */
8677 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
8678 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
8679                                              uint32_t shift, \
8680                                              void *fpstp) \
8681 { \
8682     float_status *fpst = fpstp; \
8683     int old_exc_flags = get_float_exception_flags(fpst); \
8684     float##fsz tmp; \
8685     if (float##fsz##_is_any_nan(x)) { \
8686         float_raise(float_flag_invalid, fpst); \
8687         return 0; \
8688     } \
8689     tmp = float##fsz##_scalbn(x, shift, fpst); \
8690     old_exc_flags |= get_float_exception_flags(fpst) \
8691         & float_flag_input_denormal; \
8692     set_float_exception_flags(old_exc_flags, fpst); \
8693     return float##fsz##_to_##itype##round(tmp, fpst); \
8694 }
8695
8696 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
8697 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8698 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
8699 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8700
8701 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
8702 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
8703 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
8704
8705 VFP_CONV_FIX(sh, d, 64, 64, int16)
8706 VFP_CONV_FIX(sl, d, 64, 64, int32)
8707 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
8708 VFP_CONV_FIX(uh, d, 64, 64, uint16)
8709 VFP_CONV_FIX(ul, d, 64, 64, uint32)
8710 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
8711 VFP_CONV_FIX(sh, s, 32, 32, int16)
8712 VFP_CONV_FIX(sl, s, 32, 32, int32)
8713 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
8714 VFP_CONV_FIX(uh, s, 32, 32, uint16)
8715 VFP_CONV_FIX(ul, s, 32, 32, uint32)
8716 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
8717 #undef VFP_CONV_FIX
8718 #undef VFP_CONV_FIX_FLOAT
8719 #undef VFP_CONV_FLOAT_FIX_ROUND
8720
8721 /* Set the current fp rounding mode and return the old one.
8722  * The argument is a softfloat float_round_ value.
8723  */
8724 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
8725 {
8726     float_status *fp_status = &env->vfp.fp_status;
8727
8728     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8729     set_float_rounding_mode(rmode, fp_status);
8730
8731     return prev_rmode;
8732 }
8733
8734 /* Set the current fp rounding mode in the standard fp status and return
8735  * the old one. This is for NEON instructions that need to change the
8736  * rounding mode but wish to use the standard FPSCR values for everything
8737  * else. Always set the rounding mode back to the correct value after
8738  * modifying it.
8739  * The argument is a softfloat float_round_ value.
8740  */
8741 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
8742 {
8743     float_status *fp_status = &env->vfp.standard_fp_status;
8744
8745     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
8746     set_float_rounding_mode(rmode, fp_status);
8747
8748     return prev_rmode;
8749 }
8750
8751 /* Half precision conversions.  */
8752 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
8753 {
8754     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8755     float32 r = float16_to_float32(make_float16(a), ieee, s);
8756     if (ieee) {
8757         return float32_maybe_silence_nan(r);
8758     }
8759     return r;
8760 }
8761
8762 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
8763 {
8764     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8765     float16 r = float32_to_float16(a, ieee, s);
8766     if (ieee) {
8767         r = float16_maybe_silence_nan(r);
8768     }
8769     return float16_val(r);
8770 }
8771
8772 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8773 {
8774     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
8775 }
8776
8777 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8778 {
8779     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
8780 }
8781
8782 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
8783 {
8784     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
8785 }
8786
8787 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
8788 {
8789     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
8790 }
8791
8792 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
8793 {
8794     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8795     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
8796     if (ieee) {
8797         return float64_maybe_silence_nan(r);
8798     }
8799     return r;
8800 }
8801
8802 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
8803 {
8804     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
8805     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
8806     if (ieee) {
8807         r = float16_maybe_silence_nan(r);
8808     }
8809     return float16_val(r);
8810 }
8811
8812 #define float32_two make_float32(0x40000000)
8813 #define float32_three make_float32(0x40400000)
8814 #define float32_one_point_five make_float32(0x3fc00000)
8815
8816 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
8817 {
8818     float_status *s = &env->vfp.standard_fp_status;
8819     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8820         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8821         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8822             float_raise(float_flag_input_denormal, s);
8823         }
8824         return float32_two;
8825     }
8826     return float32_sub(float32_two, float32_mul(a, b, s), s);
8827 }
8828
8829 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
8830 {
8831     float_status *s = &env->vfp.standard_fp_status;
8832     float32 product;
8833     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
8834         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
8835         if (!(float32_is_zero(a) || float32_is_zero(b))) {
8836             float_raise(float_flag_input_denormal, s);
8837         }
8838         return float32_one_point_five;
8839     }
8840     product = float32_mul(a, b, s);
8841     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
8842 }
8843
8844 /* NEON helpers.  */
8845
8846 /* Constants 256 and 512 are used in some helpers; we avoid relying on
8847  * int->float conversions at run-time.  */
8848 #define float64_256 make_float64(0x4070000000000000LL)
8849 #define float64_512 make_float64(0x4080000000000000LL)
8850 #define float32_maxnorm make_float32(0x7f7fffff)
8851 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
8852
8853 /* Reciprocal functions
8854  *
8855  * The algorithm that must be used to calculate the estimate
8856  * is specified by the ARM ARM, see FPRecipEstimate()
8857  */
8858
8859 static float64 recip_estimate(float64 a, float_status *real_fp_status)
8860 {
8861     /* These calculations mustn't set any fp exception flags,
8862      * so we use a local copy of the fp_status.
8863      */
8864     float_status dummy_status = *real_fp_status;
8865     float_status *s = &dummy_status;
8866     /* q = (int)(a * 512.0) */
8867     float64 q = float64_mul(float64_512, a, s);
8868     int64_t q_int = float64_to_int64_round_to_zero(q, s);
8869
8870     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
8871     q = int64_to_float64(q_int, s);
8872     q = float64_add(q, float64_half, s);
8873     q = float64_div(q, float64_512, s);
8874     q = float64_div(float64_one, q, s);
8875
8876     /* s = (int)(256.0 * r + 0.5) */
8877     q = float64_mul(q, float64_256, s);
8878     q = float64_add(q, float64_half, s);
8879     q_int = float64_to_int64_round_to_zero(q, s);
8880
8881     /* return (double)s / 256.0 */
8882     return float64_div(int64_to_float64(q_int, s), float64_256, s);
8883 }
8884
8885 /* Common wrapper to call recip_estimate */
8886 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
8887 {
8888     uint64_t val64 = float64_val(num);
8889     uint64_t frac = extract64(val64, 0, 52);
8890     int64_t exp = extract64(val64, 52, 11);
8891     uint64_t sbit;
8892     float64 scaled, estimate;
8893
8894     /* Generate the scaled number for the estimate function */
8895     if (exp == 0) {
8896         if (extract64(frac, 51, 1) == 0) {
8897             exp = -1;
8898             frac = extract64(frac, 0, 50) << 2;
8899         } else {
8900             frac = extract64(frac, 0, 51) << 1;
8901         }
8902     }
8903
8904     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
8905     scaled = make_float64((0x3feULL << 52)
8906                           | extract64(frac, 44, 8) << 44);
8907
8908     estimate = recip_estimate(scaled, fpst);
8909
8910     /* Build new result */
8911     val64 = float64_val(estimate);
8912     sbit = 0x8000000000000000ULL & val64;
8913     exp = off - exp;
8914     frac = extract64(val64, 0, 52);
8915
8916     if (exp == 0) {
8917         frac = 1ULL << 51 | extract64(frac, 1, 51);
8918     } else if (exp == -1) {
8919         frac = 1ULL << 50 | extract64(frac, 2, 50);
8920         exp = 0;
8921     }
8922
8923     return make_float64(sbit | (exp << 52) | frac);
8924 }
8925
8926 static bool round_to_inf(float_status *fpst, bool sign_bit)
8927 {
8928     switch (fpst->float_rounding_mode) {
8929     case float_round_nearest_even: /* Round to Nearest */
8930         return true;
8931     case float_round_up: /* Round to +Inf */
8932         return !sign_bit;
8933     case float_round_down: /* Round to -Inf */
8934         return sign_bit;
8935     case float_round_to_zero: /* Round to Zero */
8936         return false;
8937     }
8938
8939     g_assert_not_reached();
8940 }
8941
8942 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
8943 {
8944     float_status *fpst = fpstp;
8945     float32 f32 = float32_squash_input_denormal(input, fpst);
8946     uint32_t f32_val = float32_val(f32);
8947     uint32_t f32_sbit = 0x80000000ULL & f32_val;
8948     int32_t f32_exp = extract32(f32_val, 23, 8);
8949     uint32_t f32_frac = extract32(f32_val, 0, 23);
8950     float64 f64, r64;
8951     uint64_t r64_val;
8952     int64_t r64_exp;
8953     uint64_t r64_frac;
8954
8955     if (float32_is_any_nan(f32)) {
8956         float32 nan = f32;
8957         if (float32_is_signaling_nan(f32)) {
8958             float_raise(float_flag_invalid, fpst);
8959             nan = float32_maybe_silence_nan(f32);
8960         }
8961         if (fpst->default_nan_mode) {
8962             nan =  float32_default_nan;
8963         }
8964         return nan;
8965     } else if (float32_is_infinity(f32)) {
8966         return float32_set_sign(float32_zero, float32_is_neg(f32));
8967     } else if (float32_is_zero(f32)) {
8968         float_raise(float_flag_divbyzero, fpst);
8969         return float32_set_sign(float32_infinity, float32_is_neg(f32));
8970     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
8971         /* Abs(value) < 2.0^-128 */
8972         float_raise(float_flag_overflow | float_flag_inexact, fpst);
8973         if (round_to_inf(fpst, f32_sbit)) {
8974             return float32_set_sign(float32_infinity, float32_is_neg(f32));
8975         } else {
8976             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
8977         }
8978     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
8979         float_raise(float_flag_underflow, fpst);
8980         return float32_set_sign(float32_zero, float32_is_neg(f32));
8981     }
8982
8983
8984     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
8985     r64 = call_recip_estimate(f64, 253, fpst);
8986     r64_val = float64_val(r64);
8987     r64_exp = extract64(r64_val, 52, 11);
8988     r64_frac = extract64(r64_val, 0, 52);
8989
8990     /* result = sign : result_exp<7:0> : fraction<51:29>; */
8991     return make_float32(f32_sbit |
8992                         (r64_exp & 0xff) << 23 |
8993                         extract64(r64_frac, 29, 24));
8994 }
8995
8996 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
8997 {
8998     float_status *fpst = fpstp;
8999     float64 f64 = float64_squash_input_denormal(input, fpst);
9000     uint64_t f64_val = float64_val(f64);
9001     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
9002     int64_t f64_exp = extract64(f64_val, 52, 11);
9003     float64 r64;
9004     uint64_t r64_val;
9005     int64_t r64_exp;
9006     uint64_t r64_frac;
9007
9008     /* Deal with any special cases */
9009     if (float64_is_any_nan(f64)) {
9010         float64 nan = f64;
9011         if (float64_is_signaling_nan(f64)) {
9012             float_raise(float_flag_invalid, fpst);
9013             nan = float64_maybe_silence_nan(f64);
9014         }
9015         if (fpst->default_nan_mode) {
9016             nan =  float64_default_nan;
9017         }
9018         return nan;
9019     } else if (float64_is_infinity(f64)) {
9020         return float64_set_sign(float64_zero, float64_is_neg(f64));
9021     } else if (float64_is_zero(f64)) {
9022         float_raise(float_flag_divbyzero, fpst);
9023         return float64_set_sign(float64_infinity, float64_is_neg(f64));
9024     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
9025         /* Abs(value) < 2.0^-1024 */
9026         float_raise(float_flag_overflow | float_flag_inexact, fpst);
9027         if (round_to_inf(fpst, f64_sbit)) {
9028             return float64_set_sign(float64_infinity, float64_is_neg(f64));
9029         } else {
9030             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
9031         }
9032     } else if (f64_exp >= 2045 && fpst->flush_to_zero) {
9033         float_raise(float_flag_underflow, fpst);
9034         return float64_set_sign(float64_zero, float64_is_neg(f64));
9035     }
9036
9037     r64 = call_recip_estimate(f64, 2045, fpst);
9038     r64_val = float64_val(r64);
9039     r64_exp = extract64(r64_val, 52, 11);
9040     r64_frac = extract64(r64_val, 0, 52);
9041
9042     /* result = sign : result_exp<10:0> : fraction<51:0> */
9043     return make_float64(f64_sbit |
9044                         ((r64_exp & 0x7ff) << 52) |
9045                         r64_frac);
9046 }
9047
9048 /* The algorithm that must be used to calculate the estimate
9049  * is specified by the ARM ARM.
9050  */
9051 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
9052 {
9053     /* These calculations mustn't set any fp exception flags,
9054      * so we use a local copy of the fp_status.
9055      */
9056     float_status dummy_status = *real_fp_status;
9057     float_status *s = &dummy_status;
9058     float64 q;
9059     int64_t q_int;
9060
9061     if (float64_lt(a, float64_half, s)) {
9062         /* range 0.25 <= a < 0.5 */
9063
9064         /* a in units of 1/512 rounded down */
9065         /* q0 = (int)(a * 512.0);  */
9066         q = float64_mul(float64_512, a, s);
9067         q_int = float64_to_int64_round_to_zero(q, s);
9068
9069         /* reciprocal root r */
9070         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
9071         q = int64_to_float64(q_int, s);
9072         q = float64_add(q, float64_half, s);
9073         q = float64_div(q, float64_512, s);
9074         q = float64_sqrt(q, s);
9075         q = float64_div(float64_one, q, s);
9076     } else {
9077         /* range 0.5 <= a < 1.0 */
9078
9079         /* a in units of 1/256 rounded down */
9080         /* q1 = (int)(a * 256.0); */
9081         q = float64_mul(float64_256, a, s);
9082         int64_t q_int = float64_to_int64_round_to_zero(q, s);
9083
9084         /* reciprocal root r */
9085         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
9086         q = int64_to_float64(q_int, s);
9087         q = float64_add(q, float64_half, s);
9088         q = float64_div(q, float64_256, s);
9089         q = float64_sqrt(q, s);
9090         q = float64_div(float64_one, q, s);
9091     }
9092     /* r in units of 1/256 rounded to nearest */
9093     /* s = (int)(256.0 * r + 0.5); */
9094
9095     q = float64_mul(q, float64_256,s );
9096     q = float64_add(q, float64_half, s);
9097     q_int = float64_to_int64_round_to_zero(q, s);
9098
9099     /* return (double)s / 256.0;*/
9100     return float64_div(int64_to_float64(q_int, s), float64_256, s);
9101 }
9102
9103 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
9104 {
9105     float_status *s = fpstp;
9106     float32 f32 = float32_squash_input_denormal(input, s);
9107     uint32_t val = float32_val(f32);
9108     uint32_t f32_sbit = 0x80000000 & val;
9109     int32_t f32_exp = extract32(val, 23, 8);
9110     uint32_t f32_frac = extract32(val, 0, 23);
9111     uint64_t f64_frac;
9112     uint64_t val64;
9113     int result_exp;
9114     float64 f64;
9115
9116     if (float32_is_any_nan(f32)) {
9117         float32 nan = f32;
9118         if (float32_is_signaling_nan(f32)) {
9119             float_raise(float_flag_invalid, s);
9120             nan = float32_maybe_silence_nan(f32);
9121         }
9122         if (s->default_nan_mode) {
9123             nan =  float32_default_nan;
9124         }
9125         return nan;
9126     } else if (float32_is_zero(f32)) {
9127         float_raise(float_flag_divbyzero, s);
9128         return float32_set_sign(float32_infinity, float32_is_neg(f32));
9129     } else if (float32_is_neg(f32)) {
9130         float_raise(float_flag_invalid, s);
9131         return float32_default_nan;
9132     } else if (float32_is_infinity(f32)) {
9133         return float32_zero;
9134     }
9135
9136     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9137      * preserving the parity of the exponent.  */
9138
9139     f64_frac = ((uint64_t) f32_frac) << 29;
9140     if (f32_exp == 0) {
9141         while (extract64(f64_frac, 51, 1) == 0) {
9142             f64_frac = f64_frac << 1;
9143             f32_exp = f32_exp-1;
9144         }
9145         f64_frac = extract64(f64_frac, 0, 51) << 1;
9146     }
9147
9148     if (extract64(f32_exp, 0, 1) == 0) {
9149         f64 = make_float64(((uint64_t) f32_sbit) << 32
9150                            | (0x3feULL << 52)
9151                            | f64_frac);
9152     } else {
9153         f64 = make_float64(((uint64_t) f32_sbit) << 32
9154                            | (0x3fdULL << 52)
9155                            | f64_frac);
9156     }
9157
9158     result_exp = (380 - f32_exp) / 2;
9159
9160     f64 = recip_sqrt_estimate(f64, s);
9161
9162     val64 = float64_val(f64);
9163
9164     val = ((result_exp & 0xff) << 23)
9165         | ((val64 >> 29)  & 0x7fffff);
9166     return make_float32(val);
9167 }
9168
9169 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
9170 {
9171     float_status *s = fpstp;
9172     float64 f64 = float64_squash_input_denormal(input, s);
9173     uint64_t val = float64_val(f64);
9174     uint64_t f64_sbit = 0x8000000000000000ULL & val;
9175     int64_t f64_exp = extract64(val, 52, 11);
9176     uint64_t f64_frac = extract64(val, 0, 52);
9177     int64_t result_exp;
9178     uint64_t result_frac;
9179
9180     if (float64_is_any_nan(f64)) {
9181         float64 nan = f64;
9182         if (float64_is_signaling_nan(f64)) {
9183             float_raise(float_flag_invalid, s);
9184             nan = float64_maybe_silence_nan(f64);
9185         }
9186         if (s->default_nan_mode) {
9187             nan =  float64_default_nan;
9188         }
9189         return nan;
9190     } else if (float64_is_zero(f64)) {
9191         float_raise(float_flag_divbyzero, s);
9192         return float64_set_sign(float64_infinity, float64_is_neg(f64));
9193     } else if (float64_is_neg(f64)) {
9194         float_raise(float_flag_invalid, s);
9195         return float64_default_nan;
9196     } else if (float64_is_infinity(f64)) {
9197         return float64_zero;
9198     }
9199
9200     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
9201      * preserving the parity of the exponent.  */
9202
9203     if (f64_exp == 0) {
9204         while (extract64(f64_frac, 51, 1) == 0) {
9205             f64_frac = f64_frac << 1;
9206             f64_exp = f64_exp - 1;
9207         }
9208         f64_frac = extract64(f64_frac, 0, 51) << 1;
9209     }
9210
9211     if (extract64(f64_exp, 0, 1) == 0) {
9212         f64 = make_float64(f64_sbit
9213                            | (0x3feULL << 52)
9214                            | f64_frac);
9215     } else {
9216         f64 = make_float64(f64_sbit
9217                            | (0x3fdULL << 52)
9218                            | f64_frac);
9219     }
9220
9221     result_exp = (3068 - f64_exp) / 2;
9222
9223     f64 = recip_sqrt_estimate(f64, s);
9224
9225     result_frac = extract64(float64_val(f64), 0, 52);
9226
9227     return make_float64(f64_sbit |
9228                         ((result_exp & 0x7ff) << 52) |
9229                         result_frac);
9230 }
9231
9232 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
9233 {
9234     float_status *s = fpstp;
9235     float64 f64;
9236
9237     if ((a & 0x80000000) == 0) {
9238         return 0xffffffff;
9239     }
9240
9241     f64 = make_float64((0x3feULL << 52)
9242                        | ((int64_t)(a & 0x7fffffff) << 21));
9243
9244     f64 = recip_estimate(f64, s);
9245
9246     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
9247 }
9248
9249 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
9250 {
9251     float_status *fpst = fpstp;
9252     float64 f64;
9253
9254     if ((a & 0xc0000000) == 0) {
9255         return 0xffffffff;
9256     }
9257
9258     if (a & 0x80000000) {
9259         f64 = make_float64((0x3feULL << 52)
9260                            | ((uint64_t)(a & 0x7fffffff) << 21));
9261     } else { /* bits 31-30 == '01' */
9262         f64 = make_float64((0x3fdULL << 52)
9263                            | ((uint64_t)(a & 0x3fffffff) << 22));
9264     }
9265
9266     f64 = recip_sqrt_estimate(f64, fpst);
9267
9268     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
9269 }
9270
9271 /* VFPv4 fused multiply-accumulate */
9272 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
9273 {
9274     float_status *fpst = fpstp;
9275     return float32_muladd(a, b, c, 0, fpst);
9276 }
9277
9278 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
9279 {
9280     float_status *fpst = fpstp;
9281     return float64_muladd(a, b, c, 0, fpst);
9282 }
9283
9284 /* ARMv8 round to integral */
9285 float32 HELPER(rints_exact)(float32 x, void *fp_status)
9286 {
9287     return float32_round_to_int(x, fp_status);
9288 }
9289
9290 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
9291 {
9292     return float64_round_to_int(x, fp_status);
9293 }
9294
9295 float32 HELPER(rints)(float32 x, void *fp_status)
9296 {
9297     int old_flags = get_float_exception_flags(fp_status), new_flags;
9298     float32 ret;
9299
9300     ret = float32_round_to_int(x, fp_status);
9301
9302     /* Suppress any inexact exceptions the conversion produced */
9303     if (!(old_flags & float_flag_inexact)) {
9304         new_flags = get_float_exception_flags(fp_status);
9305         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
9306     }
9307
9308     return ret;
9309 }
9310
9311 float64 HELPER(rintd)(float64 x, void *fp_status)
9312 {
9313     int old_flags = get_float_exception_flags(fp_status), new_flags;
9314     float64 ret;
9315
9316     ret = float64_round_to_int(x, fp_status);
9317
9318     new_flags = get_float_exception_flags(fp_status);
9319
9320     /* Suppress any inexact exceptions the conversion produced */
9321     if (!(old_flags & float_flag_inexact)) {
9322         new_flags = get_float_exception_flags(fp_status);
9323         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
9324     }
9325
9326     return ret;
9327 }
9328
9329 /* Convert ARM rounding mode to softfloat */
9330 int arm_rmode_to_sf(int rmode)
9331 {
9332     switch (rmode) {
9333     case FPROUNDING_TIEAWAY:
9334         rmode = float_round_ties_away;
9335         break;
9336     case FPROUNDING_ODD:
9337         /* FIXME: add support for TIEAWAY and ODD */
9338         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
9339                       rmode);
9340     case FPROUNDING_TIEEVEN:
9341     default:
9342         rmode = float_round_nearest_even;
9343         break;
9344     case FPROUNDING_POSINF:
9345         rmode = float_round_up;
9346         break;
9347     case FPROUNDING_NEGINF:
9348         rmode = float_round_down;
9349         break;
9350     case FPROUNDING_ZERO:
9351         rmode = float_round_to_zero;
9352         break;
9353     }
9354     return rmode;
9355 }
9356
9357 /* CRC helpers.
9358  * The upper bytes of val (above the number specified by 'bytes') must have
9359  * been zeroed out by the caller.
9360  */
9361 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
9362 {
9363     uint8_t buf[4];
9364
9365     stl_le_p(buf, val);
9366
9367     /* zlib crc32 converts the accumulator and output to one's complement.  */
9368     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
9369 }
9370
9371 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
9372 {
9373     uint8_t buf[4];
9374
9375     stl_le_p(buf, val);
9376
9377     /* Linux crc32c converts the output to one's complement.  */
9378     return crc32c(acc, buf, bytes) ^ 0xffffffff;
9379 }