hw/intc/pl190.c

   1 /*
   2  * Arm PrimeCell PL190 Vector Interrupt Controller
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licensed under the GPL.
   8  */
   9
  10 #include "qemu/osdep.h"
  11 #include "hw/sysbus.h"
  12 #include "qemu/log.h"
  13
  14 /* The number of virtual priority levels.  16 user vectors plus the
  15    unvectored IRQ.  Chained interrupts would require an additional level
  16    if implemented.  */
  17
  18 #define PL190_NUM_PRIO 17
  19
  20 #define TYPE_PL190 "pl190"
  21 #define PL190(obj) OBJECT_CHECK(PL190State, (obj), TYPE_PL190)
  22
  23 typedef struct PL190State {
  24     SysBusDevice parent_obj;
  25
  26     MemoryRegion iomem;
  27     uint32_t level;
  28     uint32_t soft_level;
  29     uint32_t irq_enable;
  30     uint32_t fiq_select;
  31     uint8_t vect_control[16];
  32     uint32_t vect_addr[PL190_NUM_PRIO];
  33     /* Mask containing interrupts with higher priority than this one.  */
  34     uint32_t prio_mask[PL190_NUM_PRIO + 1];
  35     int protected;
  36     /* Current priority level.  */
  37     int priority;
  38     int prev_prio[PL190_NUM_PRIO];
  39     qemu_irq irq;
  40     qemu_irq fiq;
  41 } PL190State;
  42
  43 static const unsigned char pl190_id[] =
  44 { 0x90, 0x11, 0x04, 0x00, 0x0D, 0xf0, 0x05, 0xb1 };
  45
  46 static inline uint32_t pl190_irq_level(PL190State *s)
  47 {
  48     return (s->level | s->soft_level) & s->irq_enable & ~s->fiq_select;
  49 }
  50
  51 /* Update interrupts.  */
  52 static void pl190_update(PL190State *s)
  53 {
  54     uint32_t level = pl190_irq_level(s);
  55     int set;
  56
  57     set = (level & s->prio_mask[s->priority]) != 0;
  58     qemu_set_irq(s->irq, set);
  59     set = ((s->level | s->soft_level) & s->fiq_select) != 0;
  60     qemu_set_irq(s->fiq, set);
  61 }
  62
  63 static void pl190_set_irq(void *opaque, int irq, int level)
  64 {
  65     PL190State *s = (PL190State *)opaque;
  66
  67     if (level)
  68         s->level |= 1u << irq;
  69     else
  70         s->level &= ~(1u << irq);
  71     pl190_update(s);
  72 }
  73
  74 static void pl190_update_vectors(PL190State *s)
  75 {
  76     uint32_t mask;
  77     int i;
  78     int n;
  79
  80     mask = 0;
  81     for (i = 0; i < 16; i++)
  82       {
  83         s->prio_mask[i] = mask;
  84         if (s->vect_control[i] & 0x20)
  85           {
  86             n = s->vect_control[i] & 0x1f;
  87             mask |= 1 << n;
  88           }
  89       }
  90     s->prio_mask[16] = mask;
  91     pl190_update(s);
  92 }
  93
  94 static uint64_t pl190_read(void *opaque, hwaddr offset,
  95                            unsigned size)
  96 {
  97     PL190State *s = (PL190State *)opaque;
  98     int i;
  99
 100     if (offset >= 0xfe0 && offset < 0x1000) {
 101         return pl190_id[(offset - 0xfe0) >> 2];
 102     }
 103     if (offset >= 0x100 && offset < 0x140) {
 104         return s->vect_addr[(offset - 0x100) >> 2];
 105     }
 106     if (offset >= 0x200 && offset < 0x240) {
 107         return s->vect_control[(offset - 0x200) >> 2];
 108     }
 109     switch (offset >> 2) {
 110     case 0: /* IRQSTATUS */
 111         return pl190_irq_level(s);
 112     case 1: /* FIQSATUS */
 113         return (s->level | s->soft_level) & s->fiq_select;
 114     case 2: /* RAWINTR */
 115         return s->level | s->soft_level;
 116     case 3: /* INTSELECT */
 117         return s->fiq_select;
 118     case 4: /* INTENABLE */
 119         return s->irq_enable;
 120     case 6: /* SOFTINT */
 121         return s->soft_level;
 122     case 8: /* PROTECTION */
 123         return s->protected;
 124     case 12: /* VECTADDR */
 125         /* Read vector address at the start of an ISR.  Increases the
 126          * current priority level to that of the current interrupt.
 127          *
 128          * Since an enabled interrupt X at priority P causes prio_mask[Y]
 129          * to have bit X set for all Y > P, this loop will stop with
 130          * i == the priority of the highest priority set interrupt.
 131          */
 132         for (i = 0; i < s->priority; i++) {
 133             if ((s->level | s->soft_level) & s->prio_mask[i + 1]) {
 134                 break;
 135             }
 136         }
 137
 138         /* Reading this value with no pending interrupts is undefined.
 139            We return the default address.  */
 140         if (i == PL190_NUM_PRIO)
 141           return s->vect_addr[16];
 142         if (i < s->priority)
 143           {
 144             s->prev_prio[i] = s->priority;
 145             s->priority = i;
 146             pl190_update(s);
 147           }
 148         return s->vect_addr[s->priority];
 149     case 13: /* DEFVECTADDR */
 150         return s->vect_addr[16];
 151     default:
 152         qemu_log_mask(LOG_GUEST_ERROR,
 153                       "pl190_read: Bad offset %x\n", (int)offset);
 154         return 0;
 155     }
 156 }
 157
 158 static void pl190_write(void *opaque, hwaddr offset,
 159                         uint64_t val, unsigned size)
 160 {
 161     PL190State *s = (PL190State *)opaque;
 162
 163     if (offset >= 0x100 && offset < 0x140) {
 164         s->vect_addr[(offset - 0x100) >> 2] = val;
 165         pl190_update_vectors(s);
 166         return;
 167     }
 168     if (offset >= 0x200 && offset < 0x240) {
 169         s->vect_control[(offset - 0x200) >> 2] = val;
 170         pl190_update_vectors(s);
 171         return;
 172     }
 173     switch (offset >> 2) {
 174     case 0: /* SELECT */
 175         /* This is a readonly register, but linux tries to write to it
 176            anyway.  Ignore the write.  */
 177         break;
 178     case 3: /* INTSELECT */
 179         s->fiq_select = val;
 180         break;
 181     case 4: /* INTENABLE */
 182         s->irq_enable |= val;
 183         break;
 184     case 5: /* INTENCLEAR */
 185         s->irq_enable &= ~val;
 186         break;
 187     case 6: /* SOFTINT */
 188         s->soft_level |= val;
 189         break;
 190     case 7: /* SOFTINTCLEAR */
 191         s->soft_level &= ~val;
 192         break;
 193     case 8: /* PROTECTION */
 194         /* TODO: Protection (supervisor only access) is not implemented.  */
 195         s->protected = val & 1;
 196         break;
 197     case 12: /* VECTADDR */
 198         /* Restore the previous priority level.  The value written is
 199            ignored.  */
 200         if (s->priority < PL190_NUM_PRIO)
 201             s->priority = s->prev_prio[s->priority];
 202         break;
 203     case 13: /* DEFVECTADDR */
 204         s->vect_addr[16] = val;
 205         break;
 206     case 0xc0: /* ITCR */
 207         if (val) {
 208             qemu_log_mask(LOG_UNIMP, "pl190: Test mode not implemented\n");
 209         }
 210         break;
 211     default:
 212         qemu_log_mask(LOG_GUEST_ERROR,
 213                      "pl190_write: Bad offset %x\n", (int)offset);
 214         return;
 215     }
 216     pl190_update(s);
 217 }
 218
 219 static const MemoryRegionOps pl190_ops = {
 220     .read = pl190_read,
 221     .write = pl190_write,
 222     .endianness = DEVICE_NATIVE_ENDIAN,
 223 };
 224
 225 static void pl190_reset(DeviceState *d)
 226 {
 227     PL190State *s = PL190(d);
 228     int i;
 229
 230     for (i = 0; i < 16; i++) {
 231         s->vect_addr[i] = 0;
 232         s->vect_control[i] = 0;
 233     }
 234     s->vect_addr[16] = 0;
 235     s->prio_mask[17] = 0xffffffff;
 236     s->priority = PL190_NUM_PRIO;
 237     pl190_update_vectors(s);
 238 }
 239
 240 static void pl190_init(Object *obj)
 241 {
 242     DeviceState *dev = DEVICE(obj);
 243     PL190State *s = PL190(obj);
 244     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 245
 246     memory_region_init_io(&s->iomem, obj, &pl190_ops, s, "pl190", 0x1000);
 247     sysbus_init_mmio(sbd, &s->iomem);
 248     qdev_init_gpio_in(dev, pl190_set_irq, 32);
 249     sysbus_init_irq(sbd, &s->irq);
 250     sysbus_init_irq(sbd, &s->fiq);
 251 }
 252
 253 static const VMStateDescription vmstate_pl190 = {
 254     .name = "pl190",
 255     .version_id = 1,
 256     .minimum_version_id = 1,
 257     .fields = (VMStateField[]) {
 258         VMSTATE_UINT32(level, PL190State),
 259         VMSTATE_UINT32(soft_level, PL190State),
 260         VMSTATE_UINT32(irq_enable, PL190State),
 261         VMSTATE_UINT32(fiq_select, PL190State),
 262         VMSTATE_UINT8_ARRAY(vect_control, PL190State, 16),
 263         VMSTATE_UINT32_ARRAY(vect_addr, PL190State, PL190_NUM_PRIO),
 264         VMSTATE_UINT32_ARRAY(prio_mask, PL190State, PL190_NUM_PRIO+1),
 265         VMSTATE_INT32(protected, PL190State),
 266         VMSTATE_INT32(priority, PL190State),
 267         VMSTATE_INT32_ARRAY(prev_prio, PL190State, PL190_NUM_PRIO),
 268         VMSTATE_END_OF_LIST()
 269     }
 270 };
 271
 272 static void pl190_class_init(ObjectClass *klass, void *data)
 273 {
 274     DeviceClass *dc = DEVICE_CLASS(klass);
 275
 276     dc->reset = pl190_reset;
 277     dc->vmsd = &vmstate_pl190;
 278 }
 279
 280 static const TypeInfo pl190_info = {
 281     .name          = TYPE_PL190,
 282     .parent        = TYPE_SYS_BUS_DEVICE,
 283     .instance_size = sizeof(PL190State),
 284     .instance_init = pl190_init,
 285     .class_init    = pl190_class_init,
 286 };
 287
 288 static void pl190_register_types(void)
 289 {
 290     type_register_static(&pl190_info);
 291 }
 292
 293 type_init(pl190_register_types)