3 * TI X3130 pci express downstream port switch
5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
6 * VA Linux Systems Japan K.K.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, see <http://www.gnu.org/licenses/>.
25 #include "xio3130_downstream.h"
27 #define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */
28 #define XIO3130_REVISION 0x1
29 #define XIO3130_MSI_OFFSET 0x70
30 #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT
31 #define XIO3130_MSI_NR_VECTOR 1
32 #define XIO3130_SSVID_OFFSET 0x80
33 #define XIO3130_SSVID_SVID 0
34 #define XIO3130_SSVID_SSID 0
35 #define XIO3130_EXP_OFFSET 0x90
36 #define XIO3130_AER_OFFSET 0x100
38 static void xio3130_downstream_write_config(PCIDevice
*d
, uint32_t address
,
39 uint32_t val
, int len
)
41 pci_bridge_write_config(d
, address
, val
, len
);
42 pcie_cap_flr_write_config(d
, address
, val
, len
);
43 pcie_cap_slot_write_config(d
, address
, val
, len
);
44 msi_write_config(d
, address
, val
, len
);
48 static void xio3130_downstream_reset(DeviceState
*qdev
)
50 PCIDevice
*d
= DO_UPCAST(PCIDevice
, qdev
, qdev
);
52 pcie_cap_deverr_reset(d
);
53 pcie_cap_slot_reset(d
);
54 pcie_cap_ari_reset(d
);
55 pci_bridge_reset(qdev
);
58 static int xio3130_downstream_initfn(PCIDevice
*d
)
60 PCIBridge
* br
= DO_UPCAST(PCIBridge
, dev
, d
);
61 PCIEPort
*p
= DO_UPCAST(PCIEPort
, br
, br
);
62 PCIESlot
*s
= DO_UPCAST(PCIESlot
, port
, p
);
65 rc
= pci_bridge_initfn(d
);
70 pcie_port_init_reg(d
);
71 pci_config_set_vendor_id(d
->config
, PCI_VENDOR_ID_TI
);
72 pci_config_set_device_id(d
->config
, PCI_DEVICE_ID_TI_XIO3130D
);
73 d
->config
[PCI_REVISION_ID
] = XIO3130_REVISION
;
75 rc
= msi_init(d
, XIO3130_MSI_OFFSET
, XIO3130_MSI_NR_VECTOR
,
76 XIO3130_MSI_SUPPORTED_FLAGS
& PCI_MSI_FLAGS_64BIT
,
77 XIO3130_MSI_SUPPORTED_FLAGS
& PCI_MSI_FLAGS_MASKBIT
);
81 rc
= pci_bridge_ssvid_init(d
, XIO3130_SSVID_OFFSET
,
82 XIO3130_SSVID_SVID
, XIO3130_SSVID_SSID
);
86 rc
= pcie_cap_init(d
, XIO3130_EXP_OFFSET
, PCI_EXP_TYPE_DOWNSTREAM
,
91 pcie_cap_flr_init(d
); /* TODO: implement FLR */
92 pcie_cap_deverr_init(d
);
93 pcie_cap_slot_init(d
, s
->slot
);
94 pcie_chassis_create(s
->chassis
);
95 rc
= pcie_chassis_add_slot(s
);
105 static int xio3130_downstream_exitfn(PCIDevice
*d
)
110 return pci_bridge_exitfn(d
);
113 PCIESlot
*xio3130_downstream_init(PCIBus
*bus
, int devfn
, bool multifunction
,
114 const char *bus_name
, pci_map_irq_fn map_irq
,
115 uint8_t port
, uint8_t chassis
,
122 d
= pci_create_multifunction(bus
, devfn
, multifunction
,
123 "xio3130-downstream");
127 br
= DO_UPCAST(PCIBridge
, dev
, d
);
129 qdev
= &br
->dev
.qdev
;
130 pci_bridge_map_irq(br
, bus_name
, map_irq
);
131 qdev_prop_set_uint8(qdev
, "port", port
);
132 qdev_prop_set_uint8(qdev
, "chassis", chassis
);
133 qdev_prop_set_uint16(qdev
, "slot", slot
);
134 qdev_init_nofail(qdev
);
136 return DO_UPCAST(PCIESlot
, port
, DO_UPCAST(PCIEPort
, br
, br
));
139 static const VMStateDescription vmstate_xio3130_downstream
= {
140 .name
= "xio3130-express-downstream-port",
142 .minimum_version_id
= 1,
143 .minimum_version_id_old
= 1,
144 .post_load
= pcie_cap_slot_post_load
,
145 .fields
= (VMStateField
[]) {
146 VMSTATE_PCIE_DEVICE(port
.br
.dev
, PCIESlot
),
148 VMSTATE_END_OF_LIST()
152 static PCIDeviceInfo xio3130_downstream_info
= {
153 .qdev
.name
= "xio3130-downstream",
154 .qdev
.desc
= "TI X3130 Downstream Port of PCI Express Switch",
155 .qdev
.size
= sizeof(PCIESlot
),
156 .qdev
.reset
= xio3130_downstream_reset
,
157 .qdev
.vmsd
= &vmstate_xio3130_downstream
,
161 .config_write
= xio3130_downstream_write_config
,
162 .init
= xio3130_downstream_initfn
,
163 .exit
= xio3130_downstream_exitfn
,
165 .qdev
.props
= (Property
[]) {
166 DEFINE_PROP_UINT8("port", PCIESlot
, port
.port
, 0),
167 DEFINE_PROP_UINT8("chassis", PCIESlot
, chassis
, 0),
168 DEFINE_PROP_UINT16("slot", PCIESlot
, slot
, 0),
170 DEFINE_PROP_END_OF_LIST(),
174 static void xio3130_downstream_register(void)
176 pci_qdev_register(&xio3130_downstream_info
);
179 device_init(xio3130_downstream_register
);
186 * indent-tab-mode: nil