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spice: don't create updates in spice server context.
[qemu.git] / hw / qxl.c
blobbd250db8850c42932f44423c18e4cde2840c1710
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <pthread.h>
22
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "qemu-queue.h"
26 #include "monitor.h"
27 #include "sysemu.h"
28
29 #include "qxl.h"
30
31 #undef SPICE_RING_PROD_ITEM
32 #define SPICE_RING_PROD_ITEM(r, ret) { \
33 typeof(r) start = r; \
34 typeof(r) end = r + 1; \
35 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
36 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
37 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
38 abort(); \
39 } \
40 ret = &m_item->el; \
41 }
42
43 #undef SPICE_RING_CONS_ITEM
44 #define SPICE_RING_CONS_ITEM(r, ret) { \
45 typeof(r) start = r; \
46 typeof(r) end = r + 1; \
47 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
48 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
49 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
50 abort(); \
51 } \
52 ret = &m_item->el; \
53 }
54
55 #undef ALIGN
56 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
57
58 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
59
60 #define QXL_MODE(_x, _y, _b, _o) \
61 { .x_res = _x, \
62 .y_res = _y, \
63 .bits = _b, \
64 .stride = (_x) * (_b) / 8, \
65 .x_mili = PIXEL_SIZE * (_x), \
66 .y_mili = PIXEL_SIZE * (_y), \
67 .orientation = _o, \
68 }
69
70 #define QXL_MODE_16_32(x_res, y_res, orientation) \
71 QXL_MODE(x_res, y_res, 16, orientation), \
72 QXL_MODE(x_res, y_res, 32, orientation)
73
74 #define QXL_MODE_EX(x_res, y_res) \
75 QXL_MODE_16_32(x_res, y_res, 0), \
76 QXL_MODE_16_32(y_res, x_res, 1), \
77 QXL_MODE_16_32(x_res, y_res, 2), \
78 QXL_MODE_16_32(y_res, x_res, 3)
79
80 static QXLMode qxl_modes[] = {
81 QXL_MODE_EX(640, 480),
82 QXL_MODE_EX(800, 480),
83 QXL_MODE_EX(800, 600),
84 QXL_MODE_EX(832, 624),
85 QXL_MODE_EX(960, 640),
86 QXL_MODE_EX(1024, 600),
87 QXL_MODE_EX(1024, 768),
88 QXL_MODE_EX(1152, 864),
89 QXL_MODE_EX(1152, 870),
90 QXL_MODE_EX(1280, 720),
91 QXL_MODE_EX(1280, 760),
92 QXL_MODE_EX(1280, 768),
93 QXL_MODE_EX(1280, 800),
94 QXL_MODE_EX(1280, 960),
95 QXL_MODE_EX(1280, 1024),
96 QXL_MODE_EX(1360, 768),
97 QXL_MODE_EX(1366, 768),
98 QXL_MODE_EX(1400, 1050),
99 QXL_MODE_EX(1440, 900),
100 QXL_MODE_EX(1600, 900),
101 QXL_MODE_EX(1600, 1200),
102 QXL_MODE_EX(1680, 1050),
103 QXL_MODE_EX(1920, 1080),
104 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
105 /* these modes need more than 8 MB video memory */
106 QXL_MODE_EX(1920, 1200),
107 QXL_MODE_EX(1920, 1440),
108 QXL_MODE_EX(2048, 1536),
109 QXL_MODE_EX(2560, 1440),
110 QXL_MODE_EX(2560, 1600),
111 #endif
112 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
113 /* these modes need more than 16 MB video memory */
114 QXL_MODE_EX(2560, 2048),
115 QXL_MODE_EX(2800, 2100),
116 QXL_MODE_EX(3200, 2400),
117 #endif
118 };
119
120 static PCIQXLDevice *qxl0;
121
122 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
123 static void qxl_destroy_primary(PCIQXLDevice *d);
124 static void qxl_reset_memslots(PCIQXLDevice *d);
125 static void qxl_reset_surfaces(PCIQXLDevice *d);
126 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
127
128 static inline uint32_t msb_mask(uint32_t val)
129 {
130 uint32_t mask;
131
132 do {
133 mask = ~(val - 1) & val;
134 val &= ~mask;
135 } while (mask < val);
136
137 return mask;
138 }
139
140 static ram_addr_t qxl_rom_size(void)
141 {
142 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
143 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
144 rom_size = msb_mask(rom_size * 2 - 1);
145 return rom_size;
146 }
147
148 static void init_qxl_rom(PCIQXLDevice *d)
149 {
150 QXLRom *rom = qemu_get_ram_ptr(d->rom_offset);
151 QXLModes *modes = (QXLModes *)(rom + 1);
152 uint32_t ram_header_size;
153 uint32_t surface0_area_size;
154 uint32_t num_pages;
155 uint32_t fb, maxfb = 0;
156 int i;
157
158 memset(rom, 0, d->rom_size);
159
160 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
161 rom->id = cpu_to_le32(d->id);
162 rom->log_level = cpu_to_le32(d->guestdebug);
163 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
164
165 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
166 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
167 rom->slots_start = 1;
168 rom->slots_end = NUM_MEMSLOTS - 1;
169 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
170
171 modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes));
172 for (i = 0; i < modes->n_modes; i++) {
173 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
174 if (maxfb < fb) {
175 maxfb = fb;
176 }
177 modes->modes[i].id = cpu_to_le32(i);
178 modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res);
179 modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res);
180 modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits);
181 modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride);
182 modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
183 modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
184 modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
185 }
186 if (maxfb < VGA_RAM_SIZE && d->id == 0)
187 maxfb = VGA_RAM_SIZE;
188
189 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
190 surface0_area_size = ALIGN(maxfb, 4096);
191 num_pages = d->vga.vram_size;
192 num_pages -= ram_header_size;
193 num_pages -= surface0_area_size;
194 num_pages = num_pages / TARGET_PAGE_SIZE;
195
196 rom->draw_area_offset = cpu_to_le32(0);
197 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
198 rom->pages_offset = cpu_to_le32(surface0_area_size);
199 rom->num_pages = cpu_to_le32(num_pages);
200 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
201
202 d->shadow_rom = *rom;
203 d->rom = rom;
204 d->modes = modes;
205 }
206
207 static void init_qxl_ram(PCIQXLDevice *d)
208 {
209 uint8_t *buf;
210 uint64_t *item;
211
212 buf = d->vga.vram_ptr;
213 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
214 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
215 d->ram->int_pending = cpu_to_le32(0);
216 d->ram->int_mask = cpu_to_le32(0);
217 SPICE_RING_INIT(&d->ram->cmd_ring);
218 SPICE_RING_INIT(&d->ram->cursor_ring);
219 SPICE_RING_INIT(&d->ram->release_ring);
220 SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
221 *item = 0;
222 qxl_ring_set_dirty(d);
223 }
224
225 /* can be called from spice server thread context */
226 static void qxl_set_dirty(ram_addr_t addr, ram_addr_t end)
227 {
228 while (addr < end) {
229 cpu_physical_memory_set_dirty(addr);
230 addr += TARGET_PAGE_SIZE;
231 }
232 }
233
234 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
235 {
236 ram_addr_t addr = qxl->rom_offset;
237 qxl_set_dirty(addr, addr + qxl->rom_size);
238 }
239
240 /* called from spice server thread context only */
241 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
242 {
243 ram_addr_t addr = qxl->vga.vram_offset;
244 void *base = qxl->vga.vram_ptr;
245 intptr_t offset;
246
247 offset = ptr - base;
248 offset &= ~(TARGET_PAGE_SIZE-1);
249 assert(offset < qxl->vga.vram_size);
250 qxl_set_dirty(addr + offset, addr + offset + TARGET_PAGE_SIZE);
251 }
252
253 /* can be called from spice server thread context */
254 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
255 {
256 ram_addr_t addr = qxl->vga.vram_offset + qxl->shadow_rom.ram_header_offset;
257 ram_addr_t end = qxl->vga.vram_offset + qxl->vga.vram_size;
258 qxl_set_dirty(addr, end);
259 }
260
261 /*
262 * keep track of some command state, for savevm/loadvm.
263 * called from spice server thread context only
264 */
265 static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
266 {
267 switch (le32_to_cpu(ext->cmd.type)) {
268 case QXL_CMD_SURFACE:
269 {
270 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
271 uint32_t id = le32_to_cpu(cmd->surface_id);
272 PANIC_ON(id >= NUM_SURFACES);
273 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
274 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
275 qxl->guest_surfaces.count++;
276 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
277 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
278 }
279 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
280 qxl->guest_surfaces.cmds[id] = 0;
281 qxl->guest_surfaces.count--;
282 }
283 break;
284 }
285 case QXL_CMD_CURSOR:
286 {
287 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
288 if (cmd->type == QXL_CURSOR_SET) {
289 qxl->guest_cursor = ext->cmd.data;
290 }
291 break;
292 }
293 }
294 }
295
296 /* spice display interface callbacks */
297
298 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
299 {
300 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
301
302 dprint(qxl, 1, "%s:\n", __FUNCTION__);
303 qxl->ssd.worker = qxl_worker;
304 }
305
306 static void interface_set_compression_level(QXLInstance *sin, int level)
307 {
308 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
309
310 dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level);
311 qxl->shadow_rom.compression_level = cpu_to_le32(level);
312 qxl->rom->compression_level = cpu_to_le32(level);
313 qxl_rom_set_dirty(qxl);
314 }
315
316 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
317 {
318 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
319
320 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
321 qxl->rom->mm_clock = cpu_to_le32(mm_time);
322 qxl_rom_set_dirty(qxl);
323 }
324
325 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
326 {
327 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
328
329 dprint(qxl, 1, "%s:\n", __FUNCTION__);
330 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
331 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
332 info->num_memslots = NUM_MEMSLOTS;
333 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
334 info->internal_groupslot_id = 0;
335 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
336 info->n_surfaces = NUM_SURFACES;
337 }
338
339 /* called from spice server thread context only */
340 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
341 {
342 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
343 SimpleSpiceUpdate *update;
344 QXLCommandRing *ring;
345 QXLCommand *cmd;
346 int notify, ret;
347
348 switch (qxl->mode) {
349 case QXL_MODE_VGA:
350 dprint(qxl, 2, "%s: vga\n", __FUNCTION__);
351 ret = false;
352 qemu_mutex_lock(&qxl->ssd.lock);
353 if (qxl->ssd.update != NULL) {
354 update = qxl->ssd.update;
355 qxl->ssd.update = NULL;
356 *ext = update->ext;
357 ret = true;
358 }
359 qemu_mutex_unlock(&qxl->ssd.lock);
360 qxl_log_command(qxl, "vga", ext);
361 return ret;
362 case QXL_MODE_COMPAT:
363 case QXL_MODE_NATIVE:
364 case QXL_MODE_UNDEFINED:
365 dprint(qxl, 2, "%s: %s\n", __FUNCTION__,
366 qxl->cmdflags ? "compat" : "native");
367 ring = &qxl->ram->cmd_ring;
368 if (SPICE_RING_IS_EMPTY(ring)) {
369 return false;
370 }
371 SPICE_RING_CONS_ITEM(ring, cmd);
372 ext->cmd = *cmd;
373 ext->group_id = MEMSLOT_GROUP_GUEST;
374 ext->flags = qxl->cmdflags;
375 SPICE_RING_POP(ring, notify);
376 qxl_ring_set_dirty(qxl);
377 if (notify) {
378 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
379 }
380 qxl->guest_primary.commands++;
381 qxl_track_command(qxl, ext);
382 qxl_log_command(qxl, "cmd", ext);
383 return true;
384 default:
385 return false;
386 }
387 }
388
389 /* called from spice server thread context only */
390 static int interface_req_cmd_notification(QXLInstance *sin)
391 {
392 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
393 int wait = 1;
394
395 switch (qxl->mode) {
396 case QXL_MODE_COMPAT:
397 case QXL_MODE_NATIVE:
398 case QXL_MODE_UNDEFINED:
399 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
400 qxl_ring_set_dirty(qxl);
401 break;
402 default:
403 /* nothing */
404 break;
405 }
406 return wait;
407 }
408
409 /* called from spice server thread context only */
410 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
411 {
412 QXLReleaseRing *ring = &d->ram->release_ring;
413 uint64_t *item;
414 int notify;
415
416 #define QXL_FREE_BUNCH_SIZE 32
417
418 if (ring->prod - ring->cons + 1 == ring->num_items) {
419 /* ring full -- can't push */
420 return;
421 }
422 if (!flush && d->oom_running) {
423 /* collect everything from oom handler before pushing */
424 return;
425 }
426 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
427 /* collect a bit more before pushing */
428 return;
429 }
430
431 SPICE_RING_PUSH(ring, notify);
432 dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
433 d->num_free_res, notify ? "yes" : "no",
434 ring->prod - ring->cons, ring->num_items,
435 ring->prod, ring->cons);
436 if (notify) {
437 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
438 }
439 SPICE_RING_PROD_ITEM(ring, item);
440 *item = 0;
441 d->num_free_res = 0;
442 d->last_release = NULL;
443 qxl_ring_set_dirty(d);
444 }
445
446 /* called from spice server thread context only */
447 static void interface_release_resource(QXLInstance *sin,
448 struct QXLReleaseInfoExt ext)
449 {
450 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
451 QXLReleaseRing *ring;
452 uint64_t *item, id;
453
454 if (ext.group_id == MEMSLOT_GROUP_HOST) {
455 /* host group -> vga mode update request */
456 qemu_spice_destroy_update(&qxl->ssd, (void*)ext.info->id);
457 return;
458 }
459
460 /*
461 * ext->info points into guest-visible memory
462 * pci bar 0, $command.release_info
463 */
464 ring = &qxl->ram->release_ring;
465 SPICE_RING_PROD_ITEM(ring, item);
466 if (*item == 0) {
467 /* stick head into the ring */
468 id = ext.info->id;
469 ext.info->next = 0;
470 qxl_ram_set_dirty(qxl, &ext.info->next);
471 *item = id;
472 qxl_ring_set_dirty(qxl);
473 } else {
474 /* append item to the list */
475 qxl->last_release->next = ext.info->id;
476 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
477 ext.info->next = 0;
478 qxl_ram_set_dirty(qxl, &ext.info->next);
479 }
480 qxl->last_release = ext.info;
481 qxl->num_free_res++;
482 dprint(qxl, 3, "%4d\r", qxl->num_free_res);
483 qxl_push_free_res(qxl, 0);
484 }
485
486 /* called from spice server thread context only */
487 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
488 {
489 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
490 QXLCursorRing *ring;
491 QXLCommand *cmd;
492 int notify;
493
494 switch (qxl->mode) {
495 case QXL_MODE_COMPAT:
496 case QXL_MODE_NATIVE:
497 case QXL_MODE_UNDEFINED:
498 ring = &qxl->ram->cursor_ring;
499 if (SPICE_RING_IS_EMPTY(ring)) {
500 return false;
501 }
502 SPICE_RING_CONS_ITEM(ring, cmd);
503 ext->cmd = *cmd;
504 ext->group_id = MEMSLOT_GROUP_GUEST;
505 ext->flags = qxl->cmdflags;
506 SPICE_RING_POP(ring, notify);
507 qxl_ring_set_dirty(qxl);
508 if (notify) {
509 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
510 }
511 qxl->guest_primary.commands++;
512 qxl_track_command(qxl, ext);
513 qxl_log_command(qxl, "csr", ext);
514 if (qxl->id == 0) {
515 qxl_render_cursor(qxl, ext);
516 }
517 return true;
518 default:
519 return false;
520 }
521 }
522
523 /* called from spice server thread context only */
524 static int interface_req_cursor_notification(QXLInstance *sin)
525 {
526 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
527 int wait = 1;
528
529 switch (qxl->mode) {
530 case QXL_MODE_COMPAT:
531 case QXL_MODE_NATIVE:
532 case QXL_MODE_UNDEFINED:
533 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
534 qxl_ring_set_dirty(qxl);
535 break;
536 default:
537 /* nothing */
538 break;
539 }
540 return wait;
541 }
542
543 /* called from spice server thread context */
544 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
545 {
546 fprintf(stderr, "%s: abort()\n", __FUNCTION__);
547 abort();
548 }
549
550 /* called from spice server thread context only */
551 static int interface_flush_resources(QXLInstance *sin)
552 {
553 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
554 int ret;
555
556 dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res);
557 ret = qxl->num_free_res;
558 if (ret) {
559 qxl_push_free_res(qxl, 1);
560 }
561 return ret;
562 }
563
564 static const QXLInterface qxl_interface = {
565 .base.type = SPICE_INTERFACE_QXL,
566 .base.description = "qxl gpu",
567 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
568 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
569
570 .attache_worker = interface_attach_worker,
571 .set_compression_level = interface_set_compression_level,
572 .set_mm_time = interface_set_mm_time,
573 .get_init_info = interface_get_init_info,
574
575 /* the callbacks below are called from spice server thread context */
576 .get_command = interface_get_command,
577 .req_cmd_notification = interface_req_cmd_notification,
578 .release_resource = interface_release_resource,
579 .get_cursor_command = interface_get_cursor_command,
580 .req_cursor_notification = interface_req_cursor_notification,
581 .notify_update = interface_notify_update,
582 .flush_resources = interface_flush_resources,
583 };
584
585 static void qxl_enter_vga_mode(PCIQXLDevice *d)
586 {
587 if (d->mode == QXL_MODE_VGA) {
588 return;
589 }
590 dprint(d, 1, "%s\n", __FUNCTION__);
591 qemu_spice_create_host_primary(&d->ssd);
592 d->mode = QXL_MODE_VGA;
593 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
594 }
595
596 static void qxl_exit_vga_mode(PCIQXLDevice *d)
597 {
598 if (d->mode != QXL_MODE_VGA) {
599 return;
600 }
601 dprint(d, 1, "%s\n", __FUNCTION__);
602 qxl_destroy_primary(d);
603 }
604
605 static void qxl_set_irq(PCIQXLDevice *d)
606 {
607 uint32_t pending = le32_to_cpu(d->ram->int_pending);
608 uint32_t mask = le32_to_cpu(d->ram->int_mask);
609 int level = !!(pending & mask);
610 qemu_set_irq(d->pci.irq[0], level);
611 qxl_ring_set_dirty(d);
612 }
613
614 static void qxl_write_config(PCIDevice *d, uint32_t address,
615 uint32_t val, int len)
616 {
617 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, d);
618 VGACommonState *vga = &qxl->vga;
619
620 vga_dirty_log_stop(vga);
621 pci_default_write_config(d, address, val, len);
622 if (vga->map_addr && qxl->pci.io_regions[0].addr == -1) {
623 vga->map_addr = 0;
624 }
625 vga_dirty_log_start(vga);
626 }
627
628 static void qxl_check_state(PCIQXLDevice *d)
629 {
630 QXLRam *ram = d->ram;
631
632 assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring));
633 assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring));
634 }
635
636 static void qxl_reset_state(PCIQXLDevice *d)
637 {
638 QXLRam *ram = d->ram;
639 QXLRom *rom = d->rom;
640
641 assert(SPICE_RING_IS_EMPTY(&ram->cmd_ring));
642 assert(SPICE_RING_IS_EMPTY(&ram->cursor_ring));
643 d->shadow_rom.update_id = cpu_to_le32(0);
644 *rom = d->shadow_rom;
645 qxl_rom_set_dirty(d);
646 init_qxl_ram(d);
647 d->num_free_res = 0;
648 d->last_release = NULL;
649 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
650 }
651
652 static void qxl_soft_reset(PCIQXLDevice *d)
653 {
654 dprint(d, 1, "%s:\n", __FUNCTION__);
655 qxl_check_state(d);
656
657 if (d->id == 0) {
658 qxl_enter_vga_mode(d);
659 } else {
660 d->mode = QXL_MODE_UNDEFINED;
661 }
662 }
663
664 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
665 {
666 dprint(d, 1, "%s: start%s\n", __FUNCTION__,
667 loadvm ? " (loadvm)" : "");
668
669 qemu_mutex_unlock_iothread();
670 d->ssd.worker->reset_cursor(d->ssd.worker);
671 d->ssd.worker->reset_image_cache(d->ssd.worker);
672 qemu_mutex_lock_iothread();
673 qxl_reset_surfaces(d);
674 qxl_reset_memslots(d);
675
676 /* pre loadvm reset must not touch QXLRam. This lives in
677 * device memory, is migrated together with RAM and thus
678 * already loaded at this point */
679 if (!loadvm) {
680 qxl_reset_state(d);
681 }
682 qemu_spice_create_host_memslot(&d->ssd);
683 qxl_soft_reset(d);
684
685 dprint(d, 1, "%s: done\n", __FUNCTION__);
686 }
687
688 static void qxl_reset_handler(DeviceState *dev)
689 {
690 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
691 qxl_hard_reset(d, 0);
692 }
693
694 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
695 {
696 VGACommonState *vga = opaque;
697 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
698
699 if (qxl->mode != QXL_MODE_VGA) {
700 dprint(qxl, 1, "%s\n", __FUNCTION__);
701 qxl_destroy_primary(qxl);
702 qxl_soft_reset(qxl);
703 }
704 vga_ioport_write(opaque, addr, val);
705 }
706
707 static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta)
708 {
709 static const int regions[] = {
710 QXL_RAM_RANGE_INDEX,
711 QXL_VRAM_RANGE_INDEX,
712 };
713 uint64_t guest_start;
714 uint64_t guest_end;
715 int pci_region;
716 pcibus_t pci_start;
717 pcibus_t pci_end;
718 intptr_t virt_start;
719 QXLDevMemSlot memslot;
720 int i;
721
722 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
723 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
724
725 dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n",
726 __FUNCTION__, slot_id,
727 guest_start, guest_end);
728
729 PANIC_ON(slot_id >= NUM_MEMSLOTS);
730 PANIC_ON(guest_start > guest_end);
731
732 for (i = 0; i < ARRAY_SIZE(regions); i++) {
733 pci_region = regions[i];
734 pci_start = d->pci.io_regions[pci_region].addr;
735 pci_end = pci_start + d->pci.io_regions[pci_region].size;
736 /* mapped? */
737 if (pci_start == -1) {
738 continue;
739 }
740 /* start address in range ? */
741 if (guest_start < pci_start || guest_start > pci_end) {
742 continue;
743 }
744 /* end address in range ? */
745 if (guest_end > pci_end) {
746 continue;
747 }
748 /* passed */
749 break;
750 }
751 PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
752
753 switch (pci_region) {
754 case QXL_RAM_RANGE_INDEX:
755 virt_start = (intptr_t)qemu_get_ram_ptr(d->vga.vram_offset);
756 break;
757 case QXL_VRAM_RANGE_INDEX:
758 virt_start = (intptr_t)qemu_get_ram_ptr(d->vram_offset);
759 break;
760 default:
761 /* should not happen */
762 abort();
763 }
764
765 memslot.slot_id = slot_id;
766 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
767 memslot.virt_start = virt_start + (guest_start - pci_start);
768 memslot.virt_end = virt_start + (guest_end - pci_start);
769 memslot.addr_delta = memslot.virt_start - delta;
770 memslot.generation = d->rom->slot_generation = 0;
771 qxl_rom_set_dirty(d);
772
773 dprint(d, 1, "%s: slot %d: host virt 0x%" PRIx64 " - 0x%" PRIx64 "\n",
774 __FUNCTION__, memslot.slot_id,
775 memslot.virt_start, memslot.virt_end);
776
777 d->ssd.worker->add_memslot(d->ssd.worker, &memslot);
778 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
779 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
780 d->guest_slots[slot_id].delta = delta;
781 d->guest_slots[slot_id].active = 1;
782 }
783
784 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
785 {
786 dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id);
787 d->ssd.worker->del_memslot(d->ssd.worker, MEMSLOT_GROUP_HOST, slot_id);
788 d->guest_slots[slot_id].active = 0;
789 }
790
791 static void qxl_reset_memslots(PCIQXLDevice *d)
792 {
793 dprint(d, 1, "%s:\n", __FUNCTION__);
794 d->ssd.worker->reset_memslots(d->ssd.worker);
795 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
796 }
797
798 static void qxl_reset_surfaces(PCIQXLDevice *d)
799 {
800 dprint(d, 1, "%s:\n", __FUNCTION__);
801 d->mode = QXL_MODE_UNDEFINED;
802 qemu_mutex_unlock_iothread();
803 d->ssd.worker->destroy_surfaces(d->ssd.worker);
804 qemu_mutex_lock_iothread();
805 memset(&d->guest_surfaces.cmds, 0, sizeof(d->guest_surfaces.cmds));
806 }
807
808 /* called from spice server thread context only */
809 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
810 {
811 uint64_t phys = le64_to_cpu(pqxl);
812 uint32_t slot = (phys >> (64 - 8)) & 0xff;
813 uint64_t offset = phys & 0xffffffffffff;
814
815 switch (group_id) {
816 case MEMSLOT_GROUP_HOST:
817 return (void*)offset;
818 case MEMSLOT_GROUP_GUEST:
819 PANIC_ON(slot > NUM_MEMSLOTS);
820 PANIC_ON(!qxl->guest_slots[slot].active);
821 PANIC_ON(offset < qxl->guest_slots[slot].delta);
822 offset -= qxl->guest_slots[slot].delta;
823 PANIC_ON(offset > qxl->guest_slots[slot].size)
824 return qxl->guest_slots[slot].ptr + offset;
825 default:
826 PANIC_ON(1);
827 }
828 }
829
830 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm)
831 {
832 QXLDevSurfaceCreate surface;
833 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
834
835 assert(qxl->mode != QXL_MODE_NATIVE);
836 qxl_exit_vga_mode(qxl);
837
838 dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__,
839 le32_to_cpu(sc->width), le32_to_cpu(sc->height));
840
841 surface.format = le32_to_cpu(sc->format);
842 surface.height = le32_to_cpu(sc->height);
843 surface.mem = le64_to_cpu(sc->mem);
844 surface.position = le32_to_cpu(sc->position);
845 surface.stride = le32_to_cpu(sc->stride);
846 surface.width = le32_to_cpu(sc->width);
847 surface.type = le32_to_cpu(sc->type);
848 surface.flags = le32_to_cpu(sc->flags);
849
850 surface.mouse_mode = true;
851 surface.group_id = MEMSLOT_GROUP_GUEST;
852 if (loadvm) {
853 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
854 }
855
856 qxl->mode = QXL_MODE_NATIVE;
857 qxl->cmdflags = 0;
858 qxl->ssd.worker->create_primary_surface(qxl->ssd.worker, 0, &surface);
859
860 /* for local rendering */
861 qxl_render_resize(qxl);
862 }
863
864 static void qxl_destroy_primary(PCIQXLDevice *d)
865 {
866 if (d->mode == QXL_MODE_UNDEFINED) {
867 return;
868 }
869
870 dprint(d, 1, "%s\n", __FUNCTION__);
871
872 d->mode = QXL_MODE_UNDEFINED;
873 qemu_mutex_unlock_iothread();
874 d->ssd.worker->destroy_primary_surface(d->ssd.worker, 0);
875 qemu_mutex_lock_iothread();
876 }
877
878 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
879 {
880 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
881 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
882 QXLMode *mode = d->modes->modes + modenr;
883 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
884 QXLMemSlot slot = {
885 .mem_start = start,
886 .mem_end = end
887 };
888 QXLSurfaceCreate surface = {
889 .width = mode->x_res,
890 .height = mode->y_res,
891 .stride = -mode->x_res * 4,
892 .format = SPICE_SURFACE_FMT_32_xRGB,
893 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
894 .mouse_mode = true,
895 .mem = devmem + d->shadow_rom.draw_area_offset,
896 };
897
898 dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%lx ]\n", __FUNCTION__,
899 modenr, mode->x_res, mode->y_res, mode->bits, devmem);
900 if (!loadvm) {
901 qxl_hard_reset(d, 0);
902 }
903
904 d->guest_slots[0].slot = slot;
905 qxl_add_memslot(d, 0, devmem);
906
907 d->guest_primary.surface = surface;
908 qxl_create_guest_primary(d, 0);
909
910 d->mode = QXL_MODE_COMPAT;
911 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
912 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
913 if (mode->bits == 16) {
914 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
915 }
916 #endif
917 d->shadow_rom.mode = cpu_to_le32(modenr);
918 d->rom->mode = cpu_to_le32(modenr);
919 qxl_rom_set_dirty(d);
920 }
921
922 static void ioport_write(void *opaque, uint32_t addr, uint32_t val)
923 {
924 PCIQXLDevice *d = opaque;
925 uint32_t io_port = addr - d->io_base;
926
927 switch (io_port) {
928 case QXL_IO_RESET:
929 case QXL_IO_SET_MODE:
930 case QXL_IO_MEMSLOT_ADD:
931 case QXL_IO_MEMSLOT_DEL:
932 case QXL_IO_CREATE_PRIMARY:
933 break;
934 default:
935 if (d->mode == QXL_MODE_NATIVE || d->mode == QXL_MODE_COMPAT)
936 break;
937 dprint(d, 1, "%s: unexpected port 0x%x in vga mode\n", __FUNCTION__, io_port);
938 return;
939 }
940
941 switch (io_port) {
942 case QXL_IO_UPDATE_AREA:
943 {
944 QXLRect update = d->ram->update_area;
945 qemu_mutex_unlock_iothread();
946 d->ssd.worker->update_area(d->ssd.worker, d->ram->update_surface,
947 &update, NULL, 0, 0);
948 qemu_mutex_lock_iothread();
949 break;
950 }
951 case QXL_IO_NOTIFY_CMD:
952 d->ssd.worker->wakeup(d->ssd.worker);
953 break;
954 case QXL_IO_NOTIFY_CURSOR:
955 d->ssd.worker->wakeup(d->ssd.worker);
956 break;
957 case QXL_IO_UPDATE_IRQ:
958 qxl_set_irq(d);
959 break;
960 case QXL_IO_NOTIFY_OOM:
961 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
962 break;
963 }
964 pthread_yield();
965 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
966 break;
967 }
968 d->oom_running = 1;
969 d->ssd.worker->oom(d->ssd.worker);
970 d->oom_running = 0;
971 break;
972 case QXL_IO_SET_MODE:
973 dprint(d, 1, "QXL_SET_MODE %d\n", val);
974 qxl_set_mode(d, val, 0);
975 break;
976 case QXL_IO_LOG:
977 if (d->guestdebug) {
978 fprintf(stderr, "qxl/guest: %s", d->ram->log_buf);
979 }
980 break;
981 case QXL_IO_RESET:
982 dprint(d, 1, "QXL_IO_RESET\n");
983 qxl_hard_reset(d, 0);
984 break;
985 case QXL_IO_MEMSLOT_ADD:
986 PANIC_ON(val >= NUM_MEMSLOTS);
987 PANIC_ON(d->guest_slots[val].active);
988 d->guest_slots[val].slot = d->ram->mem_slot;
989 qxl_add_memslot(d, val, 0);
990 break;
991 case QXL_IO_MEMSLOT_DEL:
992 qxl_del_memslot(d, val);
993 break;
994 case QXL_IO_CREATE_PRIMARY:
995 PANIC_ON(val != 0);
996 dprint(d, 1, "QXL_IO_CREATE_PRIMARY\n");
997 d->guest_primary.surface = d->ram->create_surface;
998 qxl_create_guest_primary(d, 0);
999 break;
1000 case QXL_IO_DESTROY_PRIMARY:
1001 PANIC_ON(val != 0);
1002 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY\n");
1003 qxl_destroy_primary(d);
1004 break;
1005 case QXL_IO_DESTROY_SURFACE_WAIT:
1006 d->ssd.worker->destroy_surface_wait(d->ssd.worker, val);
1007 break;
1008 case QXL_IO_DESTROY_ALL_SURFACES:
1009 d->ssd.worker->destroy_surfaces(d->ssd.worker);
1010 break;
1011 default:
1012 fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1013 abort();
1014 }
1015 }
1016
1017 static uint32_t ioport_read(void *opaque, uint32_t addr)
1018 {
1019 PCIQXLDevice *d = opaque;
1020
1021 dprint(d, 1, "%s: unexpected\n", __FUNCTION__);
1022 return 0xff;
1023 }
1024
1025 static void qxl_map(PCIDevice *pci, int region_num,
1026 pcibus_t addr, pcibus_t size, int type)
1027 {
1028 static const char *names[] = {
1029 [ QXL_IO_RANGE_INDEX ] = "ioports",
1030 [ QXL_RAM_RANGE_INDEX ] = "devram",
1031 [ QXL_ROM_RANGE_INDEX ] = "rom",
1032 [ QXL_VRAM_RANGE_INDEX ] = "vram",
1033 };
1034 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, pci);
1035
1036 dprint(qxl, 1, "%s: bar %d [%s] addr 0x%lx size 0x%lx\n", __FUNCTION__,
1037 region_num, names[region_num], addr, size);
1038
1039 switch (region_num) {
1040 case QXL_IO_RANGE_INDEX:
1041 register_ioport_write(addr, size, 1, ioport_write, pci);
1042 register_ioport_read(addr, size, 1, ioport_read, pci);
1043 qxl->io_base = addr;
1044 break;
1045 case QXL_RAM_RANGE_INDEX:
1046 cpu_register_physical_memory(addr, size, qxl->vga.vram_offset | IO_MEM_RAM);
1047 qxl->vga.map_addr = addr;
1048 qxl->vga.map_end = addr + size;
1049 if (qxl->id == 0) {
1050 vga_dirty_log_start(&qxl->vga);
1051 }
1052 break;
1053 case QXL_ROM_RANGE_INDEX:
1054 cpu_register_physical_memory(addr, size, qxl->rom_offset | IO_MEM_ROM);
1055 break;
1056 case QXL_VRAM_RANGE_INDEX:
1057 cpu_register_physical_memory(addr, size, qxl->vram_offset | IO_MEM_RAM);
1058 break;
1059 }
1060 }
1061
1062 static void pipe_read(void *opaque)
1063 {
1064 PCIQXLDevice *d = opaque;
1065 char dummy;
1066 int len;
1067
1068 do {
1069 len = read(d->pipe[0], &dummy, sizeof(dummy));
1070 } while (len == sizeof(dummy));
1071 qxl_set_irq(d);
1072 }
1073
1074 /* called from spice server thread context only */
1075 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1076 {
1077 uint32_t old_pending;
1078 uint32_t le_events = cpu_to_le32(events);
1079
1080 assert(d->ssd.running);
1081 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1082 if ((old_pending & le_events) == le_events) {
1083 return;
1084 }
1085 if (pthread_self() == d->main) {
1086 qxl_set_irq(d);
1087 } else {
1088 if (write(d->pipe[1], d, 1) != 1) {
1089 dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1090 }
1091 }
1092 }
1093
1094 static void init_pipe_signaling(PCIQXLDevice *d)
1095 {
1096 if (pipe(d->pipe) < 0) {
1097 dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__);
1098 return;
1099 }
1100 #ifdef CONFIG_IOTHREAD
1101 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1102 #else
1103 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK /* | O_ASYNC */);
1104 #endif
1105 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1106 fcntl(d->pipe[0], F_SETOWN, getpid());
1107
1108 d->main = pthread_self();
1109 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1110 }
1111
1112 /* graphics console */
1113
1114 static void qxl_hw_update(void *opaque)
1115 {
1116 PCIQXLDevice *qxl = opaque;
1117 VGACommonState *vga = &qxl->vga;
1118
1119 switch (qxl->mode) {
1120 case QXL_MODE_VGA:
1121 vga->update(vga);
1122 break;
1123 case QXL_MODE_COMPAT:
1124 case QXL_MODE_NATIVE:
1125 qxl_render_update(qxl);
1126 break;
1127 default:
1128 break;
1129 }
1130 }
1131
1132 static void qxl_hw_invalidate(void *opaque)
1133 {
1134 PCIQXLDevice *qxl = opaque;
1135 VGACommonState *vga = &qxl->vga;
1136
1137 vga->invalidate(vga);
1138 }
1139
1140 static void qxl_hw_screen_dump(void *opaque, const char *filename)
1141 {
1142 PCIQXLDevice *qxl = opaque;
1143 VGACommonState *vga = &qxl->vga;
1144
1145 switch (qxl->mode) {
1146 case QXL_MODE_COMPAT:
1147 case QXL_MODE_NATIVE:
1148 qxl_render_update(qxl);
1149 ppm_save(filename, qxl->ssd.ds->surface);
1150 break;
1151 case QXL_MODE_VGA:
1152 vga->screen_dump(vga, filename);
1153 break;
1154 default:
1155 break;
1156 }
1157 }
1158
1159 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1160 {
1161 PCIQXLDevice *qxl = opaque;
1162 VGACommonState *vga = &qxl->vga;
1163
1164 if (qxl->mode == QXL_MODE_VGA) {
1165 vga->text_update(vga, chardata);
1166 return;
1167 }
1168 }
1169
1170 static void qxl_vm_change_state_handler(void *opaque, int running, int reason)
1171 {
1172 PCIQXLDevice *qxl = opaque;
1173 qemu_spice_vm_change_state_handler(&qxl->ssd, running, reason);
1174
1175 if (!running && qxl->mode == QXL_MODE_NATIVE) {
1176 /* dirty all vram (which holds surfaces) to make sure it is saved */
1177 /* FIXME #1: should go out during "live" stage */
1178 /* FIXME #2: we only need to save the areas which are actually used */
1179 ram_addr_t addr = qxl->vram_offset;
1180 qxl_set_dirty(addr, addr + qxl->vram_size);
1181 }
1182 }
1183
1184 /* display change listener */
1185
1186 static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1187 {
1188 if (qxl0->mode == QXL_MODE_VGA) {
1189 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1190 }
1191 }
1192
1193 static void display_resize(struct DisplayState *ds)
1194 {
1195 if (qxl0->mode == QXL_MODE_VGA) {
1196 qemu_spice_display_resize(&qxl0->ssd);
1197 }
1198 }
1199
1200 static void display_refresh(struct DisplayState *ds)
1201 {
1202 if (qxl0->mode == QXL_MODE_VGA) {
1203 qemu_spice_display_refresh(&qxl0->ssd);
1204 }
1205 }
1206
1207 static DisplayChangeListener display_listener = {
1208 .dpy_update = display_update,
1209 .dpy_resize = display_resize,
1210 .dpy_refresh = display_refresh,
1211 };
1212
1213 static int qxl_init_common(PCIQXLDevice *qxl)
1214 {
1215 uint8_t* config = qxl->pci.config;
1216 uint32_t pci_device_id;
1217 uint32_t pci_device_rev;
1218 uint32_t io_size;
1219
1220 qxl->mode = QXL_MODE_UNDEFINED;
1221 qxl->generation = 1;
1222 qxl->num_memslots = NUM_MEMSLOTS;
1223 qxl->num_surfaces = NUM_SURFACES;
1224
1225 switch (qxl->revision) {
1226 case 1: /* spice 0.4 -- qxl-1 */
1227 pci_device_id = QXL_DEVICE_ID_STABLE;
1228 pci_device_rev = QXL_REVISION_STABLE_V04;
1229 break;
1230 case 2: /* spice 0.6 -- qxl-2 */
1231 pci_device_id = QXL_DEVICE_ID_STABLE;
1232 pci_device_rev = QXL_REVISION_STABLE_V06;
1233 break;
1234 default: /* experimental */
1235 pci_device_id = QXL_DEVICE_ID_DEVEL;
1236 pci_device_rev = 1;
1237 break;
1238 }
1239
1240 pci_config_set_vendor_id(config, REDHAT_PCI_VENDOR_ID);
1241 pci_config_set_device_id(config, pci_device_id);
1242 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1243 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1244
1245 qxl->rom_size = qxl_rom_size();
1246 qxl->rom_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vrom", qxl->rom_size);
1247 init_qxl_rom(qxl);
1248 init_qxl_ram(qxl);
1249
1250 if (qxl->vram_size < 16 * 1024 * 1024) {
1251 qxl->vram_size = 16 * 1024 * 1024;
1252 }
1253 if (qxl->revision == 1) {
1254 qxl->vram_size = 4096;
1255 }
1256 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1257 qxl->vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vram", qxl->vram_size);
1258
1259 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1260 if (qxl->revision == 1) {
1261 io_size = 8;
1262 }
1263
1264 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1265 io_size, PCI_BASE_ADDRESS_SPACE_IO, qxl_map);
1266
1267 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1268 qxl->rom_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
1269 qxl_map);
1270
1271 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1272 qxl->vga.vram_size, PCI_BASE_ADDRESS_SPACE_MEMORY,
1273 qxl_map);
1274
1275 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX, qxl->vram_size,
1276 PCI_BASE_ADDRESS_SPACE_MEMORY, qxl_map);
1277
1278 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1279 qxl->ssd.qxl.id = qxl->id;
1280 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1281 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1282
1283 init_pipe_signaling(qxl);
1284 qxl_reset_state(qxl);
1285
1286 return 0;
1287 }
1288
1289 static int qxl_init_primary(PCIDevice *dev)
1290 {
1291 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1292 VGACommonState *vga = &qxl->vga;
1293 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1294
1295 qxl->id = 0;
1296
1297 if (ram_size < 32 * 1024 * 1024) {
1298 ram_size = 32 * 1024 * 1024;
1299 }
1300 vga_common_init(vga, ram_size);
1301 vga_init(vga);
1302 register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga);
1303 register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga);
1304 register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga);
1305 register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write, vga);
1306 register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write, vga);
1307
1308 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1309 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
1310 qxl->ssd.ds = vga->ds;
1311 qemu_mutex_init(&qxl->ssd.lock);
1312 qxl->ssd.bufsize = (16 * 1024 * 1024);
1313 qxl->ssd.buf = qemu_malloc(qxl->ssd.bufsize);
1314
1315 qxl0 = qxl;
1316 register_displaychangelistener(vga->ds, &display_listener);
1317
1318 pci_config_set_class(dev->config, PCI_CLASS_DISPLAY_VGA);
1319 return qxl_init_common(qxl);
1320 }
1321
1322 static int qxl_init_secondary(PCIDevice *dev)
1323 {
1324 static int device_id = 1;
1325 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1326 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1327
1328 qxl->id = device_id++;
1329
1330 if (ram_size < 16 * 1024 * 1024) {
1331 ram_size = 16 * 1024 * 1024;
1332 }
1333 qxl->vga.vram_size = ram_size;
1334 qxl->vga.vram_offset = qemu_ram_alloc(&qxl->pci.qdev, "qxl.vgavram",
1335 qxl->vga.vram_size);
1336 qxl->vga.vram_ptr = qemu_get_ram_ptr(qxl->vga.vram_offset);
1337
1338 pci_config_set_class(dev->config, PCI_CLASS_DISPLAY_OTHER);
1339 return qxl_init_common(qxl);
1340 }
1341
1342 static void qxl_pre_save(void *opaque)
1343 {
1344 PCIQXLDevice* d = opaque;
1345 uint8_t *ram_start = d->vga.vram_ptr;
1346
1347 dprint(d, 1, "%s:\n", __FUNCTION__);
1348 if (d->last_release == NULL) {
1349 d->last_release_offset = 0;
1350 } else {
1351 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1352 }
1353 assert(d->last_release_offset < d->vga.vram_size);
1354 }
1355
1356 static int qxl_pre_load(void *opaque)
1357 {
1358 PCIQXLDevice* d = opaque;
1359
1360 dprint(d, 1, "%s: start\n", __FUNCTION__);
1361 qxl_hard_reset(d, 1);
1362 qxl_exit_vga_mode(d);
1363 dprint(d, 1, "%s: done\n", __FUNCTION__);
1364 return 0;
1365 }
1366
1367 static int qxl_post_load(void *opaque, int version)
1368 {
1369 PCIQXLDevice* d = opaque;
1370 uint8_t *ram_start = d->vga.vram_ptr;
1371 QXLCommandExt *cmds;
1372 int in, out, i, newmode;
1373
1374 dprint(d, 1, "%s: start\n", __FUNCTION__);
1375
1376 assert(d->last_release_offset < d->vga.vram_size);
1377 if (d->last_release_offset == 0) {
1378 d->last_release = NULL;
1379 } else {
1380 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1381 }
1382
1383 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1384
1385 dprint(d, 1, "%s: restore mode\n", __FUNCTION__);
1386 newmode = d->mode;
1387 d->mode = QXL_MODE_UNDEFINED;
1388 switch (newmode) {
1389 case QXL_MODE_UNDEFINED:
1390 break;
1391 case QXL_MODE_VGA:
1392 qxl_enter_vga_mode(d);
1393 break;
1394 case QXL_MODE_NATIVE:
1395 for (i = 0; i < NUM_MEMSLOTS; i++) {
1396 if (!d->guest_slots[i].active) {
1397 continue;
1398 }
1399 qxl_add_memslot(d, i, 0);
1400 }
1401 qxl_create_guest_primary(d, 1);
1402
1403 /* replay surface-create and cursor-set commands */
1404 cmds = qemu_mallocz(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1405 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1406 if (d->guest_surfaces.cmds[in] == 0) {
1407 continue;
1408 }
1409 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1410 cmds[out].cmd.type = QXL_CMD_SURFACE;
1411 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1412 out++;
1413 }
1414 cmds[out].cmd.data = d->guest_cursor;
1415 cmds[out].cmd.type = QXL_CMD_CURSOR;
1416 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1417 out++;
1418 d->ssd.worker->loadvm_commands(d->ssd.worker, cmds, out);
1419 qemu_free(cmds);
1420
1421 break;
1422 case QXL_MODE_COMPAT:
1423 qxl_set_mode(d, d->shadow_rom.mode, 1);
1424 break;
1425 }
1426 dprint(d, 1, "%s: done\n", __FUNCTION__);
1427
1428 return 0;
1429 }
1430
1431 #define QXL_SAVE_VERSION 21
1432
1433 static VMStateDescription qxl_memslot = {
1434 .name = "qxl-memslot",
1435 .version_id = QXL_SAVE_VERSION,
1436 .minimum_version_id = QXL_SAVE_VERSION,
1437 .fields = (VMStateField[]) {
1438 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1439 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
1440 VMSTATE_UINT32(active, struct guest_slots),
1441 VMSTATE_END_OF_LIST()
1442 }
1443 };
1444
1445 static VMStateDescription qxl_surface = {
1446 .name = "qxl-surface",
1447 .version_id = QXL_SAVE_VERSION,
1448 .minimum_version_id = QXL_SAVE_VERSION,
1449 .fields = (VMStateField[]) {
1450 VMSTATE_UINT32(width, QXLSurfaceCreate),
1451 VMSTATE_UINT32(height, QXLSurfaceCreate),
1452 VMSTATE_INT32(stride, QXLSurfaceCreate),
1453 VMSTATE_UINT32(format, QXLSurfaceCreate),
1454 VMSTATE_UINT32(position, QXLSurfaceCreate),
1455 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1456 VMSTATE_UINT32(flags, QXLSurfaceCreate),
1457 VMSTATE_UINT32(type, QXLSurfaceCreate),
1458 VMSTATE_UINT64(mem, QXLSurfaceCreate),
1459 VMSTATE_END_OF_LIST()
1460 }
1461 };
1462
1463 static VMStateDescription qxl_vmstate = {
1464 .name = "qxl",
1465 .version_id = QXL_SAVE_VERSION,
1466 .minimum_version_id = QXL_SAVE_VERSION,
1467 .pre_save = qxl_pre_save,
1468 .pre_load = qxl_pre_load,
1469 .post_load = qxl_post_load,
1470 .fields = (VMStateField []) {
1471 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1472 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1473 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1474 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1475 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1476 VMSTATE_UINT32(mode, PCIQXLDevice),
1477 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
1478 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1479 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1480 qxl_memslot, struct guest_slots),
1481 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1482 qxl_surface, QXLSurfaceCreate),
1483 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1484 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1485 vmstate_info_uint64, uint64_t),
1486 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
1487 VMSTATE_END_OF_LIST()
1488 },
1489 };
1490
1491 static PCIDeviceInfo qxl_info_primary = {
1492 .qdev.name = "qxl-vga",
1493 .qdev.desc = "Spice QXL GPU (primary, vga compatible)",
1494 .qdev.size = sizeof(PCIQXLDevice),
1495 .qdev.reset = qxl_reset_handler,
1496 .qdev.vmsd = &qxl_vmstate,
1497 .no_hotplug = 1,
1498 .init = qxl_init_primary,
1499 .config_write = qxl_write_config,
1500 .romfile = "vgabios-qxl.bin",
1501 .qdev.props = (Property[]) {
1502 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
1503 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
1504 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
1505 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1506 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1507 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1508 DEFINE_PROP_END_OF_LIST(),
1509 }
1510 };
1511
1512 static PCIDeviceInfo qxl_info_secondary = {
1513 .qdev.name = "qxl",
1514 .qdev.desc = "Spice QXL GPU (secondary)",
1515 .qdev.size = sizeof(PCIQXLDevice),
1516 .qdev.reset = qxl_reset_handler,
1517 .qdev.vmsd = &qxl_vmstate,
1518 .init = qxl_init_secondary,
1519 .qdev.props = (Property[]) {
1520 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size, 64 * 1024 * 1024),
1521 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size, 64 * 1024 * 1024),
1522 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision, 2),
1523 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1524 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1525 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1526 DEFINE_PROP_END_OF_LIST(),
1527 }
1528 };
1529
1530 static void qxl_register(void)
1531 {
1532 pci_qdev_register(&qxl_info_primary);
1533 pci_qdev_register(&qxl_info_secondary);
1534 }
1535
1536 device_init(qxl_register);
QEmu