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build: fix race with creating qapi-generated
[qemu.git] / hw / qxl.c
blob6db2f1a466b36b2da084d11316145c7a77c3e49c
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include <pthread.h>
22
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "qemu-queue.h"
26 #include "monitor.h"
27 #include "sysemu.h"
28
29 #include "qxl.h"
30
31 #undef SPICE_RING_PROD_ITEM
32 #define SPICE_RING_PROD_ITEM(r, ret) { \
33 typeof(r) start = r; \
34 typeof(r) end = r + 1; \
35 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
36 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
37 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
38 abort(); \
39 } \
40 ret = &m_item->el; \
41 }
42
43 #undef SPICE_RING_CONS_ITEM
44 #define SPICE_RING_CONS_ITEM(r, ret) { \
45 typeof(r) start = r; \
46 typeof(r) end = r + 1; \
47 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
48 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
49 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
50 abort(); \
51 } \
52 ret = &m_item->el; \
53 }
54
55 #undef ALIGN
56 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
57
58 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
59
60 #define QXL_MODE(_x, _y, _b, _o) \
61 { .x_res = _x, \
62 .y_res = _y, \
63 .bits = _b, \
64 .stride = (_x) * (_b) / 8, \
65 .x_mili = PIXEL_SIZE * (_x), \
66 .y_mili = PIXEL_SIZE * (_y), \
67 .orientation = _o, \
68 }
69
70 #define QXL_MODE_16_32(x_res, y_res, orientation) \
71 QXL_MODE(x_res, y_res, 16, orientation), \
72 QXL_MODE(x_res, y_res, 32, orientation)
73
74 #define QXL_MODE_EX(x_res, y_res) \
75 QXL_MODE_16_32(x_res, y_res, 0), \
76 QXL_MODE_16_32(y_res, x_res, 1), \
77 QXL_MODE_16_32(x_res, y_res, 2), \
78 QXL_MODE_16_32(y_res, x_res, 3)
79
80 static QXLMode qxl_modes[] = {
81 QXL_MODE_EX(640, 480),
82 QXL_MODE_EX(800, 480),
83 QXL_MODE_EX(800, 600),
84 QXL_MODE_EX(832, 624),
85 QXL_MODE_EX(960, 640),
86 QXL_MODE_EX(1024, 600),
87 QXL_MODE_EX(1024, 768),
88 QXL_MODE_EX(1152, 864),
89 QXL_MODE_EX(1152, 870),
90 QXL_MODE_EX(1280, 720),
91 QXL_MODE_EX(1280, 760),
92 QXL_MODE_EX(1280, 768),
93 QXL_MODE_EX(1280, 800),
94 QXL_MODE_EX(1280, 960),
95 QXL_MODE_EX(1280, 1024),
96 QXL_MODE_EX(1360, 768),
97 QXL_MODE_EX(1366, 768),
98 QXL_MODE_EX(1400, 1050),
99 QXL_MODE_EX(1440, 900),
100 QXL_MODE_EX(1600, 900),
101 QXL_MODE_EX(1600, 1200),
102 QXL_MODE_EX(1680, 1050),
103 QXL_MODE_EX(1920, 1080),
104 #if VGA_RAM_SIZE >= (16 * 1024 * 1024)
105 /* these modes need more than 8 MB video memory */
106 QXL_MODE_EX(1920, 1200),
107 QXL_MODE_EX(1920, 1440),
108 QXL_MODE_EX(2048, 1536),
109 QXL_MODE_EX(2560, 1440),
110 QXL_MODE_EX(2560, 1600),
111 #endif
112 #if VGA_RAM_SIZE >= (32 * 1024 * 1024)
113 /* these modes need more than 16 MB video memory */
114 QXL_MODE_EX(2560, 2048),
115 QXL_MODE_EX(2800, 2100),
116 QXL_MODE_EX(3200, 2400),
117 #endif
118 };
119
120 static PCIQXLDevice *qxl0;
121
122 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
123 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
124 static void qxl_reset_memslots(PCIQXLDevice *d);
125 static void qxl_reset_surfaces(PCIQXLDevice *d);
126 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
127
128 void qxl_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
129 {
130 #if SPICE_INTERFACE_QXL_MINOR >= 1
131 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
132 #endif
133 if (qxl->guestdebug) {
134 va_list ap;
135 va_start(ap, msg);
136 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
137 vfprintf(stderr, msg, ap);
138 fprintf(stderr, "\n");
139 va_end(ap);
140 }
141 }
142
143
144 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
145 struct QXLRect *area, struct QXLRect *dirty_rects,
146 uint32_t num_dirty_rects,
147 uint32_t clear_dirty_region,
148 qxl_async_io async)
149 {
150 if (async == QXL_SYNC) {
151 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
152 dirty_rects, num_dirty_rects, clear_dirty_region);
153 } else {
154 #if SPICE_INTERFACE_QXL_MINOR >= 1
155 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
156 clear_dirty_region, 0);
157 #else
158 abort();
159 #endif
160 }
161 }
162
163 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
164 uint32_t id)
165 {
166 qemu_mutex_lock(&qxl->track_lock);
167 qxl->guest_surfaces.cmds[id] = 0;
168 qxl->guest_surfaces.count--;
169 qemu_mutex_unlock(&qxl->track_lock);
170 }
171
172 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
173 qxl_async_io async)
174 {
175 if (async) {
176 #if SPICE_INTERFACE_QXL_MINOR < 1
177 abort();
178 #else
179 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id,
180 (uint64_t)id);
181 #endif
182 } else {
183 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
184 qxl_spice_destroy_surface_wait_complete(qxl, id);
185 }
186 }
187
188 #if SPICE_INTERFACE_QXL_MINOR >= 1
189 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
190 {
191 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl, 0);
192 }
193 #endif
194
195 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
196 uint32_t count)
197 {
198 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
199 }
200
201 void qxl_spice_oom(PCIQXLDevice *qxl)
202 {
203 qxl->ssd.worker->oom(qxl->ssd.worker);
204 }
205
206 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
207 {
208 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
209 }
210
211 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
212 {
213 qemu_mutex_lock(&qxl->track_lock);
214 memset(&qxl->guest_surfaces.cmds, 0, sizeof(qxl->guest_surfaces.cmds));
215 qxl->guest_surfaces.count = 0;
216 qemu_mutex_unlock(&qxl->track_lock);
217 }
218
219 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
220 {
221 if (async) {
222 #if SPICE_INTERFACE_QXL_MINOR < 1
223 abort();
224 #else
225 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl, 0);
226 #endif
227 } else {
228 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
229 qxl_spice_destroy_surfaces_complete(qxl);
230 }
231 }
232
233 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
234 {
235 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
236 }
237
238 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
239 {
240 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
241 }
242
243
244 static inline uint32_t msb_mask(uint32_t val)
245 {
246 uint32_t mask;
247
248 do {
249 mask = ~(val - 1) & val;
250 val &= ~mask;
251 } while (mask < val);
252
253 return mask;
254 }
255
256 static ram_addr_t qxl_rom_size(void)
257 {
258 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
259 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
260 rom_size = msb_mask(rom_size * 2 - 1);
261 return rom_size;
262 }
263
264 static void init_qxl_rom(PCIQXLDevice *d)
265 {
266 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
267 QXLModes *modes = (QXLModes *)(rom + 1);
268 uint32_t ram_header_size;
269 uint32_t surface0_area_size;
270 uint32_t num_pages;
271 uint32_t fb, maxfb = 0;
272 int i;
273
274 memset(rom, 0, d->rom_size);
275
276 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
277 rom->id = cpu_to_le32(d->id);
278 rom->log_level = cpu_to_le32(d->guestdebug);
279 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
280
281 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
282 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
283 rom->slots_start = 1;
284 rom->slots_end = NUM_MEMSLOTS - 1;
285 rom->n_surfaces = cpu_to_le32(NUM_SURFACES);
286
287 modes->n_modes = cpu_to_le32(ARRAY_SIZE(qxl_modes));
288 for (i = 0; i < modes->n_modes; i++) {
289 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
290 if (maxfb < fb) {
291 maxfb = fb;
292 }
293 modes->modes[i].id = cpu_to_le32(i);
294 modes->modes[i].x_res = cpu_to_le32(qxl_modes[i].x_res);
295 modes->modes[i].y_res = cpu_to_le32(qxl_modes[i].y_res);
296 modes->modes[i].bits = cpu_to_le32(qxl_modes[i].bits);
297 modes->modes[i].stride = cpu_to_le32(qxl_modes[i].stride);
298 modes->modes[i].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
299 modes->modes[i].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
300 modes->modes[i].orientation = cpu_to_le32(qxl_modes[i].orientation);
301 }
302 if (maxfb < VGA_RAM_SIZE && d->id == 0)
303 maxfb = VGA_RAM_SIZE;
304
305 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
306 surface0_area_size = ALIGN(maxfb, 4096);
307 num_pages = d->vga.vram_size;
308 num_pages -= ram_header_size;
309 num_pages -= surface0_area_size;
310 num_pages = num_pages / TARGET_PAGE_SIZE;
311
312 rom->draw_area_offset = cpu_to_le32(0);
313 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
314 rom->pages_offset = cpu_to_le32(surface0_area_size);
315 rom->num_pages = cpu_to_le32(num_pages);
316 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
317
318 d->shadow_rom = *rom;
319 d->rom = rom;
320 d->modes = modes;
321 }
322
323 static void init_qxl_ram(PCIQXLDevice *d)
324 {
325 uint8_t *buf;
326 uint64_t *item;
327
328 buf = d->vga.vram_ptr;
329 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
330 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
331 d->ram->int_pending = cpu_to_le32(0);
332 d->ram->int_mask = cpu_to_le32(0);
333 SPICE_RING_INIT(&d->ram->cmd_ring);
334 SPICE_RING_INIT(&d->ram->cursor_ring);
335 SPICE_RING_INIT(&d->ram->release_ring);
336 SPICE_RING_PROD_ITEM(&d->ram->release_ring, item);
337 *item = 0;
338 qxl_ring_set_dirty(d);
339 }
340
341 /* can be called from spice server thread context */
342 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
343 {
344 while (addr < end) {
345 memory_region_set_dirty(mr, addr);
346 addr += TARGET_PAGE_SIZE;
347 }
348 }
349
350 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
351 {
352 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
353 }
354
355 /* called from spice server thread context only */
356 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
357 {
358 void *base = qxl->vga.vram_ptr;
359 intptr_t offset;
360
361 offset = ptr - base;
362 offset &= ~(TARGET_PAGE_SIZE-1);
363 assert(offset < qxl->vga.vram_size);
364 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
365 }
366
367 /* can be called from spice server thread context */
368 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
369 {
370 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
371 ram_addr_t end = qxl->vga.vram_size;
372 qxl_set_dirty(&qxl->vga.vram, addr, end);
373 }
374
375 /*
376 * keep track of some command state, for savevm/loadvm.
377 * called from spice server thread context only
378 */
379 static void qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
380 {
381 switch (le32_to_cpu(ext->cmd.type)) {
382 case QXL_CMD_SURFACE:
383 {
384 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
385 uint32_t id = le32_to_cpu(cmd->surface_id);
386 PANIC_ON(id >= NUM_SURFACES);
387 qemu_mutex_lock(&qxl->track_lock);
388 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
389 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
390 qxl->guest_surfaces.count++;
391 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
392 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
393 }
394 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
395 qxl->guest_surfaces.cmds[id] = 0;
396 qxl->guest_surfaces.count--;
397 }
398 qemu_mutex_unlock(&qxl->track_lock);
399 break;
400 }
401 case QXL_CMD_CURSOR:
402 {
403 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
404 if (cmd->type == QXL_CURSOR_SET) {
405 qxl->guest_cursor = ext->cmd.data;
406 }
407 break;
408 }
409 }
410 }
411
412 /* spice display interface callbacks */
413
414 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
415 {
416 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
417
418 dprint(qxl, 1, "%s:\n", __FUNCTION__);
419 qxl->ssd.worker = qxl_worker;
420 }
421
422 static void interface_set_compression_level(QXLInstance *sin, int level)
423 {
424 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
425
426 dprint(qxl, 1, "%s: %d\n", __FUNCTION__, level);
427 qxl->shadow_rom.compression_level = cpu_to_le32(level);
428 qxl->rom->compression_level = cpu_to_le32(level);
429 qxl_rom_set_dirty(qxl);
430 }
431
432 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
433 {
434 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
435
436 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
437 qxl->rom->mm_clock = cpu_to_le32(mm_time);
438 qxl_rom_set_dirty(qxl);
439 }
440
441 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
442 {
443 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
444
445 dprint(qxl, 1, "%s:\n", __FUNCTION__);
446 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
447 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
448 info->num_memslots = NUM_MEMSLOTS;
449 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
450 info->internal_groupslot_id = 0;
451 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
452 info->n_surfaces = NUM_SURFACES;
453 }
454
455 static const char *qxl_mode_to_string(int mode)
456 {
457 switch (mode) {
458 case QXL_MODE_COMPAT:
459 return "compat";
460 case QXL_MODE_NATIVE:
461 return "native";
462 case QXL_MODE_UNDEFINED:
463 return "undefined";
464 case QXL_MODE_VGA:
465 return "vga";
466 }
467 return "INVALID";
468 }
469
470 static const char *io_port_to_string(uint32_t io_port)
471 {
472 if (io_port >= QXL_IO_RANGE_SIZE) {
473 return "out of range";
474 }
475 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
476 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
477 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
478 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
479 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
480 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
481 [QXL_IO_RESET] = "QXL_IO_RESET",
482 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
483 [QXL_IO_LOG] = "QXL_IO_LOG",
484 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
485 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
486 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
487 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
488 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
489 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
490 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
491 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
492 #if SPICE_INTERFACE_QXL_MINOR >= 1
493 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
494 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
495 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
496 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
497 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
498 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
499 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
500 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
501 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
502 #endif
503 };
504 return io_port_to_string[io_port];
505 }
506
507 /* called from spice server thread context only */
508 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
509 {
510 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
511 SimpleSpiceUpdate *update;
512 QXLCommandRing *ring;
513 QXLCommand *cmd;
514 int notify, ret;
515
516 switch (qxl->mode) {
517 case QXL_MODE_VGA:
518 dprint(qxl, 2, "%s: vga\n", __FUNCTION__);
519 ret = false;
520 qemu_mutex_lock(&qxl->ssd.lock);
521 if (qxl->ssd.update != NULL) {
522 update = qxl->ssd.update;
523 qxl->ssd.update = NULL;
524 *ext = update->ext;
525 ret = true;
526 }
527 qemu_mutex_unlock(&qxl->ssd.lock);
528 if (ret) {
529 dprint(qxl, 2, "%s %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
530 qxl_log_command(qxl, "vga", ext);
531 }
532 return ret;
533 case QXL_MODE_COMPAT:
534 case QXL_MODE_NATIVE:
535 case QXL_MODE_UNDEFINED:
536 dprint(qxl, 4, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
537 ring = &qxl->ram->cmd_ring;
538 if (SPICE_RING_IS_EMPTY(ring)) {
539 return false;
540 }
541 dprint(qxl, 2, "%s: %s\n", __FUNCTION__, qxl_mode_to_string(qxl->mode));
542 SPICE_RING_CONS_ITEM(ring, cmd);
543 ext->cmd = *cmd;
544 ext->group_id = MEMSLOT_GROUP_GUEST;
545 ext->flags = qxl->cmdflags;
546 SPICE_RING_POP(ring, notify);
547 qxl_ring_set_dirty(qxl);
548 if (notify) {
549 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
550 }
551 qxl->guest_primary.commands++;
552 qxl_track_command(qxl, ext);
553 qxl_log_command(qxl, "cmd", ext);
554 return true;
555 default:
556 return false;
557 }
558 }
559
560 /* called from spice server thread context only */
561 static int interface_req_cmd_notification(QXLInstance *sin)
562 {
563 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
564 int wait = 1;
565
566 switch (qxl->mode) {
567 case QXL_MODE_COMPAT:
568 case QXL_MODE_NATIVE:
569 case QXL_MODE_UNDEFINED:
570 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
571 qxl_ring_set_dirty(qxl);
572 break;
573 default:
574 /* nothing */
575 break;
576 }
577 return wait;
578 }
579
580 /* called from spice server thread context only */
581 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
582 {
583 QXLReleaseRing *ring = &d->ram->release_ring;
584 uint64_t *item;
585 int notify;
586
587 #define QXL_FREE_BUNCH_SIZE 32
588
589 if (ring->prod - ring->cons + 1 == ring->num_items) {
590 /* ring full -- can't push */
591 return;
592 }
593 if (!flush && d->oom_running) {
594 /* collect everything from oom handler before pushing */
595 return;
596 }
597 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
598 /* collect a bit more before pushing */
599 return;
600 }
601
602 SPICE_RING_PUSH(ring, notify);
603 dprint(d, 2, "free: push %d items, notify %s, ring %d/%d [%d,%d]\n",
604 d->num_free_res, notify ? "yes" : "no",
605 ring->prod - ring->cons, ring->num_items,
606 ring->prod, ring->cons);
607 if (notify) {
608 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
609 }
610 SPICE_RING_PROD_ITEM(ring, item);
611 *item = 0;
612 d->num_free_res = 0;
613 d->last_release = NULL;
614 qxl_ring_set_dirty(d);
615 }
616
617 /* called from spice server thread context only */
618 static void interface_release_resource(QXLInstance *sin,
619 struct QXLReleaseInfoExt ext)
620 {
621 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
622 QXLReleaseRing *ring;
623 uint64_t *item, id;
624
625 if (ext.group_id == MEMSLOT_GROUP_HOST) {
626 /* host group -> vga mode update request */
627 qemu_spice_destroy_update(&qxl->ssd, (void*)ext.info->id);
628 return;
629 }
630
631 /*
632 * ext->info points into guest-visible memory
633 * pci bar 0, $command.release_info
634 */
635 ring = &qxl->ram->release_ring;
636 SPICE_RING_PROD_ITEM(ring, item);
637 if (*item == 0) {
638 /* stick head into the ring */
639 id = ext.info->id;
640 ext.info->next = 0;
641 qxl_ram_set_dirty(qxl, &ext.info->next);
642 *item = id;
643 qxl_ring_set_dirty(qxl);
644 } else {
645 /* append item to the list */
646 qxl->last_release->next = ext.info->id;
647 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
648 ext.info->next = 0;
649 qxl_ram_set_dirty(qxl, &ext.info->next);
650 }
651 qxl->last_release = ext.info;
652 qxl->num_free_res++;
653 dprint(qxl, 3, "%4d\r", qxl->num_free_res);
654 qxl_push_free_res(qxl, 0);
655 }
656
657 /* called from spice server thread context only */
658 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
659 {
660 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
661 QXLCursorRing *ring;
662 QXLCommand *cmd;
663 int notify;
664
665 switch (qxl->mode) {
666 case QXL_MODE_COMPAT:
667 case QXL_MODE_NATIVE:
668 case QXL_MODE_UNDEFINED:
669 ring = &qxl->ram->cursor_ring;
670 if (SPICE_RING_IS_EMPTY(ring)) {
671 return false;
672 }
673 SPICE_RING_CONS_ITEM(ring, cmd);
674 ext->cmd = *cmd;
675 ext->group_id = MEMSLOT_GROUP_GUEST;
676 ext->flags = qxl->cmdflags;
677 SPICE_RING_POP(ring, notify);
678 qxl_ring_set_dirty(qxl);
679 if (notify) {
680 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
681 }
682 qxl->guest_primary.commands++;
683 qxl_track_command(qxl, ext);
684 qxl_log_command(qxl, "csr", ext);
685 if (qxl->id == 0) {
686 qxl_render_cursor(qxl, ext);
687 }
688 return true;
689 default:
690 return false;
691 }
692 }
693
694 /* called from spice server thread context only */
695 static int interface_req_cursor_notification(QXLInstance *sin)
696 {
697 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
698 int wait = 1;
699
700 switch (qxl->mode) {
701 case QXL_MODE_COMPAT:
702 case QXL_MODE_NATIVE:
703 case QXL_MODE_UNDEFINED:
704 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
705 qxl_ring_set_dirty(qxl);
706 break;
707 default:
708 /* nothing */
709 break;
710 }
711 return wait;
712 }
713
714 /* called from spice server thread context */
715 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
716 {
717 fprintf(stderr, "%s: abort()\n", __FUNCTION__);
718 abort();
719 }
720
721 /* called from spice server thread context only */
722 static int interface_flush_resources(QXLInstance *sin)
723 {
724 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
725 int ret;
726
727 dprint(qxl, 1, "free: guest flush (have %d)\n", qxl->num_free_res);
728 ret = qxl->num_free_res;
729 if (ret) {
730 qxl_push_free_res(qxl, 1);
731 }
732 return ret;
733 }
734
735 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
736
737 #if SPICE_INTERFACE_QXL_MINOR >= 1
738
739 /* called from spice server thread context only */
740 static void interface_async_complete(QXLInstance *sin, uint64_t cookie)
741 {
742 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
743 uint32_t current_async;
744
745 qemu_mutex_lock(&qxl->async_lock);
746 current_async = qxl->current_async;
747 qxl->current_async = QXL_UNDEFINED_IO;
748 qemu_mutex_unlock(&qxl->async_lock);
749
750 dprint(qxl, 2, "async_complete: %d (%ld) done\n", current_async, cookie);
751 switch (current_async) {
752 case QXL_IO_CREATE_PRIMARY_ASYNC:
753 qxl_create_guest_primary_complete(qxl);
754 break;
755 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
756 qxl_spice_destroy_surfaces_complete(qxl);
757 break;
758 case QXL_IO_DESTROY_SURFACE_ASYNC:
759 qxl_spice_destroy_surface_wait_complete(qxl, (uint32_t)cookie);
760 break;
761 }
762 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
763 }
764
765 #endif
766
767 static const QXLInterface qxl_interface = {
768 .base.type = SPICE_INTERFACE_QXL,
769 .base.description = "qxl gpu",
770 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
771 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
772
773 .attache_worker = interface_attach_worker,
774 .set_compression_level = interface_set_compression_level,
775 .set_mm_time = interface_set_mm_time,
776 .get_init_info = interface_get_init_info,
777
778 /* the callbacks below are called from spice server thread context */
779 .get_command = interface_get_command,
780 .req_cmd_notification = interface_req_cmd_notification,
781 .release_resource = interface_release_resource,
782 .get_cursor_command = interface_get_cursor_command,
783 .req_cursor_notification = interface_req_cursor_notification,
784 .notify_update = interface_notify_update,
785 .flush_resources = interface_flush_resources,
786 #if SPICE_INTERFACE_QXL_MINOR >= 1
787 .async_complete = interface_async_complete,
788 #endif
789 };
790
791 static void qxl_enter_vga_mode(PCIQXLDevice *d)
792 {
793 if (d->mode == QXL_MODE_VGA) {
794 return;
795 }
796 dprint(d, 1, "%s\n", __FUNCTION__);
797 qemu_spice_create_host_primary(&d->ssd);
798 d->mode = QXL_MODE_VGA;
799 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
800 }
801
802 static void qxl_exit_vga_mode(PCIQXLDevice *d)
803 {
804 if (d->mode != QXL_MODE_VGA) {
805 return;
806 }
807 dprint(d, 1, "%s\n", __FUNCTION__);
808 qxl_destroy_primary(d, QXL_SYNC);
809 }
810
811 static void qxl_update_irq(PCIQXLDevice *d)
812 {
813 uint32_t pending = le32_to_cpu(d->ram->int_pending);
814 uint32_t mask = le32_to_cpu(d->ram->int_mask);
815 int level = !!(pending & mask);
816 qemu_set_irq(d->pci.irq[0], level);
817 qxl_ring_set_dirty(d);
818 }
819
820 static void qxl_check_state(PCIQXLDevice *d)
821 {
822 QXLRam *ram = d->ram;
823
824 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
825 assert(!d->ssd.running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
826 }
827
828 static void qxl_reset_state(PCIQXLDevice *d)
829 {
830 QXLRom *rom = d->rom;
831
832 qxl_check_state(d);
833 d->shadow_rom.update_id = cpu_to_le32(0);
834 *rom = d->shadow_rom;
835 qxl_rom_set_dirty(d);
836 init_qxl_ram(d);
837 d->num_free_res = 0;
838 d->last_release = NULL;
839 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
840 }
841
842 static void qxl_soft_reset(PCIQXLDevice *d)
843 {
844 dprint(d, 1, "%s:\n", __FUNCTION__);
845 qxl_check_state(d);
846
847 if (d->id == 0) {
848 qxl_enter_vga_mode(d);
849 } else {
850 d->mode = QXL_MODE_UNDEFINED;
851 }
852 }
853
854 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
855 {
856 dprint(d, 1, "%s: start%s\n", __FUNCTION__,
857 loadvm ? " (loadvm)" : "");
858
859 qxl_spice_reset_cursor(d);
860 qxl_spice_reset_image_cache(d);
861 qxl_reset_surfaces(d);
862 qxl_reset_memslots(d);
863
864 /* pre loadvm reset must not touch QXLRam. This lives in
865 * device memory, is migrated together with RAM and thus
866 * already loaded at this point */
867 if (!loadvm) {
868 qxl_reset_state(d);
869 }
870 qemu_spice_create_host_memslot(&d->ssd);
871 qxl_soft_reset(d);
872
873 dprint(d, 1, "%s: done\n", __FUNCTION__);
874 }
875
876 static void qxl_reset_handler(DeviceState *dev)
877 {
878 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
879 qxl_hard_reset(d, 0);
880 }
881
882 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
883 {
884 VGACommonState *vga = opaque;
885 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
886
887 if (qxl->mode != QXL_MODE_VGA) {
888 dprint(qxl, 1, "%s\n", __FUNCTION__);
889 qxl_destroy_primary(qxl, QXL_SYNC);
890 qxl_soft_reset(qxl);
891 }
892 vga_ioport_write(opaque, addr, val);
893 }
894
895 static void qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
896 qxl_async_io async)
897 {
898 static const int regions[] = {
899 QXL_RAM_RANGE_INDEX,
900 QXL_VRAM_RANGE_INDEX,
901 };
902 uint64_t guest_start;
903 uint64_t guest_end;
904 int pci_region;
905 pcibus_t pci_start;
906 pcibus_t pci_end;
907 intptr_t virt_start;
908 QXLDevMemSlot memslot;
909 int i;
910
911 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
912 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
913
914 dprint(d, 1, "%s: slot %d: guest phys 0x%" PRIx64 " - 0x%" PRIx64 "\n",
915 __FUNCTION__, slot_id,
916 guest_start, guest_end);
917
918 PANIC_ON(slot_id >= NUM_MEMSLOTS);
919 PANIC_ON(guest_start > guest_end);
920
921 for (i = 0; i < ARRAY_SIZE(regions); i++) {
922 pci_region = regions[i];
923 pci_start = d->pci.io_regions[pci_region].addr;
924 pci_end = pci_start + d->pci.io_regions[pci_region].size;
925 /* mapped? */
926 if (pci_start == -1) {
927 continue;
928 }
929 /* start address in range ? */
930 if (guest_start < pci_start || guest_start > pci_end) {
931 continue;
932 }
933 /* end address in range ? */
934 if (guest_end > pci_end) {
935 continue;
936 }
937 /* passed */
938 break;
939 }
940 PANIC_ON(i == ARRAY_SIZE(regions)); /* finished loop without match */
941
942 switch (pci_region) {
943 case QXL_RAM_RANGE_INDEX:
944 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
945 break;
946 case QXL_VRAM_RANGE_INDEX:
947 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
948 break;
949 default:
950 /* should not happen */
951 abort();
952 }
953
954 memslot.slot_id = slot_id;
955 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
956 memslot.virt_start = virt_start + (guest_start - pci_start);
957 memslot.virt_end = virt_start + (guest_end - pci_start);
958 memslot.addr_delta = memslot.virt_start - delta;
959 memslot.generation = d->rom->slot_generation = 0;
960 qxl_rom_set_dirty(d);
961
962 dprint(d, 1, "%s: slot %d: host virt 0x%lx - 0x%lx\n",
963 __FUNCTION__, memslot.slot_id,
964 memslot.virt_start, memslot.virt_end);
965
966 qemu_spice_add_memslot(&d->ssd, &memslot, async);
967 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
968 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
969 d->guest_slots[slot_id].delta = delta;
970 d->guest_slots[slot_id].active = 1;
971 }
972
973 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
974 {
975 dprint(d, 1, "%s: slot %d\n", __FUNCTION__, slot_id);
976 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
977 d->guest_slots[slot_id].active = 0;
978 }
979
980 static void qxl_reset_memslots(PCIQXLDevice *d)
981 {
982 dprint(d, 1, "%s:\n", __FUNCTION__);
983 qxl_spice_reset_memslots(d);
984 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
985 }
986
987 static void qxl_reset_surfaces(PCIQXLDevice *d)
988 {
989 dprint(d, 1, "%s:\n", __FUNCTION__);
990 d->mode = QXL_MODE_UNDEFINED;
991 qxl_spice_destroy_surfaces(d, QXL_SYNC);
992 }
993
994 /* called from spice server thread context only */
995 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
996 {
997 uint64_t phys = le64_to_cpu(pqxl);
998 uint32_t slot = (phys >> (64 - 8)) & 0xff;
999 uint64_t offset = phys & 0xffffffffffff;
1000
1001 switch (group_id) {
1002 case MEMSLOT_GROUP_HOST:
1003 return (void*)offset;
1004 case MEMSLOT_GROUP_GUEST:
1005 PANIC_ON(slot > NUM_MEMSLOTS);
1006 PANIC_ON(!qxl->guest_slots[slot].active);
1007 PANIC_ON(offset < qxl->guest_slots[slot].delta);
1008 offset -= qxl->guest_slots[slot].delta;
1009 PANIC_ON(offset > qxl->guest_slots[slot].size)
1010 return qxl->guest_slots[slot].ptr + offset;
1011 default:
1012 PANIC_ON(1);
1013 }
1014 }
1015
1016 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1017 {
1018 /* for local rendering */
1019 qxl_render_resize(qxl);
1020 }
1021
1022 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1023 qxl_async_io async)
1024 {
1025 QXLDevSurfaceCreate surface;
1026 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1027
1028 assert(qxl->mode != QXL_MODE_NATIVE);
1029 qxl_exit_vga_mode(qxl);
1030
1031 dprint(qxl, 1, "%s: %dx%d\n", __FUNCTION__,
1032 le32_to_cpu(sc->width), le32_to_cpu(sc->height));
1033
1034 surface.format = le32_to_cpu(sc->format);
1035 surface.height = le32_to_cpu(sc->height);
1036 surface.mem = le64_to_cpu(sc->mem);
1037 surface.position = le32_to_cpu(sc->position);
1038 surface.stride = le32_to_cpu(sc->stride);
1039 surface.width = le32_to_cpu(sc->width);
1040 surface.type = le32_to_cpu(sc->type);
1041 surface.flags = le32_to_cpu(sc->flags);
1042
1043 surface.mouse_mode = true;
1044 surface.group_id = MEMSLOT_GROUP_GUEST;
1045 if (loadvm) {
1046 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1047 }
1048
1049 qxl->mode = QXL_MODE_NATIVE;
1050 qxl->cmdflags = 0;
1051 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1052
1053 if (async == QXL_SYNC) {
1054 qxl_create_guest_primary_complete(qxl);
1055 }
1056 }
1057
1058 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1059 * done (in QXL_SYNC case), 0 otherwise. */
1060 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1061 {
1062 if (d->mode == QXL_MODE_UNDEFINED) {
1063 return 0;
1064 }
1065
1066 dprint(d, 1, "%s\n", __FUNCTION__);
1067
1068 d->mode = QXL_MODE_UNDEFINED;
1069 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1070 return 1;
1071 }
1072
1073 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1074 {
1075 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1076 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1077 QXLMode *mode = d->modes->modes + modenr;
1078 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1079 QXLMemSlot slot = {
1080 .mem_start = start,
1081 .mem_end = end
1082 };
1083 QXLSurfaceCreate surface = {
1084 .width = mode->x_res,
1085 .height = mode->y_res,
1086 .stride = -mode->x_res * 4,
1087 .format = SPICE_SURFACE_FMT_32_xRGB,
1088 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1089 .mouse_mode = true,
1090 .mem = devmem + d->shadow_rom.draw_area_offset,
1091 };
1092
1093 dprint(d, 1, "%s: mode %d [ %d x %d @ %d bpp devmem 0x%" PRIx64 " ]\n",
1094 __func__, modenr, mode->x_res, mode->y_res, mode->bits, devmem);
1095 if (!loadvm) {
1096 qxl_hard_reset(d, 0);
1097 }
1098
1099 d->guest_slots[0].slot = slot;
1100 qxl_add_memslot(d, 0, devmem, QXL_SYNC);
1101
1102 d->guest_primary.surface = surface;
1103 qxl_create_guest_primary(d, 0, QXL_SYNC);
1104
1105 d->mode = QXL_MODE_COMPAT;
1106 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1107 #ifdef QXL_COMMAND_FLAG_COMPAT_16BPP /* new in spice 0.6.1 */
1108 if (mode->bits == 16) {
1109 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1110 }
1111 #endif
1112 d->shadow_rom.mode = cpu_to_le32(modenr);
1113 d->rom->mode = cpu_to_le32(modenr);
1114 qxl_rom_set_dirty(d);
1115 }
1116
1117 static void ioport_write(void *opaque, target_phys_addr_t addr,
1118 uint64_t val, unsigned size)
1119 {
1120 PCIQXLDevice *d = opaque;
1121 uint32_t io_port = addr;
1122 qxl_async_io async = QXL_SYNC;
1123 #if SPICE_INTERFACE_QXL_MINOR >= 1
1124 uint32_t orig_io_port = io_port;
1125 #endif
1126
1127 switch (io_port) {
1128 case QXL_IO_RESET:
1129 case QXL_IO_SET_MODE:
1130 case QXL_IO_MEMSLOT_ADD:
1131 case QXL_IO_MEMSLOT_DEL:
1132 case QXL_IO_CREATE_PRIMARY:
1133 case QXL_IO_UPDATE_IRQ:
1134 case QXL_IO_LOG:
1135 #if SPICE_INTERFACE_QXL_MINOR >= 1
1136 case QXL_IO_MEMSLOT_ADD_ASYNC:
1137 case QXL_IO_CREATE_PRIMARY_ASYNC:
1138 #endif
1139 break;
1140 default:
1141 if (d->mode != QXL_MODE_VGA) {
1142 break;
1143 }
1144 dprint(d, 1, "%s: unexpected port 0x%x (%s) in vga mode\n",
1145 __func__, io_port, io_port_to_string(io_port));
1146 #if SPICE_INTERFACE_QXL_MINOR >= 1
1147 /* be nice to buggy guest drivers */
1148 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1149 io_port <= QXL_IO_DESTROY_ALL_SURFACES_ASYNC) {
1150 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1151 }
1152 #endif
1153 return;
1154 }
1155
1156 #if SPICE_INTERFACE_QXL_MINOR >= 1
1157 /* we change the io_port to avoid ifdeffery in the main switch */
1158 orig_io_port = io_port;
1159 switch (io_port) {
1160 case QXL_IO_UPDATE_AREA_ASYNC:
1161 io_port = QXL_IO_UPDATE_AREA;
1162 goto async_common;
1163 case QXL_IO_MEMSLOT_ADD_ASYNC:
1164 io_port = QXL_IO_MEMSLOT_ADD;
1165 goto async_common;
1166 case QXL_IO_CREATE_PRIMARY_ASYNC:
1167 io_port = QXL_IO_CREATE_PRIMARY;
1168 goto async_common;
1169 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1170 io_port = QXL_IO_DESTROY_PRIMARY;
1171 goto async_common;
1172 case QXL_IO_DESTROY_SURFACE_ASYNC:
1173 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1174 goto async_common;
1175 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1176 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1177 goto async_common;
1178 case QXL_IO_FLUSH_SURFACES_ASYNC:
1179 async_common:
1180 async = QXL_ASYNC;
1181 qemu_mutex_lock(&d->async_lock);
1182 if (d->current_async != QXL_UNDEFINED_IO) {
1183 qxl_guest_bug(d, "%d async started before last (%d) complete",
1184 io_port, d->current_async);
1185 qemu_mutex_unlock(&d->async_lock);
1186 return;
1187 }
1188 d->current_async = orig_io_port;
1189 qemu_mutex_unlock(&d->async_lock);
1190 dprint(d, 2, "start async %d (%"PRId64")\n", io_port, val);
1191 break;
1192 default:
1193 break;
1194 }
1195 #endif
1196
1197 switch (io_port) {
1198 case QXL_IO_UPDATE_AREA:
1199 {
1200 QXLRect update = d->ram->update_area;
1201 qxl_spice_update_area(d, d->ram->update_surface,
1202 &update, NULL, 0, 0, async);
1203 break;
1204 }
1205 case QXL_IO_NOTIFY_CMD:
1206 qemu_spice_wakeup(&d->ssd);
1207 break;
1208 case QXL_IO_NOTIFY_CURSOR:
1209 qemu_spice_wakeup(&d->ssd);
1210 break;
1211 case QXL_IO_UPDATE_IRQ:
1212 qxl_update_irq(d);
1213 break;
1214 case QXL_IO_NOTIFY_OOM:
1215 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1216 break;
1217 }
1218 pthread_yield();
1219 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1220 break;
1221 }
1222 d->oom_running = 1;
1223 qxl_spice_oom(d);
1224 d->oom_running = 0;
1225 break;
1226 case QXL_IO_SET_MODE:
1227 dprint(d, 1, "QXL_SET_MODE %d\n", (int)val);
1228 qxl_set_mode(d, val, 0);
1229 break;
1230 case QXL_IO_LOG:
1231 if (d->guestdebug) {
1232 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1233 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
1234 }
1235 break;
1236 case QXL_IO_RESET:
1237 dprint(d, 1, "QXL_IO_RESET\n");
1238 qxl_hard_reset(d, 0);
1239 break;
1240 case QXL_IO_MEMSLOT_ADD:
1241 if (val >= NUM_MEMSLOTS) {
1242 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1243 break;
1244 }
1245 if (d->guest_slots[val].active) {
1246 qxl_guest_bug(d, "QXL_IO_MEMSLOT_ADD: memory slot already active");
1247 break;
1248 }
1249 d->guest_slots[val].slot = d->ram->mem_slot;
1250 qxl_add_memslot(d, val, 0, async);
1251 break;
1252 case QXL_IO_MEMSLOT_DEL:
1253 if (val >= NUM_MEMSLOTS) {
1254 qxl_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1255 break;
1256 }
1257 qxl_del_memslot(d, val);
1258 break;
1259 case QXL_IO_CREATE_PRIMARY:
1260 if (val != 0) {
1261 qxl_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1262 async);
1263 goto cancel_async;
1264 }
1265 dprint(d, 1, "QXL_IO_CREATE_PRIMARY async=%d\n", async);
1266 d->guest_primary.surface = d->ram->create_surface;
1267 qxl_create_guest_primary(d, 0, async);
1268 break;
1269 case QXL_IO_DESTROY_PRIMARY:
1270 if (val != 0) {
1271 qxl_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1272 async);
1273 goto cancel_async;
1274 }
1275 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY (async=%d) (%s)\n", async,
1276 qxl_mode_to_string(d->mode));
1277 if (!qxl_destroy_primary(d, async)) {
1278 dprint(d, 1, "QXL_IO_DESTROY_PRIMARY_ASYNC in %s, ignored\n",
1279 qxl_mode_to_string(d->mode));
1280 goto cancel_async;
1281 }
1282 break;
1283 case QXL_IO_DESTROY_SURFACE_WAIT:
1284 if (val >= NUM_SURFACES) {
1285 qxl_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1286 "%d >= NUM_SURFACES", async, val);
1287 goto cancel_async;
1288 }
1289 qxl_spice_destroy_surface_wait(d, val, async);
1290 break;
1291 #if SPICE_INTERFACE_QXL_MINOR >= 1
1292 case QXL_IO_FLUSH_RELEASE: {
1293 QXLReleaseRing *ring = &d->ram->release_ring;
1294 if (ring->prod - ring->cons + 1 == ring->num_items) {
1295 fprintf(stderr,
1296 "ERROR: no flush, full release ring [p%d,%dc]\n",
1297 ring->prod, ring->cons);
1298 }
1299 qxl_push_free_res(d, 1 /* flush */);
1300 dprint(d, 1, "QXL_IO_FLUSH_RELEASE exit (%s, s#=%d, res#=%d,%p)\n",
1301 qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1302 d->num_free_res, d->last_release);
1303 break;
1304 }
1305 case QXL_IO_FLUSH_SURFACES_ASYNC:
1306 dprint(d, 1, "QXL_IO_FLUSH_SURFACES_ASYNC"
1307 " (%"PRId64") (%s, s#=%d, res#=%d)\n",
1308 val, qxl_mode_to_string(d->mode), d->guest_surfaces.count,
1309 d->num_free_res);
1310 qxl_spice_flush_surfaces_async(d);
1311 break;
1312 #endif
1313 case QXL_IO_DESTROY_ALL_SURFACES:
1314 d->mode = QXL_MODE_UNDEFINED;
1315 qxl_spice_destroy_surfaces(d, async);
1316 break;
1317 default:
1318 fprintf(stderr, "%s: ioport=0x%x, abort()\n", __FUNCTION__, io_port);
1319 abort();
1320 }
1321 return;
1322 cancel_async:
1323 #if SPICE_INTERFACE_QXL_MINOR >= 1
1324 if (async) {
1325 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1326 qemu_mutex_lock(&d->async_lock);
1327 d->current_async = QXL_UNDEFINED_IO;
1328 qemu_mutex_unlock(&d->async_lock);
1329 }
1330 #else
1331 return;
1332 #endif
1333 }
1334
1335 static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
1336 unsigned size)
1337 {
1338 PCIQXLDevice *d = opaque;
1339
1340 dprint(d, 1, "%s: unexpected\n", __FUNCTION__);
1341 return 0xff;
1342 }
1343
1344 static const MemoryRegionOps qxl_io_ops = {
1345 .read = ioport_read,
1346 .write = ioport_write,
1347 .valid = {
1348 .min_access_size = 1,
1349 .max_access_size = 1,
1350 },
1351 };
1352
1353 static void pipe_read(void *opaque)
1354 {
1355 PCIQXLDevice *d = opaque;
1356 char dummy;
1357 int len;
1358
1359 do {
1360 len = read(d->pipe[0], &dummy, sizeof(dummy));
1361 } while (len == sizeof(dummy));
1362 qxl_update_irq(d);
1363 }
1364
1365 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1366 {
1367 uint32_t old_pending;
1368 uint32_t le_events = cpu_to_le32(events);
1369
1370 assert(d->ssd.running);
1371 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1372 if ((old_pending & le_events) == le_events) {
1373 return;
1374 }
1375 if (pthread_self() == d->main) {
1376 qxl_update_irq(d);
1377 } else {
1378 if (write(d->pipe[1], d, 1) != 1) {
1379 dprint(d, 1, "%s: write to pipe failed\n", __FUNCTION__);
1380 }
1381 }
1382 }
1383
1384 static void init_pipe_signaling(PCIQXLDevice *d)
1385 {
1386 if (pipe(d->pipe) < 0) {
1387 dprint(d, 1, "%s: pipe creation failed\n", __FUNCTION__);
1388 return;
1389 }
1390 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1391 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1392 fcntl(d->pipe[0], F_SETOWN, getpid());
1393
1394 d->main = pthread_self();
1395 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1396 }
1397
1398 /* graphics console */
1399
1400 static void qxl_hw_update(void *opaque)
1401 {
1402 PCIQXLDevice *qxl = opaque;
1403 VGACommonState *vga = &qxl->vga;
1404
1405 switch (qxl->mode) {
1406 case QXL_MODE_VGA:
1407 vga->update(vga);
1408 break;
1409 case QXL_MODE_COMPAT:
1410 case QXL_MODE_NATIVE:
1411 qxl_render_update(qxl);
1412 break;
1413 default:
1414 break;
1415 }
1416 }
1417
1418 static void qxl_hw_invalidate(void *opaque)
1419 {
1420 PCIQXLDevice *qxl = opaque;
1421 VGACommonState *vga = &qxl->vga;
1422
1423 vga->invalidate(vga);
1424 }
1425
1426 static void qxl_hw_screen_dump(void *opaque, const char *filename)
1427 {
1428 PCIQXLDevice *qxl = opaque;
1429 VGACommonState *vga = &qxl->vga;
1430
1431 switch (qxl->mode) {
1432 case QXL_MODE_COMPAT:
1433 case QXL_MODE_NATIVE:
1434 qxl_render_update(qxl);
1435 ppm_save(filename, qxl->ssd.ds->surface);
1436 break;
1437 case QXL_MODE_VGA:
1438 vga->screen_dump(vga, filename);
1439 break;
1440 default:
1441 break;
1442 }
1443 }
1444
1445 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1446 {
1447 PCIQXLDevice *qxl = opaque;
1448 VGACommonState *vga = &qxl->vga;
1449
1450 if (qxl->mode == QXL_MODE_VGA) {
1451 vga->text_update(vga, chardata);
1452 return;
1453 }
1454 }
1455
1456 static void qxl_vm_change_state_handler(void *opaque, int running,
1457 RunState state)
1458 {
1459 PCIQXLDevice *qxl = opaque;
1460 qemu_spice_vm_change_state_handler(&qxl->ssd, running, state);
1461
1462 if (running) {
1463 /*
1464 * if qxl_send_events was called from spice server context before
1465 * migration ended, qxl_update_irq for these events might not have been
1466 * called
1467 */
1468 qxl_update_irq(qxl);
1469 } else if (qxl->mode == QXL_MODE_NATIVE) {
1470 /* dirty all vram (which holds surfaces) and devram (primary surface)
1471 * to make sure they are saved */
1472 /* FIXME #1: should go out during "live" stage */
1473 /* FIXME #2: we only need to save the areas which are actually used */
1474 qxl_set_dirty(&qxl->vram_bar, 0, qxl->vram_size);
1475 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1476 qxl->shadow_rom.surface0_area_size);
1477 }
1478 }
1479
1480 /* display change listener */
1481
1482 static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1483 {
1484 if (qxl0->mode == QXL_MODE_VGA) {
1485 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1486 }
1487 }
1488
1489 static void display_resize(struct DisplayState *ds)
1490 {
1491 if (qxl0->mode == QXL_MODE_VGA) {
1492 qemu_spice_display_resize(&qxl0->ssd);
1493 }
1494 }
1495
1496 static void display_refresh(struct DisplayState *ds)
1497 {
1498 if (qxl0->mode == QXL_MODE_VGA) {
1499 qemu_spice_display_refresh(&qxl0->ssd);
1500 }
1501 }
1502
1503 static DisplayChangeListener display_listener = {
1504 .dpy_update = display_update,
1505 .dpy_resize = display_resize,
1506 .dpy_refresh = display_refresh,
1507 };
1508
1509 static int qxl_init_common(PCIQXLDevice *qxl)
1510 {
1511 uint8_t* config = qxl->pci.config;
1512 uint32_t pci_device_rev;
1513 uint32_t io_size;
1514
1515 qxl->mode = QXL_MODE_UNDEFINED;
1516 qxl->generation = 1;
1517 qxl->num_memslots = NUM_MEMSLOTS;
1518 qxl->num_surfaces = NUM_SURFACES;
1519 qemu_mutex_init(&qxl->track_lock);
1520 qemu_mutex_init(&qxl->async_lock);
1521 qxl->current_async = QXL_UNDEFINED_IO;
1522
1523 switch (qxl->revision) {
1524 case 1: /* spice 0.4 -- qxl-1 */
1525 pci_device_rev = QXL_REVISION_STABLE_V04;
1526 break;
1527 case 2: /* spice 0.6 -- qxl-2 */
1528 pci_device_rev = QXL_REVISION_STABLE_V06;
1529 break;
1530 #if SPICE_INTERFACE_QXL_MINOR >= 1
1531 case 3: /* qxl-3 */
1532 #endif
1533 default:
1534 pci_device_rev = QXL_DEFAULT_REVISION;
1535 break;
1536 }
1537
1538 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1539 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1540
1541 qxl->rom_size = qxl_rom_size();
1542 memory_region_init_ram(&qxl->rom_bar, &qxl->pci.qdev, "qxl.vrom",
1543 qxl->rom_size);
1544 init_qxl_rom(qxl);
1545 init_qxl_ram(qxl);
1546
1547 if (qxl->vram_size < 16 * 1024 * 1024) {
1548 qxl->vram_size = 16 * 1024 * 1024;
1549 }
1550 if (qxl->revision == 1) {
1551 qxl->vram_size = 4096;
1552 }
1553 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1554 memory_region_init_ram(&qxl->vram_bar, &qxl->pci.qdev, "qxl.vram",
1555 qxl->vram_size);
1556
1557 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1558 if (qxl->revision == 1) {
1559 io_size = 8;
1560 }
1561
1562 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
1563 "qxl-ioports", io_size);
1564 if (qxl->id == 0) {
1565 vga_dirty_log_start(&qxl->vga);
1566 }
1567
1568
1569 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
1570 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
1571
1572 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
1573 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
1574
1575 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
1576 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
1577
1578 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
1579 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram_bar);
1580
1581 qxl->ssd.qxl.base.sif = &qxl_interface.base;
1582 qxl->ssd.qxl.id = qxl->id;
1583 qemu_spice_add_interface(&qxl->ssd.qxl.base);
1584 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
1585
1586 init_pipe_signaling(qxl);
1587 qxl_reset_state(qxl);
1588
1589 return 0;
1590 }
1591
1592 static int qxl_init_primary(PCIDevice *dev)
1593 {
1594 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1595 VGACommonState *vga = &qxl->vga;
1596 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1597
1598 qxl->id = 0;
1599
1600 if (ram_size < 32 * 1024 * 1024) {
1601 ram_size = 32 * 1024 * 1024;
1602 }
1603 vga_common_init(vga, ram_size);
1604 vga_init(vga, pci_address_space(dev));
1605 register_ioport_write(0x3c0, 16, 1, qxl_vga_ioport_write, vga);
1606 register_ioport_write(0x3b4, 2, 1, qxl_vga_ioport_write, vga);
1607 register_ioport_write(0x3d4, 2, 1, qxl_vga_ioport_write, vga);
1608 register_ioport_write(0x3ba, 1, 1, qxl_vga_ioport_write, vga);
1609 register_ioport_write(0x3da, 1, 1, qxl_vga_ioport_write, vga);
1610
1611 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
1612 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
1613 qemu_spice_display_init_common(&qxl->ssd, vga->ds);
1614
1615 qxl0 = qxl;
1616 register_displaychangelistener(vga->ds, &display_listener);
1617
1618 return qxl_init_common(qxl);
1619 }
1620
1621 static int qxl_init_secondary(PCIDevice *dev)
1622 {
1623 static int device_id = 1;
1624 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
1625 ram_addr_t ram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1626
1627 qxl->id = device_id++;
1628
1629 if (ram_size < 16 * 1024 * 1024) {
1630 ram_size = 16 * 1024 * 1024;
1631 }
1632 qxl->vga.vram_size = ram_size;
1633 memory_region_init_ram(&qxl->vga.vram, &qxl->pci.qdev, "qxl.vgavram",
1634 qxl->vga.vram_size);
1635 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
1636
1637 return qxl_init_common(qxl);
1638 }
1639
1640 static void qxl_pre_save(void *opaque)
1641 {
1642 PCIQXLDevice* d = opaque;
1643 uint8_t *ram_start = d->vga.vram_ptr;
1644
1645 dprint(d, 1, "%s:\n", __FUNCTION__);
1646 if (d->last_release == NULL) {
1647 d->last_release_offset = 0;
1648 } else {
1649 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
1650 }
1651 assert(d->last_release_offset < d->vga.vram_size);
1652 }
1653
1654 static int qxl_pre_load(void *opaque)
1655 {
1656 PCIQXLDevice* d = opaque;
1657
1658 dprint(d, 1, "%s: start\n", __FUNCTION__);
1659 qxl_hard_reset(d, 1);
1660 qxl_exit_vga_mode(d);
1661 dprint(d, 1, "%s: done\n", __FUNCTION__);
1662 return 0;
1663 }
1664
1665 static int qxl_post_load(void *opaque, int version)
1666 {
1667 PCIQXLDevice* d = opaque;
1668 uint8_t *ram_start = d->vga.vram_ptr;
1669 QXLCommandExt *cmds;
1670 int in, out, i, newmode;
1671
1672 dprint(d, 1, "%s: start\n", __FUNCTION__);
1673
1674 assert(d->last_release_offset < d->vga.vram_size);
1675 if (d->last_release_offset == 0) {
1676 d->last_release = NULL;
1677 } else {
1678 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
1679 }
1680
1681 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
1682
1683 dprint(d, 1, "%s: restore mode (%s)\n", __FUNCTION__,
1684 qxl_mode_to_string(d->mode));
1685 newmode = d->mode;
1686 d->mode = QXL_MODE_UNDEFINED;
1687 switch (newmode) {
1688 case QXL_MODE_UNDEFINED:
1689 break;
1690 case QXL_MODE_VGA:
1691 qxl_enter_vga_mode(d);
1692 break;
1693 case QXL_MODE_NATIVE:
1694 for (i = 0; i < NUM_MEMSLOTS; i++) {
1695 if (!d->guest_slots[i].active) {
1696 continue;
1697 }
1698 qxl_add_memslot(d, i, 0, QXL_SYNC);
1699 }
1700 qxl_create_guest_primary(d, 1, QXL_SYNC);
1701
1702 /* replay surface-create and cursor-set commands */
1703 cmds = g_malloc0(sizeof(QXLCommandExt) * (NUM_SURFACES + 1));
1704 for (in = 0, out = 0; in < NUM_SURFACES; in++) {
1705 if (d->guest_surfaces.cmds[in] == 0) {
1706 continue;
1707 }
1708 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
1709 cmds[out].cmd.type = QXL_CMD_SURFACE;
1710 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1711 out++;
1712 }
1713 cmds[out].cmd.data = d->guest_cursor;
1714 cmds[out].cmd.type = QXL_CMD_CURSOR;
1715 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
1716 out++;
1717 qxl_spice_loadvm_commands(d, cmds, out);
1718 g_free(cmds);
1719
1720 break;
1721 case QXL_MODE_COMPAT:
1722 qxl_set_mode(d, d->shadow_rom.mode, 1);
1723 break;
1724 }
1725 dprint(d, 1, "%s: done\n", __FUNCTION__);
1726
1727 return 0;
1728 }
1729
1730 #define QXL_SAVE_VERSION 21
1731
1732 static VMStateDescription qxl_memslot = {
1733 .name = "qxl-memslot",
1734 .version_id = QXL_SAVE_VERSION,
1735 .minimum_version_id = QXL_SAVE_VERSION,
1736 .fields = (VMStateField[]) {
1737 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
1738 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
1739 VMSTATE_UINT32(active, struct guest_slots),
1740 VMSTATE_END_OF_LIST()
1741 }
1742 };
1743
1744 static VMStateDescription qxl_surface = {
1745 .name = "qxl-surface",
1746 .version_id = QXL_SAVE_VERSION,
1747 .minimum_version_id = QXL_SAVE_VERSION,
1748 .fields = (VMStateField[]) {
1749 VMSTATE_UINT32(width, QXLSurfaceCreate),
1750 VMSTATE_UINT32(height, QXLSurfaceCreate),
1751 VMSTATE_INT32(stride, QXLSurfaceCreate),
1752 VMSTATE_UINT32(format, QXLSurfaceCreate),
1753 VMSTATE_UINT32(position, QXLSurfaceCreate),
1754 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
1755 VMSTATE_UINT32(flags, QXLSurfaceCreate),
1756 VMSTATE_UINT32(type, QXLSurfaceCreate),
1757 VMSTATE_UINT64(mem, QXLSurfaceCreate),
1758 VMSTATE_END_OF_LIST()
1759 }
1760 };
1761
1762 static VMStateDescription qxl_vmstate = {
1763 .name = "qxl",
1764 .version_id = QXL_SAVE_VERSION,
1765 .minimum_version_id = QXL_SAVE_VERSION,
1766 .pre_save = qxl_pre_save,
1767 .pre_load = qxl_pre_load,
1768 .post_load = qxl_post_load,
1769 .fields = (VMStateField []) {
1770 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
1771 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
1772 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
1773 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
1774 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
1775 VMSTATE_UINT32(mode, PCIQXLDevice),
1776 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
1777 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
1778 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
1779 qxl_memslot, struct guest_slots),
1780 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
1781 qxl_surface, QXLSurfaceCreate),
1782 VMSTATE_INT32_EQUAL(num_surfaces, PCIQXLDevice),
1783 VMSTATE_ARRAY(guest_surfaces.cmds, PCIQXLDevice, NUM_SURFACES, 0,
1784 vmstate_info_uint64, uint64_t),
1785 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
1786 VMSTATE_END_OF_LIST()
1787 },
1788 };
1789
1790 static PCIDeviceInfo qxl_info_primary = {
1791 .qdev.name = "qxl-vga",
1792 .qdev.desc = "Spice QXL GPU (primary, vga compatible)",
1793 .qdev.size = sizeof(PCIQXLDevice),
1794 .qdev.reset = qxl_reset_handler,
1795 .qdev.vmsd = &qxl_vmstate,
1796 .no_hotplug = 1,
1797 .init = qxl_init_primary,
1798 .romfile = "vgabios-qxl.bin",
1799 .vendor_id = REDHAT_PCI_VENDOR_ID,
1800 .device_id = QXL_DEVICE_ID_STABLE,
1801 .class_id = PCI_CLASS_DISPLAY_VGA,
1802 .qdev.props = (Property[]) {
1803 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
1804 64 * 1024 * 1024),
1805 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size,
1806 64 * 1024 * 1024),
1807 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
1808 QXL_DEFAULT_REVISION),
1809 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1810 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1811 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1812 DEFINE_PROP_END_OF_LIST(),
1813 }
1814 };
1815
1816 static PCIDeviceInfo qxl_info_secondary = {
1817 .qdev.name = "qxl",
1818 .qdev.desc = "Spice QXL GPU (secondary)",
1819 .qdev.size = sizeof(PCIQXLDevice),
1820 .qdev.reset = qxl_reset_handler,
1821 .qdev.vmsd = &qxl_vmstate,
1822 .init = qxl_init_secondary,
1823 .vendor_id = REDHAT_PCI_VENDOR_ID,
1824 .device_id = QXL_DEVICE_ID_STABLE,
1825 .class_id = PCI_CLASS_DISPLAY_OTHER,
1826 .qdev.props = (Property[]) {
1827 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
1828 64 * 1024 * 1024),
1829 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram_size,
1830 64 * 1024 * 1024),
1831 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
1832 QXL_DEFAULT_REVISION),
1833 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
1834 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
1835 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
1836 DEFINE_PROP_END_OF_LIST(),
1837 }
1838 };
1839
1840 static void qxl_register(void)
1841 {
1842 pci_qdev_register(&qxl_info_primary);
1843 pci_qdev_register(&qxl_info_secondary);
1844 }
1845
1846 device_init(qxl_register);
QEmu