hw/m48t59.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
   3  *
   4  * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "qemu-timer.h"
  27 #include "sysemu.h"
  28 #include "sysbus.h"
  29 #include "isa.h"
  30
  31 //#define DEBUG_NVRAM
  32
  33 #if defined(DEBUG_NVRAM)
  34 #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
  35 #else
  36 #define NVRAM_PRINTF(fmt, ...) do { } while (0)
  37 #endif
  38
  39 /*
  40  * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
  41  * alarm and a watchdog timer and related control registers. In the
  42  * PPC platform there is also a nvram lock function.
  43  */
  44
  45 /*
  46  * Chipset docs:
  47  * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
  48  * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
  49  * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
  50  */
  51
  52 struct M48t59State {
  53     /* Hardware parameters */
  54     qemu_irq IRQ;
  55     uint32_t io_base;
  56     uint32_t size;
  57     /* RTC management */
  58     time_t   time_offset;
  59     time_t   stop_time;
  60     /* Alarm & watchdog */
  61     struct tm alarm;
  62     struct QEMUTimer *alrm_timer;
  63     struct QEMUTimer *wd_timer;
  64     /* NVRAM storage */
  65     uint8_t *buffer;
  66     /* Model parameters */
  67     uint32_t type; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
  68     /* NVRAM storage */
  69     uint16_t addr;
  70     uint8_t  lock;
  71 };
  72
  73 typedef struct M48t59ISAState {
  74     ISADevice busdev;
  75     M48t59State state;
  76 } M48t59ISAState;
  77
  78 typedef struct M48t59SysBusState {
  79     SysBusDevice busdev;
  80     M48t59State state;
  81 } M48t59SysBusState;
  82
  83 /* Fake timer functions */
  84
  85 /* Alarm management */
  86 static void alarm_cb (void *opaque)
  87 {
  88     struct tm tm;
  89     uint64_t next_time;
  90     M48t59State *NVRAM = opaque;
  91
  92     qemu_set_irq(NVRAM->IRQ, 1);
  93     if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
  94         (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
  95         (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
  96         (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
  97         /* Repeat once a month */
  98         qemu_get_timedate(&tm, NVRAM->time_offset);
  99         tm.tm_mon++;
 100         if (tm.tm_mon == 13) {
 101             tm.tm_mon = 1;
 102             tm.tm_year++;
 103         }
 104         next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
 105     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 106                (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 107                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 108                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 109         /* Repeat once a day */
 110         next_time = 24 * 60 * 60;
 111     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 112                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 113                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 114                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 115         /* Repeat once an hour */
 116         next_time = 60 * 60;
 117     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 118                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 119                (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
 120                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 121         /* Repeat once a minute */
 122         next_time = 60;
 123     } else {
 124         /* Repeat once a second */
 125         next_time = 1;
 126     }
 127     qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(vm_clock) +
 128                     next_time * 1000);
 129     qemu_set_irq(NVRAM->IRQ, 0);
 130 }
 131
 132 static void set_alarm(M48t59State *NVRAM)
 133 {
 134     int diff;
 135     if (NVRAM->alrm_timer != NULL) {
 136         qemu_del_timer(NVRAM->alrm_timer);
 137         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 138         if (diff > 0)
 139             qemu_mod_timer(NVRAM->alrm_timer, diff * 1000);
 140     }
 141 }
 142
 143 /* RTC management helpers */
 144 static inline void get_time(M48t59State *NVRAM, struct tm *tm)
 145 {
 146     qemu_get_timedate(tm, NVRAM->time_offset);
 147 }
 148
 149 static void set_time(M48t59State *NVRAM, struct tm *tm)
 150 {
 151     NVRAM->time_offset = qemu_timedate_diff(tm);
 152     set_alarm(NVRAM);
 153 }
 154
 155 /* Watchdog management */
 156 static void watchdog_cb (void *opaque)
 157 {
 158     M48t59State *NVRAM = opaque;
 159
 160     NVRAM->buffer[0x1FF0] |= 0x80;
 161     if (NVRAM->buffer[0x1FF7] & 0x80) {
 162         NVRAM->buffer[0x1FF7] = 0x00;
 163         NVRAM->buffer[0x1FFC] &= ~0x40;
 164         /* May it be a hw CPU Reset instead ? */
 165         qemu_system_reset_request();
 166     } else {
 167         qemu_set_irq(NVRAM->IRQ, 1);
 168         qemu_set_irq(NVRAM->IRQ, 0);
 169     }
 170 }
 171
 172 static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
 173 {
 174     uint64_t interval; /* in 1/16 seconds */
 175
 176     NVRAM->buffer[0x1FF0] &= ~0x80;
 177     if (NVRAM->wd_timer != NULL) {
 178         qemu_del_timer(NVRAM->wd_timer);
 179         if (value != 0) {
 180             interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
 181             qemu_mod_timer(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
 182                            ((interval * 1000) >> 4));
 183         }
 184     }
 185 }
 186
 187 /* Direct access to NVRAM */
 188 void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
 189 {
 190     M48t59State *NVRAM = opaque;
 191     struct tm tm;
 192     int tmp;
 193
 194     if (addr > 0x1FF8 && addr < 0x2000)
 195         NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 196
 197     /* check for NVRAM access */
 198     if ((NVRAM->type == 2 && addr < 0x7f8) ||
 199         (NVRAM->type == 8 && addr < 0x1ff8) ||
 200         (NVRAM->type == 59 && addr < 0x1ff0))
 201         goto do_write;
 202
 203     /* TOD access */
 204     switch (addr) {
 205     case 0x1FF0:
 206         /* flags register : read-only */
 207         break;
 208     case 0x1FF1:
 209         /* unused */
 210         break;
 211     case 0x1FF2:
 212         /* alarm seconds */
 213         tmp = from_bcd(val & 0x7F);
 214         if (tmp >= 0 && tmp <= 59) {
 215             NVRAM->alarm.tm_sec = tmp;
 216             NVRAM->buffer[0x1FF2] = val;
 217             set_alarm(NVRAM);
 218         }
 219         break;
 220     case 0x1FF3:
 221         /* alarm minutes */
 222         tmp = from_bcd(val & 0x7F);
 223         if (tmp >= 0 && tmp <= 59) {
 224             NVRAM->alarm.tm_min = tmp;
 225             NVRAM->buffer[0x1FF3] = val;
 226             set_alarm(NVRAM);
 227         }
 228         break;
 229     case 0x1FF4:
 230         /* alarm hours */
 231         tmp = from_bcd(val & 0x3F);
 232         if (tmp >= 0 && tmp <= 23) {
 233             NVRAM->alarm.tm_hour = tmp;
 234             NVRAM->buffer[0x1FF4] = val;
 235             set_alarm(NVRAM);
 236         }
 237         break;
 238     case 0x1FF5:
 239         /* alarm date */
 240         tmp = from_bcd(val & 0x1F);
 241         if (tmp != 0) {
 242             NVRAM->alarm.tm_mday = tmp;
 243             NVRAM->buffer[0x1FF5] = val;
 244             set_alarm(NVRAM);
 245         }
 246         break;
 247     case 0x1FF6:
 248         /* interrupts */
 249         NVRAM->buffer[0x1FF6] = val;
 250         break;
 251     case 0x1FF7:
 252         /* watchdog */
 253         NVRAM->buffer[0x1FF7] = val;
 254         set_up_watchdog(NVRAM, val);
 255         break;
 256     case 0x1FF8:
 257     case 0x07F8:
 258         /* control */
 259        NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
 260         break;
 261     case 0x1FF9:
 262     case 0x07F9:
 263         /* seconds (BCD) */
 264         tmp = from_bcd(val & 0x7F);
 265         if (tmp >= 0 && tmp <= 59) {
 266             get_time(NVRAM, &tm);
 267             tm.tm_sec = tmp;
 268             set_time(NVRAM, &tm);
 269         }
 270         if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
 271             if (val & 0x80) {
 272                 NVRAM->stop_time = time(NULL);
 273             } else {
 274                 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
 275                 NVRAM->stop_time = 0;
 276             }
 277         }
 278         NVRAM->buffer[addr] = val & 0x80;
 279         break;
 280     case 0x1FFA:
 281     case 0x07FA:
 282         /* minutes (BCD) */
 283         tmp = from_bcd(val & 0x7F);
 284         if (tmp >= 0 && tmp <= 59) {
 285             get_time(NVRAM, &tm);
 286             tm.tm_min = tmp;
 287             set_time(NVRAM, &tm);
 288         }
 289         break;
 290     case 0x1FFB:
 291     case 0x07FB:
 292         /* hours (BCD) */
 293         tmp = from_bcd(val & 0x3F);
 294         if (tmp >= 0 && tmp <= 23) {
 295             get_time(NVRAM, &tm);
 296             tm.tm_hour = tmp;
 297             set_time(NVRAM, &tm);
 298         }
 299         break;
 300     case 0x1FFC:
 301     case 0x07FC:
 302         /* day of the week / century */
 303         tmp = from_bcd(val & 0x07);
 304         get_time(NVRAM, &tm);
 305         tm.tm_wday = tmp;
 306         set_time(NVRAM, &tm);
 307         NVRAM->buffer[addr] = val & 0x40;
 308         break;
 309     case 0x1FFD:
 310     case 0x07FD:
 311         /* date */
 312         tmp = from_bcd(val & 0x1F);
 313         if (tmp != 0) {
 314             get_time(NVRAM, &tm);
 315             tm.tm_mday = tmp;
 316             set_time(NVRAM, &tm);
 317         }
 318         break;
 319     case 0x1FFE:
 320     case 0x07FE:
 321         /* month */
 322         tmp = from_bcd(val & 0x1F);
 323         if (tmp >= 1 && tmp <= 12) {
 324             get_time(NVRAM, &tm);
 325             tm.tm_mon = tmp - 1;
 326             set_time(NVRAM, &tm);
 327         }
 328         break;
 329     case 0x1FFF:
 330     case 0x07FF:
 331         /* year */
 332         tmp = from_bcd(val);
 333         if (tmp >= 0 && tmp <= 99) {
 334             get_time(NVRAM, &tm);
 335             if (NVRAM->type == 8)
 336                 tm.tm_year = from_bcd(val) + 68; // Base year is 1968
 337             else
 338                 tm.tm_year = from_bcd(val);
 339             set_time(NVRAM, &tm);
 340         }
 341         break;
 342     default:
 343         /* Check lock registers state */
 344         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 345             break;
 346         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 347             break;
 348     do_write:
 349         if (addr < NVRAM->size) {
 350             NVRAM->buffer[addr] = val & 0xFF;
 351         }
 352         break;
 353     }
 354 }
 355
 356 uint32_t m48t59_read (void *opaque, uint32_t addr)
 357 {
 358     M48t59State *NVRAM = opaque;
 359     struct tm tm;
 360     uint32_t retval = 0xFF;
 361
 362     /* check for NVRAM access */
 363     if ((NVRAM->type == 2 && addr < 0x078f) ||
 364         (NVRAM->type == 8 && addr < 0x1ff8) ||
 365         (NVRAM->type == 59 && addr < 0x1ff0))
 366         goto do_read;
 367
 368     /* TOD access */
 369     switch (addr) {
 370     case 0x1FF0:
 371         /* flags register */
 372         goto do_read;
 373     case 0x1FF1:
 374         /* unused */
 375         retval = 0;
 376         break;
 377     case 0x1FF2:
 378         /* alarm seconds */
 379         goto do_read;
 380     case 0x1FF3:
 381         /* alarm minutes */
 382         goto do_read;
 383     case 0x1FF4:
 384         /* alarm hours */
 385         goto do_read;
 386     case 0x1FF5:
 387         /* alarm date */
 388         goto do_read;
 389     case 0x1FF6:
 390         /* interrupts */
 391         goto do_read;
 392     case 0x1FF7:
 393         /* A read resets the watchdog */
 394         set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
 395         goto do_read;
 396     case 0x1FF8:
 397     case 0x07F8:
 398         /* control */
 399         goto do_read;
 400     case 0x1FF9:
 401     case 0x07F9:
 402         /* seconds (BCD) */
 403         get_time(NVRAM, &tm);
 404         retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
 405         break;
 406     case 0x1FFA:
 407     case 0x07FA:
 408         /* minutes (BCD) */
 409         get_time(NVRAM, &tm);
 410         retval = to_bcd(tm.tm_min);
 411         break;
 412     case 0x1FFB:
 413     case 0x07FB:
 414         /* hours (BCD) */
 415         get_time(NVRAM, &tm);
 416         retval = to_bcd(tm.tm_hour);
 417         break;
 418     case 0x1FFC:
 419     case 0x07FC:
 420         /* day of the week / century */
 421         get_time(NVRAM, &tm);
 422         retval = NVRAM->buffer[addr] | tm.tm_wday;
 423         break;
 424     case 0x1FFD:
 425     case 0x07FD:
 426         /* date */
 427         get_time(NVRAM, &tm);
 428         retval = to_bcd(tm.tm_mday);
 429         break;
 430     case 0x1FFE:
 431     case 0x07FE:
 432         /* month */
 433         get_time(NVRAM, &tm);
 434         retval = to_bcd(tm.tm_mon + 1);
 435         break;
 436     case 0x1FFF:
 437     case 0x07FF:
 438         /* year */
 439         get_time(NVRAM, &tm);
 440         if (NVRAM->type == 8)
 441             retval = to_bcd(tm.tm_year - 68); // Base year is 1968
 442         else
 443             retval = to_bcd(tm.tm_year);
 444         break;
 445     default:
 446         /* Check lock registers state */
 447         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 448             break;
 449         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 450             break;
 451     do_read:
 452         if (addr < NVRAM->size) {
 453             retval = NVRAM->buffer[addr];
 454         }
 455         break;
 456     }
 457     if (addr > 0x1FF9 && addr < 0x2000)
 458        NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 459
 460     return retval;
 461 }
 462
 463 void m48t59_set_addr (void *opaque, uint32_t addr)
 464 {
 465     M48t59State *NVRAM = opaque;
 466
 467     NVRAM->addr = addr;
 468 }
 469
 470 void m48t59_toggle_lock (void *opaque, int lock)
 471 {
 472     M48t59State *NVRAM = opaque;
 473
 474     NVRAM->lock ^= 1 << lock;
 475 }
 476
 477 /* IO access to NVRAM */
 478 static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
 479 {
 480     M48t59State *NVRAM = opaque;
 481
 482     addr -= NVRAM->io_base;
 483     NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 484     switch (addr) {
 485     case 0:
 486         NVRAM->addr &= ~0x00FF;
 487         NVRAM->addr |= val;
 488         break;
 489     case 1:
 490         NVRAM->addr &= ~0xFF00;
 491         NVRAM->addr |= val << 8;
 492         break;
 493     case 3:
 494         m48t59_write(NVRAM, val, NVRAM->addr);
 495         NVRAM->addr = 0x0000;
 496         break;
 497     default:
 498         break;
 499     }
 500 }
 501
 502 static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
 503 {
 504     M48t59State *NVRAM = opaque;
 505     uint32_t retval;
 506
 507     addr -= NVRAM->io_base;
 508     switch (addr) {
 509     case 3:
 510         retval = m48t59_read(NVRAM, NVRAM->addr);
 511         break;
 512     default:
 513         retval = -1;
 514         break;
 515     }
 516     NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 517
 518     return retval;
 519 }
 520
 521 static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
 522 {
 523     M48t59State *NVRAM = opaque;
 524
 525     m48t59_write(NVRAM, addr, value & 0xff);
 526 }
 527
 528 static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
 529 {
 530     M48t59State *NVRAM = opaque;
 531
 532     m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
 533     m48t59_write(NVRAM, addr + 1, value & 0xff);
 534 }
 535
 536 static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
 537 {
 538     M48t59State *NVRAM = opaque;
 539
 540     m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
 541     m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
 542     m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
 543     m48t59_write(NVRAM, addr + 3, value & 0xff);
 544 }
 545
 546 static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
 547 {
 548     M48t59State *NVRAM = opaque;
 549     uint32_t retval;
 550
 551     retval = m48t59_read(NVRAM, addr);
 552     return retval;
 553 }
 554
 555 static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
 556 {
 557     M48t59State *NVRAM = opaque;
 558     uint32_t retval;
 559
 560     retval = m48t59_read(NVRAM, addr) << 8;
 561     retval |= m48t59_read(NVRAM, addr + 1);
 562     return retval;
 563 }
 564
 565 static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
 566 {
 567     M48t59State *NVRAM = opaque;
 568     uint32_t retval;
 569
 570     retval = m48t59_read(NVRAM, addr) << 24;
 571     retval |= m48t59_read(NVRAM, addr + 1) << 16;
 572     retval |= m48t59_read(NVRAM, addr + 2) << 8;
 573     retval |= m48t59_read(NVRAM, addr + 3);
 574     return retval;
 575 }
 576
 577 static CPUWriteMemoryFunc * const nvram_write[] = {
 578     &nvram_writeb,
 579     &nvram_writew,
 580     &nvram_writel,
 581 };
 582
 583 static CPUReadMemoryFunc * const nvram_read[] = {
 584     &nvram_readb,
 585     &nvram_readw,
 586     &nvram_readl,
 587 };
 588
 589 static const VMStateDescription vmstate_m48t59 = {
 590     .name = "m48t59",
 591     .version_id = 1,
 592     .minimum_version_id = 1,
 593     .minimum_version_id_old = 1,
 594     .fields      = (VMStateField[]) {
 595         VMSTATE_UINT8(lock, M48t59State),
 596         VMSTATE_UINT16(addr, M48t59State),
 597         VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
 598         VMSTATE_END_OF_LIST()
 599     }
 600 };
 601
 602 static void m48t59_reset_common(M48t59State *NVRAM)
 603 {
 604     NVRAM->addr = 0;
 605     NVRAM->lock = 0;
 606     if (NVRAM->alrm_timer != NULL)
 607         qemu_del_timer(NVRAM->alrm_timer);
 608
 609     if (NVRAM->wd_timer != NULL)
 610         qemu_del_timer(NVRAM->wd_timer);
 611 }
 612
 613 static void m48t59_reset_isa(DeviceState *d)
 614 {
 615     M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev);
 616     M48t59State *NVRAM = &isa->state;
 617
 618     m48t59_reset_common(NVRAM);
 619 }
 620
 621 static void m48t59_reset_sysbus(DeviceState *d)
 622 {
 623     M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);
 624     M48t59State *NVRAM = &sys->state;
 625
 626     m48t59_reset_common(NVRAM);
 627 }
 628
 629 /* Initialisation routine */
 630 M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
 631                          uint32_t io_base, uint16_t size, int type)
 632 {
 633     DeviceState *dev;
 634     SysBusDevice *s;
 635     M48t59SysBusState *d;
 636     M48t59State *state;
 637
 638     dev = qdev_create(NULL, "m48t59");
 639     qdev_prop_set_uint32(dev, "type", type);
 640     qdev_prop_set_uint32(dev, "size", size);
 641     qdev_prop_set_uint32(dev, "io_base", io_base);
 642     qdev_init_nofail(dev);
 643     s = sysbus_from_qdev(dev);
 644     d = FROM_SYSBUS(M48t59SysBusState, s);
 645     state = &d->state;
 646     sysbus_connect_irq(s, 0, IRQ);
 647     if (io_base != 0) {
 648         register_ioport_read(io_base, 0x04, 1, NVRAM_readb, state);
 649         register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, state);
 650     }
 651     if (mem_base != 0) {
 652         sysbus_mmio_map(s, 0, mem_base);
 653     }
 654
 655     return state;
 656 }
 657
 658 M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
 659 {
 660     M48t59ISAState *d;
 661     ISADevice *dev;
 662     M48t59State *s;
 663
 664     dev = isa_create("m48t59_isa");
 665     qdev_prop_set_uint32(&dev->qdev, "type", type);
 666     qdev_prop_set_uint32(&dev->qdev, "size", size);
 667     qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
 668     qdev_init_nofail(&dev->qdev);
 669     d = DO_UPCAST(M48t59ISAState, busdev, dev);
 670     s = &d->state;
 671
 672     if (io_base != 0) {
 673         register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
 674         register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
 675         isa_init_ioport_range(dev, io_base, 4);
 676     }
 677
 678     return s;
 679 }
 680
 681 static void m48t59_init_common(M48t59State *s)
 682 {
 683     s->buffer = g_malloc0(s->size);
 684     if (s->type == 59) {
 685         s->alrm_timer = qemu_new_timer_ns(vm_clock, &alarm_cb, s);
 686         s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s);
 687     }
 688     qemu_get_timedate(&s->alarm, 0);
 689
 690     vmstate_register(NULL, -1, &vmstate_m48t59, s);
 691 }
 692
 693 static int m48t59_init_isa1(ISADevice *dev)
 694 {
 695     M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
 696     M48t59State *s = &d->state;
 697
 698     isa_init_irq(dev, &s->IRQ, 8);
 699     m48t59_init_common(s);
 700
 701     return 0;
 702 }
 703
 704 static int m48t59_init1(SysBusDevice *dev)
 705 {
 706     M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
 707     M48t59State *s = &d->state;
 708     int mem_index;
 709
 710     sysbus_init_irq(dev, &s->IRQ);
 711
 712     mem_index = cpu_register_io_memory(nvram_read, nvram_write, s,
 713                                        DEVICE_NATIVE_ENDIAN);
 714     sysbus_init_mmio(dev, s->size, mem_index);
 715     m48t59_init_common(s);
 716
 717     return 0;
 718 }
 719
 720 static ISADeviceInfo m48t59_isa_info = {
 721     .init = m48t59_init_isa1,
 722     .qdev.name = "m48t59_isa",
 723     .qdev.size = sizeof(M48t59ISAState),
 724     .qdev.reset = m48t59_reset_isa,
 725     .qdev.no_user = 1,
 726     .qdev.props = (Property[]) {
 727         DEFINE_PROP_UINT32("size",    M48t59ISAState, state.size,    -1),
 728         DEFINE_PROP_UINT32("type",    M48t59ISAState, state.type,    -1),
 729         DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base,  0),
 730         DEFINE_PROP_END_OF_LIST(),
 731     }
 732 };
 733
 734 static SysBusDeviceInfo m48t59_info = {
 735     .init = m48t59_init1,
 736     .qdev.name  = "m48t59",
 737     .qdev.size = sizeof(M48t59SysBusState),
 738     .qdev.reset = m48t59_reset_sysbus,
 739     .qdev.props = (Property[]) {
 740         DEFINE_PROP_UINT32("size",    M48t59SysBusState, state.size,    -1),
 741         DEFINE_PROP_UINT32("type",    M48t59SysBusState, state.type,    -1),
 742         DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base,  0),
 743         DEFINE_PROP_END_OF_LIST(),
 744     }
 745 };
 746
 747 static void m48t59_register_devices(void)
 748 {
 749     sysbus_register_withprop(&m48t59_info);
 750     isa_qdev_register(&m48t59_isa_info);
 751 }
 752
 753 device_init(m48t59_register_devices)