hw/ioh3420.c

   1 /*
   2  * ioh3420.c
   3  * Intel X58 north bridge IOH
   4  * PCI Express root port device id 3420
   5  *
   6  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   7  *                    VA Linux Systems Japan K.K.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "pci_ids.h"
  24 #include "msi.h"
  25 #include "pcie.h"
  26 #include "ioh3420.h"
  27
  28 #define PCI_DEVICE_ID_IOH_EPORT         0x3420  /* D0:F0 express mode */
  29 #define PCI_DEVICE_ID_IOH_REV           0x2
  30 #define IOH_EP_SSVID_OFFSET             0x40
  31 #define IOH_EP_SSVID_SVID               PCI_VENDOR_ID_INTEL
  32 #define IOH_EP_SSVID_SSID               0
  33 #define IOH_EP_MSI_OFFSET               0x60
  34 #define IOH_EP_MSI_SUPPORTED_FLAGS      PCI_MSI_FLAGS_MASKBIT
  35 #define IOH_EP_MSI_NR_VECTOR            2
  36 #define IOH_EP_EXP_OFFSET               0x90
  37 #define IOH_EP_AER_OFFSET               0x100
  38
  39 /*
  40  * If two MSI vector are allocated, Advanced Error Interrupt Message Number
  41  * is 1. otherwise 0.
  42  * 17.12.5.10 RPERRSTS,  32:27 bit Advanced Error Interrupt Message Number.
  43  */
  44 static uint8_t ioh3420_aer_vector(const PCIDevice *d)
  45 {
  46     switch (msi_nr_vectors_allocated(d)) {
  47     case 1:
  48         return 0;
  49     case 2:
  50         return 1;
  51     case 4:
  52     case 8:
  53     case 16:
  54     case 32:
  55     default:
  56         break;
  57     }
  58     abort();
  59     return 0;
  60 }
  61
  62 static void ioh3420_aer_vector_update(PCIDevice *d)
  63 {
  64     pcie_aer_root_set_vector(d, ioh3420_aer_vector(d));
  65 }
  66
  67 static void ioh3420_write_config(PCIDevice *d,
  68                                    uint32_t address, uint32_t val, int len)
  69 {
  70     uint32_t root_cmd =
  71         pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
  72
  73     pci_bridge_write_config(d, address, val, len);
  74     msi_write_config(d, address, val, len);
  75     ioh3420_aer_vector_update(d);
  76     pcie_cap_slot_write_config(d, address, val, len);
  77     pcie_aer_write_config(d, address, val, len);
  78     pcie_aer_root_write_config(d, address, val, len, root_cmd);
  79 }
  80
  81 static void ioh3420_reset(DeviceState *qdev)
  82 {
  83     PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
  84     msi_reset(d);
  85     ioh3420_aer_vector_update(d);
  86     pcie_cap_root_reset(d);
  87     pcie_cap_deverr_reset(d);
  88     pcie_cap_slot_reset(d);
  89     pcie_aer_root_reset(d);
  90     pci_bridge_reset(qdev);
  91     pci_bridge_disable_base_limit(d);
  92 }
  93
  94 static int ioh3420_initfn(PCIDevice *d)
  95 {
  96     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
  97     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
  98     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
  99     int rc;
 100     int tmp;
 101
 102     rc = pci_bridge_initfn(d);
 103     if (rc < 0) {
 104         return rc;
 105     }
 106
 107     pcie_port_init_reg(d);
 108
 109     rc = pci_bridge_ssvid_init(d, IOH_EP_SSVID_OFFSET,
 110                                IOH_EP_SSVID_SVID, IOH_EP_SSVID_SSID);
 111     if (rc < 0) {
 112         goto err_bridge;
 113     }
 114     rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR,
 115                   IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
 116                   IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
 117     if (rc < 0) {
 118         goto err_bridge;
 119     }
 120     rc = pcie_cap_init(d, IOH_EP_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, p->port);
 121     if (rc < 0) {
 122         goto err_msi;
 123     }
 124     pcie_cap_deverr_init(d);
 125     pcie_cap_slot_init(d, s->slot);
 126     pcie_chassis_create(s->chassis);
 127     rc = pcie_chassis_add_slot(s);
 128     if (rc < 0) {
 129         goto err_pcie_cap;
 130         return rc;
 131     }
 132     pcie_cap_root_init(d);
 133     rc = pcie_aer_init(d, IOH_EP_AER_OFFSET);
 134     if (rc < 0) {
 135         goto err;
 136     }
 137     pcie_aer_root_init(d);
 138     ioh3420_aer_vector_update(d);
 139     return 0;
 140
 141 err:
 142     pcie_chassis_del_slot(s);
 143 err_pcie_cap:
 144     pcie_cap_exit(d);
 145 err_msi:
 146     msi_uninit(d);
 147 err_bridge:
 148     tmp = pci_bridge_exitfn(d);
 149     assert(!tmp);
 150     return rc;
 151 }
 152
 153 static int ioh3420_exitfn(PCIDevice *d)
 154 {
 155     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
 156     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
 157     PCIESlot *s = DO_UPCAST(PCIESlot, port, p);
 158
 159     pcie_aer_exit(d);
 160     pcie_chassis_del_slot(s);
 161     pcie_cap_exit(d);
 162     msi_uninit(d);
 163     return pci_bridge_exitfn(d);
 164 }
 165
 166 PCIESlot *ioh3420_init(PCIBus *bus, int devfn, bool multifunction,
 167                          const char *bus_name, pci_map_irq_fn map_irq,
 168                          uint8_t port, uint8_t chassis, uint16_t slot)
 169 {
 170     PCIDevice *d;
 171     PCIBridge *br;
 172     DeviceState *qdev;
 173
 174     d = pci_create_multifunction(bus, devfn, multifunction, "ioh3420");
 175     if (!d) {
 176         return NULL;
 177     }
 178     br = DO_UPCAST(PCIBridge, dev, d);
 179
 180     qdev = &br->dev.qdev;
 181     pci_bridge_map_irq(br, bus_name, map_irq);
 182     qdev_prop_set_uint8(qdev, "port", port);
 183     qdev_prop_set_uint8(qdev, "chassis", chassis);
 184     qdev_prop_set_uint16(qdev, "slot", slot);
 185     qdev_init_nofail(qdev);
 186
 187     return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br));
 188 }
 189
 190 static const VMStateDescription vmstate_ioh3420 = {
 191     .name = "ioh-3240-express-root-port",
 192     .version_id = 1,
 193     .minimum_version_id = 1,
 194     .minimum_version_id_old = 1,
 195     .post_load = pcie_cap_slot_post_load,
 196     .fields = (VMStateField[]) {
 197         VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
 198         VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
 199                        vmstate_pcie_aer_log, PCIEAERLog),
 200         VMSTATE_END_OF_LIST()
 201     }
 202 };
 203
 204 static PCIDeviceInfo ioh3420_info = {
 205     .qdev.name = "ioh3420",
 206     .qdev.desc = "Intel IOH device id 3420 PCIE Root Port",
 207     .qdev.size = sizeof(PCIESlot),
 208     .qdev.reset = ioh3420_reset,
 209     .qdev.vmsd = &vmstate_ioh3420,
 210
 211     .is_express = 1,
 212     .is_bridge = 1,
 213     .config_write = ioh3420_write_config,
 214     .init = ioh3420_initfn,
 215     .exit = ioh3420_exitfn,
 216     .vendor_id = PCI_VENDOR_ID_INTEL,
 217     .device_id = PCI_DEVICE_ID_IOH_EPORT,
 218     .revision = PCI_DEVICE_ID_IOH_REV,
 219
 220     .qdev.props = (Property[]) {
 221         DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
 222         DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
 223         DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
 224         DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
 225                            port.br.dev.exp.aer_log.log_max,
 226                            PCIE_AER_LOG_MAX_DEFAULT),
 227         DEFINE_PROP_END_OF_LIST(),
 228     }
 229 };
 230
 231 static void ioh3420_register(void)
 232 {
 233     pci_qdev_register(&ioh3420_info);
 234 }
 235
 236 device_init(ioh3420_register);
 237
 238 /*
 239  * Local variables:
 240  *  c-indent-level: 4
 241  *  c-basic-offset: 4
 242  *  tab-width: 8
 243  *  indent-tab-mode: nil
 244  * End:
 245  */