hw/char/sifive_uart.c

   1 /*
   2  * QEMU model of the UART on the SiFive E300 and U500 series SOCs.
   3  *
   4  * Copyright (c) 2016 Stefan O'Rear
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include "qemu/osdep.h"
  20 #include "qapi/error.h"
  21 #include "qemu/log.h"
  22 #include "hw/sysbus.h"
  23 #include "chardev/char.h"
  24 #include "chardev/char-fe.h"
  25 #include "hw/irq.h"
  26 #include "hw/char/sifive_uart.h"
  27
  28 /*
  29  * Not yet implemented:
  30  *
  31  * Transmit FIFO using "qemu/fifo8.h"
  32  */
  33
  34 /* Returns the state of the IP (interrupt pending) register */
  35 static uint64_t uart_ip(SiFiveUARTState *s)
  36 {
  37     uint64_t ret = 0;
  38
  39     uint64_t txcnt = SIFIVE_UART_GET_TXCNT(s->txctrl);
  40     uint64_t rxcnt = SIFIVE_UART_GET_RXCNT(s->rxctrl);
  41
  42     if (txcnt != 0) {
  43         ret |= SIFIVE_UART_IP_TXWM;
  44     }
  45     if (s->rx_fifo_len > rxcnt) {
  46         ret |= SIFIVE_UART_IP_RXWM;
  47     }
  48
  49     return ret;
  50 }
  51
  52 static void update_irq(SiFiveUARTState *s)
  53 {
  54     int cond = 0;
  55     if ((s->ie & SIFIVE_UART_IE_TXWM) ||
  56         ((s->ie & SIFIVE_UART_IE_RXWM) && s->rx_fifo_len)) {
  57         cond = 1;
  58     }
  59     if (cond) {
  60         qemu_irq_raise(s->irq);
  61     } else {
  62         qemu_irq_lower(s->irq);
  63     }
  64 }
  65
  66 static uint64_t
  67 uart_read(void *opaque, hwaddr addr, unsigned int size)
  68 {
  69     SiFiveUARTState *s = opaque;
  70     unsigned char r;
  71     switch (addr) {
  72     case SIFIVE_UART_RXFIFO:
  73         if (s->rx_fifo_len) {
  74             r = s->rx_fifo[0];
  75             memmove(s->rx_fifo, s->rx_fifo + 1, s->rx_fifo_len - 1);
  76             s->rx_fifo_len--;
  77             qemu_chr_fe_accept_input(&s->chr);
  78             update_irq(s);
  79             return r;
  80         }
  81         return 0x80000000;
  82
  83     case SIFIVE_UART_TXFIFO:
  84         return 0; /* Should check tx fifo */
  85     case SIFIVE_UART_IE:
  86         return s->ie;
  87     case SIFIVE_UART_IP:
  88         return uart_ip(s);
  89     case SIFIVE_UART_TXCTRL:
  90         return s->txctrl;
  91     case SIFIVE_UART_RXCTRL:
  92         return s->rxctrl;
  93     case SIFIVE_UART_DIV:
  94         return s->div;
  95     }
  96
  97     qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n",
  98                   __func__, (int)addr);
  99     return 0;
 100 }
 101
 102 static void
 103 uart_write(void *opaque, hwaddr addr,
 104            uint64_t val64, unsigned int size)
 105 {
 106     SiFiveUARTState *s = opaque;
 107     uint32_t value = val64;
 108     unsigned char ch = value;
 109
 110     switch (addr) {
 111     case SIFIVE_UART_TXFIFO:
 112         qemu_chr_fe_write(&s->chr, &ch, 1);
 113         update_irq(s);
 114         return;
 115     case SIFIVE_UART_IE:
 116         s->ie = val64;
 117         update_irq(s);
 118         return;
 119     case SIFIVE_UART_TXCTRL:
 120         s->txctrl = val64;
 121         return;
 122     case SIFIVE_UART_RXCTRL:
 123         s->rxctrl = val64;
 124         return;
 125     case SIFIVE_UART_DIV:
 126         s->div = val64;
 127         return;
 128     }
 129     qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
 130                   __func__, (int)addr, (int)value);
 131 }
 132
 133 static const MemoryRegionOps uart_ops = {
 134     .read = uart_read,
 135     .write = uart_write,
 136     .endianness = DEVICE_NATIVE_ENDIAN,
 137     .valid = {
 138         .min_access_size = 4,
 139         .max_access_size = 4
 140     }
 141 };
 142
 143 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 144 {
 145     SiFiveUARTState *s = opaque;
 146
 147     /* Got a byte.  */
 148     if (s->rx_fifo_len >= sizeof(s->rx_fifo)) {
 149         printf("WARNING: UART dropped char.\n");
 150         return;
 151     }
 152     s->rx_fifo[s->rx_fifo_len++] = *buf;
 153
 154     update_irq(s);
 155 }
 156
 157 static int uart_can_rx(void *opaque)
 158 {
 159     SiFiveUARTState *s = opaque;
 160
 161     return s->rx_fifo_len < sizeof(s->rx_fifo);
 162 }
 163
 164 static void uart_event(void *opaque, QEMUChrEvent event)
 165 {
 166 }
 167
 168 static int uart_be_change(void *opaque)
 169 {
 170     SiFiveUARTState *s = opaque;
 171
 172     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
 173         uart_be_change, s, NULL, true);
 174
 175     return 0;
 176 }
 177
 178 /*
 179  * Create UART device.
 180  */
 181 SiFiveUARTState *sifive_uart_create(MemoryRegion *address_space, hwaddr base,
 182     Chardev *chr, qemu_irq irq)
 183 {
 184     SiFiveUARTState *s = g_malloc0(sizeof(SiFiveUARTState));
 185     s->irq = irq;
 186     qemu_chr_fe_init(&s->chr, chr, &error_abort);
 187     qemu_chr_fe_set_handlers(&s->chr, uart_can_rx, uart_rx, uart_event,
 188         uart_be_change, s, NULL, true);
 189     memory_region_init_io(&s->mmio, NULL, &uart_ops, s,
 190                           TYPE_SIFIVE_UART, SIFIVE_UART_MAX);
 191     memory_region_add_subregion(address_space, base, &s->mmio);
 192     return s;
 193 }