2 * StrongARM SA-1100/SA-1110 emulation
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Contributions after 2012-01-13 are licensed under the terms of the
27 * GNU GPL, version 2 or (at your option) any later version.
29 #include "hw/sysbus.h"
30 #include "strongarm.h"
31 #include "qemu/error-report.h"
32 #include "hw/arm/arm.h"
33 #include "sysemu/char.h"
34 #include "sysemu/sysemu.h"
41 - Implement cp15, c14 ?
42 - Implement cp15, c15 !!! (idle used in L)
43 - Implement idle mode handling/DIM
44 - Implement sleep mode/Wake sources
45 - Implement reset control
46 - Implement memory control regs
48 - Maybe support MBGNT/MBREQ
53 - Enhance UART with modem signals
57 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
59 # define DPRINTF(format, ...) do { } while (0)
66 { 0x80010000, SA_PIC_UART1
},
67 { 0x80030000, SA_PIC_UART2
},
68 { 0x80050000, SA_PIC_UART3
},
72 /* Interrupt Controller */
74 #define TYPE_STRONGARM_PIC "strongarm_pic"
75 #define STRONGARM_PIC(obj) \
76 OBJECT_CHECK(StrongARMPICState, (obj), TYPE_STRONGARM_PIC)
78 typedef struct StrongARMPICState
{
79 SysBusDevice parent_obj
;
98 #define SA_PIC_SRCS 32
101 static void strongarm_pic_update(void *opaque
)
103 StrongARMPICState
*s
= opaque
;
105 /* FIXME: reflect DIM */
106 qemu_set_irq(s
->fiq
, s
->pending
& s
->enabled
& s
->is_fiq
);
107 qemu_set_irq(s
->irq
, s
->pending
& s
->enabled
& ~s
->is_fiq
);
110 static void strongarm_pic_set_irq(void *opaque
, int irq
, int level
)
112 StrongARMPICState
*s
= opaque
;
115 s
->pending
|= 1 << irq
;
117 s
->pending
&= ~(1 << irq
);
120 strongarm_pic_update(s
);
123 static uint64_t strongarm_pic_mem_read(void *opaque
, hwaddr offset
,
126 StrongARMPICState
*s
= opaque
;
130 return s
->pending
& ~s
->is_fiq
& s
->enabled
;
136 return s
->int_idle
== 0;
138 return s
->pending
& s
->is_fiq
& s
->enabled
;
142 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
148 static void strongarm_pic_mem_write(void *opaque
, hwaddr offset
,
149 uint64_t value
, unsigned size
)
151 StrongARMPICState
*s
= opaque
;
161 s
->int_idle
= (value
& 1) ? 0 : ~0;
164 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
168 strongarm_pic_update(s
);
171 static const MemoryRegionOps strongarm_pic_ops
= {
172 .read
= strongarm_pic_mem_read
,
173 .write
= strongarm_pic_mem_write
,
174 .endianness
= DEVICE_NATIVE_ENDIAN
,
177 static int strongarm_pic_initfn(SysBusDevice
*sbd
)
179 DeviceState
*dev
= DEVICE(sbd
);
180 StrongARMPICState
*s
= STRONGARM_PIC(dev
);
182 qdev_init_gpio_in(dev
, strongarm_pic_set_irq
, SA_PIC_SRCS
);
183 memory_region_init_io(&s
->iomem
, OBJECT(s
), &strongarm_pic_ops
, s
,
185 sysbus_init_mmio(sbd
, &s
->iomem
);
186 sysbus_init_irq(sbd
, &s
->irq
);
187 sysbus_init_irq(sbd
, &s
->fiq
);
192 static int strongarm_pic_post_load(void *opaque
, int version_id
)
194 strongarm_pic_update(opaque
);
198 static VMStateDescription vmstate_strongarm_pic_regs
= {
199 .name
= "strongarm_pic",
201 .minimum_version_id
= 0,
202 .post_load
= strongarm_pic_post_load
,
203 .fields
= (VMStateField
[]) {
204 VMSTATE_UINT32(pending
, StrongARMPICState
),
205 VMSTATE_UINT32(enabled
, StrongARMPICState
),
206 VMSTATE_UINT32(is_fiq
, StrongARMPICState
),
207 VMSTATE_UINT32(int_idle
, StrongARMPICState
),
208 VMSTATE_END_OF_LIST(),
212 static void strongarm_pic_class_init(ObjectClass
*klass
, void *data
)
214 DeviceClass
*dc
= DEVICE_CLASS(klass
);
215 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
217 k
->init
= strongarm_pic_initfn
;
218 dc
->desc
= "StrongARM PIC";
219 dc
->vmsd
= &vmstate_strongarm_pic_regs
;
222 static const TypeInfo strongarm_pic_info
= {
223 .name
= TYPE_STRONGARM_PIC
,
224 .parent
= TYPE_SYS_BUS_DEVICE
,
225 .instance_size
= sizeof(StrongARMPICState
),
226 .class_init
= strongarm_pic_class_init
,
229 /* Real-Time Clock */
230 #define RTAR 0x00 /* RTC Alarm register */
231 #define RCNR 0x04 /* RTC Counter register */
232 #define RTTR 0x08 /* RTC Timer Trim register */
233 #define RTSR 0x10 /* RTC Status register */
235 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
236 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
237 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
238 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
240 /* 16 LSB of RTTR are clockdiv for internal trim logic,
241 * trim delete isn't emulated, so
242 * f = 32 768 / (RTTR_trim + 1) */
244 #define TYPE_STRONGARM_RTC "strongarm-rtc"
245 #define STRONGARM_RTC(obj) \
246 OBJECT_CHECK(StrongARMRTCState, (obj), TYPE_STRONGARM_RTC)
248 typedef struct StrongARMRTCState
{
249 SysBusDevice parent_obj
;
257 QEMUTimer
*rtc_alarm
;
263 static inline void strongarm_rtc_int_update(StrongARMRTCState
*s
)
265 qemu_set_irq(s
->rtc_irq
, s
->rtsr
& RTSR_AL
);
266 qemu_set_irq(s
->rtc_hz_irq
, s
->rtsr
& RTSR_HZ
);
269 static void strongarm_rtc_hzupdate(StrongARMRTCState
*s
)
271 int64_t rt
= qemu_clock_get_ms(rtc_clock
);
272 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
273 (1000 * ((s
->rttr
& 0xffff) + 1));
277 static inline void strongarm_rtc_timer_update(StrongARMRTCState
*s
)
279 if ((s
->rtsr
& RTSR_HZE
) && !(s
->rtsr
& RTSR_HZ
)) {
280 timer_mod(s
->rtc_hz
, s
->last_hz
+ 1000);
282 timer_del(s
->rtc_hz
);
285 if ((s
->rtsr
& RTSR_ALE
) && !(s
->rtsr
& RTSR_AL
)) {
286 timer_mod(s
->rtc_alarm
, s
->last_hz
+
287 (((s
->rtar
- s
->last_rcnr
) * 1000 *
288 ((s
->rttr
& 0xffff) + 1)) >> 15));
290 timer_del(s
->rtc_alarm
);
294 static inline void strongarm_rtc_alarm_tick(void *opaque
)
296 StrongARMRTCState
*s
= opaque
;
298 strongarm_rtc_timer_update(s
);
299 strongarm_rtc_int_update(s
);
302 static inline void strongarm_rtc_hz_tick(void *opaque
)
304 StrongARMRTCState
*s
= opaque
;
306 strongarm_rtc_timer_update(s
);
307 strongarm_rtc_int_update(s
);
310 static uint64_t strongarm_rtc_read(void *opaque
, hwaddr addr
,
313 StrongARMRTCState
*s
= opaque
;
323 return s
->last_rcnr
+
324 ((qemu_clock_get_ms(rtc_clock
) - s
->last_hz
) << 15) /
325 (1000 * ((s
->rttr
& 0xffff) + 1));
327 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
332 static void strongarm_rtc_write(void *opaque
, hwaddr addr
,
333 uint64_t value
, unsigned size
)
335 StrongARMRTCState
*s
= opaque
;
340 strongarm_rtc_hzupdate(s
);
342 strongarm_rtc_timer_update(s
);
347 s
->rtsr
= (value
& (RTSR_ALE
| RTSR_HZE
)) |
348 (s
->rtsr
& ~(value
& (RTSR_AL
| RTSR_HZ
)));
350 if (s
->rtsr
!= old_rtsr
) {
351 strongarm_rtc_timer_update(s
);
354 strongarm_rtc_int_update(s
);
359 strongarm_rtc_timer_update(s
);
363 strongarm_rtc_hzupdate(s
);
364 s
->last_rcnr
= value
;
365 strongarm_rtc_timer_update(s
);
369 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
373 static const MemoryRegionOps strongarm_rtc_ops
= {
374 .read
= strongarm_rtc_read
,
375 .write
= strongarm_rtc_write
,
376 .endianness
= DEVICE_NATIVE_ENDIAN
,
379 static int strongarm_rtc_init(SysBusDevice
*dev
)
381 StrongARMRTCState
*s
= STRONGARM_RTC(dev
);
387 qemu_get_timedate(&tm
, 0);
389 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
390 s
->last_hz
= qemu_clock_get_ms(rtc_clock
);
392 s
->rtc_alarm
= timer_new_ms(rtc_clock
, strongarm_rtc_alarm_tick
, s
);
393 s
->rtc_hz
= timer_new_ms(rtc_clock
, strongarm_rtc_hz_tick
, s
);
395 sysbus_init_irq(dev
, &s
->rtc_irq
);
396 sysbus_init_irq(dev
, &s
->rtc_hz_irq
);
398 memory_region_init_io(&s
->iomem
, OBJECT(s
), &strongarm_rtc_ops
, s
,
400 sysbus_init_mmio(dev
, &s
->iomem
);
405 static void strongarm_rtc_pre_save(void *opaque
)
407 StrongARMRTCState
*s
= opaque
;
409 strongarm_rtc_hzupdate(s
);
412 static int strongarm_rtc_post_load(void *opaque
, int version_id
)
414 StrongARMRTCState
*s
= opaque
;
416 strongarm_rtc_timer_update(s
);
417 strongarm_rtc_int_update(s
);
422 static const VMStateDescription vmstate_strongarm_rtc_regs
= {
423 .name
= "strongarm-rtc",
425 .minimum_version_id
= 0,
426 .pre_save
= strongarm_rtc_pre_save
,
427 .post_load
= strongarm_rtc_post_load
,
428 .fields
= (VMStateField
[]) {
429 VMSTATE_UINT32(rttr
, StrongARMRTCState
),
430 VMSTATE_UINT32(rtsr
, StrongARMRTCState
),
431 VMSTATE_UINT32(rtar
, StrongARMRTCState
),
432 VMSTATE_UINT32(last_rcnr
, StrongARMRTCState
),
433 VMSTATE_INT64(last_hz
, StrongARMRTCState
),
434 VMSTATE_END_OF_LIST(),
438 static void strongarm_rtc_sysbus_class_init(ObjectClass
*klass
, void *data
)
440 DeviceClass
*dc
= DEVICE_CLASS(klass
);
441 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
443 k
->init
= strongarm_rtc_init
;
444 dc
->desc
= "StrongARM RTC Controller";
445 dc
->vmsd
= &vmstate_strongarm_rtc_regs
;
448 static const TypeInfo strongarm_rtc_sysbus_info
= {
449 .name
= TYPE_STRONGARM_RTC
,
450 .parent
= TYPE_SYS_BUS_DEVICE
,
451 .instance_size
= sizeof(StrongARMRTCState
),
452 .class_init
= strongarm_rtc_sysbus_class_init
,
465 #define TYPE_STRONGARM_GPIO "strongarm-gpio"
466 #define STRONGARM_GPIO(obj) \
467 OBJECT_CHECK(StrongARMGPIOInfo, (obj), TYPE_STRONGARM_GPIO)
469 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo
;
470 struct StrongARMGPIOInfo
{
473 qemu_irq handler
[28];
489 static void strongarm_gpio_irq_update(StrongARMGPIOInfo
*s
)
492 for (i
= 0; i
< 11; i
++) {
493 qemu_set_irq(s
->irqs
[i
], s
->status
& (1 << i
));
496 qemu_set_irq(s
->irqX
, (s
->status
& ~0x7ff));
499 static void strongarm_gpio_set(void *opaque
, int line
, int level
)
501 StrongARMGPIOInfo
*s
= opaque
;
507 s
->status
|= s
->rising
& mask
&
508 ~s
->ilevel
& ~s
->dir
;
511 s
->status
|= s
->falling
& mask
&
516 if (s
->status
& mask
) {
517 strongarm_gpio_irq_update(s
);
521 static void strongarm_gpio_handler_update(StrongARMGPIOInfo
*s
)
523 uint32_t level
, diff
;
526 level
= s
->olevel
& s
->dir
;
528 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
530 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
533 s
->prev_level
= level
;
536 static uint64_t strongarm_gpio_read(void *opaque
, hwaddr offset
,
539 StrongARMGPIOInfo
*s
= opaque
;
542 case GPDR
: /* GPIO Pin-Direction registers */
545 case GPSR
: /* GPIO Pin-Output Set registers */
546 qemu_log_mask(LOG_GUEST_ERROR
,
547 "strongarm GPIO: read from write only register GPSR\n");
550 case GPCR
: /* GPIO Pin-Output Clear registers */
551 qemu_log_mask(LOG_GUEST_ERROR
,
552 "strongarm GPIO: read from write only register GPCR\n");
555 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
558 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
561 case GAFR
: /* GPIO Alternate Function registers */
564 case GPLR
: /* GPIO Pin-Level registers */
565 return (s
->olevel
& s
->dir
) |
566 (s
->ilevel
& ~s
->dir
);
568 case GEDR
: /* GPIO Edge Detect Status registers */
572 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
578 static void strongarm_gpio_write(void *opaque
, hwaddr offset
,
579 uint64_t value
, unsigned size
)
581 StrongARMGPIOInfo
*s
= opaque
;
584 case GPDR
: /* GPIO Pin-Direction registers */
586 strongarm_gpio_handler_update(s
);
589 case GPSR
: /* GPIO Pin-Output Set registers */
591 strongarm_gpio_handler_update(s
);
594 case GPCR
: /* GPIO Pin-Output Clear registers */
596 strongarm_gpio_handler_update(s
);
599 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
603 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
607 case GAFR
: /* GPIO Alternate Function registers */
611 case GEDR
: /* GPIO Edge Detect Status registers */
613 strongarm_gpio_irq_update(s
);
617 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
621 static const MemoryRegionOps strongarm_gpio_ops
= {
622 .read
= strongarm_gpio_read
,
623 .write
= strongarm_gpio_write
,
624 .endianness
= DEVICE_NATIVE_ENDIAN
,
627 static DeviceState
*strongarm_gpio_init(hwaddr base
,
633 dev
= qdev_create(NULL
, TYPE_STRONGARM_GPIO
);
634 qdev_init_nofail(dev
);
636 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0, base
);
637 for (i
= 0; i
< 12; i
++)
638 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), i
,
639 qdev_get_gpio_in(pic
, SA_PIC_GPIO0_EDGE
+ i
));
644 static int strongarm_gpio_initfn(SysBusDevice
*sbd
)
646 DeviceState
*dev
= DEVICE(sbd
);
647 StrongARMGPIOInfo
*s
= STRONGARM_GPIO(dev
);
650 qdev_init_gpio_in(dev
, strongarm_gpio_set
, 28);
651 qdev_init_gpio_out(dev
, s
->handler
, 28);
653 memory_region_init_io(&s
->iomem
, OBJECT(s
), &strongarm_gpio_ops
, s
,
656 sysbus_init_mmio(sbd
, &s
->iomem
);
657 for (i
= 0; i
< 11; i
++) {
658 sysbus_init_irq(sbd
, &s
->irqs
[i
]);
660 sysbus_init_irq(sbd
, &s
->irqX
);
665 static const VMStateDescription vmstate_strongarm_gpio_regs
= {
666 .name
= "strongarm-gpio",
668 .minimum_version_id
= 0,
669 .fields
= (VMStateField
[]) {
670 VMSTATE_UINT32(ilevel
, StrongARMGPIOInfo
),
671 VMSTATE_UINT32(olevel
, StrongARMGPIOInfo
),
672 VMSTATE_UINT32(dir
, StrongARMGPIOInfo
),
673 VMSTATE_UINT32(rising
, StrongARMGPIOInfo
),
674 VMSTATE_UINT32(falling
, StrongARMGPIOInfo
),
675 VMSTATE_UINT32(status
, StrongARMGPIOInfo
),
676 VMSTATE_UINT32(gafr
, StrongARMGPIOInfo
),
677 VMSTATE_UINT32(prev_level
, StrongARMGPIOInfo
),
678 VMSTATE_END_OF_LIST(),
682 static void strongarm_gpio_class_init(ObjectClass
*klass
, void *data
)
684 DeviceClass
*dc
= DEVICE_CLASS(klass
);
685 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
687 k
->init
= strongarm_gpio_initfn
;
688 dc
->desc
= "StrongARM GPIO controller";
689 dc
->vmsd
= &vmstate_strongarm_gpio_regs
;
692 static const TypeInfo strongarm_gpio_info
= {
693 .name
= TYPE_STRONGARM_GPIO
,
694 .parent
= TYPE_SYS_BUS_DEVICE
,
695 .instance_size
= sizeof(StrongARMGPIOInfo
),
696 .class_init
= strongarm_gpio_class_init
,
699 /* Peripheral Pin Controller */
706 #define TYPE_STRONGARM_PPC "strongarm-ppc"
707 #define STRONGARM_PPC(obj) \
708 OBJECT_CHECK(StrongARMPPCInfo, (obj), TYPE_STRONGARM_PPC)
710 typedef struct StrongARMPPCInfo StrongARMPPCInfo
;
711 struct StrongARMPPCInfo
{
712 SysBusDevice parent_obj
;
715 qemu_irq handler
[28];
727 static void strongarm_ppc_set(void *opaque
, int line
, int level
)
729 StrongARMPPCInfo
*s
= opaque
;
732 s
->ilevel
|= 1 << line
;
734 s
->ilevel
&= ~(1 << line
);
738 static void strongarm_ppc_handler_update(StrongARMPPCInfo
*s
)
740 uint32_t level
, diff
;
743 level
= s
->olevel
& s
->dir
;
745 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
747 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
750 s
->prev_level
= level
;
753 static uint64_t strongarm_ppc_read(void *opaque
, hwaddr offset
,
756 StrongARMPPCInfo
*s
= opaque
;
759 case PPDR
: /* PPC Pin Direction registers */
760 return s
->dir
| ~0x3fffff;
762 case PPSR
: /* PPC Pin State registers */
763 return (s
->olevel
& s
->dir
) |
764 (s
->ilevel
& ~s
->dir
) |
768 return s
->ppar
| ~0x41000;
774 return s
->ppfr
| ~0x7f001;
777 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
783 static void strongarm_ppc_write(void *opaque
, hwaddr offset
,
784 uint64_t value
, unsigned size
)
786 StrongARMPPCInfo
*s
= opaque
;
789 case PPDR
: /* PPC Pin Direction registers */
790 s
->dir
= value
& 0x3fffff;
791 strongarm_ppc_handler_update(s
);
794 case PPSR
: /* PPC Pin State registers */
795 s
->olevel
= value
& s
->dir
& 0x3fffff;
796 strongarm_ppc_handler_update(s
);
800 s
->ppar
= value
& 0x41000;
804 s
->psdr
= value
& 0x3fffff;
808 s
->ppfr
= value
& 0x7f001;
812 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
816 static const MemoryRegionOps strongarm_ppc_ops
= {
817 .read
= strongarm_ppc_read
,
818 .write
= strongarm_ppc_write
,
819 .endianness
= DEVICE_NATIVE_ENDIAN
,
822 static int strongarm_ppc_init(SysBusDevice
*sbd
)
824 DeviceState
*dev
= DEVICE(sbd
);
825 StrongARMPPCInfo
*s
= STRONGARM_PPC(dev
);
827 qdev_init_gpio_in(dev
, strongarm_ppc_set
, 22);
828 qdev_init_gpio_out(dev
, s
->handler
, 22);
830 memory_region_init_io(&s
->iomem
, OBJECT(s
), &strongarm_ppc_ops
, s
,
833 sysbus_init_mmio(sbd
, &s
->iomem
);
838 static const VMStateDescription vmstate_strongarm_ppc_regs
= {
839 .name
= "strongarm-ppc",
841 .minimum_version_id
= 0,
842 .fields
= (VMStateField
[]) {
843 VMSTATE_UINT32(ilevel
, StrongARMPPCInfo
),
844 VMSTATE_UINT32(olevel
, StrongARMPPCInfo
),
845 VMSTATE_UINT32(dir
, StrongARMPPCInfo
),
846 VMSTATE_UINT32(ppar
, StrongARMPPCInfo
),
847 VMSTATE_UINT32(psdr
, StrongARMPPCInfo
),
848 VMSTATE_UINT32(ppfr
, StrongARMPPCInfo
),
849 VMSTATE_UINT32(prev_level
, StrongARMPPCInfo
),
850 VMSTATE_END_OF_LIST(),
854 static void strongarm_ppc_class_init(ObjectClass
*klass
, void *data
)
856 DeviceClass
*dc
= DEVICE_CLASS(klass
);
857 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
859 k
->init
= strongarm_ppc_init
;
860 dc
->desc
= "StrongARM PPC controller";
861 dc
->vmsd
= &vmstate_strongarm_ppc_regs
;
864 static const TypeInfo strongarm_ppc_info
= {
865 .name
= TYPE_STRONGARM_PPC
,
866 .parent
= TYPE_SYS_BUS_DEVICE
,
867 .instance_size
= sizeof(StrongARMPPCInfo
),
868 .class_init
= strongarm_ppc_class_init
,
880 #define UTCR0_PE (1 << 0) /* Parity enable */
881 #define UTCR0_OES (1 << 1) /* Even parity */
882 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
883 #define UTCR0_DSS (1 << 3) /* 8-bit data */
885 #define UTCR3_RXE (1 << 0) /* Rx enable */
886 #define UTCR3_TXE (1 << 1) /* Tx enable */
887 #define UTCR3_BRK (1 << 2) /* Force Break */
888 #define UTCR3_RIE (1 << 3) /* Rx int enable */
889 #define UTCR3_TIE (1 << 4) /* Tx int enable */
890 #define UTCR3_LBM (1 << 5) /* Loopback */
892 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
893 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
894 #define UTSR0_RID (1 << 2) /* Receiver Idle */
895 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
896 #define UTSR0_REB (1 << 4) /* Receiver end break */
897 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
899 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
900 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
901 #define UTSR1_PRE (1 << 3) /* Parity error */
902 #define UTSR1_FRE (1 << 4) /* Frame error */
903 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
905 #define RX_FIFO_PRE (1 << 8)
906 #define RX_FIFO_FRE (1 << 9)
907 #define RX_FIFO_ROR (1 << 10)
909 #define TYPE_STRONGARM_UART "strongarm-uart"
910 #define STRONGARM_UART(obj) \
911 OBJECT_CHECK(StrongARMUARTState, (obj), TYPE_STRONGARM_UART)
913 typedef struct StrongARMUARTState
{
914 SysBusDevice parent_obj
;
917 CharDriverState
*chr
;
929 uint16_t rx_fifo
[12]; /* value + error flags in high bits */
933 uint64_t char_transmit_time
; /* time to transmit a char in ticks*/
935 QEMUTimer
*rx_timeout_timer
;
937 } StrongARMUARTState
;
939 static void strongarm_uart_update_status(StrongARMUARTState
*s
)
943 if (s
->tx_len
!= 8) {
947 if (s
->rx_len
!= 0) {
948 uint16_t ent
= s
->rx_fifo
[s
->rx_start
];
951 if (ent
& RX_FIFO_PRE
) {
952 s
->utsr1
|= UTSR1_PRE
;
954 if (ent
& RX_FIFO_FRE
) {
955 s
->utsr1
|= UTSR1_FRE
;
957 if (ent
& RX_FIFO_ROR
) {
958 s
->utsr1
|= UTSR1_ROR
;
965 static void strongarm_uart_update_int_status(StrongARMUARTState
*s
)
967 uint16_t utsr0
= s
->utsr0
&
968 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
);
971 if ((s
->utcr3
& UTCR3_TXE
) &&
972 (s
->utcr3
& UTCR3_TIE
) &&
977 if ((s
->utcr3
& UTCR3_RXE
) &&
978 (s
->utcr3
& UTCR3_RIE
) &&
983 for (i
= 0; i
< s
->rx_len
&& i
< 4; i
++)
984 if (s
->rx_fifo
[(s
->rx_start
+ i
) % 12] & ~0xff) {
990 qemu_set_irq(s
->irq
, utsr0
);
993 static void strongarm_uart_update_parameters(StrongARMUARTState
*s
)
995 int speed
, parity
, data_bits
, stop_bits
, frame_size
;
996 QEMUSerialSetParams ssp
;
1000 if (s
->utcr0
& UTCR0_PE
) {
1003 if (s
->utcr0
& UTCR0_OES
) {
1011 if (s
->utcr0
& UTCR0_SBS
) {
1017 data_bits
= (s
->utcr0
& UTCR0_DSS
) ? 8 : 7;
1018 frame_size
+= data_bits
+ stop_bits
;
1019 speed
= 3686400 / 16 / (s
->brd
+ 1);
1021 ssp
.parity
= parity
;
1022 ssp
.data_bits
= data_bits
;
1023 ssp
.stop_bits
= stop_bits
;
1024 s
->char_transmit_time
= (get_ticks_per_sec() / speed
) * frame_size
;
1026 qemu_chr_fe_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
1029 DPRINTF(stderr
, "%s speed=%d parity=%c data=%d stop=%d\n", s
->chr
->label
,
1030 speed
, parity
, data_bits
, stop_bits
);
1033 static void strongarm_uart_rx_to(void *opaque
)
1035 StrongARMUARTState
*s
= opaque
;
1038 s
->utsr0
|= UTSR0_RID
;
1039 strongarm_uart_update_int_status(s
);
1043 static void strongarm_uart_rx_push(StrongARMUARTState
*s
, uint16_t c
)
1045 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1050 if (s
->wait_break_end
) {
1051 s
->utsr0
|= UTSR0_REB
;
1052 s
->wait_break_end
= false;
1055 if (s
->rx_len
< 12) {
1056 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
) % 12] = c
;
1059 s
->rx_fifo
[(s
->rx_start
+ 11) % 12] |= RX_FIFO_ROR
;
1062 static int strongarm_uart_can_receive(void *opaque
)
1064 StrongARMUARTState
*s
= opaque
;
1066 if (s
->rx_len
== 12) {
1069 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1070 if (s
->rx_len
< 8) {
1071 return 8 - s
->rx_len
;
1076 static void strongarm_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
1078 StrongARMUARTState
*s
= opaque
;
1081 for (i
= 0; i
< size
; i
++) {
1082 strongarm_uart_rx_push(s
, buf
[i
]);
1085 /* call the timeout receive callback in 3 char transmit time */
1086 timer_mod(s
->rx_timeout_timer
,
1087 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 3);
1089 strongarm_uart_update_status(s
);
1090 strongarm_uart_update_int_status(s
);
1093 static void strongarm_uart_event(void *opaque
, int event
)
1095 StrongARMUARTState
*s
= opaque
;
1096 if (event
== CHR_EVENT_BREAK
) {
1097 s
->utsr0
|= UTSR0_RBB
;
1098 strongarm_uart_rx_push(s
, RX_FIFO_FRE
);
1099 s
->wait_break_end
= true;
1100 strongarm_uart_update_status(s
);
1101 strongarm_uart_update_int_status(s
);
1105 static void strongarm_uart_tx(void *opaque
)
1107 StrongARMUARTState
*s
= opaque
;
1108 uint64_t new_xmit_ts
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
1110 if (s
->utcr3
& UTCR3_LBM
) /* loopback */ {
1111 strongarm_uart_receive(s
, &s
->tx_fifo
[s
->tx_start
], 1);
1112 } else if (s
->chr
) {
1113 qemu_chr_fe_write(s
->chr
, &s
->tx_fifo
[s
->tx_start
], 1);
1116 s
->tx_start
= (s
->tx_start
+ 1) % 8;
1119 timer_mod(s
->tx_timer
, new_xmit_ts
+ s
->char_transmit_time
);
1121 strongarm_uart_update_status(s
);
1122 strongarm_uart_update_int_status(s
);
1125 static uint64_t strongarm_uart_read(void *opaque
, hwaddr addr
,
1128 StrongARMUARTState
*s
= opaque
;
1139 return s
->brd
& 0xff;
1145 if (s
->rx_len
!= 0) {
1146 ret
= s
->rx_fifo
[s
->rx_start
];
1147 s
->rx_start
= (s
->rx_start
+ 1) % 12;
1149 strongarm_uart_update_status(s
);
1150 strongarm_uart_update_int_status(s
);
1162 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1167 static void strongarm_uart_write(void *opaque
, hwaddr addr
,
1168 uint64_t value
, unsigned size
)
1170 StrongARMUARTState
*s
= opaque
;
1174 s
->utcr0
= value
& 0x7f;
1175 strongarm_uart_update_parameters(s
);
1179 s
->brd
= (s
->brd
& 0xff) | ((value
& 0xf) << 8);
1180 strongarm_uart_update_parameters(s
);
1184 s
->brd
= (s
->brd
& 0xf00) | (value
& 0xff);
1185 strongarm_uart_update_parameters(s
);
1189 s
->utcr3
= value
& 0x3f;
1190 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1193 if ((s
->utcr3
& UTCR3_TXE
) == 0) {
1196 strongarm_uart_update_status(s
);
1197 strongarm_uart_update_int_status(s
);
1201 if ((s
->utcr3
& UTCR3_TXE
) && s
->tx_len
!= 8) {
1202 s
->tx_fifo
[(s
->tx_start
+ s
->tx_len
) % 8] = value
;
1204 strongarm_uart_update_status(s
);
1205 strongarm_uart_update_int_status(s
);
1206 if (s
->tx_len
== 1) {
1207 strongarm_uart_tx(s
);
1213 s
->utsr0
= s
->utsr0
& ~(value
&
1214 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
));
1215 strongarm_uart_update_int_status(s
);
1219 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1223 static const MemoryRegionOps strongarm_uart_ops
= {
1224 .read
= strongarm_uart_read
,
1225 .write
= strongarm_uart_write
,
1226 .endianness
= DEVICE_NATIVE_ENDIAN
,
1229 static int strongarm_uart_init(SysBusDevice
*dev
)
1231 StrongARMUARTState
*s
= STRONGARM_UART(dev
);
1233 memory_region_init_io(&s
->iomem
, OBJECT(s
), &strongarm_uart_ops
, s
,
1235 sysbus_init_mmio(dev
, &s
->iomem
);
1236 sysbus_init_irq(dev
, &s
->irq
);
1238 s
->rx_timeout_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, strongarm_uart_rx_to
, s
);
1239 s
->tx_timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, strongarm_uart_tx
, s
);
1242 qemu_chr_add_handlers(s
->chr
,
1243 strongarm_uart_can_receive
,
1244 strongarm_uart_receive
,
1245 strongarm_uart_event
,
1252 static void strongarm_uart_reset(DeviceState
*dev
)
1254 StrongARMUARTState
*s
= STRONGARM_UART(dev
);
1256 s
->utcr0
= UTCR0_DSS
; /* 8 data, no parity */
1257 s
->brd
= 23; /* 9600 */
1258 /* enable send & recv - this actually violates spec */
1259 s
->utcr3
= UTCR3_TXE
| UTCR3_RXE
;
1261 s
->rx_len
= s
->tx_len
= 0;
1263 strongarm_uart_update_parameters(s
);
1264 strongarm_uart_update_status(s
);
1265 strongarm_uart_update_int_status(s
);
1268 static int strongarm_uart_post_load(void *opaque
, int version_id
)
1270 StrongARMUARTState
*s
= opaque
;
1272 strongarm_uart_update_parameters(s
);
1273 strongarm_uart_update_status(s
);
1274 strongarm_uart_update_int_status(s
);
1276 /* tx and restart timer */
1278 strongarm_uart_tx(s
);
1281 /* restart rx timeout timer */
1283 timer_mod(s
->rx_timeout_timer
,
1284 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) + s
->char_transmit_time
* 3);
1290 static const VMStateDescription vmstate_strongarm_uart_regs
= {
1291 .name
= "strongarm-uart",
1293 .minimum_version_id
= 0,
1294 .post_load
= strongarm_uart_post_load
,
1295 .fields
= (VMStateField
[]) {
1296 VMSTATE_UINT8(utcr0
, StrongARMUARTState
),
1297 VMSTATE_UINT16(brd
, StrongARMUARTState
),
1298 VMSTATE_UINT8(utcr3
, StrongARMUARTState
),
1299 VMSTATE_UINT8(utsr0
, StrongARMUARTState
),
1300 VMSTATE_UINT8_ARRAY(tx_fifo
, StrongARMUARTState
, 8),
1301 VMSTATE_UINT8(tx_start
, StrongARMUARTState
),
1302 VMSTATE_UINT8(tx_len
, StrongARMUARTState
),
1303 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMUARTState
, 12),
1304 VMSTATE_UINT8(rx_start
, StrongARMUARTState
),
1305 VMSTATE_UINT8(rx_len
, StrongARMUARTState
),
1306 VMSTATE_BOOL(wait_break_end
, StrongARMUARTState
),
1307 VMSTATE_END_OF_LIST(),
1311 static Property strongarm_uart_properties
[] = {
1312 DEFINE_PROP_CHR("chardev", StrongARMUARTState
, chr
),
1313 DEFINE_PROP_END_OF_LIST(),
1316 static void strongarm_uart_class_init(ObjectClass
*klass
, void *data
)
1318 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1319 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1321 k
->init
= strongarm_uart_init
;
1322 dc
->desc
= "StrongARM UART controller";
1323 dc
->reset
= strongarm_uart_reset
;
1324 dc
->vmsd
= &vmstate_strongarm_uart_regs
;
1325 dc
->props
= strongarm_uart_properties
;
1328 static const TypeInfo strongarm_uart_info
= {
1329 .name
= TYPE_STRONGARM_UART
,
1330 .parent
= TYPE_SYS_BUS_DEVICE
,
1331 .instance_size
= sizeof(StrongARMUARTState
),
1332 .class_init
= strongarm_uart_class_init
,
1335 /* Synchronous Serial Ports */
1337 #define TYPE_STRONGARM_SSP "strongarm-ssp"
1338 #define STRONGARM_SSP(obj) \
1339 OBJECT_CHECK(StrongARMSSPState, (obj), TYPE_STRONGARM_SSP)
1341 typedef struct StrongARMSSPState
{
1342 SysBusDevice parent_obj
;
1351 uint16_t rx_fifo
[8];
1354 } StrongARMSSPState
;
1356 #define SSCR0 0x60 /* SSP Control register 0 */
1357 #define SSCR1 0x64 /* SSP Control register 1 */
1358 #define SSDR 0x6c /* SSP Data register */
1359 #define SSSR 0x74 /* SSP Status register */
1361 /* Bitfields for above registers */
1362 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1363 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1364 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1365 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1366 #define SSCR0_SSE (1 << 7)
1367 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1368 #define SSCR1_RIE (1 << 0)
1369 #define SSCR1_TIE (1 << 1)
1370 #define SSCR1_LBM (1 << 2)
1371 #define SSSR_TNF (1 << 2)
1372 #define SSSR_RNE (1 << 3)
1373 #define SSSR_TFS (1 << 5)
1374 #define SSSR_RFS (1 << 6)
1375 #define SSSR_ROR (1 << 7)
1376 #define SSSR_RW 0x0080
1378 static void strongarm_ssp_int_update(StrongARMSSPState
*s
)
1382 level
|= (s
->sssr
& SSSR_ROR
);
1383 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
1384 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
1385 qemu_set_irq(s
->irq
, level
);
1388 static void strongarm_ssp_fifo_update(StrongARMSSPState
*s
)
1390 s
->sssr
&= ~SSSR_TFS
;
1391 s
->sssr
&= ~SSSR_TNF
;
1392 if (s
->sscr
[0] & SSCR0_SSE
) {
1393 if (s
->rx_level
>= 4) {
1394 s
->sssr
|= SSSR_RFS
;
1396 s
->sssr
&= ~SSSR_RFS
;
1399 s
->sssr
|= SSSR_RNE
;
1401 s
->sssr
&= ~SSSR_RNE
;
1403 /* TX FIFO is never filled, so it is always in underrun
1404 condition if SSP is enabled */
1405 s
->sssr
|= SSSR_TFS
;
1406 s
->sssr
|= SSSR_TNF
;
1409 strongarm_ssp_int_update(s
);
1412 static uint64_t strongarm_ssp_read(void *opaque
, hwaddr addr
,
1415 StrongARMSSPState
*s
= opaque
;
1426 if (~s
->sscr
[0] & SSCR0_SSE
) {
1429 if (s
->rx_level
< 1) {
1430 printf("%s: SSP Rx Underrun\n", __func__
);
1434 retval
= s
->rx_fifo
[s
->rx_start
++];
1436 strongarm_ssp_fifo_update(s
);
1439 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1445 static void strongarm_ssp_write(void *opaque
, hwaddr addr
,
1446 uint64_t value
, unsigned size
)
1448 StrongARMSSPState
*s
= opaque
;
1452 s
->sscr
[0] = value
& 0xffbf;
1453 if ((s
->sscr
[0] & SSCR0_SSE
) && SSCR0_DSS(value
) < 4) {
1454 printf("%s: Wrong data size: %i bits\n", __func__
,
1455 (int)SSCR0_DSS(value
));
1457 if (!(value
& SSCR0_SSE
)) {
1461 strongarm_ssp_fifo_update(s
);
1465 s
->sscr
[1] = value
& 0x2f;
1466 if (value
& SSCR1_LBM
) {
1467 printf("%s: Attempt to use SSP LBM mode\n", __func__
);
1469 strongarm_ssp_fifo_update(s
);
1473 s
->sssr
&= ~(value
& SSSR_RW
);
1474 strongarm_ssp_int_update(s
);
1478 if (SSCR0_UWIRE(s
->sscr
[0])) {
1481 /* Note how 32bits overflow does no harm here */
1482 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
1484 /* Data goes from here to the Tx FIFO and is shifted out from
1485 * there directly to the slave, no need to buffer it.
1487 if (s
->sscr
[0] & SSCR0_SSE
) {
1489 if (s
->sscr
[1] & SSCR1_LBM
) {
1492 readval
= ssi_transfer(s
->bus
, value
);
1495 if (s
->rx_level
< 0x08) {
1496 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0x7] = readval
;
1498 s
->sssr
|= SSSR_ROR
;
1501 strongarm_ssp_fifo_update(s
);
1505 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1510 static const MemoryRegionOps strongarm_ssp_ops
= {
1511 .read
= strongarm_ssp_read
,
1512 .write
= strongarm_ssp_write
,
1513 .endianness
= DEVICE_NATIVE_ENDIAN
,
1516 static int strongarm_ssp_post_load(void *opaque
, int version_id
)
1518 StrongARMSSPState
*s
= opaque
;
1520 strongarm_ssp_fifo_update(s
);
1525 static int strongarm_ssp_init(SysBusDevice
*sbd
)
1527 DeviceState
*dev
= DEVICE(sbd
);
1528 StrongARMSSPState
*s
= STRONGARM_SSP(dev
);
1530 sysbus_init_irq(sbd
, &s
->irq
);
1532 memory_region_init_io(&s
->iomem
, OBJECT(s
), &strongarm_ssp_ops
, s
,
1534 sysbus_init_mmio(sbd
, &s
->iomem
);
1536 s
->bus
= ssi_create_bus(dev
, "ssi");
1540 static void strongarm_ssp_reset(DeviceState
*dev
)
1542 StrongARMSSPState
*s
= STRONGARM_SSP(dev
);
1544 s
->sssr
= 0x03; /* 3 bit data, SPI, disabled */
1549 static const VMStateDescription vmstate_strongarm_ssp_regs
= {
1550 .name
= "strongarm-ssp",
1552 .minimum_version_id
= 0,
1553 .post_load
= strongarm_ssp_post_load
,
1554 .fields
= (VMStateField
[]) {
1555 VMSTATE_UINT16_ARRAY(sscr
, StrongARMSSPState
, 2),
1556 VMSTATE_UINT16(sssr
, StrongARMSSPState
),
1557 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMSSPState
, 8),
1558 VMSTATE_UINT8(rx_start
, StrongARMSSPState
),
1559 VMSTATE_UINT8(rx_level
, StrongARMSSPState
),
1560 VMSTATE_END_OF_LIST(),
1564 static void strongarm_ssp_class_init(ObjectClass
*klass
, void *data
)
1566 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1567 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
1569 k
->init
= strongarm_ssp_init
;
1570 dc
->desc
= "StrongARM SSP controller";
1571 dc
->reset
= strongarm_ssp_reset
;
1572 dc
->vmsd
= &vmstate_strongarm_ssp_regs
;
1575 static const TypeInfo strongarm_ssp_info
= {
1576 .name
= TYPE_STRONGARM_SSP
,
1577 .parent
= TYPE_SYS_BUS_DEVICE
,
1578 .instance_size
= sizeof(StrongARMSSPState
),
1579 .class_init
= strongarm_ssp_class_init
,
1582 /* Main CPU functions */
1583 StrongARMState
*sa1110_init(MemoryRegion
*sysmem
,
1584 unsigned int sdram_size
, const char *rev
)
1589 s
= g_malloc0(sizeof(StrongARMState
));
1595 if (strncmp(rev
, "sa1110", 6)) {
1596 error_report("Machine requires a SA1110 processor.");
1600 s
->cpu
= cpu_arm_init(rev
);
1603 error_report("Unable to find CPU definition");
1607 memory_region_init_ram(&s
->sdram
, NULL
, "strongarm.sdram", sdram_size
,
1609 vmstate_register_ram_global(&s
->sdram
);
1610 memory_region_add_subregion(sysmem
, SA_SDCS0
, &s
->sdram
);
1612 s
->pic
= sysbus_create_varargs("strongarm_pic", 0x90050000,
1613 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_IRQ
),
1614 qdev_get_gpio_in(DEVICE(s
->cpu
), ARM_CPU_FIQ
),
1617 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1618 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC0
),
1619 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC1
),
1620 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC2
),
1621 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC3
),
1624 sysbus_create_simple(TYPE_STRONGARM_RTC
, 0x90010000,
1625 qdev_get_gpio_in(s
->pic
, SA_PIC_RTC_ALARM
));
1627 s
->gpio
= strongarm_gpio_init(0x90040000, s
->pic
);
1629 s
->ppc
= sysbus_create_varargs(TYPE_STRONGARM_PPC
, 0x90060000, NULL
);
1631 for (i
= 0; sa_serial
[i
].io_base
; i
++) {
1632 DeviceState
*dev
= qdev_create(NULL
, TYPE_STRONGARM_UART
);
1633 qdev_prop_set_chr(dev
, "chardev", serial_hds
[i
]);
1634 qdev_init_nofail(dev
);
1635 sysbus_mmio_map(SYS_BUS_DEVICE(dev
), 0,
1636 sa_serial
[i
].io_base
);
1637 sysbus_connect_irq(SYS_BUS_DEVICE(dev
), 0,
1638 qdev_get_gpio_in(s
->pic
, sa_serial
[i
].irq
));
1641 s
->ssp
= sysbus_create_varargs(TYPE_STRONGARM_SSP
, 0x80070000,
1642 qdev_get_gpio_in(s
->pic
, SA_PIC_SSP
), NULL
);
1643 s
->ssp_bus
= (SSIBus
*)qdev_get_child_bus(s
->ssp
, "ssi");
1648 static void strongarm_register_types(void)
1650 type_register_static(&strongarm_pic_info
);
1651 type_register_static(&strongarm_rtc_sysbus_info
);
1652 type_register_static(&strongarm_gpio_info
);
1653 type_register_static(&strongarm_ppc_info
);
1654 type_register_static(&strongarm_uart_info
);
1655 type_register_static(&strongarm_ssp_info
);
1658 type_init(strongarm_register_types
)