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spapr_iommu: Introduce "enabled" state for TCE table
[qemu.git] / hw / arm / omap2.c
blob3a0d77714a257a89fbece047968cec4fe83ac923
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/block-backend.h"
26 #include "sysemu/blockdev.h"
27 #include "hw/boards.h"
28 #include "hw/hw.h"
29 #include "hw/arm/arm.h"
30 #include "hw/arm/omap.h"
31 #include "sysemu/sysemu.h"
32 #include "qemu/timer.h"
33 #include "sysemu/char.h"
34 #include "hw/block/flash.h"
35 #include "hw/arm/soc_dma.h"
36 #include "hw/sysbus.h"
37 #include "audio/audio.h"
38
39 /* Enhanced Audio Controller (CODEC only) */
40 struct omap_eac_s {
41 qemu_irq irq;
42 MemoryRegion iomem;
43
44 uint16_t sysconfig;
45 uint8_t config[4];
46 uint8_t control;
47 uint8_t address;
48 uint16_t data;
49 uint8_t vtol;
50 uint8_t vtsl;
51 uint16_t mixer;
52 uint16_t gain[4];
53 uint8_t att;
54 uint16_t max[7];
55
56 struct {
57 qemu_irq txdrq;
58 qemu_irq rxdrq;
59 uint32_t (*txrx)(void *opaque, uint32_t, int);
60 void *opaque;
61
62 #define EAC_BUF_LEN 1024
63 uint32_t rxbuf[EAC_BUF_LEN];
64 int rxoff;
65 int rxlen;
66 int rxavail;
67 uint32_t txbuf[EAC_BUF_LEN];
68 int txlen;
69 int txavail;
70
71 int enable;
72 int rate;
73
74 uint16_t config[4];
75
76 /* These need to be moved to the actual codec */
77 QEMUSoundCard card;
78 SWVoiceIn *in_voice;
79 SWVoiceOut *out_voice;
80 int hw_enable;
81 } codec;
82
83 struct {
84 uint8_t control;
85 uint16_t config;
86 } modem, bt;
87 };
88
89 static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
90 {
91 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
92 }
93
94 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
95 {
96 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
97 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
98 }
99
100 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
101 {
102 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
103 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
104 }
105
106 static inline void omap_eac_in_refill(struct omap_eac_s *s)
107 {
108 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
109 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
110 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
111 int recv = 1;
112 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
113
114 left -= leftwrap;
115 start = 0;
116 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
117 leftwrap)) > 0) { /* Be defensive */
118 start += recv;
119 leftwrap -= recv;
120 }
121 if (recv <= 0)
122 s->codec.rxavail = 0;
123 else
124 s->codec.rxavail -= start >> 2;
125 s->codec.rxlen += start >> 2;
126
127 if (recv > 0 && left > 0) {
128 start = 0;
129 while (left && (recv = AUD_read(s->codec.in_voice,
130 (uint8_t *) s->codec.rxbuf + start,
131 left)) > 0) { /* Be defensive */
132 start += recv;
133 left -= recv;
134 }
135 if (recv <= 0)
136 s->codec.rxavail = 0;
137 else
138 s->codec.rxavail -= start >> 2;
139 s->codec.rxlen += start >> 2;
140 }
141 }
142
143 static inline void omap_eac_out_empty(struct omap_eac_s *s)
144 {
145 int left = s->codec.txlen << 2;
146 int start = 0;
147 int sent = 1;
148
149 while (left && (sent = AUD_write(s->codec.out_voice,
150 (uint8_t *) s->codec.txbuf + start,
151 left)) > 0) { /* Be defensive */
152 start += sent;
153 left -= sent;
154 }
155
156 if (!sent) {
157 s->codec.txavail = 0;
158 omap_eac_out_dmarequest_update(s);
159 }
160
161 if (start)
162 s->codec.txlen = 0;
163 }
164
165 static void omap_eac_in_cb(void *opaque, int avail_b)
166 {
167 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
168
169 s->codec.rxavail = avail_b >> 2;
170 omap_eac_in_refill(s);
171 /* TODO: possibly discard current buffer if overrun */
172 omap_eac_in_dmarequest_update(s);
173 }
174
175 static void omap_eac_out_cb(void *opaque, int free_b)
176 {
177 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
178
179 s->codec.txavail = free_b >> 2;
180 if (s->codec.txlen)
181 omap_eac_out_empty(s);
182 else
183 omap_eac_out_dmarequest_update(s);
184 }
185
186 static void omap_eac_enable_update(struct omap_eac_s *s)
187 {
188 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
189 (s->codec.config[1] & 2) && /* AUDEN */
190 s->codec.hw_enable;
191 }
192
193 static const int omap_eac_fsint[4] = {
194 8000,
195 11025,
196 22050,
197 44100,
198 };
199
200 static const int omap_eac_fsint2[8] = {
201 8000,
202 11025,
203 22050,
204 44100,
205 48000,
206 0, 0, 0,
207 };
208
209 static const int omap_eac_fsint3[16] = {
210 8000,
211 11025,
212 16000,
213 22050,
214 24000,
215 32000,
216 44100,
217 48000,
218 0, 0, 0, 0, 0, 0, 0, 0,
219 };
220
221 static void omap_eac_rate_update(struct omap_eac_s *s)
222 {
223 int fsint[3];
224
225 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
226 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
227 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
228 if (fsint[2] < 0xf)
229 s->codec.rate = omap_eac_fsint3[fsint[2]];
230 else if (fsint[1] < 0x7)
231 s->codec.rate = omap_eac_fsint2[fsint[1]];
232 else
233 s->codec.rate = omap_eac_fsint[fsint[0]];
234 }
235
236 static void omap_eac_volume_update(struct omap_eac_s *s)
237 {
238 /* TODO */
239 }
240
241 static void omap_eac_format_update(struct omap_eac_s *s)
242 {
243 struct audsettings fmt;
244
245 /* The hardware buffers at most one sample */
246 if (s->codec.rxlen)
247 s->codec.rxlen = 1;
248
249 if (s->codec.in_voice) {
250 AUD_set_active_in(s->codec.in_voice, 0);
251 AUD_close_in(&s->codec.card, s->codec.in_voice);
252 s->codec.in_voice = NULL;
253 }
254 if (s->codec.out_voice) {
255 omap_eac_out_empty(s);
256 AUD_set_active_out(s->codec.out_voice, 0);
257 AUD_close_out(&s->codec.card, s->codec.out_voice);
258 s->codec.out_voice = NULL;
259 s->codec.txavail = 0;
260 }
261 /* Discard what couldn't be written */
262 s->codec.txlen = 0;
263
264 omap_eac_enable_update(s);
265 if (!s->codec.enable)
266 return;
267
268 omap_eac_rate_update(s);
269 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
270 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
271 fmt.freq = s->codec.rate;
272 /* TODO: signedness possibly depends on the CODEC hardware - or
273 * does I2S specify it? */
274 /* All register writes are 16 bits so we we store 16-bit samples
275 * in the buffers regardless of AGCFR[B8_16] value. */
276 fmt.fmt = AUD_FMT_U16;
277
278 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
279 "eac.codec.in", s, omap_eac_in_cb, &fmt);
280 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
281 "eac.codec.out", s, omap_eac_out_cb, &fmt);
282
283 omap_eac_volume_update(s);
284
285 AUD_set_active_in(s->codec.in_voice, 1);
286 AUD_set_active_out(s->codec.out_voice, 1);
287 }
288
289 static void omap_eac_reset(struct omap_eac_s *s)
290 {
291 s->sysconfig = 0;
292 s->config[0] = 0x0c;
293 s->config[1] = 0x09;
294 s->config[2] = 0xab;
295 s->config[3] = 0x03;
296 s->control = 0x00;
297 s->address = 0x00;
298 s->data = 0x0000;
299 s->vtol = 0x00;
300 s->vtsl = 0x00;
301 s->mixer = 0x0000;
302 s->gain[0] = 0xe7e7;
303 s->gain[1] = 0x6767;
304 s->gain[2] = 0x6767;
305 s->gain[3] = 0x6767;
306 s->att = 0xce;
307 s->max[0] = 0;
308 s->max[1] = 0;
309 s->max[2] = 0;
310 s->max[3] = 0;
311 s->max[4] = 0;
312 s->max[5] = 0;
313 s->max[6] = 0;
314
315 s->modem.control = 0x00;
316 s->modem.config = 0x0000;
317 s->bt.control = 0x00;
318 s->bt.config = 0x0000;
319 s->codec.config[0] = 0x0649;
320 s->codec.config[1] = 0x0000;
321 s->codec.config[2] = 0x0007;
322 s->codec.config[3] = 0x1ffc;
323 s->codec.rxoff = 0;
324 s->codec.rxlen = 0;
325 s->codec.txlen = 0;
326 s->codec.rxavail = 0;
327 s->codec.txavail = 0;
328
329 omap_eac_format_update(s);
330 omap_eac_interrupt_update(s);
331 }
332
333 static uint64_t omap_eac_read(void *opaque, hwaddr addr,
334 unsigned size)
335 {
336 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
337 uint32_t ret;
338
339 if (size != 2) {
340 return omap_badwidth_read16(opaque, addr);
341 }
342
343 switch (addr) {
344 case 0x000: /* CPCFR1 */
345 return s->config[0];
346 case 0x004: /* CPCFR2 */
347 return s->config[1];
348 case 0x008: /* CPCFR3 */
349 return s->config[2];
350 case 0x00c: /* CPCFR4 */
351 return s->config[3];
352
353 case 0x010: /* CPTCTL */
354 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
355 ((s->codec.txlen < s->codec.txavail) << 5);
356
357 case 0x014: /* CPTTADR */
358 return s->address;
359 case 0x018: /* CPTDATL */
360 return s->data & 0xff;
361 case 0x01c: /* CPTDATH */
362 return s->data >> 8;
363 case 0x020: /* CPTVSLL */
364 return s->vtol;
365 case 0x024: /* CPTVSLH */
366 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
367 case 0x040: /* MPCTR */
368 return s->modem.control;
369 case 0x044: /* MPMCCFR */
370 return s->modem.config;
371 case 0x060: /* BPCTR */
372 return s->bt.control;
373 case 0x064: /* BPMCCFR */
374 return s->bt.config;
375 case 0x080: /* AMSCFR */
376 return s->mixer;
377 case 0x084: /* AMVCTR */
378 return s->gain[0];
379 case 0x088: /* AM1VCTR */
380 return s->gain[1];
381 case 0x08c: /* AM2VCTR */
382 return s->gain[2];
383 case 0x090: /* AM3VCTR */
384 return s->gain[3];
385 case 0x094: /* ASTCTR */
386 return s->att;
387 case 0x098: /* APD1LCR */
388 return s->max[0];
389 case 0x09c: /* APD1RCR */
390 return s->max[1];
391 case 0x0a0: /* APD2LCR */
392 return s->max[2];
393 case 0x0a4: /* APD2RCR */
394 return s->max[3];
395 case 0x0a8: /* APD3LCR */
396 return s->max[4];
397 case 0x0ac: /* APD3RCR */
398 return s->max[5];
399 case 0x0b0: /* APD4R */
400 return s->max[6];
401 case 0x0b4: /* ADWR */
402 /* This should be write-only? Docs list it as read-only. */
403 return 0x0000;
404 case 0x0b8: /* ADRDR */
405 if (likely(s->codec.rxlen > 1)) {
406 ret = s->codec.rxbuf[s->codec.rxoff ++];
407 s->codec.rxlen --;
408 s->codec.rxoff &= EAC_BUF_LEN - 1;
409 return ret;
410 } else if (s->codec.rxlen) {
411 ret = s->codec.rxbuf[s->codec.rxoff ++];
412 s->codec.rxlen --;
413 s->codec.rxoff &= EAC_BUF_LEN - 1;
414 if (s->codec.rxavail)
415 omap_eac_in_refill(s);
416 omap_eac_in_dmarequest_update(s);
417 return ret;
418 }
419 return 0x0000;
420 case 0x0bc: /* AGCFR */
421 return s->codec.config[0];
422 case 0x0c0: /* AGCTR */
423 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
424 case 0x0c4: /* AGCFR2 */
425 return s->codec.config[2];
426 case 0x0c8: /* AGCFR3 */
427 return s->codec.config[3];
428 case 0x0cc: /* MBPDMACTR */
429 case 0x0d0: /* MPDDMARR */
430 case 0x0d8: /* MPUDMARR */
431 case 0x0e4: /* BPDDMARR */
432 case 0x0ec: /* BPUDMARR */
433 return 0x0000;
434
435 case 0x100: /* VERSION_NUMBER */
436 return 0x0010;
437
438 case 0x104: /* SYSCONFIG */
439 return s->sysconfig;
440
441 case 0x108: /* SYSSTATUS */
442 return 1 | 0xe; /* RESETDONE | stuff */
443 }
444
445 OMAP_BAD_REG(addr);
446 return 0;
447 }
448
449 static void omap_eac_write(void *opaque, hwaddr addr,
450 uint64_t value, unsigned size)
451 {
452 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
453
454 if (size != 2) {
455 omap_badwidth_write16(opaque, addr, value);
456 return;
457 }
458
459 switch (addr) {
460 case 0x098: /* APD1LCR */
461 case 0x09c: /* APD1RCR */
462 case 0x0a0: /* APD2LCR */
463 case 0x0a4: /* APD2RCR */
464 case 0x0a8: /* APD3LCR */
465 case 0x0ac: /* APD3RCR */
466 case 0x0b0: /* APD4R */
467 case 0x0b8: /* ADRDR */
468 case 0x0d0: /* MPDDMARR */
469 case 0x0d8: /* MPUDMARR */
470 case 0x0e4: /* BPDDMARR */
471 case 0x0ec: /* BPUDMARR */
472 case 0x100: /* VERSION_NUMBER */
473 case 0x108: /* SYSSTATUS */
474 OMAP_RO_REG(addr);
475 return;
476
477 case 0x000: /* CPCFR1 */
478 s->config[0] = value & 0xff;
479 omap_eac_format_update(s);
480 break;
481 case 0x004: /* CPCFR2 */
482 s->config[1] = value & 0xff;
483 omap_eac_format_update(s);
484 break;
485 case 0x008: /* CPCFR3 */
486 s->config[2] = value & 0xff;
487 omap_eac_format_update(s);
488 break;
489 case 0x00c: /* CPCFR4 */
490 s->config[3] = value & 0xff;
491 omap_eac_format_update(s);
492 break;
493
494 case 0x010: /* CPTCTL */
495 /* Assuming TXF and TXE bits are read-only... */
496 s->control = value & 0x5f;
497 omap_eac_interrupt_update(s);
498 break;
499
500 case 0x014: /* CPTTADR */
501 s->address = value & 0xff;
502 break;
503 case 0x018: /* CPTDATL */
504 s->data &= 0xff00;
505 s->data |= value & 0xff;
506 break;
507 case 0x01c: /* CPTDATH */
508 s->data &= 0x00ff;
509 s->data |= value << 8;
510 break;
511 case 0x020: /* CPTVSLL */
512 s->vtol = value & 0xf8;
513 break;
514 case 0x024: /* CPTVSLH */
515 s->vtsl = value & 0x9f;
516 break;
517 case 0x040: /* MPCTR */
518 s->modem.control = value & 0x8f;
519 break;
520 case 0x044: /* MPMCCFR */
521 s->modem.config = value & 0x7fff;
522 break;
523 case 0x060: /* BPCTR */
524 s->bt.control = value & 0x8f;
525 break;
526 case 0x064: /* BPMCCFR */
527 s->bt.config = value & 0x7fff;
528 break;
529 case 0x080: /* AMSCFR */
530 s->mixer = value & 0x0fff;
531 break;
532 case 0x084: /* AMVCTR */
533 s->gain[0] = value & 0xffff;
534 break;
535 case 0x088: /* AM1VCTR */
536 s->gain[1] = value & 0xff7f;
537 break;
538 case 0x08c: /* AM2VCTR */
539 s->gain[2] = value & 0xff7f;
540 break;
541 case 0x090: /* AM3VCTR */
542 s->gain[3] = value & 0xff7f;
543 break;
544 case 0x094: /* ASTCTR */
545 s->att = value & 0xff;
546 break;
547
548 case 0x0b4: /* ADWR */
549 s->codec.txbuf[s->codec.txlen ++] = value;
550 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
551 s->codec.txlen == s->codec.txavail)) {
552 if (s->codec.txavail)
553 omap_eac_out_empty(s);
554 /* Discard what couldn't be written */
555 s->codec.txlen = 0;
556 }
557 break;
558
559 case 0x0bc: /* AGCFR */
560 s->codec.config[0] = value & 0x07ff;
561 omap_eac_format_update(s);
562 break;
563 case 0x0c0: /* AGCTR */
564 s->codec.config[1] = value & 0x780f;
565 omap_eac_format_update(s);
566 break;
567 case 0x0c4: /* AGCFR2 */
568 s->codec.config[2] = value & 0x003f;
569 omap_eac_format_update(s);
570 break;
571 case 0x0c8: /* AGCFR3 */
572 s->codec.config[3] = value & 0xffff;
573 omap_eac_format_update(s);
574 break;
575 case 0x0cc: /* MBPDMACTR */
576 case 0x0d4: /* MPDDMAWR */
577 case 0x0e0: /* MPUDMAWR */
578 case 0x0e8: /* BPDDMAWR */
579 case 0x0f0: /* BPUDMAWR */
580 break;
581
582 case 0x104: /* SYSCONFIG */
583 if (value & (1 << 1)) /* SOFTRESET */
584 omap_eac_reset(s);
585 s->sysconfig = value & 0x31d;
586 break;
587
588 default:
589 OMAP_BAD_REG(addr);
590 return;
591 }
592 }
593
594 static const MemoryRegionOps omap_eac_ops = {
595 .read = omap_eac_read,
596 .write = omap_eac_write,
597 .endianness = DEVICE_NATIVE_ENDIAN,
598 };
599
600 static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
601 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
602 {
603 struct omap_eac_s *s = g_new0(struct omap_eac_s, 1);
604
605 s->irq = irq;
606 s->codec.rxdrq = *drq ++;
607 s->codec.txdrq = *drq;
608 omap_eac_reset(s);
609
610 AUD_register_card("OMAP EAC", &s->codec.card);
611
612 memory_region_init_io(&s->iomem, NULL, &omap_eac_ops, s, "omap.eac",
613 omap_l4_region_size(ta, 0));
614 omap_l4_attach(ta, 0, &s->iomem);
615
616 return s;
617 }
618
619 /* STI/XTI (emulation interface) console - reverse engineered only */
620 struct omap_sti_s {
621 qemu_irq irq;
622 MemoryRegion iomem;
623 MemoryRegion iomem_fifo;
624 CharDriverState *chr;
625
626 uint32_t sysconfig;
627 uint32_t systest;
628 uint32_t irqst;
629 uint32_t irqen;
630 uint32_t clkcontrol;
631 uint32_t serial_config;
632 };
633
634 #define STI_TRACE_CONSOLE_CHANNEL 239
635 #define STI_TRACE_CONTROL_CHANNEL 253
636
637 static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
638 {
639 qemu_set_irq(s->irq, s->irqst & s->irqen);
640 }
641
642 static void omap_sti_reset(struct omap_sti_s *s)
643 {
644 s->sysconfig = 0;
645 s->irqst = 0;
646 s->irqen = 0;
647 s->clkcontrol = 0;
648 s->serial_config = 0;
649
650 omap_sti_interrupt_update(s);
651 }
652
653 static uint64_t omap_sti_read(void *opaque, hwaddr addr,
654 unsigned size)
655 {
656 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
657
658 if (size != 4) {
659 return omap_badwidth_read32(opaque, addr);
660 }
661
662 switch (addr) {
663 case 0x00: /* STI_REVISION */
664 return 0x10;
665
666 case 0x10: /* STI_SYSCONFIG */
667 return s->sysconfig;
668
669 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
670 return 0x00;
671
672 case 0x18: /* STI_IRQSTATUS */
673 return s->irqst;
674
675 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
676 return s->irqen;
677
678 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
679 case 0x28: /* STI_RX_DR / XTI_RXDATA */
680 /* TODO */
681 return 0;
682
683 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
684 return s->clkcontrol;
685
686 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
687 return s->serial_config;
688 }
689
690 OMAP_BAD_REG(addr);
691 return 0;
692 }
693
694 static void omap_sti_write(void *opaque, hwaddr addr,
695 uint64_t value, unsigned size)
696 {
697 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
698
699 if (size != 4) {
700 omap_badwidth_write32(opaque, addr, value);
701 return;
702 }
703
704 switch (addr) {
705 case 0x00: /* STI_REVISION */
706 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
707 OMAP_RO_REG(addr);
708 return;
709
710 case 0x10: /* STI_SYSCONFIG */
711 if (value & (1 << 1)) /* SOFTRESET */
712 omap_sti_reset(s);
713 s->sysconfig = value & 0xfe;
714 break;
715
716 case 0x18: /* STI_IRQSTATUS */
717 s->irqst &= ~value;
718 omap_sti_interrupt_update(s);
719 break;
720
721 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
722 s->irqen = value & 0xffff;
723 omap_sti_interrupt_update(s);
724 break;
725
726 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
727 s->clkcontrol = value & 0xff;
728 break;
729
730 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
731 s->serial_config = value & 0xff;
732 break;
733
734 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
735 case 0x28: /* STI_RX_DR / XTI_RXDATA */
736 /* TODO */
737 return;
738
739 default:
740 OMAP_BAD_REG(addr);
741 return;
742 }
743 }
744
745 static const MemoryRegionOps omap_sti_ops = {
746 .read = omap_sti_read,
747 .write = omap_sti_write,
748 .endianness = DEVICE_NATIVE_ENDIAN,
749 };
750
751 static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
752 unsigned size)
753 {
754 OMAP_BAD_REG(addr);
755 return 0;
756 }
757
758 static void omap_sti_fifo_write(void *opaque, hwaddr addr,
759 uint64_t value, unsigned size)
760 {
761 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
762 int ch = addr >> 6;
763 uint8_t byte = value;
764
765 if (size != 1) {
766 omap_badwidth_write8(opaque, addr, size);
767 return;
768 }
769
770 if (ch == STI_TRACE_CONTROL_CHANNEL) {
771 /* Flush channel <i>value</i>. */
772 qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1);
773 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
774 if (value == 0xc0 || value == 0xc3) {
775 /* Open channel <i>ch</i>. */
776 } else if (value == 0x00)
777 qemu_chr_fe_write(s->chr, (const uint8_t *) "\n", 1);
778 else
779 qemu_chr_fe_write(s->chr, &byte, 1);
780 }
781 }
782
783 static const MemoryRegionOps omap_sti_fifo_ops = {
784 .read = omap_sti_fifo_read,
785 .write = omap_sti_fifo_write,
786 .endianness = DEVICE_NATIVE_ENDIAN,
787 };
788
789 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
790 MemoryRegion *sysmem,
791 hwaddr channel_base, qemu_irq irq, omap_clk clk,
792 CharDriverState *chr)
793 {
794 struct omap_sti_s *s = g_new0(struct omap_sti_s, 1);
795
796 s->irq = irq;
797 omap_sti_reset(s);
798
799 s->chr = chr ?: qemu_chr_new("null", "null", NULL);
800
801 memory_region_init_io(&s->iomem, NULL, &omap_sti_ops, s, "omap.sti",
802 omap_l4_region_size(ta, 0));
803 omap_l4_attach(ta, 0, &s->iomem);
804
805 memory_region_init_io(&s->iomem_fifo, NULL, &omap_sti_fifo_ops, s,
806 "omap.sti.fifo", 0x10000);
807 memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo);
808
809 return s;
810 }
811
812 /* L4 Interconnect */
813 #define L4TA(n) (n)
814 #define L4TAO(n) ((n) + 39)
815
816 static const struct omap_l4_region_s omap_l4_region[125] = {
817 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
818 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
819 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
820 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
821 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
822 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
823 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
824 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
825 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
826 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
827 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
828 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
829 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
830 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
831 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
832 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
833 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
834 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
835 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
836 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
837 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
838 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
839 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
840 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
841 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
842 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
843 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
844 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
845 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
846 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
847 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
848 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
849 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
850 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
851 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
852 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
853 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
854 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
855 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
856 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
857 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
858 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
859 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
860 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
861 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
862 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
863 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
864 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
865 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
866 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
867 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
868 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
869 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
870 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
871 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
872 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
873 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
874 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
875 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
876 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
877 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
878 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
879 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
880 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
881 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
882 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
883 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
884 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
885 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
886 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
887 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
888 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
889 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
890 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
891 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
892 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
893 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
894 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
895 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
896 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
897 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
898 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
899 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
900 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
901 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
902 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
903 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
904 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
905 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
906 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
907 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
908 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
909 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
910 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
911 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
912 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
913 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
914 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
915 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
916 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
917 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
918 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
919 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
920 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
921 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
922 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
923 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
924 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
925 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
926 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
927 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
928 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
929 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
930 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
931 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
932 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
933 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
934 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
935 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
936 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
937 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
938 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
939 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
940 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
941 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
942 };
943
944 static const struct omap_l4_agent_info_s omap_l4_agent_info[54] = {
945 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
946 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
947 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
948 { L4TAO(3), 7, 3, 2 }, /* PRCM */
949 { L4TA(1), 10, 2, 1 }, /* BCM */
950 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
951 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
952 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
953 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
954 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
955 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
956 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
957 { L4TA(12), 38, 2, 1 }, /* sDMA */
958 { L4TA(13), 40, 5, 4 }, /* SSI */
959 { L4TAO(4), 45, 2, 1 }, /* USB */
960 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
961 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
962 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
963 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
964 { L4TA(18), 55, 2, 1 }, /* XTI */
965 { L4TA(19), 57, 2, 1 }, /* UART1 */
966 { L4TA(20), 59, 2, 1 }, /* UART2 */
967 { L4TA(21), 61, 2, 1 }, /* UART3 */
968 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
969 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
970 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
971 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
972 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
973 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
974 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
975 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
976 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
977 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
978 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
979 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
980 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
981 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
982 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
983 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
984 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
985 { L4TA(32), 97, 2, 1 }, /* EAC */
986 { L4TA(33), 99, 2, 1 }, /* FAC */
987 { L4TA(34), 101, 2, 1 }, /* IPC */
988 { L4TA(35), 103, 2, 1 }, /* SPI1 */
989 { L4TA(36), 105, 2, 1 }, /* SPI2 */
990 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
991 { L4TAO(10), 109, 2, 1 },
992 { L4TAO(11), 111, 2, 1 }, /* RNG */
993 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
994 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
995 { L4TA(37), 117, 2, 1 }, /* AES */
996 { L4TA(38), 119, 2, 1 }, /* PKA */
997 { -1, 121, 2, 1 },
998 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
999 };
1000
1001 #define omap_l4ta(bus, cs) \
1002 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TA(cs))
1003 #define omap_l4tao(bus, cs) \
1004 omap_l4ta_get(bus, omap_l4_region, omap_l4_agent_info, L4TAO(cs))
1005
1006 /* Power, Reset, and Clock Management */
1007 struct omap_prcm_s {
1008 qemu_irq irq[3];
1009 struct omap_mpu_state_s *mpu;
1010 MemoryRegion iomem0;
1011 MemoryRegion iomem1;
1012
1013 uint32_t irqst[3];
1014 uint32_t irqen[3];
1015
1016 uint32_t sysconfig;
1017 uint32_t voltctrl;
1018 uint32_t scratch[20];
1019
1020 uint32_t clksrc[1];
1021 uint32_t clkout[1];
1022 uint32_t clkemul[1];
1023 uint32_t clkpol[1];
1024 uint32_t clksel[8];
1025 uint32_t clken[12];
1026 uint32_t clkctrl[4];
1027 uint32_t clkidle[7];
1028 uint32_t setuptime[2];
1029
1030 uint32_t wkup[3];
1031 uint32_t wken[3];
1032 uint32_t wkst[3];
1033 uint32_t rst[4];
1034 uint32_t rstctrl[1];
1035 uint32_t power[4];
1036 uint32_t rsttime_wkup;
1037
1038 uint32_t ev;
1039 uint32_t evtime[2];
1040
1041 int dpll_lock, apll_lock[2];
1042 };
1043
1044 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
1045 {
1046 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
1047 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
1048 }
1049
1050 static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
1051 unsigned size)
1052 {
1053 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1054 uint32_t ret;
1055
1056 if (size != 4) {
1057 return omap_badwidth_read32(opaque, addr);
1058 }
1059
1060 switch (addr) {
1061 case 0x000: /* PRCM_REVISION */
1062 return 0x10;
1063
1064 case 0x010: /* PRCM_SYSCONFIG */
1065 return s->sysconfig;
1066
1067 case 0x018: /* PRCM_IRQSTATUS_MPU */
1068 return s->irqst[0];
1069
1070 case 0x01c: /* PRCM_IRQENABLE_MPU */
1071 return s->irqen[0];
1072
1073 case 0x050: /* PRCM_VOLTCTRL */
1074 return s->voltctrl;
1075 case 0x054: /* PRCM_VOLTST */
1076 return s->voltctrl & 3;
1077
1078 case 0x060: /* PRCM_CLKSRC_CTRL */
1079 return s->clksrc[0];
1080 case 0x070: /* PRCM_CLKOUT_CTRL */
1081 return s->clkout[0];
1082 case 0x078: /* PRCM_CLKEMUL_CTRL */
1083 return s->clkemul[0];
1084 case 0x080: /* PRCM_CLKCFG_CTRL */
1085 case 0x084: /* PRCM_CLKCFG_STATUS */
1086 return 0;
1087
1088 case 0x090: /* PRCM_VOLTSETUP */
1089 return s->setuptime[0];
1090
1091 case 0x094: /* PRCM_CLKSSETUP */
1092 return s->setuptime[1];
1093
1094 case 0x098: /* PRCM_POLCTRL */
1095 return s->clkpol[0];
1096
1097 case 0x0b0: /* GENERAL_PURPOSE1 */
1098 case 0x0b4: /* GENERAL_PURPOSE2 */
1099 case 0x0b8: /* GENERAL_PURPOSE3 */
1100 case 0x0bc: /* GENERAL_PURPOSE4 */
1101 case 0x0c0: /* GENERAL_PURPOSE5 */
1102 case 0x0c4: /* GENERAL_PURPOSE6 */
1103 case 0x0c8: /* GENERAL_PURPOSE7 */
1104 case 0x0cc: /* GENERAL_PURPOSE8 */
1105 case 0x0d0: /* GENERAL_PURPOSE9 */
1106 case 0x0d4: /* GENERAL_PURPOSE10 */
1107 case 0x0d8: /* GENERAL_PURPOSE11 */
1108 case 0x0dc: /* GENERAL_PURPOSE12 */
1109 case 0x0e0: /* GENERAL_PURPOSE13 */
1110 case 0x0e4: /* GENERAL_PURPOSE14 */
1111 case 0x0e8: /* GENERAL_PURPOSE15 */
1112 case 0x0ec: /* GENERAL_PURPOSE16 */
1113 case 0x0f0: /* GENERAL_PURPOSE17 */
1114 case 0x0f4: /* GENERAL_PURPOSE18 */
1115 case 0x0f8: /* GENERAL_PURPOSE19 */
1116 case 0x0fc: /* GENERAL_PURPOSE20 */
1117 return s->scratch[(addr - 0xb0) >> 2];
1118
1119 case 0x140: /* CM_CLKSEL_MPU */
1120 return s->clksel[0];
1121 case 0x148: /* CM_CLKSTCTRL_MPU */
1122 return s->clkctrl[0];
1123
1124 case 0x158: /* RM_RSTST_MPU */
1125 return s->rst[0];
1126 case 0x1c8: /* PM_WKDEP_MPU */
1127 return s->wkup[0];
1128 case 0x1d4: /* PM_EVGENCTRL_MPU */
1129 return s->ev;
1130 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1131 return s->evtime[0];
1132 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1133 return s->evtime[1];
1134 case 0x1e0: /* PM_PWSTCTRL_MPU */
1135 return s->power[0];
1136 case 0x1e4: /* PM_PWSTST_MPU */
1137 return 0;
1138
1139 case 0x200: /* CM_FCLKEN1_CORE */
1140 return s->clken[0];
1141 case 0x204: /* CM_FCLKEN2_CORE */
1142 return s->clken[1];
1143 case 0x210: /* CM_ICLKEN1_CORE */
1144 return s->clken[2];
1145 case 0x214: /* CM_ICLKEN2_CORE */
1146 return s->clken[3];
1147 case 0x21c: /* CM_ICLKEN4_CORE */
1148 return s->clken[4];
1149
1150 case 0x220: /* CM_IDLEST1_CORE */
1151 /* TODO: check the actual iclk status */
1152 return 0x7ffffff9;
1153 case 0x224: /* CM_IDLEST2_CORE */
1154 /* TODO: check the actual iclk status */
1155 return 0x00000007;
1156 case 0x22c: /* CM_IDLEST4_CORE */
1157 /* TODO: check the actual iclk status */
1158 return 0x0000001f;
1159
1160 case 0x230: /* CM_AUTOIDLE1_CORE */
1161 return s->clkidle[0];
1162 case 0x234: /* CM_AUTOIDLE2_CORE */
1163 return s->clkidle[1];
1164 case 0x238: /* CM_AUTOIDLE3_CORE */
1165 return s->clkidle[2];
1166 case 0x23c: /* CM_AUTOIDLE4_CORE */
1167 return s->clkidle[3];
1168
1169 case 0x240: /* CM_CLKSEL1_CORE */
1170 return s->clksel[1];
1171 case 0x244: /* CM_CLKSEL2_CORE */
1172 return s->clksel[2];
1173
1174 case 0x248: /* CM_CLKSTCTRL_CORE */
1175 return s->clkctrl[1];
1176
1177 case 0x2a0: /* PM_WKEN1_CORE */
1178 return s->wken[0];
1179 case 0x2a4: /* PM_WKEN2_CORE */
1180 return s->wken[1];
1181
1182 case 0x2b0: /* PM_WKST1_CORE */
1183 return s->wkst[0];
1184 case 0x2b4: /* PM_WKST2_CORE */
1185 return s->wkst[1];
1186 case 0x2c8: /* PM_WKDEP_CORE */
1187 return 0x1e;
1188
1189 case 0x2e0: /* PM_PWSTCTRL_CORE */
1190 return s->power[1];
1191 case 0x2e4: /* PM_PWSTST_CORE */
1192 return 0x000030 | (s->power[1] & 0xfc00);
1193
1194 case 0x300: /* CM_FCLKEN_GFX */
1195 return s->clken[5];
1196 case 0x310: /* CM_ICLKEN_GFX */
1197 return s->clken[6];
1198 case 0x320: /* CM_IDLEST_GFX */
1199 /* TODO: check the actual iclk status */
1200 return 0x00000001;
1201 case 0x340: /* CM_CLKSEL_GFX */
1202 return s->clksel[3];
1203 case 0x348: /* CM_CLKSTCTRL_GFX */
1204 return s->clkctrl[2];
1205 case 0x350: /* RM_RSTCTRL_GFX */
1206 return s->rstctrl[0];
1207 case 0x358: /* RM_RSTST_GFX */
1208 return s->rst[1];
1209 case 0x3c8: /* PM_WKDEP_GFX */
1210 return s->wkup[1];
1211
1212 case 0x3e0: /* PM_PWSTCTRL_GFX */
1213 return s->power[2];
1214 case 0x3e4: /* PM_PWSTST_GFX */
1215 return s->power[2] & 3;
1216
1217 case 0x400: /* CM_FCLKEN_WKUP */
1218 return s->clken[7];
1219 case 0x410: /* CM_ICLKEN_WKUP */
1220 return s->clken[8];
1221 case 0x420: /* CM_IDLEST_WKUP */
1222 /* TODO: check the actual iclk status */
1223 return 0x0000003f;
1224 case 0x430: /* CM_AUTOIDLE_WKUP */
1225 return s->clkidle[4];
1226 case 0x440: /* CM_CLKSEL_WKUP */
1227 return s->clksel[4];
1228 case 0x450: /* RM_RSTCTRL_WKUP */
1229 return 0;
1230 case 0x454: /* RM_RSTTIME_WKUP */
1231 return s->rsttime_wkup;
1232 case 0x458: /* RM_RSTST_WKUP */
1233 return s->rst[2];
1234 case 0x4a0: /* PM_WKEN_WKUP */
1235 return s->wken[2];
1236 case 0x4b0: /* PM_WKST_WKUP */
1237 return s->wkst[2];
1238
1239 case 0x500: /* CM_CLKEN_PLL */
1240 return s->clken[9];
1241 case 0x520: /* CM_IDLEST_CKGEN */
1242 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
1243 if (!(s->clksel[6] & 3))
1244 /* Core uses 32-kHz clock */
1245 ret |= 3 << 0;
1246 else if (!s->dpll_lock)
1247 /* DPLL not locked, core uses ref_clk */
1248 ret |= 1 << 0;
1249 else
1250 /* Core uses DPLL */
1251 ret |= 2 << 0;
1252 return ret;
1253 case 0x530: /* CM_AUTOIDLE_PLL */
1254 return s->clkidle[5];
1255 case 0x540: /* CM_CLKSEL1_PLL */
1256 return s->clksel[5];
1257 case 0x544: /* CM_CLKSEL2_PLL */
1258 return s->clksel[6];
1259
1260 case 0x800: /* CM_FCLKEN_DSP */
1261 return s->clken[10];
1262 case 0x810: /* CM_ICLKEN_DSP */
1263 return s->clken[11];
1264 case 0x820: /* CM_IDLEST_DSP */
1265 /* TODO: check the actual iclk status */
1266 return 0x00000103;
1267 case 0x830: /* CM_AUTOIDLE_DSP */
1268 return s->clkidle[6];
1269 case 0x840: /* CM_CLKSEL_DSP */
1270 return s->clksel[7];
1271 case 0x848: /* CM_CLKSTCTRL_DSP */
1272 return s->clkctrl[3];
1273 case 0x850: /* RM_RSTCTRL_DSP */
1274 return 0;
1275 case 0x858: /* RM_RSTST_DSP */
1276 return s->rst[3];
1277 case 0x8c8: /* PM_WKDEP_DSP */
1278 return s->wkup[2];
1279 case 0x8e0: /* PM_PWSTCTRL_DSP */
1280 return s->power[3];
1281 case 0x8e4: /* PM_PWSTST_DSP */
1282 return 0x008030 | (s->power[3] & 0x3003);
1283
1284 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1285 return s->irqst[1];
1286 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1287 return s->irqen[1];
1288
1289 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1290 return s->irqst[2];
1291 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1292 return s->irqen[2];
1293 }
1294
1295 OMAP_BAD_REG(addr);
1296 return 0;
1297 }
1298
1299 static void omap_prcm_apll_update(struct omap_prcm_s *s)
1300 {
1301 int mode[2];
1302
1303 mode[0] = (s->clken[9] >> 6) & 3;
1304 s->apll_lock[0] = (mode[0] == 3);
1305 mode[1] = (s->clken[9] >> 2) & 3;
1306 s->apll_lock[1] = (mode[1] == 3);
1307 /* TODO: update clocks */
1308
1309 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[1] == 2)
1310 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
1311 __FUNCTION__);
1312 }
1313
1314 static void omap_prcm_dpll_update(struct omap_prcm_s *s)
1315 {
1316 omap_clk dpll = omap_findclk(s->mpu, "dpll");
1317 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
1318 omap_clk core = omap_findclk(s->mpu, "core_clk");
1319 int mode = (s->clken[9] >> 0) & 3;
1320 int mult, div;
1321
1322 mult = (s->clksel[5] >> 12) & 0x3ff;
1323 div = (s->clksel[5] >> 8) & 0xf;
1324 if (mult == 0 || mult == 1)
1325 mode = 1; /* Bypass */
1326
1327 s->dpll_lock = 0;
1328 switch (mode) {
1329 case 0:
1330 fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
1331 break;
1332 case 1: /* Low-power bypass mode (Default) */
1333 case 2: /* Fast-relock bypass mode */
1334 omap_clk_setrate(dpll, 1, 1);
1335 omap_clk_setrate(dpll_x2, 1, 1);
1336 break;
1337 case 3: /* Lock mode */
1338 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
1339
1340 omap_clk_setrate(dpll, div + 1, mult);
1341 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
1342 break;
1343 }
1344
1345 switch ((s->clksel[6] >> 0) & 3) {
1346 case 0:
1347 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
1348 break;
1349 case 1:
1350 omap_clk_reparent(core, dpll);
1351 break;
1352 case 2:
1353 /* Default */
1354 omap_clk_reparent(core, dpll_x2);
1355 break;
1356 case 3:
1357 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
1358 break;
1359 }
1360 }
1361
1362 static void omap_prcm_write(void *opaque, hwaddr addr,
1363 uint64_t value, unsigned size)
1364 {
1365 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
1366
1367 if (size != 4) {
1368 omap_badwidth_write32(opaque, addr, value);
1369 return;
1370 }
1371
1372 switch (addr) {
1373 case 0x000: /* PRCM_REVISION */
1374 case 0x054: /* PRCM_VOLTST */
1375 case 0x084: /* PRCM_CLKCFG_STATUS */
1376 case 0x1e4: /* PM_PWSTST_MPU */
1377 case 0x220: /* CM_IDLEST1_CORE */
1378 case 0x224: /* CM_IDLEST2_CORE */
1379 case 0x22c: /* CM_IDLEST4_CORE */
1380 case 0x2c8: /* PM_WKDEP_CORE */
1381 case 0x2e4: /* PM_PWSTST_CORE */
1382 case 0x320: /* CM_IDLEST_GFX */
1383 case 0x3e4: /* PM_PWSTST_GFX */
1384 case 0x420: /* CM_IDLEST_WKUP */
1385 case 0x520: /* CM_IDLEST_CKGEN */
1386 case 0x820: /* CM_IDLEST_DSP */
1387 case 0x8e4: /* PM_PWSTST_DSP */
1388 OMAP_RO_REG(addr);
1389 return;
1390
1391 case 0x010: /* PRCM_SYSCONFIG */
1392 s->sysconfig = value & 1;
1393 break;
1394
1395 case 0x018: /* PRCM_IRQSTATUS_MPU */
1396 s->irqst[0] &= ~value;
1397 omap_prcm_int_update(s, 0);
1398 break;
1399 case 0x01c: /* PRCM_IRQENABLE_MPU */
1400 s->irqen[0] = value & 0x3f;
1401 omap_prcm_int_update(s, 0);
1402 break;
1403
1404 case 0x050: /* PRCM_VOLTCTRL */
1405 s->voltctrl = value & 0xf1c3;
1406 break;
1407
1408 case 0x060: /* PRCM_CLKSRC_CTRL */
1409 s->clksrc[0] = value & 0xdb;
1410 /* TODO update clocks */
1411 break;
1412
1413 case 0x070: /* PRCM_CLKOUT_CTRL */
1414 s->clkout[0] = value & 0xbbbb;
1415 /* TODO update clocks */
1416 break;
1417
1418 case 0x078: /* PRCM_CLKEMUL_CTRL */
1419 s->clkemul[0] = value & 1;
1420 /* TODO update clocks */
1421 break;
1422
1423 case 0x080: /* PRCM_CLKCFG_CTRL */
1424 break;
1425
1426 case 0x090: /* PRCM_VOLTSETUP */
1427 s->setuptime[0] = value & 0xffff;
1428 break;
1429 case 0x094: /* PRCM_CLKSSETUP */
1430 s->setuptime[1] = value & 0xffff;
1431 break;
1432
1433 case 0x098: /* PRCM_POLCTRL */
1434 s->clkpol[0] = value & 0x701;
1435 break;
1436
1437 case 0x0b0: /* GENERAL_PURPOSE1 */
1438 case 0x0b4: /* GENERAL_PURPOSE2 */
1439 case 0x0b8: /* GENERAL_PURPOSE3 */
1440 case 0x0bc: /* GENERAL_PURPOSE4 */
1441 case 0x0c0: /* GENERAL_PURPOSE5 */
1442 case 0x0c4: /* GENERAL_PURPOSE6 */
1443 case 0x0c8: /* GENERAL_PURPOSE7 */
1444 case 0x0cc: /* GENERAL_PURPOSE8 */
1445 case 0x0d0: /* GENERAL_PURPOSE9 */
1446 case 0x0d4: /* GENERAL_PURPOSE10 */
1447 case 0x0d8: /* GENERAL_PURPOSE11 */
1448 case 0x0dc: /* GENERAL_PURPOSE12 */
1449 case 0x0e0: /* GENERAL_PURPOSE13 */
1450 case 0x0e4: /* GENERAL_PURPOSE14 */
1451 case 0x0e8: /* GENERAL_PURPOSE15 */
1452 case 0x0ec: /* GENERAL_PURPOSE16 */
1453 case 0x0f0: /* GENERAL_PURPOSE17 */
1454 case 0x0f4: /* GENERAL_PURPOSE18 */
1455 case 0x0f8: /* GENERAL_PURPOSE19 */
1456 case 0x0fc: /* GENERAL_PURPOSE20 */
1457 s->scratch[(addr - 0xb0) >> 2] = value;
1458 break;
1459
1460 case 0x140: /* CM_CLKSEL_MPU */
1461 s->clksel[0] = value & 0x1f;
1462 /* TODO update clocks */
1463 break;
1464 case 0x148: /* CM_CLKSTCTRL_MPU */
1465 s->clkctrl[0] = value & 0x1f;
1466 break;
1467
1468 case 0x158: /* RM_RSTST_MPU */
1469 s->rst[0] &= ~value;
1470 break;
1471 case 0x1c8: /* PM_WKDEP_MPU */
1472 s->wkup[0] = value & 0x15;
1473 break;
1474
1475 case 0x1d4: /* PM_EVGENCTRL_MPU */
1476 s->ev = value & 0x1f;
1477 break;
1478 case 0x1d8: /* PM_EVEGENONTIM_MPU */
1479 s->evtime[0] = value;
1480 break;
1481 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
1482 s->evtime[1] = value;
1483 break;
1484
1485 case 0x1e0: /* PM_PWSTCTRL_MPU */
1486 s->power[0] = value & 0xc0f;
1487 break;
1488
1489 case 0x200: /* CM_FCLKEN1_CORE */
1490 s->clken[0] = value & 0xbfffffff;
1491 /* TODO update clocks */
1492 /* The EN_EAC bit only gets/puts func_96m_clk. */
1493 break;
1494 case 0x204: /* CM_FCLKEN2_CORE */
1495 s->clken[1] = value & 0x00000007;
1496 /* TODO update clocks */
1497 break;
1498 case 0x210: /* CM_ICLKEN1_CORE */
1499 s->clken[2] = value & 0xfffffff9;
1500 /* TODO update clocks */
1501 /* The EN_EAC bit only gets/puts core_l4_iclk. */
1502 break;
1503 case 0x214: /* CM_ICLKEN2_CORE */
1504 s->clken[3] = value & 0x00000007;
1505 /* TODO update clocks */
1506 break;
1507 case 0x21c: /* CM_ICLKEN4_CORE */
1508 s->clken[4] = value & 0x0000001f;
1509 /* TODO update clocks */
1510 break;
1511
1512 case 0x230: /* CM_AUTOIDLE1_CORE */
1513 s->clkidle[0] = value & 0xfffffff9;
1514 /* TODO update clocks */
1515 break;
1516 case 0x234: /* CM_AUTOIDLE2_CORE */
1517 s->clkidle[1] = value & 0x00000007;
1518 /* TODO update clocks */
1519 break;
1520 case 0x238: /* CM_AUTOIDLE3_CORE */
1521 s->clkidle[2] = value & 0x00000007;
1522 /* TODO update clocks */
1523 break;
1524 case 0x23c: /* CM_AUTOIDLE4_CORE */
1525 s->clkidle[3] = value & 0x0000001f;
1526 /* TODO update clocks */
1527 break;
1528
1529 case 0x240: /* CM_CLKSEL1_CORE */
1530 s->clksel[1] = value & 0x0fffbf7f;
1531 /* TODO update clocks */
1532 break;
1533
1534 case 0x244: /* CM_CLKSEL2_CORE */
1535 s->clksel[2] = value & 0x00fffffc;
1536 /* TODO update clocks */
1537 break;
1538
1539 case 0x248: /* CM_CLKSTCTRL_CORE */
1540 s->clkctrl[1] = value & 0x7;
1541 break;
1542
1543 case 0x2a0: /* PM_WKEN1_CORE */
1544 s->wken[0] = value & 0x04667ff8;
1545 break;
1546 case 0x2a4: /* PM_WKEN2_CORE */
1547 s->wken[1] = value & 0x00000005;
1548 break;
1549
1550 case 0x2b0: /* PM_WKST1_CORE */
1551 s->wkst[0] &= ~value;
1552 break;
1553 case 0x2b4: /* PM_WKST2_CORE */
1554 s->wkst[1] &= ~value;
1555 break;
1556
1557 case 0x2e0: /* PM_PWSTCTRL_CORE */
1558 s->power[1] = (value & 0x00fc3f) | (1 << 2);
1559 break;
1560
1561 case 0x300: /* CM_FCLKEN_GFX */
1562 s->clken[5] = value & 6;
1563 /* TODO update clocks */
1564 break;
1565 case 0x310: /* CM_ICLKEN_GFX */
1566 s->clken[6] = value & 1;
1567 /* TODO update clocks */
1568 break;
1569 case 0x340: /* CM_CLKSEL_GFX */
1570 s->clksel[3] = value & 7;
1571 /* TODO update clocks */
1572 break;
1573 case 0x348: /* CM_CLKSTCTRL_GFX */
1574 s->clkctrl[2] = value & 1;
1575 break;
1576 case 0x350: /* RM_RSTCTRL_GFX */
1577 s->rstctrl[0] = value & 1;
1578 /* TODO: reset */
1579 break;
1580 case 0x358: /* RM_RSTST_GFX */
1581 s->rst[1] &= ~value;
1582 break;
1583 case 0x3c8: /* PM_WKDEP_GFX */
1584 s->wkup[1] = value & 0x13;
1585 break;
1586 case 0x3e0: /* PM_PWSTCTRL_GFX */
1587 s->power[2] = (value & 0x00c0f) | (3 << 2);
1588 break;
1589
1590 case 0x400: /* CM_FCLKEN_WKUP */
1591 s->clken[7] = value & 0xd;
1592 /* TODO update clocks */
1593 break;
1594 case 0x410: /* CM_ICLKEN_WKUP */
1595 s->clken[8] = value & 0x3f;
1596 /* TODO update clocks */
1597 break;
1598 case 0x430: /* CM_AUTOIDLE_WKUP */
1599 s->clkidle[4] = value & 0x0000003f;
1600 /* TODO update clocks */
1601 break;
1602 case 0x440: /* CM_CLKSEL_WKUP */
1603 s->clksel[4] = value & 3;
1604 /* TODO update clocks */
1605 break;
1606 case 0x450: /* RM_RSTCTRL_WKUP */
1607 /* TODO: reset */
1608 if (value & 2)
1609 qemu_system_reset_request();
1610 break;
1611 case 0x454: /* RM_RSTTIME_WKUP */
1612 s->rsttime_wkup = value & 0x1fff;
1613 break;
1614 case 0x458: /* RM_RSTST_WKUP */
1615 s->rst[2] &= ~value;
1616 break;
1617 case 0x4a0: /* PM_WKEN_WKUP */
1618 s->wken[2] = value & 0x00000005;
1619 break;
1620 case 0x4b0: /* PM_WKST_WKUP */
1621 s->wkst[2] &= ~value;
1622 break;
1623
1624 case 0x500: /* CM_CLKEN_PLL */
1625 if (value & 0xffffff30)
1626 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
1627 "future compatibility\n", __FUNCTION__);
1628 if ((s->clken[9] ^ value) & 0xcc) {
1629 s->clken[9] &= ~0xcc;
1630 s->clken[9] |= value & 0xcc;
1631 omap_prcm_apll_update(s);
1632 }
1633 if ((s->clken[9] ^ value) & 3) {
1634 s->clken[9] &= ~3;
1635 s->clken[9] |= value & 3;
1636 omap_prcm_dpll_update(s);
1637 }
1638 break;
1639 case 0x530: /* CM_AUTOIDLE_PLL */
1640 s->clkidle[5] = value & 0x000000cf;
1641 /* TODO update clocks */
1642 break;
1643 case 0x540: /* CM_CLKSEL1_PLL */
1644 if (value & 0xfc4000d7)
1645 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
1646 "future compatibility\n", __FUNCTION__);
1647 if ((s->clksel[5] ^ value) & 0x003fff00) {
1648 s->clksel[5] = value & 0x03bfff28;
1649 omap_prcm_dpll_update(s);
1650 }
1651 /* TODO update the other clocks */
1652
1653 s->clksel[5] = value & 0x03bfff28;
1654 break;
1655 case 0x544: /* CM_CLKSEL2_PLL */
1656 if (value & ~3)
1657 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
1658 "future compatibility\n", __FUNCTION__);
1659 if (s->clksel[6] != (value & 3)) {
1660 s->clksel[6] = value & 3;
1661 omap_prcm_dpll_update(s);
1662 }
1663 break;
1664
1665 case 0x800: /* CM_FCLKEN_DSP */
1666 s->clken[10] = value & 0x501;
1667 /* TODO update clocks */
1668 break;
1669 case 0x810: /* CM_ICLKEN_DSP */
1670 s->clken[11] = value & 0x2;
1671 /* TODO update clocks */
1672 break;
1673 case 0x830: /* CM_AUTOIDLE_DSP */
1674 s->clkidle[6] = value & 0x2;
1675 /* TODO update clocks */
1676 break;
1677 case 0x840: /* CM_CLKSEL_DSP */
1678 s->clksel[7] = value & 0x3fff;
1679 /* TODO update clocks */
1680 break;
1681 case 0x848: /* CM_CLKSTCTRL_DSP */
1682 s->clkctrl[3] = value & 0x101;
1683 break;
1684 case 0x850: /* RM_RSTCTRL_DSP */
1685 /* TODO: reset */
1686 break;
1687 case 0x858: /* RM_RSTST_DSP */
1688 s->rst[3] &= ~value;
1689 break;
1690 case 0x8c8: /* PM_WKDEP_DSP */
1691 s->wkup[2] = value & 0x13;
1692 break;
1693 case 0x8e0: /* PM_PWSTCTRL_DSP */
1694 s->power[3] = (value & 0x03017) | (3 << 2);
1695 break;
1696
1697 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
1698 s->irqst[1] &= ~value;
1699 omap_prcm_int_update(s, 1);
1700 break;
1701 case 0x8f4: /* PRCM_IRQENABLE_DSP */
1702 s->irqen[1] = value & 0x7;
1703 omap_prcm_int_update(s, 1);
1704 break;
1705
1706 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
1707 s->irqst[2] &= ~value;
1708 omap_prcm_int_update(s, 2);
1709 break;
1710 case 0x8fc: /* PRCM_IRQENABLE_IVA */
1711 s->irqen[2] = value & 0x7;
1712 omap_prcm_int_update(s, 2);
1713 break;
1714
1715 default:
1716 OMAP_BAD_REG(addr);
1717 return;
1718 }
1719 }
1720
1721 static const MemoryRegionOps omap_prcm_ops = {
1722 .read = omap_prcm_read,
1723 .write = omap_prcm_write,
1724 .endianness = DEVICE_NATIVE_ENDIAN,
1725 };
1726
1727 static void omap_prcm_reset(struct omap_prcm_s *s)
1728 {
1729 s->sysconfig = 0;
1730 s->irqst[0] = 0;
1731 s->irqst[1] = 0;
1732 s->irqst[2] = 0;
1733 s->irqen[0] = 0;
1734 s->irqen[1] = 0;
1735 s->irqen[2] = 0;
1736 s->voltctrl = 0x1040;
1737 s->ev = 0x14;
1738 s->evtime[0] = 0;
1739 s->evtime[1] = 0;
1740 s->clkctrl[0] = 0;
1741 s->clkctrl[1] = 0;
1742 s->clkctrl[2] = 0;
1743 s->clkctrl[3] = 0;
1744 s->clken[1] = 7;
1745 s->clken[3] = 7;
1746 s->clken[4] = 0;
1747 s->clken[5] = 0;
1748 s->clken[6] = 0;
1749 s->clken[7] = 0xc;
1750 s->clken[8] = 0x3e;
1751 s->clken[9] = 0x0d;
1752 s->clken[10] = 0;
1753 s->clken[11] = 0;
1754 s->clkidle[0] = 0;
1755 s->clkidle[2] = 7;
1756 s->clkidle[3] = 0;
1757 s->clkidle[4] = 0;
1758 s->clkidle[5] = 0x0c;
1759 s->clkidle[6] = 0;
1760 s->clksel[0] = 0x01;
1761 s->clksel[1] = 0x02100121;
1762 s->clksel[2] = 0x00000000;
1763 s->clksel[3] = 0x01;
1764 s->clksel[4] = 0;
1765 s->clksel[7] = 0x0121;
1766 s->wkup[0] = 0x15;
1767 s->wkup[1] = 0x13;
1768 s->wkup[2] = 0x13;
1769 s->wken[0] = 0x04667ff8;
1770 s->wken[1] = 0x00000005;
1771 s->wken[2] = 5;
1772 s->wkst[0] = 0;
1773 s->wkst[1] = 0;
1774 s->wkst[2] = 0;
1775 s->power[0] = 0x00c;
1776 s->power[1] = 4;
1777 s->power[2] = 0x0000c;
1778 s->power[3] = 0x14;
1779 s->rstctrl[0] = 1;
1780 s->rst[3] = 1;
1781 omap_prcm_apll_update(s);
1782 omap_prcm_dpll_update(s);
1783 }
1784
1785 static void omap_prcm_coldreset(struct omap_prcm_s *s)
1786 {
1787 s->setuptime[0] = 0;
1788 s->setuptime[1] = 0;
1789 memset(&s->scratch, 0, sizeof(s->scratch));
1790 s->rst[0] = 0x01;
1791 s->rst[1] = 0x00;
1792 s->rst[2] = 0x01;
1793 s->clken[0] = 0;
1794 s->clken[2] = 0;
1795 s->clkidle[1] = 0;
1796 s->clksel[5] = 0;
1797 s->clksel[6] = 2;
1798 s->clksrc[0] = 0x43;
1799 s->clkout[0] = 0x0303;
1800 s->clkemul[0] = 0;
1801 s->clkpol[0] = 0x100;
1802 s->rsttime_wkup = 0x1002;
1803
1804 omap_prcm_reset(s);
1805 }
1806
1807 static struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
1808 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
1809 struct omap_mpu_state_s *mpu)
1810 {
1811 struct omap_prcm_s *s = g_new0(struct omap_prcm_s, 1);
1812
1813 s->irq[0] = mpu_int;
1814 s->irq[1] = dsp_int;
1815 s->irq[2] = iva_int;
1816 s->mpu = mpu;
1817 omap_prcm_coldreset(s);
1818
1819 memory_region_init_io(&s->iomem0, NULL, &omap_prcm_ops, s, "omap.pcrm0",
1820 omap_l4_region_size(ta, 0));
1821 memory_region_init_io(&s->iomem1, NULL, &omap_prcm_ops, s, "omap.pcrm1",
1822 omap_l4_region_size(ta, 1));
1823 omap_l4_attach(ta, 0, &s->iomem0);
1824 omap_l4_attach(ta, 1, &s->iomem1);
1825
1826 return s;
1827 }
1828
1829 /* System and Pinout control */
1830 struct omap_sysctl_s {
1831 struct omap_mpu_state_s *mpu;
1832 MemoryRegion iomem;
1833
1834 uint32_t sysconfig;
1835 uint32_t devconfig;
1836 uint32_t psaconfig;
1837 uint32_t padconf[0x45];
1838 uint8_t obs;
1839 uint32_t msuspendmux[5];
1840 };
1841
1842 static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
1843 {
1844
1845 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1846 int pad_offset, byte_offset;
1847 int value;
1848
1849 switch (addr) {
1850 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1851 pad_offset = (addr - 0x30) >> 2;
1852 byte_offset = (addr - 0x30) & (4 - 1);
1853
1854 value = s->padconf[pad_offset];
1855 value = (value >> (byte_offset * 8)) & 0xff;
1856
1857 return value;
1858
1859 default:
1860 break;
1861 }
1862
1863 OMAP_BAD_REG(addr);
1864 return 0;
1865 }
1866
1867 static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
1868 {
1869 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1870
1871 switch (addr) {
1872 case 0x000: /* CONTROL_REVISION */
1873 return 0x20;
1874
1875 case 0x010: /* CONTROL_SYSCONFIG */
1876 return s->sysconfig;
1877
1878 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1879 return s->padconf[(addr - 0x30) >> 2];
1880
1881 case 0x270: /* CONTROL_DEBOBS */
1882 return s->obs;
1883
1884 case 0x274: /* CONTROL_DEVCONF */
1885 return s->devconfig;
1886
1887 case 0x28c: /* CONTROL_EMU_SUPPORT */
1888 return 0;
1889
1890 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
1891 return s->msuspendmux[0];
1892 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
1893 return s->msuspendmux[1];
1894 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
1895 return s->msuspendmux[2];
1896 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
1897 return s->msuspendmux[3];
1898 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
1899 return s->msuspendmux[4];
1900 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1901 return 0;
1902
1903 case 0x2b8: /* CONTROL_PSA_CTRL */
1904 return s->psaconfig;
1905 case 0x2bc: /* CONTROL_PSA_CMD */
1906 case 0x2c0: /* CONTROL_PSA_VALUE */
1907 return 0;
1908
1909 case 0x2b0: /* CONTROL_SEC_CTRL */
1910 return 0x800000f1;
1911 case 0x2d0: /* CONTROL_SEC_EMU */
1912 return 0x80000015;
1913 case 0x2d4: /* CONTROL_SEC_TAP */
1914 return 0x8000007f;
1915 case 0x2b4: /* CONTROL_SEC_TEST */
1916 case 0x2f0: /* CONTROL_SEC_STATUS */
1917 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
1918 /* Secure mode is not present on general-pusrpose device. Outside
1919 * secure mode these values cannot be read or written. */
1920 return 0;
1921
1922 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
1923 return 0xff;
1924 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
1925 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
1926 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
1927 /* No secure mode so no Extended Secure RAM present. */
1928 return 0;
1929
1930 case 0x2f8: /* CONTROL_STATUS */
1931 /* Device Type => General-purpose */
1932 return 0x0300;
1933 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
1934
1935 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
1936 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
1937 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
1938 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
1939 return 0xdecafbad;
1940
1941 case 0x310: /* CONTROL_RAND_KEY_0 */
1942 case 0x314: /* CONTROL_RAND_KEY_1 */
1943 case 0x318: /* CONTROL_RAND_KEY_2 */
1944 case 0x31c: /* CONTROL_RAND_KEY_3 */
1945 case 0x320: /* CONTROL_CUST_KEY_0 */
1946 case 0x324: /* CONTROL_CUST_KEY_1 */
1947 case 0x330: /* CONTROL_TEST_KEY_0 */
1948 case 0x334: /* CONTROL_TEST_KEY_1 */
1949 case 0x338: /* CONTROL_TEST_KEY_2 */
1950 case 0x33c: /* CONTROL_TEST_KEY_3 */
1951 case 0x340: /* CONTROL_TEST_KEY_4 */
1952 case 0x344: /* CONTROL_TEST_KEY_5 */
1953 case 0x348: /* CONTROL_TEST_KEY_6 */
1954 case 0x34c: /* CONTROL_TEST_KEY_7 */
1955 case 0x350: /* CONTROL_TEST_KEY_8 */
1956 case 0x354: /* CONTROL_TEST_KEY_9 */
1957 /* Can only be accessed in secure mode and when C_FieldAccEnable
1958 * bit is set in CONTROL_SEC_CTRL.
1959 * TODO: otherwise an interconnect access error is generated. */
1960 return 0;
1961 }
1962
1963 OMAP_BAD_REG(addr);
1964 return 0;
1965 }
1966
1967 static void omap_sysctl_write8(void *opaque, hwaddr addr,
1968 uint32_t value)
1969 {
1970 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1971 int pad_offset, byte_offset;
1972 int prev_value;
1973
1974 switch (addr) {
1975 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
1976 pad_offset = (addr - 0x30) >> 2;
1977 byte_offset = (addr - 0x30) & (4 - 1);
1978
1979 prev_value = s->padconf[pad_offset];
1980 prev_value &= ~(0xff << (byte_offset * 8));
1981 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
1982 s->padconf[pad_offset] = prev_value;
1983 break;
1984
1985 default:
1986 OMAP_BAD_REG(addr);
1987 break;
1988 }
1989 }
1990
1991 static void omap_sysctl_write(void *opaque, hwaddr addr,
1992 uint32_t value)
1993 {
1994 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
1995
1996 switch (addr) {
1997 case 0x000: /* CONTROL_REVISION */
1998 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
1999 case 0x2c0: /* CONTROL_PSA_VALUE */
2000 case 0x2f8: /* CONTROL_STATUS */
2001 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
2002 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
2003 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
2004 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
2005 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
2006 case 0x310: /* CONTROL_RAND_KEY_0 */
2007 case 0x314: /* CONTROL_RAND_KEY_1 */
2008 case 0x318: /* CONTROL_RAND_KEY_2 */
2009 case 0x31c: /* CONTROL_RAND_KEY_3 */
2010 case 0x320: /* CONTROL_CUST_KEY_0 */
2011 case 0x324: /* CONTROL_CUST_KEY_1 */
2012 case 0x330: /* CONTROL_TEST_KEY_0 */
2013 case 0x334: /* CONTROL_TEST_KEY_1 */
2014 case 0x338: /* CONTROL_TEST_KEY_2 */
2015 case 0x33c: /* CONTROL_TEST_KEY_3 */
2016 case 0x340: /* CONTROL_TEST_KEY_4 */
2017 case 0x344: /* CONTROL_TEST_KEY_5 */
2018 case 0x348: /* CONTROL_TEST_KEY_6 */
2019 case 0x34c: /* CONTROL_TEST_KEY_7 */
2020 case 0x350: /* CONTROL_TEST_KEY_8 */
2021 case 0x354: /* CONTROL_TEST_KEY_9 */
2022 OMAP_RO_REG(addr);
2023 return;
2024
2025 case 0x010: /* CONTROL_SYSCONFIG */
2026 s->sysconfig = value & 0x1e;
2027 break;
2028
2029 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
2030 /* XXX: should check constant bits */
2031 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
2032 break;
2033
2034 case 0x270: /* CONTROL_DEBOBS */
2035 s->obs = value & 0xff;
2036 break;
2037
2038 case 0x274: /* CONTROL_DEVCONF */
2039 s->devconfig = value & 0xffffc7ff;
2040 break;
2041
2042 case 0x28c: /* CONTROL_EMU_SUPPORT */
2043 break;
2044
2045 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
2046 s->msuspendmux[0] = value & 0x3fffffff;
2047 break;
2048 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
2049 s->msuspendmux[1] = value & 0x3fffffff;
2050 break;
2051 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
2052 s->msuspendmux[2] = value & 0x3fffffff;
2053 break;
2054 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
2055 s->msuspendmux[3] = value & 0x3fffffff;
2056 break;
2057 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
2058 s->msuspendmux[4] = value & 0x3fffffff;
2059 break;
2060
2061 case 0x2b8: /* CONTROL_PSA_CTRL */
2062 s->psaconfig = value & 0x1c;
2063 s->psaconfig |= (value & 0x20) ? 2 : 1;
2064 break;
2065 case 0x2bc: /* CONTROL_PSA_CMD */
2066 break;
2067
2068 case 0x2b0: /* CONTROL_SEC_CTRL */
2069 case 0x2b4: /* CONTROL_SEC_TEST */
2070 case 0x2d0: /* CONTROL_SEC_EMU */
2071 case 0x2d4: /* CONTROL_SEC_TAP */
2072 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
2073 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
2074 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
2075 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
2076 case 0x2f0: /* CONTROL_SEC_STATUS */
2077 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
2078 break;
2079
2080 default:
2081 OMAP_BAD_REG(addr);
2082 return;
2083 }
2084 }
2085
2086 static const MemoryRegionOps omap_sysctl_ops = {
2087 .old_mmio = {
2088 .read = {
2089 omap_sysctl_read8,
2090 omap_badwidth_read32, /* TODO */
2091 omap_sysctl_read,
2092 },
2093 .write = {
2094 omap_sysctl_write8,
2095 omap_badwidth_write32, /* TODO */
2096 omap_sysctl_write,
2097 },
2098 },
2099 .endianness = DEVICE_NATIVE_ENDIAN,
2100 };
2101
2102 static void omap_sysctl_reset(struct omap_sysctl_s *s)
2103 {
2104 /* (power-on reset) */
2105 s->sysconfig = 0;
2106 s->obs = 0;
2107 s->devconfig = 0x0c000000;
2108 s->msuspendmux[0] = 0x00000000;
2109 s->msuspendmux[1] = 0x00000000;
2110 s->msuspendmux[2] = 0x00000000;
2111 s->msuspendmux[3] = 0x00000000;
2112 s->msuspendmux[4] = 0x00000000;
2113 s->psaconfig = 1;
2114
2115 s->padconf[0x00] = 0x000f0f0f;
2116 s->padconf[0x01] = 0x00000000;
2117 s->padconf[0x02] = 0x00000000;
2118 s->padconf[0x03] = 0x00000000;
2119 s->padconf[0x04] = 0x00000000;
2120 s->padconf[0x05] = 0x00000000;
2121 s->padconf[0x06] = 0x00000000;
2122 s->padconf[0x07] = 0x00000000;
2123 s->padconf[0x08] = 0x08080800;
2124 s->padconf[0x09] = 0x08080808;
2125 s->padconf[0x0a] = 0x08080808;
2126 s->padconf[0x0b] = 0x08080808;
2127 s->padconf[0x0c] = 0x08080808;
2128 s->padconf[0x0d] = 0x08080800;
2129 s->padconf[0x0e] = 0x08080808;
2130 s->padconf[0x0f] = 0x08080808;
2131 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
2132 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
2133 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
2134 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
2135 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
2136 s->padconf[0x15] = 0x18181818;
2137 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
2138 s->padconf[0x17] = 0x1f001f00;
2139 s->padconf[0x18] = 0x1f1f1f1f;
2140 s->padconf[0x19] = 0x00000000;
2141 s->padconf[0x1a] = 0x1f180000;
2142 s->padconf[0x1b] = 0x00001f1f;
2143 s->padconf[0x1c] = 0x1f001f00;
2144 s->padconf[0x1d] = 0x00000000;
2145 s->padconf[0x1e] = 0x00000000;
2146 s->padconf[0x1f] = 0x08000000;
2147 s->padconf[0x20] = 0x08080808;
2148 s->padconf[0x21] = 0x08080808;
2149 s->padconf[0x22] = 0x0f080808;
2150 s->padconf[0x23] = 0x0f0f0f0f;
2151 s->padconf[0x24] = 0x000f0f0f;
2152 s->padconf[0x25] = 0x1f1f1f0f;
2153 s->padconf[0x26] = 0x080f0f1f;
2154 s->padconf[0x27] = 0x070f1808;
2155 s->padconf[0x28] = 0x0f070707;
2156 s->padconf[0x29] = 0x000f0f1f;
2157 s->padconf[0x2a] = 0x0f0f0f1f;
2158 s->padconf[0x2b] = 0x08000000;
2159 s->padconf[0x2c] = 0x0000001f;
2160 s->padconf[0x2d] = 0x0f0f1f00;
2161 s->padconf[0x2e] = 0x1f1f0f0f;
2162 s->padconf[0x2f] = 0x0f1f1f1f;
2163 s->padconf[0x30] = 0x0f0f0f0f;
2164 s->padconf[0x31] = 0x0f1f0f1f;
2165 s->padconf[0x32] = 0x0f0f0f0f;
2166 s->padconf[0x33] = 0x0f1f0f1f;
2167 s->padconf[0x34] = 0x1f1f0f0f;
2168 s->padconf[0x35] = 0x0f0f1f1f;
2169 s->padconf[0x36] = 0x0f0f1f0f;
2170 s->padconf[0x37] = 0x0f0f0f0f;
2171 s->padconf[0x38] = 0x1f18180f;
2172 s->padconf[0x39] = 0x1f1f1f1f;
2173 s->padconf[0x3a] = 0x00001f1f;
2174 s->padconf[0x3b] = 0x00000000;
2175 s->padconf[0x3c] = 0x00000000;
2176 s->padconf[0x3d] = 0x0f0f0f0f;
2177 s->padconf[0x3e] = 0x18000f0f;
2178 s->padconf[0x3f] = 0x00070000;
2179 s->padconf[0x40] = 0x00000707;
2180 s->padconf[0x41] = 0x0f1f0700;
2181 s->padconf[0x42] = 0x1f1f070f;
2182 s->padconf[0x43] = 0x0008081f;
2183 s->padconf[0x44] = 0x00000800;
2184 }
2185
2186 static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
2187 omap_clk iclk, struct omap_mpu_state_s *mpu)
2188 {
2189 struct omap_sysctl_s *s = g_new0(struct omap_sysctl_s, 1);
2190
2191 s->mpu = mpu;
2192 omap_sysctl_reset(s);
2193
2194 memory_region_init_io(&s->iomem, NULL, &omap_sysctl_ops, s, "omap.sysctl",
2195 omap_l4_region_size(ta, 0));
2196 omap_l4_attach(ta, 0, &s->iomem);
2197
2198 return s;
2199 }
2200
2201 /* General chip reset */
2202 static void omap2_mpu_reset(void *opaque)
2203 {
2204 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
2205
2206 omap_dma_reset(mpu->dma);
2207 omap_prcm_reset(mpu->prcm);
2208 omap_sysctl_reset(mpu->sysc);
2209 omap_gp_timer_reset(mpu->gptimer[0]);
2210 omap_gp_timer_reset(mpu->gptimer[1]);
2211 omap_gp_timer_reset(mpu->gptimer[2]);
2212 omap_gp_timer_reset(mpu->gptimer[3]);
2213 omap_gp_timer_reset(mpu->gptimer[4]);
2214 omap_gp_timer_reset(mpu->gptimer[5]);
2215 omap_gp_timer_reset(mpu->gptimer[6]);
2216 omap_gp_timer_reset(mpu->gptimer[7]);
2217 omap_gp_timer_reset(mpu->gptimer[8]);
2218 omap_gp_timer_reset(mpu->gptimer[9]);
2219 omap_gp_timer_reset(mpu->gptimer[10]);
2220 omap_gp_timer_reset(mpu->gptimer[11]);
2221 omap_synctimer_reset(mpu->synctimer);
2222 omap_sdrc_reset(mpu->sdrc);
2223 omap_gpmc_reset(mpu->gpmc);
2224 omap_dss_reset(mpu->dss);
2225 omap_uart_reset(mpu->uart[0]);
2226 omap_uart_reset(mpu->uart[1]);
2227 omap_uart_reset(mpu->uart[2]);
2228 omap_mmc_reset(mpu->mmc);
2229 omap_mcspi_reset(mpu->mcspi[0]);
2230 omap_mcspi_reset(mpu->mcspi[1]);
2231 cpu_reset(CPU(mpu->cpu));
2232 }
2233
2234 static int omap2_validate_addr(struct omap_mpu_state_s *s,
2235 hwaddr addr)
2236 {
2237 return 1;
2238 }
2239
2240 static const struct dma_irq_map omap2_dma_irq_map[] = {
2241 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
2242 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
2243 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
2244 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
2245 };
2246
2247 struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
2248 unsigned long sdram_size,
2249 const char *core)
2250 {
2251 struct omap_mpu_state_s *s = g_new0(struct omap_mpu_state_s, 1);
2252 qemu_irq dma_irqs[4];
2253 DriveInfo *dinfo;
2254 int i;
2255 SysBusDevice *busdev;
2256 struct omap_target_agent_s *ta;
2257
2258 /* Core */
2259 s->mpu_model = omap2420;
2260 s->cpu = cpu_arm_init(core ?: "arm1136-r2");
2261 if (s->cpu == NULL) {
2262 fprintf(stderr, "Unable to find CPU definition\n");
2263 exit(1);
2264 }
2265 s->sdram_size = sdram_size;
2266 s->sram_size = OMAP242X_SRAM_SIZE;
2267
2268 s->wakeup = qemu_allocate_irq(omap_mpu_wakeup, s, 0);
2269
2270 /* Clocks */
2271 omap_clk_init(s);
2272
2273 /* Memory-mapped stuff */
2274 memory_region_allocate_system_memory(&s->sdram, NULL, "omap2.dram",
2275 s->sdram_size);
2276 memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
2277 memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size,
2278 &error_fatal);
2279 vmstate_register_ram_global(&s->sram);
2280 memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
2281
2282 s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
2283
2284 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
2285 s->ih[0] = qdev_create(NULL, "omap2-intc");
2286 qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
2287 qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk"));
2288 qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk"));
2289 qdev_init_nofail(s->ih[0]);
2290 busdev = SYS_BUS_DEVICE(s->ih[0]);
2291 sysbus_connect_irq(busdev, 0,
2292 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
2293 sysbus_connect_irq(busdev, 1,
2294 qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_FIQ));
2295 sysbus_mmio_map(busdev, 0, 0x480fe000);
2296 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
2297 qdev_get_gpio_in(s->ih[0],
2298 OMAP_INT_24XX_PRCM_MPU_IRQ),
2299 NULL, NULL, s);
2300
2301 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
2302 omap_findclk(s, "omapctrl_iclk"), s);
2303
2304 for (i = 0; i < 4; i++) {
2305 dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih],
2306 omap2_dma_irq_map[i].intr);
2307 }
2308 s->dma = omap_dma4_init(0x48056000, dma_irqs, sysmem, s, 256, 32,
2309 omap_findclk(s, "sdma_iclk"),
2310 omap_findclk(s, "sdma_fclk"));
2311 s->port->addr_valid = omap2_validate_addr;
2312
2313 /* Register SDRAM and SRAM ports for fast DMA transfers. */
2314 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram),
2315 OMAP2_Q2_BASE, s->sdram_size);
2316 soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram),
2317 OMAP2_SRAM_BASE, s->sram_size);
2318
2319 s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19),
2320 qdev_get_gpio_in(s->ih[0],
2321 OMAP_INT_24XX_UART1_IRQ),
2322 omap_findclk(s, "uart1_fclk"),
2323 omap_findclk(s, "uart1_iclk"),
2324 s->drq[OMAP24XX_DMA_UART1_TX],
2325 s->drq[OMAP24XX_DMA_UART1_RX],
2326 "uart1",
2327 serial_hds[0]);
2328 s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20),
2329 qdev_get_gpio_in(s->ih[0],
2330 OMAP_INT_24XX_UART2_IRQ),
2331 omap_findclk(s, "uart2_fclk"),
2332 omap_findclk(s, "uart2_iclk"),
2333 s->drq[OMAP24XX_DMA_UART2_TX],
2334 s->drq[OMAP24XX_DMA_UART2_RX],
2335 "uart2",
2336 serial_hds[0] ? serial_hds[1] : NULL);
2337 s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21),
2338 qdev_get_gpio_in(s->ih[0],
2339 OMAP_INT_24XX_UART3_IRQ),
2340 omap_findclk(s, "uart3_fclk"),
2341 omap_findclk(s, "uart3_iclk"),
2342 s->drq[OMAP24XX_DMA_UART3_TX],
2343 s->drq[OMAP24XX_DMA_UART3_RX],
2344 "uart3",
2345 serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
2346
2347 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
2348 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1),
2349 omap_findclk(s, "wu_gpt1_clk"),
2350 omap_findclk(s, "wu_l4_iclk"));
2351 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
2352 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2),
2353 omap_findclk(s, "core_gpt2_clk"),
2354 omap_findclk(s, "core_l4_iclk"));
2355 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
2356 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3),
2357 omap_findclk(s, "core_gpt3_clk"),
2358 omap_findclk(s, "core_l4_iclk"));
2359 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
2360 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4),
2361 omap_findclk(s, "core_gpt4_clk"),
2362 omap_findclk(s, "core_l4_iclk"));
2363 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
2364 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5),
2365 omap_findclk(s, "core_gpt5_clk"),
2366 omap_findclk(s, "core_l4_iclk"));
2367 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
2368 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6),
2369 omap_findclk(s, "core_gpt6_clk"),
2370 omap_findclk(s, "core_l4_iclk"));
2371 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
2372 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7),
2373 omap_findclk(s, "core_gpt7_clk"),
2374 omap_findclk(s, "core_l4_iclk"));
2375 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
2376 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8),
2377 omap_findclk(s, "core_gpt8_clk"),
2378 omap_findclk(s, "core_l4_iclk"));
2379 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
2380 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9),
2381 omap_findclk(s, "core_gpt9_clk"),
2382 omap_findclk(s, "core_l4_iclk"));
2383 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
2384 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10),
2385 omap_findclk(s, "core_gpt10_clk"),
2386 omap_findclk(s, "core_l4_iclk"));
2387 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
2388 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11),
2389 omap_findclk(s, "core_gpt11_clk"),
2390 omap_findclk(s, "core_l4_iclk"));
2391 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
2392 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12),
2393 omap_findclk(s, "core_gpt12_clk"),
2394 omap_findclk(s, "core_l4_iclk"));
2395
2396 omap_tap_init(omap_l4ta(s->l4, 2), s);
2397
2398 s->synctimer = omap_synctimer_init(omap_l4tao(s->l4, 2), s,
2399 omap_findclk(s, "clk32-kHz"),
2400 omap_findclk(s, "core_l4_iclk"));
2401
2402 s->i2c[0] = qdev_create(NULL, "omap_i2c");
2403 qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
2404 qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk"));
2405 qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk"));
2406 qdev_init_nofail(s->i2c[0]);
2407 busdev = SYS_BUS_DEVICE(s->i2c[0]);
2408 sysbus_connect_irq(busdev, 0,
2409 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ));
2410 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]);
2411 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]);
2412 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0));
2413
2414 s->i2c[1] = qdev_create(NULL, "omap_i2c");
2415 qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
2416 qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk"));
2417 qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk"));
2418 qdev_init_nofail(s->i2c[1]);
2419 busdev = SYS_BUS_DEVICE(s->i2c[1]);
2420 sysbus_connect_irq(busdev, 0,
2421 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ));
2422 sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]);
2423 sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]);
2424 sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0));
2425
2426 s->gpio = qdev_create(NULL, "omap2-gpio");
2427 qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
2428 qdev_prop_set_ptr(s->gpio, "iclk", omap_findclk(s, "gpio_iclk"));
2429 qdev_prop_set_ptr(s->gpio, "fclk0", omap_findclk(s, "gpio1_dbclk"));
2430 qdev_prop_set_ptr(s->gpio, "fclk1", omap_findclk(s, "gpio2_dbclk"));
2431 qdev_prop_set_ptr(s->gpio, "fclk2", omap_findclk(s, "gpio3_dbclk"));
2432 qdev_prop_set_ptr(s->gpio, "fclk3", omap_findclk(s, "gpio4_dbclk"));
2433 if (s->mpu_model == omap2430) {
2434 qdev_prop_set_ptr(s->gpio, "fclk4", omap_findclk(s, "gpio5_dbclk"));
2435 }
2436 qdev_init_nofail(s->gpio);
2437 busdev = SYS_BUS_DEVICE(s->gpio);
2438 sysbus_connect_irq(busdev, 0,
2439 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
2440 sysbus_connect_irq(busdev, 3,
2441 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2));
2442 sysbus_connect_irq(busdev, 6,
2443 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3));
2444 sysbus_connect_irq(busdev, 9,
2445 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4));
2446 if (s->mpu_model == omap2430) {
2447 sysbus_connect_irq(busdev, 12,
2448 qdev_get_gpio_in(s->ih[0],
2449 OMAP_INT_243X_GPIO_BANK5));
2450 }
2451 ta = omap_l4ta(s->l4, 3);
2452 sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1));
2453 sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0));
2454 sysbus_mmio_map(busdev, 2, omap_l4_region_base(ta, 2));
2455 sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4));
2456 sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5));
2457
2458 s->sdrc = omap_sdrc_init(sysmem, 0x68009000);
2459 s->gpmc = omap_gpmc_init(s, 0x6800a000,
2460 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ),
2461 s->drq[OMAP24XX_DMA_GPMC]);
2462
2463 dinfo = drive_get(IF_SD, 0, 0);
2464 if (!dinfo) {
2465 fprintf(stderr, "qemu: missing SecureDigital device\n");
2466 exit(1);
2467 }
2468 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9),
2469 blk_by_legacy_dinfo(dinfo),
2470 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ),
2471 &s->drq[OMAP24XX_DMA_MMC1_TX],
2472 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
2473
2474 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
2475 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ),
2476 &s->drq[OMAP24XX_DMA_SPI1_TX0],
2477 omap_findclk(s, "spi1_fclk"),
2478 omap_findclk(s, "spi1_iclk"));
2479 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
2480 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ),
2481 &s->drq[OMAP24XX_DMA_SPI2_TX0],
2482 omap_findclk(s, "spi2_fclk"),
2483 omap_findclk(s, "spi2_iclk"));
2484
2485 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800,
2486 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
2487 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ),
2488 s->drq[OMAP24XX_DMA_DSS],
2489 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
2490 omap_findclk(s, "dss_54m_clk"),
2491 omap_findclk(s, "dss_l3_iclk"),
2492 omap_findclk(s, "dss_l4_iclk"));
2493
2494 omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000,
2495 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI),
2496 omap_findclk(s, "emul_ck"),
2497 serial_hds[0] && serial_hds[1] && serial_hds[2] ?
2498 serial_hds[3] : NULL);
2499
2500 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
2501 qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ),
2502 /* Ten consecutive lines */
2503 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
2504 omap_findclk(s, "func_96m_clk"),
2505 omap_findclk(s, "core_l4_iclk"));
2506
2507 /* All register mappings (includin those not currenlty implemented):
2508 * SystemControlMod 48000000 - 48000fff
2509 * SystemControlL4 48001000 - 48001fff
2510 * 32kHz Timer Mod 48004000 - 48004fff
2511 * 32kHz Timer L4 48005000 - 48005fff
2512 * PRCM ModA 48008000 - 480087ff
2513 * PRCM ModB 48008800 - 48008fff
2514 * PRCM L4 48009000 - 48009fff
2515 * TEST-BCM Mod 48012000 - 48012fff
2516 * TEST-BCM L4 48013000 - 48013fff
2517 * TEST-TAP Mod 48014000 - 48014fff
2518 * TEST-TAP L4 48015000 - 48015fff
2519 * GPIO1 Mod 48018000 - 48018fff
2520 * GPIO Top 48019000 - 48019fff
2521 * GPIO2 Mod 4801a000 - 4801afff
2522 * GPIO L4 4801b000 - 4801bfff
2523 * GPIO3 Mod 4801c000 - 4801cfff
2524 * GPIO4 Mod 4801e000 - 4801efff
2525 * WDTIMER1 Mod 48020000 - 48010fff
2526 * WDTIMER Top 48021000 - 48011fff
2527 * WDTIMER2 Mod 48022000 - 48012fff
2528 * WDTIMER L4 48023000 - 48013fff
2529 * WDTIMER3 Mod 48024000 - 48014fff
2530 * WDTIMER3 L4 48025000 - 48015fff
2531 * WDTIMER4 Mod 48026000 - 48016fff
2532 * WDTIMER4 L4 48027000 - 48017fff
2533 * GPTIMER1 Mod 48028000 - 48018fff
2534 * GPTIMER1 L4 48029000 - 48019fff
2535 * GPTIMER2 Mod 4802a000 - 4801afff
2536 * GPTIMER2 L4 4802b000 - 4801bfff
2537 * L4-Config AP 48040000 - 480407ff
2538 * L4-Config IP 48040800 - 48040fff
2539 * L4-Config LA 48041000 - 48041fff
2540 * ARM11ETB Mod 48048000 - 48049fff
2541 * ARM11ETB L4 4804a000 - 4804afff
2542 * DISPLAY Top 48050000 - 480503ff
2543 * DISPLAY DISPC 48050400 - 480507ff
2544 * DISPLAY RFBI 48050800 - 48050bff
2545 * DISPLAY VENC 48050c00 - 48050fff
2546 * DISPLAY L4 48051000 - 48051fff
2547 * CAMERA Top 48052000 - 480523ff
2548 * CAMERA core 48052400 - 480527ff
2549 * CAMERA DMA 48052800 - 48052bff
2550 * CAMERA MMU 48052c00 - 48052fff
2551 * CAMERA L4 48053000 - 48053fff
2552 * SDMA Mod 48056000 - 48056fff
2553 * SDMA L4 48057000 - 48057fff
2554 * SSI Top 48058000 - 48058fff
2555 * SSI GDD 48059000 - 48059fff
2556 * SSI Port1 4805a000 - 4805afff
2557 * SSI Port2 4805b000 - 4805bfff
2558 * SSI L4 4805c000 - 4805cfff
2559 * USB Mod 4805e000 - 480fefff
2560 * USB L4 4805f000 - 480fffff
2561 * WIN_TRACER1 Mod 48060000 - 48060fff
2562 * WIN_TRACER1 L4 48061000 - 48061fff
2563 * WIN_TRACER2 Mod 48062000 - 48062fff
2564 * WIN_TRACER2 L4 48063000 - 48063fff
2565 * WIN_TRACER3 Mod 48064000 - 48064fff
2566 * WIN_TRACER3 L4 48065000 - 48065fff
2567 * WIN_TRACER4 Top 48066000 - 480660ff
2568 * WIN_TRACER4 ETT 48066100 - 480661ff
2569 * WIN_TRACER4 WT 48066200 - 480662ff
2570 * WIN_TRACER4 L4 48067000 - 48067fff
2571 * XTI Mod 48068000 - 48068fff
2572 * XTI L4 48069000 - 48069fff
2573 * UART1 Mod 4806a000 - 4806afff
2574 * UART1 L4 4806b000 - 4806bfff
2575 * UART2 Mod 4806c000 - 4806cfff
2576 * UART2 L4 4806d000 - 4806dfff
2577 * UART3 Mod 4806e000 - 4806efff
2578 * UART3 L4 4806f000 - 4806ffff
2579 * I2C1 Mod 48070000 - 48070fff
2580 * I2C1 L4 48071000 - 48071fff
2581 * I2C2 Mod 48072000 - 48072fff
2582 * I2C2 L4 48073000 - 48073fff
2583 * McBSP1 Mod 48074000 - 48074fff
2584 * McBSP1 L4 48075000 - 48075fff
2585 * McBSP2 Mod 48076000 - 48076fff
2586 * McBSP2 L4 48077000 - 48077fff
2587 * GPTIMER3 Mod 48078000 - 48078fff
2588 * GPTIMER3 L4 48079000 - 48079fff
2589 * GPTIMER4 Mod 4807a000 - 4807afff
2590 * GPTIMER4 L4 4807b000 - 4807bfff
2591 * GPTIMER5 Mod 4807c000 - 4807cfff
2592 * GPTIMER5 L4 4807d000 - 4807dfff
2593 * GPTIMER6 Mod 4807e000 - 4807efff
2594 * GPTIMER6 L4 4807f000 - 4807ffff
2595 * GPTIMER7 Mod 48080000 - 48080fff
2596 * GPTIMER7 L4 48081000 - 48081fff
2597 * GPTIMER8 Mod 48082000 - 48082fff
2598 * GPTIMER8 L4 48083000 - 48083fff
2599 * GPTIMER9 Mod 48084000 - 48084fff
2600 * GPTIMER9 L4 48085000 - 48085fff
2601 * GPTIMER10 Mod 48086000 - 48086fff
2602 * GPTIMER10 L4 48087000 - 48087fff
2603 * GPTIMER11 Mod 48088000 - 48088fff
2604 * GPTIMER11 L4 48089000 - 48089fff
2605 * GPTIMER12 Mod 4808a000 - 4808afff
2606 * GPTIMER12 L4 4808b000 - 4808bfff
2607 * EAC Mod 48090000 - 48090fff
2608 * EAC L4 48091000 - 48091fff
2609 * FAC Mod 48092000 - 48092fff
2610 * FAC L4 48093000 - 48093fff
2611 * MAILBOX Mod 48094000 - 48094fff
2612 * MAILBOX L4 48095000 - 48095fff
2613 * SPI1 Mod 48098000 - 48098fff
2614 * SPI1 L4 48099000 - 48099fff
2615 * SPI2 Mod 4809a000 - 4809afff
2616 * SPI2 L4 4809b000 - 4809bfff
2617 * MMC/SDIO Mod 4809c000 - 4809cfff
2618 * MMC/SDIO L4 4809d000 - 4809dfff
2619 * MS_PRO Mod 4809e000 - 4809efff
2620 * MS_PRO L4 4809f000 - 4809ffff
2621 * RNG Mod 480a0000 - 480a0fff
2622 * RNG L4 480a1000 - 480a1fff
2623 * DES3DES Mod 480a2000 - 480a2fff
2624 * DES3DES L4 480a3000 - 480a3fff
2625 * SHA1MD5 Mod 480a4000 - 480a4fff
2626 * SHA1MD5 L4 480a5000 - 480a5fff
2627 * AES Mod 480a6000 - 480a6fff
2628 * AES L4 480a7000 - 480a7fff
2629 * PKA Mod 480a8000 - 480a9fff
2630 * PKA L4 480aa000 - 480aafff
2631 * MG Mod 480b0000 - 480b0fff
2632 * MG L4 480b1000 - 480b1fff
2633 * HDQ/1-wire Mod 480b2000 - 480b2fff
2634 * HDQ/1-wire L4 480b3000 - 480b3fff
2635 * MPU interrupt 480fe000 - 480fefff
2636 * STI channel base 54000000 - 5400ffff
2637 * IVA RAM 5c000000 - 5c01ffff
2638 * IVA ROM 5c020000 - 5c027fff
2639 * IMG_BUF_A 5c040000 - 5c040fff
2640 * IMG_BUF_B 5c042000 - 5c042fff
2641 * VLCDS 5c048000 - 5c0487ff
2642 * IMX_COEF 5c049000 - 5c04afff
2643 * IMX_CMD 5c051000 - 5c051fff
2644 * VLCDQ 5c053000 - 5c0533ff
2645 * VLCDH 5c054000 - 5c054fff
2646 * SEQ_CMD 5c055000 - 5c055fff
2647 * IMX_REG 5c056000 - 5c0560ff
2648 * VLCD_REG 5c056100 - 5c0561ff
2649 * SEQ_REG 5c056200 - 5c0562ff
2650 * IMG_BUF_REG 5c056300 - 5c0563ff
2651 * SEQIRQ_REG 5c056400 - 5c0564ff
2652 * OCP_REG 5c060000 - 5c060fff
2653 * SYSC_REG 5c070000 - 5c070fff
2654 * MMU_REG 5d000000 - 5d000fff
2655 * sDMA R 68000400 - 680005ff
2656 * sDMA W 68000600 - 680007ff
2657 * Display Control 68000800 - 680009ff
2658 * DSP subsystem 68000a00 - 68000bff
2659 * MPU subsystem 68000c00 - 68000dff
2660 * IVA subsystem 68001000 - 680011ff
2661 * USB 68001200 - 680013ff
2662 * Camera 68001400 - 680015ff
2663 * VLYNQ (firewall) 68001800 - 68001bff
2664 * VLYNQ 68001e00 - 68001fff
2665 * SSI 68002000 - 680021ff
2666 * L4 68002400 - 680025ff
2667 * DSP (firewall) 68002800 - 68002bff
2668 * DSP subsystem 68002e00 - 68002fff
2669 * IVA (firewall) 68003000 - 680033ff
2670 * IVA 68003600 - 680037ff
2671 * GFX 68003a00 - 68003bff
2672 * CMDWR emulation 68003c00 - 68003dff
2673 * SMS 68004000 - 680041ff
2674 * OCM 68004200 - 680043ff
2675 * GPMC 68004400 - 680045ff
2676 * RAM (firewall) 68005000 - 680053ff
2677 * RAM (err login) 68005400 - 680057ff
2678 * ROM (firewall) 68005800 - 68005bff
2679 * ROM (err login) 68005c00 - 68005fff
2680 * GPMC (firewall) 68006000 - 680063ff
2681 * GPMC (err login) 68006400 - 680067ff
2682 * SMS (err login) 68006c00 - 68006fff
2683 * SMS registers 68008000 - 68008fff
2684 * SDRC registers 68009000 - 68009fff
2685 * GPMC registers 6800a000 6800afff
2686 */
2687
2688 qemu_register_reset(omap2_mpu_reset, s);
2689
2690 return s;
2691 }
QEmu