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vl: allow "cont" from panicked state
[qemu.git] / target-openrisc / translate.c
blob8908a2e32bbf0354141106bad0db6990677aab6a
1 /*
2 * OpenRISC translation
3 *
4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
5 * Feng Gao <gf91597@gmail.com>
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "exec/exec-all.h"
23 #include "disas/disas.h"
24 #include "tcg-op.h"
25 #include "qemu-common.h"
26 #include "qemu/log.h"
27 #include "config.h"
28 #include "qemu/bitops.h"
29
30 #include "helper.h"
31 #define GEN_HELPER 1
32 #include "helper.h"
33
34 #define OPENRISC_DISAS
35
36 #ifdef OPENRISC_DISAS
37 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
38 #else
39 # define LOG_DIS(...) do { } while (0)
40 #endif
41
42 typedef struct DisasContext {
43 TranslationBlock *tb;
44 target_ulong pc, ppc, npc;
45 uint32_t tb_flags, synced_flags, flags;
46 uint32_t is_jmp;
47 uint32_t mem_idx;
48 int singlestep_enabled;
49 uint32_t delayed_branch;
50 } DisasContext;
51
52 static TCGv_ptr cpu_env;
53 static TCGv cpu_sr;
54 static TCGv cpu_R[32];
55 static TCGv cpu_pc;
56 static TCGv jmp_pc; /* l.jr/l.jalr temp pc */
57 static TCGv cpu_npc;
58 static TCGv cpu_ppc;
59 static TCGv_i32 env_btaken; /* bf/bnf , F flag taken */
60 static TCGv_i32 fpcsr;
61 static TCGv machi, maclo;
62 static TCGv fpmaddhi, fpmaddlo;
63 static TCGv_i32 env_flags;
64 #include "exec/gen-icount.h"
65
66 void openrisc_translate_init(void)
67 {
68 static const char * const regnames[] = {
69 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
70 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
71 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
72 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
73 };
74 int i;
75
76 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
77 cpu_sr = tcg_global_mem_new(TCG_AREG0,
78 offsetof(CPUOpenRISCState, sr), "sr");
79 env_flags = tcg_global_mem_new_i32(TCG_AREG0,
80 offsetof(CPUOpenRISCState, flags),
81 "flags");
82 cpu_pc = tcg_global_mem_new(TCG_AREG0,
83 offsetof(CPUOpenRISCState, pc), "pc");
84 cpu_npc = tcg_global_mem_new(TCG_AREG0,
85 offsetof(CPUOpenRISCState, npc), "npc");
86 cpu_ppc = tcg_global_mem_new(TCG_AREG0,
87 offsetof(CPUOpenRISCState, ppc), "ppc");
88 jmp_pc = tcg_global_mem_new(TCG_AREG0,
89 offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
90 env_btaken = tcg_global_mem_new_i32(TCG_AREG0,
91 offsetof(CPUOpenRISCState, btaken),
92 "btaken");
93 fpcsr = tcg_global_mem_new_i32(TCG_AREG0,
94 offsetof(CPUOpenRISCState, fpcsr),
95 "fpcsr");
96 machi = tcg_global_mem_new(TCG_AREG0,
97 offsetof(CPUOpenRISCState, machi),
98 "machi");
99 maclo = tcg_global_mem_new(TCG_AREG0,
100 offsetof(CPUOpenRISCState, maclo),
101 "maclo");
102 fpmaddhi = tcg_global_mem_new(TCG_AREG0,
103 offsetof(CPUOpenRISCState, fpmaddhi),
104 "fpmaddhi");
105 fpmaddlo = tcg_global_mem_new(TCG_AREG0,
106 offsetof(CPUOpenRISCState, fpmaddlo),
107 "fpmaddlo");
108 for (i = 0; i < 32; i++) {
109 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
110 offsetof(CPUOpenRISCState, gpr[i]),
111 regnames[i]);
112 }
113 }
114
115 /* Writeback SR_F transaltion-space to execution-space. */
116 static inline void wb_SR_F(void)
117 {
118 int label;
119
120 label = gen_new_label();
121 tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
122 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, label);
123 tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
124 gen_set_label(label);
125 }
126
127 static inline int zero_extend(unsigned int val, int width)
128 {
129 return val & ((1 << width) - 1);
130 }
131
132 static inline int sign_extend(unsigned int val, int width)
133 {
134 int sval;
135
136 /* LSL */
137 val <<= TARGET_LONG_BITS - width;
138 sval = val;
139 /* ASR. */
140 sval >>= TARGET_LONG_BITS - width;
141 return sval;
142 }
143
144 static inline void gen_sync_flags(DisasContext *dc)
145 {
146 /* Sync the tb dependent flag between translate and runtime. */
147 if (dc->tb_flags != dc->synced_flags) {
148 tcg_gen_movi_tl(env_flags, dc->tb_flags);
149 dc->synced_flags = dc->tb_flags;
150 }
151 }
152
153 static void gen_exception(DisasContext *dc, unsigned int excp)
154 {
155 TCGv_i32 tmp = tcg_const_i32(excp);
156 gen_helper_exception(cpu_env, tmp);
157 tcg_temp_free_i32(tmp);
158 }
159
160 static void gen_illegal_exception(DisasContext *dc)
161 {
162 tcg_gen_movi_tl(cpu_pc, dc->pc);
163 gen_exception(dc, EXCP_ILLEGAL);
164 dc->is_jmp = DISAS_UPDATE;
165 }
166
167 /* not used yet, open it when we need or64. */
168 /*#ifdef TARGET_OPENRISC64
169 static void check_ob64s(DisasContext *dc)
170 {
171 if (!(dc->flags & CPUCFGR_OB64S)) {
172 gen_illegal_exception(dc);
173 }
174 }
175
176 static void check_of64s(DisasContext *dc)
177 {
178 if (!(dc->flags & CPUCFGR_OF64S)) {
179 gen_illegal_exception(dc);
180 }
181 }
182
183 static void check_ov64s(DisasContext *dc)
184 {
185 if (!(dc->flags & CPUCFGR_OV64S)) {
186 gen_illegal_exception(dc);
187 }
188 }
189 #endif*/
190
191 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
192 {
193 TranslationBlock *tb;
194 tb = dc->tb;
195 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
196 likely(!dc->singlestep_enabled)) {
197 tcg_gen_movi_tl(cpu_pc, dest);
198 tcg_gen_goto_tb(n);
199 tcg_gen_exit_tb((uintptr_t)tb + n);
200 } else {
201 tcg_gen_movi_tl(cpu_pc, dest);
202 if (dc->singlestep_enabled) {
203 gen_exception(dc, EXCP_DEBUG);
204 }
205 tcg_gen_exit_tb(0);
206 }
207 }
208
209 static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
210 {
211 target_ulong tmp_pc;
212 int lab = gen_new_label();
213 TCGv sr_f = tcg_temp_new();
214 /* N26, 26bits imm */
215 tmp_pc = sign_extend((imm<<2), 26) + dc->pc;
216 tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
217
218 if (op0 == 0x00) { /* l.j */
219 tcg_gen_movi_tl(jmp_pc, tmp_pc);
220 } else if (op0 == 0x01) { /* l.jal */
221 tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
222 tcg_gen_movi_tl(jmp_pc, tmp_pc);
223 } else if (op0 == 0x03) { /* l.bnf */
224 tcg_gen_movi_tl(jmp_pc, dc->pc+8);
225 tcg_gen_brcondi_i32(TCG_COND_EQ, sr_f, SR_F, lab);
226 tcg_gen_movi_tl(jmp_pc, tmp_pc);
227 gen_set_label(lab);
228 } else if (op0 == 0x04) { /* l.bf */
229 tcg_gen_movi_tl(jmp_pc, dc->pc+8);
230 tcg_gen_brcondi_i32(TCG_COND_NE, sr_f, SR_F, lab);
231 tcg_gen_movi_tl(jmp_pc, tmp_pc);
232 gen_set_label(lab);
233 } else if (op0 == 0x11) { /* l.jr */
234 tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
235 } else if (op0 == 0x12) { /* l.jalr */
236 tcg_gen_movi_tl(cpu_R[9], (dc->pc + 8));
237 tcg_gen_mov_tl(jmp_pc, cpu_R[reg]);
238 } else {
239 gen_illegal_exception(dc);
240 }
241
242 tcg_temp_free(sr_f);
243 dc->delayed_branch = 2;
244 dc->tb_flags |= D_FLAG;
245 gen_sync_flags(dc);
246 }
247
248 static void dec_calc(DisasContext *dc, uint32_t insn)
249 {
250 uint32_t op0, op1, op2;
251 uint32_t ra, rb, rd;
252 op0 = extract32(insn, 0, 4);
253 op1 = extract32(insn, 8, 2);
254 op2 = extract32(insn, 6, 2);
255 ra = extract32(insn, 16, 5);
256 rb = extract32(insn, 11, 5);
257 rd = extract32(insn, 21, 5);
258
259 switch (op0) {
260 case 0x0000:
261 switch (op1) {
262 case 0x00: /* l.add */
263 LOG_DIS("l.add r%d, r%d, r%d\n", rd, ra, rb);
264 {
265 int lab = gen_new_label();
266 TCGv_i64 ta = tcg_temp_new_i64();
267 TCGv_i64 tb = tcg_temp_new_i64();
268 TCGv_i64 td = tcg_temp_local_new_i64();
269 TCGv_i32 res = tcg_temp_local_new_i32();
270 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
271 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
272 tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
273 tcg_gen_add_i64(td, ta, tb);
274 tcg_gen_trunc_i64_i32(res, td);
275 tcg_gen_shri_i64(td, td, 31);
276 tcg_gen_andi_i64(td, td, 0x3);
277 /* Jump to lab when no overflow. */
278 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
279 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
280 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
281 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
282 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
283 gen_exception(dc, EXCP_RANGE);
284 gen_set_label(lab);
285 tcg_gen_mov_i32(cpu_R[rd], res);
286 tcg_temp_free_i64(ta);
287 tcg_temp_free_i64(tb);
288 tcg_temp_free_i64(td);
289 tcg_temp_free_i32(res);
290 tcg_temp_free_i32(sr_ove);
291 }
292 break;
293 default:
294 gen_illegal_exception(dc);
295 break;
296 }
297 break;
298
299 case 0x0001: /* l.addc */
300 switch (op1) {
301 case 0x00:
302 LOG_DIS("l.addc r%d, r%d, r%d\n", rd, ra, rb);
303 {
304 int lab = gen_new_label();
305 TCGv_i64 ta = tcg_temp_new_i64();
306 TCGv_i64 tb = tcg_temp_new_i64();
307 TCGv_i64 tcy = tcg_temp_local_new_i64();
308 TCGv_i64 td = tcg_temp_local_new_i64();
309 TCGv_i32 res = tcg_temp_local_new_i32();
310 TCGv_i32 sr_cy = tcg_temp_local_new_i32();
311 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
312 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
313 tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
314 tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY);
315 tcg_gen_extu_i32_i64(tcy, sr_cy);
316 tcg_gen_shri_i64(tcy, tcy, 10);
317 tcg_gen_add_i64(td, ta, tb);
318 tcg_gen_add_i64(td, td, tcy);
319 tcg_gen_trunc_i64_i32(res, td);
320 tcg_gen_shri_i64(td, td, 32);
321 tcg_gen_andi_i64(td, td, 0x3);
322 /* Jump to lab when no overflow. */
323 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
324 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
325 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
326 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
327 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
328 gen_exception(dc, EXCP_RANGE);
329 gen_set_label(lab);
330 tcg_gen_mov_i32(cpu_R[rd], res);
331 tcg_temp_free_i64(ta);
332 tcg_temp_free_i64(tb);
333 tcg_temp_free_i64(tcy);
334 tcg_temp_free_i64(td);
335 tcg_temp_free_i32(res);
336 tcg_temp_free_i32(sr_cy);
337 tcg_temp_free_i32(sr_ove);
338 }
339 break;
340 default:
341 gen_illegal_exception(dc);
342 break;
343 }
344 break;
345
346 case 0x0002: /* l.sub */
347 switch (op1) {
348 case 0x00:
349 LOG_DIS("l.sub r%d, r%d, r%d\n", rd, ra, rb);
350 {
351 int lab = gen_new_label();
352 TCGv_i64 ta = tcg_temp_new_i64();
353 TCGv_i64 tb = tcg_temp_new_i64();
354 TCGv_i64 td = tcg_temp_local_new_i64();
355 TCGv_i32 res = tcg_temp_local_new_i32();
356 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
357
358 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
359 tcg_gen_extu_i32_i64(tb, cpu_R[rb]);
360 tcg_gen_sub_i64(td, ta, tb);
361 tcg_gen_trunc_i64_i32(res, td);
362 tcg_gen_shri_i64(td, td, 31);
363 tcg_gen_andi_i64(td, td, 0x3);
364 /* Jump to lab when no overflow. */
365 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
366 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
367 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
368 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
369 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
370 gen_exception(dc, EXCP_RANGE);
371 gen_set_label(lab);
372 tcg_gen_mov_i32(cpu_R[rd], res);
373 tcg_temp_free_i64(ta);
374 tcg_temp_free_i64(tb);
375 tcg_temp_free_i64(td);
376 tcg_temp_free_i32(res);
377 tcg_temp_free_i32(sr_ove);
378 }
379 break;
380 default:
381 gen_illegal_exception(dc);
382 break;
383 }
384 break;
385
386 case 0x0003: /* l.and */
387 switch (op1) {
388 case 0x00:
389 LOG_DIS("l.and r%d, r%d, r%d\n", rd, ra, rb);
390 tcg_gen_and_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
391 break;
392 default:
393 gen_illegal_exception(dc);
394 break;
395 }
396 break;
397
398 case 0x0004: /* l.or */
399 switch (op1) {
400 case 0x00:
401 LOG_DIS("l.or r%d, r%d, r%d\n", rd, ra, rb);
402 tcg_gen_or_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
403 break;
404 default:
405 gen_illegal_exception(dc);
406 break;
407 }
408 break;
409
410 case 0x0005:
411 switch (op1) {
412 case 0x00: /* l.xor */
413 LOG_DIS("l.xor r%d, r%d, r%d\n", rd, ra, rb);
414 tcg_gen_xor_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
415 break;
416 default:
417 gen_illegal_exception(dc);
418 break;
419 }
420 break;
421
422 case 0x0006:
423 switch (op1) {
424 case 0x03: /* l.mul */
425 LOG_DIS("l.mul r%d, r%d, r%d\n", rd, ra, rb);
426 if (ra != 0 && rb != 0) {
427 gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
428 } else {
429 tcg_gen_movi_tl(cpu_R[rd], 0x0);
430 }
431 break;
432 default:
433 gen_illegal_exception(dc);
434 break;
435 }
436 break;
437
438 case 0x0009:
439 switch (op1) {
440 case 0x03: /* l.div */
441 LOG_DIS("l.div r%d, r%d, r%d\n", rd, ra, rb);
442 {
443 int lab0 = gen_new_label();
444 int lab1 = gen_new_label();
445 int lab2 = gen_new_label();
446 int lab3 = gen_new_label();
447 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
448 if (rb == 0) {
449 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
450 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
451 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
452 gen_exception(dc, EXCP_RANGE);
453 gen_set_label(lab0);
454 } else {
455 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[rb],
456 0x00000000, lab1);
457 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[ra],
458 0x80000000, lab2);
459 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
460 0xffffffff, lab2);
461 gen_set_label(lab1);
462 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
463 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
464 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab3);
465 gen_exception(dc, EXCP_RANGE);
466 gen_set_label(lab2);
467 tcg_gen_div_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
468 gen_set_label(lab3);
469 }
470 tcg_temp_free_i32(sr_ove);
471 }
472 break;
473
474 default:
475 gen_illegal_exception(dc);
476 break;
477 }
478 break;
479
480 case 0x000a:
481 switch (op1) {
482 case 0x03: /* l.divu */
483 LOG_DIS("l.divu r%d, r%d, r%d\n", rd, ra, rb);
484 {
485 int lab0 = gen_new_label();
486 int lab1 = gen_new_label();
487 int lab2 = gen_new_label();
488 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
489 if (rb == 0) {
490 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
491 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
492 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab0);
493 gen_exception(dc, EXCP_RANGE);
494 gen_set_label(lab0);
495 } else {
496 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_R[rb],
497 0x00000000, lab1);
498 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
499 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
500 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab2);
501 gen_exception(dc, EXCP_RANGE);
502 gen_set_label(lab1);
503 tcg_gen_divu_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
504 gen_set_label(lab2);
505 }
506 tcg_temp_free_i32(sr_ove);
507 }
508 break;
509
510 default:
511 gen_illegal_exception(dc);
512 break;
513 }
514 break;
515
516 case 0x000b:
517 switch (op1) {
518 case 0x03: /* l.mulu */
519 LOG_DIS("l.mulu r%d, r%d, r%d\n", rd, ra, rb);
520 if (rb != 0 && ra != 0) {
521 TCGv_i64 result = tcg_temp_local_new_i64();
522 TCGv_i64 tra = tcg_temp_local_new_i64();
523 TCGv_i64 trb = tcg_temp_local_new_i64();
524 TCGv_i64 high = tcg_temp_new_i64();
525 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
526 int lab = gen_new_label();
527 /* Calculate the each result. */
528 tcg_gen_extu_i32_i64(tra, cpu_R[ra]);
529 tcg_gen_extu_i32_i64(trb, cpu_R[rb]);
530 tcg_gen_mul_i64(result, tra, trb);
531 tcg_temp_free_i64(tra);
532 tcg_temp_free_i64(trb);
533 tcg_gen_shri_i64(high, result, TARGET_LONG_BITS);
534 /* Overflow or not. */
535 tcg_gen_brcondi_i64(TCG_COND_EQ, high, 0x00000000, lab);
536 tcg_gen_ori_tl(cpu_sr, cpu_sr, (SR_OV | SR_CY));
537 tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
538 tcg_gen_brcondi_tl(TCG_COND_NE, sr_ove, SR_OVE, lab);
539 gen_exception(dc, EXCP_RANGE);
540 gen_set_label(lab);
541 tcg_temp_free_i64(high);
542 tcg_gen_trunc_i64_tl(cpu_R[rd], result);
543 tcg_temp_free_i64(result);
544 tcg_temp_free_i32(sr_ove);
545 } else {
546 tcg_gen_movi_tl(cpu_R[rd], 0);
547 }
548 break;
549
550 default:
551 gen_illegal_exception(dc);
552 break;
553 }
554 break;
555
556 case 0x000e:
557 switch (op1) {
558 case 0x00: /* l.cmov */
559 LOG_DIS("l.cmov r%d, r%d, r%d\n", rd, ra, rb);
560 {
561 int lab = gen_new_label();
562 TCGv res = tcg_temp_local_new();
563 TCGv sr_f = tcg_temp_new();
564 tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
565 tcg_gen_mov_tl(res, cpu_R[rb]);
566 tcg_gen_brcondi_tl(TCG_COND_NE, sr_f, SR_F, lab);
567 tcg_gen_mov_tl(res, cpu_R[ra]);
568 gen_set_label(lab);
569 tcg_gen_mov_tl(cpu_R[rd], res);
570 tcg_temp_free(sr_f);
571 tcg_temp_free(res);
572 }
573 break;
574
575 default:
576 gen_illegal_exception(dc);
577 break;
578 }
579 break;
580
581 case 0x000f:
582 switch (op1) {
583 case 0x00: /* l.ff1 */
584 LOG_DIS("l.ff1 r%d, r%d, r%d\n", rd, ra, rb);
585 gen_helper_ff1(cpu_R[rd], cpu_R[ra]);
586 break;
587 case 0x01: /* l.fl1 */
588 LOG_DIS("l.fl1 r%d, r%d, r%d\n", rd, ra, rb);
589 gen_helper_fl1(cpu_R[rd], cpu_R[ra]);
590 break;
591
592 default:
593 gen_illegal_exception(dc);
594 break;
595 }
596 break;
597
598 case 0x0008:
599 switch (op1) {
600 case 0x00:
601 switch (op2) {
602 case 0x00: /* l.sll */
603 LOG_DIS("l.sll r%d, r%d, r%d\n", rd, ra, rb);
604 tcg_gen_shl_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
605 break;
606 case 0x01: /* l.srl */
607 LOG_DIS("l.srl r%d, r%d, r%d\n", rd, ra, rb);
608 tcg_gen_shr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
609 break;
610 case 0x02: /* l.sra */
611 LOG_DIS("l.sra r%d, r%d, r%d\n", rd, ra, rb);
612 tcg_gen_sar_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
613 break;
614 case 0x03: /* l.ror */
615 LOG_DIS("l.ror r%d, r%d, r%d\n", rd, ra, rb);
616 tcg_gen_rotr_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
617 break;
618
619 default:
620 gen_illegal_exception(dc);
621 break;
622 }
623 break;
624
625 default:
626 gen_illegal_exception(dc);
627 break;
628 }
629 break;
630
631 case 0x000c:
632 switch (op1) {
633 case 0x00:
634 switch (op2) {
635 case 0x00: /* l.exths */
636 LOG_DIS("l.exths r%d, r%d\n", rd, ra);
637 tcg_gen_ext16s_tl(cpu_R[rd], cpu_R[ra]);
638 break;
639 case 0x01: /* l.extbs */
640 LOG_DIS("l.extbs r%d, r%d\n", rd, ra);
641 tcg_gen_ext8s_tl(cpu_R[rd], cpu_R[ra]);
642 break;
643 case 0x02: /* l.exthz */
644 LOG_DIS("l.exthz r%d, r%d\n", rd, ra);
645 tcg_gen_ext16u_tl(cpu_R[rd], cpu_R[ra]);
646 break;
647 case 0x03: /* l.extbz */
648 LOG_DIS("l.extbz r%d, r%d\n", rd, ra);
649 tcg_gen_ext8u_tl(cpu_R[rd], cpu_R[ra]);
650 break;
651
652 default:
653 gen_illegal_exception(dc);
654 break;
655 }
656 break;
657
658 default:
659 gen_illegal_exception(dc);
660 break;
661 }
662 break;
663
664 case 0x000d:
665 switch (op1) {
666 case 0x00:
667 switch (op2) {
668 case 0x00: /* l.extws */
669 LOG_DIS("l.extws r%d, r%d\n", rd, ra);
670 tcg_gen_ext32s_tl(cpu_R[rd], cpu_R[ra]);
671 break;
672 case 0x01: /* l.extwz */
673 LOG_DIS("l.extwz r%d, r%d\n", rd, ra);
674 tcg_gen_ext32u_tl(cpu_R[rd], cpu_R[ra]);
675 break;
676
677 default:
678 gen_illegal_exception(dc);
679 break;
680 }
681 break;
682
683 default:
684 gen_illegal_exception(dc);
685 break;
686 }
687 break;
688
689 default:
690 gen_illegal_exception(dc);
691 break;
692 }
693 }
694
695 static void dec_misc(DisasContext *dc, uint32_t insn)
696 {
697 uint32_t op0, op1;
698 uint32_t ra, rb, rd;
699 #ifdef OPENRISC_DISAS
700 uint32_t L6, K5;
701 #endif
702 uint32_t I16, I5, I11, N26, tmp;
703 op0 = extract32(insn, 26, 6);
704 op1 = extract32(insn, 24, 2);
705 ra = extract32(insn, 16, 5);
706 rb = extract32(insn, 11, 5);
707 rd = extract32(insn, 21, 5);
708 #ifdef OPENRISC_DISAS
709 L6 = extract32(insn, 5, 6);
710 K5 = extract32(insn, 0, 5);
711 #endif
712 I16 = extract32(insn, 0, 16);
713 I5 = extract32(insn, 21, 5);
714 I11 = extract32(insn, 0, 11);
715 N26 = extract32(insn, 0, 26);
716 tmp = (I5<<11) + I11;
717
718 switch (op0) {
719 case 0x00: /* l.j */
720 LOG_DIS("l.j %d\n", N26);
721 gen_jump(dc, N26, 0, op0);
722 break;
723
724 case 0x01: /* l.jal */
725 LOG_DIS("l.jal %d\n", N26);
726 gen_jump(dc, N26, 0, op0);
727 break;
728
729 case 0x03: /* l.bnf */
730 LOG_DIS("l.bnf %d\n", N26);
731 gen_jump(dc, N26, 0, op0);
732 break;
733
734 case 0x04: /* l.bf */
735 LOG_DIS("l.bf %d\n", N26);
736 gen_jump(dc, N26, 0, op0);
737 break;
738
739 case 0x05:
740 switch (op1) {
741 case 0x01: /* l.nop */
742 LOG_DIS("l.nop %d\n", I16);
743 break;
744
745 default:
746 gen_illegal_exception(dc);
747 break;
748 }
749 break;
750
751 case 0x11: /* l.jr */
752 LOG_DIS("l.jr r%d\n", rb);
753 gen_jump(dc, 0, rb, op0);
754 break;
755
756 case 0x12: /* l.jalr */
757 LOG_DIS("l.jalr r%d\n", rb);
758 gen_jump(dc, 0, rb, op0);
759 break;
760
761 case 0x13: /* l.maci */
762 LOG_DIS("l.maci %d, r%d, %d\n", I5, ra, I11);
763 {
764 TCGv_i64 t1 = tcg_temp_new_i64();
765 TCGv_i64 t2 = tcg_temp_new_i64();
766 TCGv_i32 dst = tcg_temp_new_i32();
767 TCGv ttmp = tcg_const_tl(tmp);
768 tcg_gen_mul_tl(dst, cpu_R[ra], ttmp);
769 tcg_gen_ext_i32_i64(t1, dst);
770 tcg_gen_concat_i32_i64(t2, maclo, machi);
771 tcg_gen_add_i64(t2, t2, t1);
772 tcg_gen_trunc_i64_i32(maclo, t2);
773 tcg_gen_shri_i64(t2, t2, 32);
774 tcg_gen_trunc_i64_i32(machi, t2);
775 tcg_temp_free_i32(dst);
776 tcg_temp_free(ttmp);
777 tcg_temp_free_i64(t1);
778 tcg_temp_free_i64(t2);
779 }
780 break;
781
782 case 0x09: /* l.rfe */
783 LOG_DIS("l.rfe\n");
784 {
785 #if defined(CONFIG_USER_ONLY)
786 return;
787 #else
788 if (dc->mem_idx == MMU_USER_IDX) {
789 gen_illegal_exception(dc);
790 return;
791 }
792 gen_helper_rfe(cpu_env);
793 dc->is_jmp = DISAS_UPDATE;
794 #endif
795 }
796 break;
797
798 case 0x1c: /* l.cust1 */
799 LOG_DIS("l.cust1\n");
800 break;
801
802 case 0x1d: /* l.cust2 */
803 LOG_DIS("l.cust2\n");
804 break;
805
806 case 0x1e: /* l.cust3 */
807 LOG_DIS("l.cust3\n");
808 break;
809
810 case 0x1f: /* l.cust4 */
811 LOG_DIS("l.cust4\n");
812 break;
813
814 case 0x3c: /* l.cust5 */
815 LOG_DIS("l.cust5 r%d, r%d, r%d, %d, %d\n", rd, ra, rb, L6, K5);
816 break;
817
818 case 0x3d: /* l.cust6 */
819 LOG_DIS("l.cust6\n");
820 break;
821
822 case 0x3e: /* l.cust7 */
823 LOG_DIS("l.cust7\n");
824 break;
825
826 case 0x3f: /* l.cust8 */
827 LOG_DIS("l.cust8\n");
828 break;
829
830 /* not used yet, open it when we need or64. */
831 /*#ifdef TARGET_OPENRISC64
832 case 0x20: l.ld
833 LOG_DIS("l.ld r%d, r%d, %d\n", rd, ra, I16);
834 {
835 check_ob64s(dc);
836 TCGv_i64 t0 = tcg_temp_new_i64();
837 tcg_gen_addi_i64(t0, cpu_R[ra], sign_extend(I16, 16));
838 tcg_gen_qemu_ld64(cpu_R[rd], t0, dc->mem_idx);
839 tcg_temp_free_i64(t0);
840 }
841 break;
842 #endif*/
843
844 case 0x21: /* l.lwz */
845 LOG_DIS("l.lwz r%d, r%d, %d\n", rd, ra, I16);
846 {
847 TCGv t0 = tcg_temp_new();
848 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
849 tcg_gen_qemu_ld32u(cpu_R[rd], t0, dc->mem_idx);
850 tcg_temp_free(t0);
851 }
852 break;
853
854 case 0x22: /* l.lws */
855 LOG_DIS("l.lws r%d, r%d, %d\n", rd, ra, I16);
856 {
857 TCGv t0 = tcg_temp_new();
858 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
859 tcg_gen_qemu_ld32s(cpu_R[rd], t0, dc->mem_idx);
860 tcg_temp_free(t0);
861 }
862 break;
863
864 case 0x23: /* l.lbz */
865 LOG_DIS("l.lbz r%d, r%d, %d\n", rd, ra, I16);
866 {
867 TCGv t0 = tcg_temp_new();
868 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
869 tcg_gen_qemu_ld8u(cpu_R[rd], t0, dc->mem_idx);
870 tcg_temp_free(t0);
871 }
872 break;
873
874 case 0x24: /* l.lbs */
875 LOG_DIS("l.lbs r%d, r%d, %d\n", rd, ra, I16);
876 {
877 TCGv t0 = tcg_temp_new();
878 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
879 tcg_gen_qemu_ld8s(cpu_R[rd], t0, dc->mem_idx);
880 tcg_temp_free(t0);
881 }
882 break;
883
884 case 0x25: /* l.lhz */
885 LOG_DIS("l.lhz r%d, r%d, %d\n", rd, ra, I16);
886 {
887 TCGv t0 = tcg_temp_new();
888 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
889 tcg_gen_qemu_ld16u(cpu_R[rd], t0, dc->mem_idx);
890 tcg_temp_free(t0);
891 }
892 break;
893
894 case 0x26: /* l.lhs */
895 LOG_DIS("l.lhs r%d, r%d, %d\n", rd, ra, I16);
896 {
897 TCGv t0 = tcg_temp_new();
898 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(I16, 16));
899 tcg_gen_qemu_ld16s(cpu_R[rd], t0, dc->mem_idx);
900 tcg_temp_free(t0);
901 }
902 break;
903
904 case 0x27: /* l.addi */
905 LOG_DIS("l.addi r%d, r%d, %d\n", rd, ra, I16);
906 {
907 int lab = gen_new_label();
908 TCGv_i64 ta = tcg_temp_new_i64();
909 TCGv_i64 td = tcg_temp_local_new_i64();
910 TCGv_i32 res = tcg_temp_local_new_i32();
911 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
912 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
913 tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
914 tcg_gen_trunc_i64_i32(res, td);
915 tcg_gen_shri_i64(td, td, 32);
916 tcg_gen_andi_i64(td, td, 0x3);
917 /* Jump to lab when no overflow. */
918 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
919 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
920 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
921 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
922 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
923 gen_exception(dc, EXCP_RANGE);
924 gen_set_label(lab);
925 tcg_gen_mov_i32(cpu_R[rd], res);
926 tcg_temp_free_i64(ta);
927 tcg_temp_free_i64(td);
928 tcg_temp_free_i32(res);
929 tcg_temp_free_i32(sr_ove);
930 }
931 break;
932
933 case 0x28: /* l.addic */
934 LOG_DIS("l.addic r%d, r%d, %d\n", rd, ra, I16);
935 {
936 int lab = gen_new_label();
937 TCGv_i64 ta = tcg_temp_new_i64();
938 TCGv_i64 td = tcg_temp_local_new_i64();
939 TCGv_i64 tcy = tcg_temp_local_new_i64();
940 TCGv_i32 res = tcg_temp_local_new_i32();
941 TCGv_i32 sr_cy = tcg_temp_local_new_i32();
942 TCGv_i32 sr_ove = tcg_temp_local_new_i32();
943 tcg_gen_extu_i32_i64(ta, cpu_R[ra]);
944 tcg_gen_andi_i32(sr_cy, cpu_sr, SR_CY);
945 tcg_gen_shri_i32(sr_cy, sr_cy, 10);
946 tcg_gen_extu_i32_i64(tcy, sr_cy);
947 tcg_gen_addi_i64(td, ta, sign_extend(I16, 16));
948 tcg_gen_add_i64(td, td, tcy);
949 tcg_gen_trunc_i64_i32(res, td);
950 tcg_gen_shri_i64(td, td, 32);
951 tcg_gen_andi_i64(td, td, 0x3);
952 /* Jump to lab when no overflow. */
953 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x0, lab);
954 tcg_gen_brcondi_i64(TCG_COND_EQ, td, 0x3, lab);
955 tcg_gen_ori_i32(cpu_sr, cpu_sr, (SR_OV | SR_CY));
956 tcg_gen_andi_i32(sr_ove, cpu_sr, SR_OVE);
957 tcg_gen_brcondi_i32(TCG_COND_NE, sr_ove, SR_OVE, lab);
958 gen_exception(dc, EXCP_RANGE);
959 gen_set_label(lab);
960 tcg_gen_mov_i32(cpu_R[rd], res);
961 tcg_temp_free_i64(ta);
962 tcg_temp_free_i64(td);
963 tcg_temp_free_i64(tcy);
964 tcg_temp_free_i32(res);
965 tcg_temp_free_i32(sr_cy);
966 tcg_temp_free_i32(sr_ove);
967 }
968 break;
969
970 case 0x29: /* l.andi */
971 LOG_DIS("l.andi r%d, r%d, %d\n", rd, ra, I16);
972 tcg_gen_andi_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16));
973 break;
974
975 case 0x2a: /* l.ori */
976 LOG_DIS("l.ori r%d, r%d, %d\n", rd, ra, I16);
977 tcg_gen_ori_tl(cpu_R[rd], cpu_R[ra], zero_extend(I16, 16));
978 break;
979
980 case 0x2b: /* l.xori */
981 LOG_DIS("l.xori r%d, r%d, %d\n", rd, ra, I16);
982 tcg_gen_xori_tl(cpu_R[rd], cpu_R[ra], sign_extend(I16, 16));
983 break;
984
985 case 0x2c: /* l.muli */
986 LOG_DIS("l.muli r%d, r%d, %d\n", rd, ra, I16);
987 if (ra != 0 && I16 != 0) {
988 TCGv_i32 im = tcg_const_i32(I16);
989 gen_helper_mul32(cpu_R[rd], cpu_env, cpu_R[ra], im);
990 tcg_temp_free_i32(im);
991 } else {
992 tcg_gen_movi_tl(cpu_R[rd], 0x0);
993 }
994 break;
995
996 case 0x2d: /* l.mfspr */
997 LOG_DIS("l.mfspr r%d, r%d, %d\n", rd, ra, I16);
998 {
999 #if defined(CONFIG_USER_ONLY)
1000 return;
1001 #else
1002 TCGv_i32 ti = tcg_const_i32(I16);
1003 if (dc->mem_idx == MMU_USER_IDX) {
1004 gen_illegal_exception(dc);
1005 return;
1006 }
1007 gen_helper_mfspr(cpu_R[rd], cpu_env, cpu_R[rd], cpu_R[ra], ti);
1008 tcg_temp_free_i32(ti);
1009 #endif
1010 }
1011 break;
1012
1013 case 0x30: /* l.mtspr */
1014 LOG_DIS("l.mtspr %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1015 {
1016 #if defined(CONFIG_USER_ONLY)
1017 return;
1018 #else
1019 TCGv_i32 im = tcg_const_i32(tmp);
1020 if (dc->mem_idx == MMU_USER_IDX) {
1021 gen_illegal_exception(dc);
1022 return;
1023 }
1024 gen_helper_mtspr(cpu_env, cpu_R[ra], cpu_R[rb], im);
1025 tcg_temp_free_i32(im);
1026 #endif
1027 }
1028 break;
1029
1030 /* not used yet, open it when we need or64. */
1031 /*#ifdef TARGET_OPENRISC64
1032 case 0x34: l.sd
1033 LOG_DIS("l.sd %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1034 {
1035 check_ob64s(dc);
1036 TCGv_i64 t0 = tcg_temp_new_i64();
1037 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
1038 tcg_gen_qemu_st64(cpu_R[rb], t0, dc->mem_idx);
1039 tcg_temp_free_i64(t0);
1040 }
1041 break;
1042 #endif*/
1043
1044 case 0x35: /* l.sw */
1045 LOG_DIS("l.sw %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1046 {
1047 TCGv t0 = tcg_temp_new();
1048 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
1049 tcg_gen_qemu_st32(cpu_R[rb], t0, dc->mem_idx);
1050 tcg_temp_free(t0);
1051 }
1052 break;
1053
1054 case 0x36: /* l.sb */
1055 LOG_DIS("l.sb %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1056 {
1057 TCGv t0 = tcg_temp_new();
1058 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
1059 tcg_gen_qemu_st8(cpu_R[rb], t0, dc->mem_idx);
1060 tcg_temp_free(t0);
1061 }
1062 break;
1063
1064 case 0x37: /* l.sh */
1065 LOG_DIS("l.sh %d, r%d, r%d, %d\n", I5, ra, rb, I11);
1066 {
1067 TCGv t0 = tcg_temp_new();
1068 tcg_gen_addi_tl(t0, cpu_R[ra], sign_extend(tmp, 16));
1069 tcg_gen_qemu_st16(cpu_R[rb], t0, dc->mem_idx);
1070 tcg_temp_free(t0);
1071 }
1072 break;
1073
1074 default:
1075 gen_illegal_exception(dc);
1076 break;
1077 }
1078 }
1079
1080 static void dec_mac(DisasContext *dc, uint32_t insn)
1081 {
1082 uint32_t op0;
1083 uint32_t ra, rb;
1084 op0 = extract32(insn, 0, 4);
1085 ra = extract32(insn, 16, 5);
1086 rb = extract32(insn, 11, 5);
1087
1088 switch (op0) {
1089 case 0x0001: /* l.mac */
1090 LOG_DIS("l.mac r%d, r%d\n", ra, rb);
1091 {
1092 TCGv_i32 t0 = tcg_temp_new_i32();
1093 TCGv_i64 t1 = tcg_temp_new_i64();
1094 TCGv_i64 t2 = tcg_temp_new_i64();
1095 tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]);
1096 tcg_gen_ext_i32_i64(t1, t0);
1097 tcg_gen_concat_i32_i64(t2, maclo, machi);
1098 tcg_gen_add_i64(t2, t2, t1);
1099 tcg_gen_trunc_i64_i32(maclo, t2);
1100 tcg_gen_shri_i64(t2, t2, 32);
1101 tcg_gen_trunc_i64_i32(machi, t2);
1102 tcg_temp_free_i32(t0);
1103 tcg_temp_free_i64(t1);
1104 tcg_temp_free_i64(t2);
1105 }
1106 break;
1107
1108 case 0x0002: /* l.msb */
1109 LOG_DIS("l.msb r%d, r%d\n", ra, rb);
1110 {
1111 TCGv_i32 t0 = tcg_temp_new_i32();
1112 TCGv_i64 t1 = tcg_temp_new_i64();
1113 TCGv_i64 t2 = tcg_temp_new_i64();
1114 tcg_gen_mul_tl(t0, cpu_R[ra], cpu_R[rb]);
1115 tcg_gen_ext_i32_i64(t1, t0);
1116 tcg_gen_concat_i32_i64(t2, maclo, machi);
1117 tcg_gen_sub_i64(t2, t2, t1);
1118 tcg_gen_trunc_i64_i32(maclo, t2);
1119 tcg_gen_shri_i64(t2, t2, 32);
1120 tcg_gen_trunc_i64_i32(machi, t2);
1121 tcg_temp_free_i32(t0);
1122 tcg_temp_free_i64(t1);
1123 tcg_temp_free_i64(t2);
1124 }
1125 break;
1126
1127 default:
1128 gen_illegal_exception(dc);
1129 break;
1130 }
1131 }
1132
1133 static void dec_logic(DisasContext *dc, uint32_t insn)
1134 {
1135 uint32_t op0;
1136 uint32_t rd, ra, L6;
1137 op0 = extract32(insn, 6, 2);
1138 rd = extract32(insn, 21, 5);
1139 ra = extract32(insn, 16, 5);
1140 L6 = extract32(insn, 0, 6);
1141
1142 switch (op0) {
1143 case 0x00: /* l.slli */
1144 LOG_DIS("l.slli r%d, r%d, %d\n", rd, ra, L6);
1145 tcg_gen_shli_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
1146 break;
1147
1148 case 0x01: /* l.srli */
1149 LOG_DIS("l.srli r%d, r%d, %d\n", rd, ra, L6);
1150 tcg_gen_shri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
1151 break;
1152
1153 case 0x02: /* l.srai */
1154 LOG_DIS("l.srai r%d, r%d, %d\n", rd, ra, L6);
1155 tcg_gen_sari_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f)); break;
1156
1157 case 0x03: /* l.rori */
1158 LOG_DIS("l.rori r%d, r%d, %d\n", rd, ra, L6);
1159 tcg_gen_rotri_tl(cpu_R[rd], cpu_R[ra], (L6 & 0x1f));
1160 break;
1161
1162 default:
1163 gen_illegal_exception(dc);
1164 break;
1165 }
1166 }
1167
1168 static void dec_M(DisasContext *dc, uint32_t insn)
1169 {
1170 uint32_t op0;
1171 uint32_t rd;
1172 uint32_t K16;
1173 op0 = extract32(insn, 16, 1);
1174 rd = extract32(insn, 21, 5);
1175 K16 = extract32(insn, 0, 16);
1176
1177 switch (op0) {
1178 case 0x0: /* l.movhi */
1179 LOG_DIS("l.movhi r%d, %d\n", rd, K16);
1180 tcg_gen_movi_tl(cpu_R[rd], (K16 << 16));
1181 break;
1182
1183 case 0x1: /* l.macrc */
1184 LOG_DIS("l.macrc r%d\n", rd);
1185 tcg_gen_mov_tl(cpu_R[rd], maclo);
1186 tcg_gen_movi_tl(maclo, 0x0);
1187 tcg_gen_movi_tl(machi, 0x0);
1188 break;
1189
1190 default:
1191 gen_illegal_exception(dc);
1192 break;
1193 }
1194 }
1195
1196 static void dec_comp(DisasContext *dc, uint32_t insn)
1197 {
1198 uint32_t op0;
1199 uint32_t ra, rb;
1200
1201 op0 = extract32(insn, 21, 5);
1202 ra = extract32(insn, 16, 5);
1203 rb = extract32(insn, 11, 5);
1204
1205 tcg_gen_movi_i32(env_btaken, 0x0);
1206 /* unsigned integers */
1207 tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]);
1208 tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]);
1209
1210 switch (op0) {
1211 case 0x0: /* l.sfeq */
1212 LOG_DIS("l.sfeq r%d, r%d\n", ra, rb);
1213 tcg_gen_setcond_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], cpu_R[rb]);
1214 break;
1215
1216 case 0x1: /* l.sfne */
1217 LOG_DIS("l.sfne r%d, r%d\n", ra, rb);
1218 tcg_gen_setcond_tl(TCG_COND_NE, env_btaken, cpu_R[ra], cpu_R[rb]);
1219 break;
1220
1221 case 0x2: /* l.sfgtu */
1222 LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb);
1223 tcg_gen_setcond_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], cpu_R[rb]);
1224 break;
1225
1226 case 0x3: /* l.sfgeu */
1227 LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb);
1228 tcg_gen_setcond_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], cpu_R[rb]);
1229 break;
1230
1231 case 0x4: /* l.sfltu */
1232 LOG_DIS("l.sfltu r%d, r%d\n", ra, rb);
1233 tcg_gen_setcond_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], cpu_R[rb]);
1234 break;
1235
1236 case 0x5: /* l.sfleu */
1237 LOG_DIS("l.sfleu r%d, r%d\n", ra, rb);
1238 tcg_gen_setcond_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], cpu_R[rb]);
1239 break;
1240
1241 case 0xa: /* l.sfgts */
1242 LOG_DIS("l.sfgts r%d, r%d\n", ra, rb);
1243 tcg_gen_setcond_tl(TCG_COND_GT, env_btaken, cpu_R[ra], cpu_R[rb]);
1244 break;
1245
1246 case 0xb: /* l.sfges */
1247 LOG_DIS("l.sfges r%d, r%d\n", ra, rb);
1248 tcg_gen_setcond_tl(TCG_COND_GE, env_btaken, cpu_R[ra], cpu_R[rb]);
1249 break;
1250
1251 case 0xc: /* l.sflts */
1252 LOG_DIS("l.sflts r%d, r%d\n", ra, rb);
1253 tcg_gen_setcond_tl(TCG_COND_LT, env_btaken, cpu_R[ra], cpu_R[rb]);
1254 break;
1255
1256 case 0xd: /* l.sfles */
1257 LOG_DIS("l.sfles r%d, r%d\n", ra, rb);
1258 tcg_gen_setcond_tl(TCG_COND_LE, env_btaken, cpu_R[ra], cpu_R[rb]);
1259 break;
1260
1261 default:
1262 gen_illegal_exception(dc);
1263 break;
1264 }
1265 wb_SR_F();
1266 }
1267
1268 static void dec_compi(DisasContext *dc, uint32_t insn)
1269 {
1270 uint32_t op0;
1271 uint32_t ra, I16;
1272
1273 op0 = extract32(insn, 21, 5);
1274 ra = extract32(insn, 16, 5);
1275 I16 = extract32(insn, 0, 16);
1276
1277 tcg_gen_movi_i32(env_btaken, 0x0);
1278 I16 = sign_extend(I16, 16);
1279
1280 switch (op0) {
1281 case 0x0: /* l.sfeqi */
1282 LOG_DIS("l.sfeqi r%d, %d\n", ra, I16);
1283 tcg_gen_setcondi_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], I16);
1284 break;
1285
1286 case 0x1: /* l.sfnei */
1287 LOG_DIS("l.sfnei r%d, %d\n", ra, I16);
1288 tcg_gen_setcondi_tl(TCG_COND_NE, env_btaken, cpu_R[ra], I16);
1289 break;
1290
1291 case 0x2: /* l.sfgtui */
1292 LOG_DIS("l.sfgtui r%d, %d\n", ra, I16);
1293 tcg_gen_setcondi_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], I16);
1294 break;
1295
1296 case 0x3: /* l.sfgeui */
1297 LOG_DIS("l.sfgeui r%d, %d\n", ra, I16);
1298 tcg_gen_setcondi_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], I16);
1299 break;
1300
1301 case 0x4: /* l.sfltui */
1302 LOG_DIS("l.sfltui r%d, %d\n", ra, I16);
1303 tcg_gen_setcondi_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], I16);
1304 break;
1305
1306 case 0x5: /* l.sfleui */
1307 LOG_DIS("l.sfleui r%d, %d\n", ra, I16);
1308 tcg_gen_setcondi_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], I16);
1309 break;
1310
1311 case 0xa: /* l.sfgtsi */
1312 LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16);
1313 tcg_gen_setcondi_tl(TCG_COND_GT, env_btaken, cpu_R[ra], I16);
1314 break;
1315
1316 case 0xb: /* l.sfgesi */
1317 LOG_DIS("l.sfgesi r%d, %d\n", ra, I16);
1318 tcg_gen_setcondi_tl(TCG_COND_GE, env_btaken, cpu_R[ra], I16);
1319 break;
1320
1321 case 0xc: /* l.sfltsi */
1322 LOG_DIS("l.sfltsi r%d, %d\n", ra, I16);
1323 tcg_gen_setcondi_tl(TCG_COND_LT, env_btaken, cpu_R[ra], I16);
1324 break;
1325
1326 case 0xd: /* l.sflesi */
1327 LOG_DIS("l.sflesi r%d, %d\n", ra, I16);
1328 tcg_gen_setcondi_tl(TCG_COND_LE, env_btaken, cpu_R[ra], I16);
1329 break;
1330
1331 default:
1332 gen_illegal_exception(dc);
1333 break;
1334 }
1335 wb_SR_F();
1336 }
1337
1338 static void dec_sys(DisasContext *dc, uint32_t insn)
1339 {
1340 uint32_t op0;
1341 #ifdef OPENRISC_DISAS
1342 uint32_t K16;
1343 #endif
1344 op0 = extract32(insn, 16, 8);
1345 #ifdef OPENRISC_DISAS
1346 K16 = extract32(insn, 0, 16);
1347 #endif
1348
1349 switch (op0) {
1350 case 0x000: /* l.sys */
1351 LOG_DIS("l.sys %d\n", K16);
1352 tcg_gen_movi_tl(cpu_pc, dc->pc);
1353 gen_exception(dc, EXCP_SYSCALL);
1354 dc->is_jmp = DISAS_UPDATE;
1355 break;
1356
1357 case 0x100: /* l.trap */
1358 LOG_DIS("l.trap %d\n", K16);
1359 #if defined(CONFIG_USER_ONLY)
1360 return;
1361 #else
1362 if (dc->mem_idx == MMU_USER_IDX) {
1363 gen_illegal_exception(dc);
1364 return;
1365 }
1366 tcg_gen_movi_tl(cpu_pc, dc->pc);
1367 gen_exception(dc, EXCP_TRAP);
1368 #endif
1369 break;
1370
1371 case 0x300: /* l.csync */
1372 LOG_DIS("l.csync\n");
1373 #if defined(CONFIG_USER_ONLY)
1374 return;
1375 #else
1376 if (dc->mem_idx == MMU_USER_IDX) {
1377 gen_illegal_exception(dc);
1378 return;
1379 }
1380 #endif
1381 break;
1382
1383 case 0x200: /* l.msync */
1384 LOG_DIS("l.msync\n");
1385 #if defined(CONFIG_USER_ONLY)
1386 return;
1387 #else
1388 if (dc->mem_idx == MMU_USER_IDX) {
1389 gen_illegal_exception(dc);
1390 return;
1391 }
1392 #endif
1393 break;
1394
1395 case 0x270: /* l.psync */
1396 LOG_DIS("l.psync\n");
1397 #if defined(CONFIG_USER_ONLY)
1398 return;
1399 #else
1400 if (dc->mem_idx == MMU_USER_IDX) {
1401 gen_illegal_exception(dc);
1402 return;
1403 }
1404 #endif
1405 break;
1406
1407 default:
1408 gen_illegal_exception(dc);
1409 break;
1410 }
1411 }
1412
1413 static void dec_float(DisasContext *dc, uint32_t insn)
1414 {
1415 uint32_t op0;
1416 uint32_t ra, rb, rd;
1417 op0 = extract32(insn, 0, 8);
1418 ra = extract32(insn, 16, 5);
1419 rb = extract32(insn, 11, 5);
1420 rd = extract32(insn, 21, 5);
1421
1422 switch (op0) {
1423 case 0x00: /* lf.add.s */
1424 LOG_DIS("lf.add.s r%d, r%d, r%d\n", rd, ra, rb);
1425 gen_helper_float_add_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1426 break;
1427
1428 case 0x01: /* lf.sub.s */
1429 LOG_DIS("lf.sub.s r%d, r%d, r%d\n", rd, ra, rb);
1430 gen_helper_float_sub_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1431 break;
1432
1433
1434 case 0x02: /* lf.mul.s */
1435 LOG_DIS("lf.mul.s r%d, r%d, r%d\n", rd, ra, rb);
1436 if (ra != 0 && rb != 0) {
1437 gen_helper_float_mul_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1438 } else {
1439 tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
1440 tcg_gen_movi_i32(cpu_R[rd], 0x0);
1441 }
1442 break;
1443
1444 case 0x03: /* lf.div.s */
1445 LOG_DIS("lf.div.s r%d, r%d, r%d\n", rd, ra, rb);
1446 gen_helper_float_div_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1447 break;
1448
1449 case 0x04: /* lf.itof.s */
1450 LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
1451 gen_helper_itofs(cpu_R[rd], cpu_env, cpu_R[ra]);
1452 break;
1453
1454 case 0x05: /* lf.ftoi.s */
1455 LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
1456 gen_helper_ftois(cpu_R[rd], cpu_env, cpu_R[ra]);
1457 break;
1458
1459 case 0x06: /* lf.rem.s */
1460 LOG_DIS("lf.rem.s r%d, r%d, r%d\n", rd, ra, rb);
1461 gen_helper_float_rem_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1462 break;
1463
1464 case 0x07: /* lf.madd.s */
1465 LOG_DIS("lf.madd.s r%d, r%d, r%d\n", rd, ra, rb);
1466 gen_helper_float_muladd_s(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1467 break;
1468
1469 case 0x08: /* lf.sfeq.s */
1470 LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb);
1471 gen_helper_float_eq_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1472 break;
1473
1474 case 0x09: /* lf.sfne.s */
1475 LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb);
1476 gen_helper_float_ne_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1477 break;
1478
1479 case 0x0a: /* lf.sfgt.s */
1480 LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb);
1481 gen_helper_float_gt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1482 break;
1483
1484 case 0x0b: /* lf.sfge.s */
1485 LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb);
1486 gen_helper_float_ge_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1487 break;
1488
1489 case 0x0c: /* lf.sflt.s */
1490 LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb);
1491 gen_helper_float_lt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1492 break;
1493
1494 case 0x0d: /* lf.sfle.s */
1495 LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb);
1496 gen_helper_float_le_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1497 break;
1498
1499 /* not used yet, open it when we need or64. */
1500 /*#ifdef TARGET_OPENRISC64
1501 case 0x10: lf.add.d
1502 LOG_DIS("lf.add.d r%d, r%d, r%d\n", rd, ra, rb);
1503 check_of64s(dc);
1504 gen_helper_float_add_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1505 break;
1506
1507 case 0x11: lf.sub.d
1508 LOG_DIS("lf.sub.d r%d, r%d, r%d\n", rd, ra, rb);
1509 check_of64s(dc);
1510 gen_helper_float_sub_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1511 break;
1512
1513 case 0x12: lf.mul.d
1514 LOG_DIS("lf.mul.d r%d, r%d, r%d\n", rd, ra, rb);
1515 check_of64s(dc);
1516 if (ra != 0 && rb != 0) {
1517 gen_helper_float_mul_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1518 } else {
1519 tcg_gen_ori_tl(fpcsr, fpcsr, FPCSR_ZF);
1520 tcg_gen_movi_i64(cpu_R[rd], 0x0);
1521 }
1522 break;
1523
1524 case 0x13: lf.div.d
1525 LOG_DIS("lf.div.d r%d, r%d, r%d\n", rd, ra, rb);
1526 check_of64s(dc);
1527 gen_helper_float_div_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1528 break;
1529
1530 case 0x14: lf.itof.d
1531 LOG_DIS("lf.itof r%d, r%d\n", rd, ra);
1532 check_of64s(dc);
1533 gen_helper_itofd(cpu_R[rd], cpu_env, cpu_R[ra]);
1534 break;
1535
1536 case 0x15: lf.ftoi.d
1537 LOG_DIS("lf.ftoi r%d, r%d\n", rd, ra);
1538 check_of64s(dc);
1539 gen_helper_ftoid(cpu_R[rd], cpu_env, cpu_R[ra]);
1540 break;
1541
1542 case 0x16: lf.rem.d
1543 LOG_DIS("lf.rem.d r%d, r%d, r%d\n", rd, ra, rb);
1544 check_of64s(dc);
1545 gen_helper_float_rem_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1546 break;
1547
1548 case 0x17: lf.madd.d
1549 LOG_DIS("lf.madd.d r%d, r%d, r%d\n", rd, ra, rb);
1550 check_of64s(dc);
1551 gen_helper_float_muladd_d(cpu_R[rd], cpu_env, cpu_R[ra], cpu_R[rb]);
1552 break;
1553
1554 case 0x18: lf.sfeq.d
1555 LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb);
1556 check_of64s(dc);
1557 gen_helper_float_eq_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1558 break;
1559
1560 case 0x1a: lf.sfgt.d
1561 LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb);
1562 check_of64s(dc);
1563 gen_helper_float_gt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1564 break;
1565
1566 case 0x1b: lf.sfge.d
1567 LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb);
1568 check_of64s(dc);
1569 gen_helper_float_ge_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1570 break;
1571
1572 case 0x19: lf.sfne.d
1573 LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb);
1574 check_of64s(dc);
1575 gen_helper_float_ne_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1576 break;
1577
1578 case 0x1c: lf.sflt.d
1579 LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb);
1580 check_of64s(dc);
1581 gen_helper_float_lt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1582 break;
1583
1584 case 0x1d: lf.sfle.d
1585 LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb);
1586 check_of64s(dc);
1587 gen_helper_float_le_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
1588 break;
1589 #endif*/
1590
1591 default:
1592 gen_illegal_exception(dc);
1593 break;
1594 }
1595 wb_SR_F();
1596 }
1597
1598 static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
1599 {
1600 uint32_t op0;
1601 uint32_t insn;
1602 insn = cpu_ldl_code(&cpu->env, dc->pc);
1603 op0 = extract32(insn, 26, 6);
1604
1605 switch (op0) {
1606 case 0x06:
1607 dec_M(dc, insn);
1608 break;
1609
1610 case 0x08:
1611 dec_sys(dc, insn);
1612 break;
1613
1614 case 0x2e:
1615 dec_logic(dc, insn);
1616 break;
1617
1618 case 0x2f:
1619 dec_compi(dc, insn);
1620 break;
1621
1622 case 0x31:
1623 dec_mac(dc, insn);
1624 break;
1625
1626 case 0x32:
1627 dec_float(dc, insn);
1628 break;
1629
1630 case 0x38:
1631 dec_calc(dc, insn);
1632 break;
1633
1634 case 0x39:
1635 dec_comp(dc, insn);
1636 break;
1637
1638 default:
1639 dec_misc(dc, insn);
1640 break;
1641 }
1642 }
1643
1644 static void check_breakpoint(OpenRISCCPU *cpu, DisasContext *dc)
1645 {
1646 CPUBreakpoint *bp;
1647
1648 if (unlikely(!QTAILQ_EMPTY(&cpu->env.breakpoints))) {
1649 QTAILQ_FOREACH(bp, &cpu->env.breakpoints, entry) {
1650 if (bp->pc == dc->pc) {
1651 tcg_gen_movi_tl(cpu_pc, dc->pc);
1652 gen_exception(dc, EXCP_DEBUG);
1653 dc->is_jmp = DISAS_UPDATE;
1654 }
1655 }
1656 }
1657 }
1658
1659 static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
1660 TranslationBlock *tb,
1661 int search_pc)
1662 {
1663 CPUState *cs = CPU(cpu);
1664 struct DisasContext ctx, *dc = &ctx;
1665 uint16_t *gen_opc_end;
1666 uint32_t pc_start;
1667 int j, k;
1668 uint32_t next_page_start;
1669 int num_insns;
1670 int max_insns;
1671
1672 pc_start = tb->pc;
1673 dc->tb = tb;
1674
1675 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
1676 dc->is_jmp = DISAS_NEXT;
1677 dc->ppc = pc_start;
1678 dc->pc = pc_start;
1679 dc->flags = cpu->env.cpucfgr;
1680 dc->mem_idx = cpu_mmu_index(&cpu->env);
1681 dc->synced_flags = dc->tb_flags = tb->flags;
1682 dc->delayed_branch = !!(dc->tb_flags & D_FLAG);
1683 dc->singlestep_enabled = cs->singlestep_enabled;
1684 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1685 qemu_log("-----------------------------------------\n");
1686 log_cpu_state(CPU(cpu), 0);
1687 }
1688
1689 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
1690 k = -1;
1691 num_insns = 0;
1692 max_insns = tb->cflags & CF_COUNT_MASK;
1693
1694 if (max_insns == 0) {
1695 max_insns = CF_COUNT_MASK;
1696 }
1697
1698 gen_tb_start();
1699
1700 do {
1701 check_breakpoint(cpu, dc);
1702 if (search_pc) {
1703 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1704 if (k < j) {
1705 k++;
1706 while (k < j) {
1707 tcg_ctx.gen_opc_instr_start[k++] = 0;
1708 }
1709 }
1710 tcg_ctx.gen_opc_pc[k] = dc->pc;
1711 tcg_ctx.gen_opc_instr_start[k] = 1;
1712 tcg_ctx.gen_opc_icount[k] = num_insns;
1713 }
1714
1715 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
1716 tcg_gen_debug_insn_start(dc->pc);
1717 }
1718
1719 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
1720 gen_io_start();
1721 }
1722 dc->ppc = dc->pc - 4;
1723 dc->npc = dc->pc + 4;
1724 tcg_gen_movi_tl(cpu_ppc, dc->ppc);
1725 tcg_gen_movi_tl(cpu_npc, dc->npc);
1726 disas_openrisc_insn(dc, cpu);
1727 dc->pc = dc->npc;
1728 num_insns++;
1729 /* delay slot */
1730 if (dc->delayed_branch) {
1731 dc->delayed_branch--;
1732 if (!dc->delayed_branch) {
1733 dc->tb_flags &= ~D_FLAG;
1734 gen_sync_flags(dc);
1735 tcg_gen_mov_tl(cpu_pc, jmp_pc);
1736 tcg_gen_mov_tl(cpu_npc, jmp_pc);
1737 tcg_gen_movi_tl(jmp_pc, 0);
1738 tcg_gen_exit_tb(0);
1739 dc->is_jmp = DISAS_JUMP;
1740 break;
1741 }
1742 }
1743 } while (!dc->is_jmp
1744 && tcg_ctx.gen_opc_ptr < gen_opc_end
1745 && !cs->singlestep_enabled
1746 && !singlestep
1747 && (dc->pc < next_page_start)
1748 && num_insns < max_insns);
1749
1750 if (tb->cflags & CF_LAST_IO) {
1751 gen_io_end();
1752 }
1753 if (dc->is_jmp == DISAS_NEXT) {
1754 dc->is_jmp = DISAS_UPDATE;
1755 tcg_gen_movi_tl(cpu_pc, dc->pc);
1756 }
1757 if (unlikely(cs->singlestep_enabled)) {
1758 if (dc->is_jmp == DISAS_NEXT) {
1759 tcg_gen_movi_tl(cpu_pc, dc->pc);
1760 }
1761 gen_exception(dc, EXCP_DEBUG);
1762 } else {
1763 switch (dc->is_jmp) {
1764 case DISAS_NEXT:
1765 gen_goto_tb(dc, 0, dc->pc);
1766 break;
1767 default:
1768 case DISAS_JUMP:
1769 break;
1770 case DISAS_UPDATE:
1771 /* indicate that the hash table must be used
1772 to find the next TB */
1773 tcg_gen_exit_tb(0);
1774 break;
1775 case DISAS_TB_JUMP:
1776 /* nothing more to generate */
1777 break;
1778 }
1779 }
1780
1781 gen_tb_end(tb, num_insns);
1782 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
1783 if (search_pc) {
1784 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
1785 k++;
1786 while (k <= j) {
1787 tcg_ctx.gen_opc_instr_start[k++] = 0;
1788 }
1789 } else {
1790 tb->size = dc->pc - pc_start;
1791 tb->icount = num_insns;
1792 }
1793
1794 #ifdef DEBUG_DISAS
1795 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
1796 qemu_log("\n");
1797 log_target_disas(&cpu->env, pc_start, dc->pc - pc_start, 0);
1798 qemu_log("\nisize=%d osize=%td\n",
1799 dc->pc - pc_start, tcg_ctx.gen_opc_ptr -
1800 tcg_ctx.gen_opc_buf);
1801 }
1802 #endif
1803 }
1804
1805 void gen_intermediate_code(CPUOpenRISCState *env, struct TranslationBlock *tb)
1806 {
1807 gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 0);
1808 }
1809
1810 void gen_intermediate_code_pc(CPUOpenRISCState *env,
1811 struct TranslationBlock *tb)
1812 {
1813 gen_intermediate_code_internal(openrisc_env_get_cpu(env), tb, 1);
1814 }
1815
1816 void openrisc_cpu_dump_state(CPUState *cs, FILE *f,
1817 fprintf_function cpu_fprintf,
1818 int flags)
1819 {
1820 OpenRISCCPU *cpu = OPENRISC_CPU(cs);
1821 CPUOpenRISCState *env = &cpu->env;
1822 int i;
1823
1824 cpu_fprintf(f, "PC=%08x\n", env->pc);
1825 for (i = 0; i < 32; ++i) {
1826 cpu_fprintf(f, "R%02d=%08x%c", i, env->gpr[i],
1827 (i % 4) == 3 ? '\n' : ' ');
1828 }
1829 }
1830
1831 void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb,
1832 int pc_pos)
1833 {
1834 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
1835 }
QEmu