hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 #include "qemu-common.h"
   5
   6 #include "qdev.h"
   7
   8 /* PCI includes legacy ISA access.  */
   9 #include "isa.h"
  10
  11 /* PCI bus */
  12
  13 #define PCI_DEVFN(slot, func)   ((((slot) & 0x1f) << 3) | ((func) & 0x07))
  14 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
  15 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  16
  17 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
  18 #include "pci_ids.h"
  19
  20 /* QEMU-specific Vendor and Device ID definitions */
  21
  22 /* IBM (0x1014) */
  23 #define PCI_DEVICE_ID_IBM_440GX          0x027f
  24 #define PCI_DEVICE_ID_IBM_OPENPIC2       0xffff
  25
  26 /* Hitachi (0x1054) */
  27 #define PCI_VENDOR_ID_HITACHI            0x1054
  28 #define PCI_DEVICE_ID_HITACHI_SH7751R    0x350e
  29
  30 /* Apple (0x106b) */
  31 #define PCI_DEVICE_ID_APPLE_343S1201     0x0010
  32 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI  0x001e
  33 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI    0x001f
  34 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL   0x0022
  35 #define PCI_DEVICE_ID_APPLE_IPID_USB     0x003f
  36
  37 /* Realtek (0x10ec) */
  38 #define PCI_DEVICE_ID_REALTEK_8029       0x8029
  39
  40 /* Xilinx (0x10ee) */
  41 #define PCI_DEVICE_ID_XILINX_XC2VP30     0x0300
  42
  43 /* Marvell (0x11ab) */
  44 #define PCI_DEVICE_ID_MARVELL_GT6412X    0x4620
  45
  46 /* QEMU/Bochs VGA (0x1234) */
  47 #define PCI_VENDOR_ID_QEMU               0x1234
  48 #define PCI_DEVICE_ID_QEMU_VGA           0x1111
  49
  50 /* VMWare (0x15ad) */
  51 #define PCI_VENDOR_ID_VMWARE             0x15ad
  52 #define PCI_DEVICE_ID_VMWARE_SVGA2       0x0405
  53 #define PCI_DEVICE_ID_VMWARE_SVGA        0x0710
  54 #define PCI_DEVICE_ID_VMWARE_NET         0x0720
  55 #define PCI_DEVICE_ID_VMWARE_SCSI        0x0730
  56 #define PCI_DEVICE_ID_VMWARE_IDE         0x1729
  57
  58 /* Intel (0x8086) */
  59 #define PCI_DEVICE_ID_INTEL_82551IT      0x1209
  60 #define PCI_DEVICE_ID_INTEL_82557        0x1229
  61
  62 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
  63 #define PCI_VENDOR_ID_REDHAT_QUMRANET    0x1af4
  64 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
  65 #define PCI_SUBDEVICE_ID_QEMU            0x1100
  66
  67 #define PCI_DEVICE_ID_VIRTIO_NET         0x1000
  68 #define PCI_DEVICE_ID_VIRTIO_BLOCK       0x1001
  69 #define PCI_DEVICE_ID_VIRTIO_BALLOON     0x1002
  70 #define PCI_DEVICE_ID_VIRTIO_CONSOLE     0x1003
  71
  72 typedef uint64_t pcibus_t;
  73 #define FMT_PCIBUS                      PRIx64
  74
  75 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  76                                 uint32_t address, uint32_t data, int len);
  77 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  78                                    uint32_t address, int len);
  79 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  80                                 pcibus_t addr, pcibus_t size, int type);
  81 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  82
  83 typedef struct PCIIORegion {
  84     pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
  85 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
  86     pcibus_t size;
  87     pcibus_t filtered_size;
  88     uint8_t type;
  89     PCIMapIORegionFunc *map_func;
  90 } PCIIORegion;
  91
  92 #define PCI_ROM_SLOT 6
  93 #define PCI_NUM_REGIONS 7
  94
  95 #include "pci_regs.h"
  96
  97 /* PCI HEADER_TYPE */
  98 #define  PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
  99
 100 #define PCI_STATUS_RESERVED_MASK_LO (PCI_STATUS_RESERVED1 | \
 101                 PCI_STATUS_INT_STATUS | PCI_STATUS_CAPABILITIES | \
 102                 PCI_STATUS_66MHZ | PCI_STATUS_RESERVED2 | PCI_STATUS_FAST_BACK)
 103
 104 #define PCI_STATUS_RESERVED_MASK_HI (PCI_STATUS_DEVSEL >> 8)
 105
 106 /* Bits in the PCI Command Register (PCI 2.3 spec) */
 107 #define PCI_COMMAND_RESERVED    0xf800
 108
 109 #define PCI_COMMAND_RESERVED_MASK_HI (PCI_COMMAND_RESERVED >> 8)
 110
 111 /* Size of the standard PCI config header */
 112 #define PCI_CONFIG_HEADER_SIZE 0x40
 113 /* Size of the standard PCI config space */
 114 #define PCI_CONFIG_SPACE_SIZE 0x100
 115 /* Size of the standart PCIe config space: 4KB */
 116 #define PCIE_CONFIG_SPACE_SIZE  0x1000
 117
 118 #define PCI_NUM_PINS 4 /* A-D */
 119
 120 /* Bits in cap_present field. */
 121 enum {
 122     QEMU_PCI_CAP_MSIX = 0x1,
 123     QEMU_PCI_CAP_EXPRESS = 0x2,
 124 };
 125
 126 struct PCIDevice {
 127     DeviceState qdev;
 128     /* PCI config space */
 129     uint8_t *config;
 130
 131     /* Used to enable config checks on load. Note that writeable bits are
 132      * never checked even if set in cmask. */
 133     uint8_t *cmask;
 134
 135     /* Used to implement R/W bytes */
 136     uint8_t *wmask;
 137
 138     /* Used to allocate config space for capabilities. */
 139     uint8_t *used;
 140
 141     /* the following fields are read only */
 142     PCIBus *bus;
 143     uint32_t devfn;
 144     char name[64];
 145     PCIIORegion io_regions[PCI_NUM_REGIONS];
 146
 147     /* do not access the following fields */
 148     PCIConfigReadFunc *config_read;
 149     PCIConfigWriteFunc *config_write;
 150
 151     /* IRQ objects for the INTA-INTD pins.  */
 152     qemu_irq *irq;
 153
 154     /* Current IRQ levels.  Used internally by the generic PCI code.  */
 155     uint8_t irq_state;
 156
 157     /* Capability bits */
 158     uint32_t cap_present;
 159
 160     /* Offset of MSI-X capability in config space */
 161     uint8_t msix_cap;
 162
 163     /* MSI-X entries */
 164     int msix_entries_nr;
 165
 166     /* Space to store MSIX table */
 167     uint8_t *msix_table_page;
 168     /* MMIO index used to map MSIX table and pending bit entries. */
 169     int msix_mmio_index;
 170     /* Reference-count for entries actually in use by driver. */
 171     unsigned *msix_entry_used;
 172     /* Region including the MSI-X table */
 173     uint32_t msix_bar_size;
 174     /* Version id needed for VMState */
 175     int32_t version_id;
 176
 177     /* Location of option rom */
 178     char *romfile;
 179     ram_addr_t rom_offset;
 180 };
 181
 182 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 183                                int instance_size, int devfn,
 184                                PCIConfigReadFunc *config_read,
 185                                PCIConfigWriteFunc *config_write);
 186
 187 void pci_register_bar(PCIDevice *pci_dev, int region_num,
 188                             pcibus_t size, int type,
 189                             PCIMapIORegionFunc *map_func);
 190
 191 int pci_add_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 192
 193 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
 194
 195 void pci_reserve_capability(PCIDevice *pci_dev, uint8_t offset, uint8_t size);
 196
 197 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
 198
 199
 200 uint32_t pci_default_read_config(PCIDevice *d,
 201                                  uint32_t address, int len);
 202 void pci_default_write_config(PCIDevice *d,
 203                               uint32_t address, uint32_t val, int len);
 204 void pci_device_save(PCIDevice *s, QEMUFile *f);
 205 int pci_device_load(PCIDevice *s, QEMUFile *f);
 206
 207 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
 208 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
 209 typedef int (*pci_hotplug_fn)(PCIDevice *pci_dev, int state);
 210 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
 211                          const char *name, int devfn_min);
 212 PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min);
 213 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 214                   void *irq_opaque, int nirq);
 215 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug);
 216 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
 217                          pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
 218                          void *irq_opaque, int devfn_min, int nirq);
 219
 220 void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base);
 221
 222 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
 223                         const char *default_devaddr);
 224 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
 225                                const char *default_devaddr);
 226 int pci_bus_num(PCIBus *s);
 227 void pci_for_each_device(PCIBus *bus, int bus_num, void (*fn)(PCIBus *bus, PCIDevice *d));
 228 PCIBus *pci_find_root_bus(int domain);
 229 PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
 230 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
 231 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
 232
 233 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
 234                      unsigned *slotp);
 235
 236 void pci_info(Monitor *mon);
 237 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 238                         pci_map_irq_fn map_irq, const char *name);
 239 PCIDevice *pci_bridge_get_device(PCIBus *bus);
 240
 241 static inline void
 242 pci_set_byte(uint8_t *config, uint8_t val)
 243 {
 244     *config = val;
 245 }
 246
 247 static inline uint8_t
 248 pci_get_byte(uint8_t *config)
 249 {
 250     return *config;
 251 }
 252
 253 static inline void
 254 pci_set_word(uint8_t *config, uint16_t val)
 255 {
 256     cpu_to_le16wu((uint16_t *)config, val);
 257 }
 258
 259 static inline uint16_t
 260 pci_get_word(uint8_t *config)
 261 {
 262     return le16_to_cpupu((uint16_t *)config);
 263 }
 264
 265 static inline void
 266 pci_set_long(uint8_t *config, uint32_t val)
 267 {
 268     cpu_to_le32wu((uint32_t *)config, val);
 269 }
 270
 271 static inline uint32_t
 272 pci_get_long(uint8_t *config)
 273 {
 274     return le32_to_cpupu((uint32_t *)config);
 275 }
 276
 277 static inline void
 278 pci_set_quad(uint8_t *config, uint64_t val)
 279 {
 280     cpu_to_le64w((uint64_t *)config, val);
 281 }
 282
 283 static inline uint64_t
 284 pci_get_quad(uint8_t *config)
 285 {
 286     return le64_to_cpup((uint64_t *)config);
 287 }
 288
 289 static inline void
 290 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
 291 {
 292     pci_set_word(&pci_config[PCI_VENDOR_ID], val);
 293 }
 294
 295 static inline void
 296 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
 297 {
 298     pci_set_word(&pci_config[PCI_DEVICE_ID], val);
 299 }
 300
 301 static inline void
 302 pci_config_set_class(uint8_t *pci_config, uint16_t val)
 303 {
 304     pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
 305 }
 306
 307 typedef int (*pci_qdev_initfn)(PCIDevice *dev);
 308 typedef struct {
 309     DeviceInfo qdev;
 310     pci_qdev_initfn init;
 311     PCIUnregisterFunc *exit;
 312     PCIConfigReadFunc *config_read;
 313     PCIConfigWriteFunc *config_write;
 314
 315     /* pci config header type */
 316     uint8_t header_type;
 317
 318     /* pcie stuff */
 319     int is_express;   /* is this device pci express? */
 320
 321     /* rom bar */
 322     const char *romfile;
 323 } PCIDeviceInfo;
 324
 325 void pci_qdev_register(PCIDeviceInfo *info);
 326 void pci_qdev_register_many(PCIDeviceInfo *info);
 327
 328 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name);
 329 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
 330
 331 static inline int pci_is_express(PCIDevice *d)
 332 {
 333     return d->cap_present & QEMU_PCI_CAP_EXPRESS;
 334 }
 335
 336 static inline uint32_t pci_config_size(PCIDevice *d)
 337 {
 338     return pci_is_express(d) ? PCIE_CONFIG_SPACE_SIZE : PCI_CONFIG_SPACE_SIZE;
 339 }
 340
 341 /* These are not pci specific. Should move into a separate header.
 342  * Only pci.c uses them, so keep them here for now.
 343  */
 344
 345 /* Get last byte of a range from offset + length.
 346  * Undefined for ranges that wrap around 0. */
 347 static inline uint64_t range_get_last(uint64_t offset, uint64_t len)
 348 {
 349     return offset + len - 1;
 350 }
 351
 352 /* Check whether a given range covers a given byte. */
 353 static inline int range_covers_byte(uint64_t offset, uint64_t len,
 354                                     uint64_t byte)
 355 {
 356     return offset <= byte && byte <= range_get_last(offset, len);
 357 }
 358
 359 /* Check whether 2 given ranges overlap.
 360  * Undefined if ranges that wrap around 0. */
 361 static inline int ranges_overlap(uint64_t first1, uint64_t len1,
 362                                  uint64_t first2, uint64_t len2)
 363 {
 364     uint64_t last1 = range_get_last(first1, len1);
 365     uint64_t last2 = range_get_last(first2, len2);
 366
 367     return !(last2 < first1 || last1 < first2);
 368 }
 369
 370 #endif