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s390x: cleanup interrupt injection
[qemu.git] / target-cris / translate.c
blobab0e47962bb4fc883d187af4efc1053b61ed183f
1 /*
2 * CRIS emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2008 AXIS Communications AB
5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /*
22 * FIXME:
23 * The condition code translation is in need of attention.
24 */
25
26 #include "cpu.h"
27 #include "disas/disas.h"
28 #include "tcg-op.h"
29 #include "exec/helper-proto.h"
30 #include "mmu.h"
31 #include "exec/cpu_ldst.h"
32 #include "crisv32-decode.h"
33
34 #include "exec/helper-gen.h"
35
36 #define DISAS_CRIS 0
37 #if DISAS_CRIS
38 # define LOG_DIS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
39 #else
40 # define LOG_DIS(...) do { } while (0)
41 #endif
42
43 #define D(x)
44 #define BUG() (gen_BUG(dc, __FILE__, __LINE__))
45 #define BUG_ON(x) ({if (x) BUG();})
46
47 #define DISAS_SWI 5
48
49 /* Used by the decoder. */
50 #define EXTRACT_FIELD(src, start, end) \
51 (((src) >> start) & ((1 << (end - start + 1)) - 1))
52
53 #define CC_MASK_NZ 0xc
54 #define CC_MASK_NZV 0xe
55 #define CC_MASK_NZVC 0xf
56 #define CC_MASK_RNZV 0x10e
57
58 static TCGv_ptr cpu_env;
59 static TCGv cpu_R[16];
60 static TCGv cpu_PR[16];
61 static TCGv cc_x;
62 static TCGv cc_src;
63 static TCGv cc_dest;
64 static TCGv cc_result;
65 static TCGv cc_op;
66 static TCGv cc_size;
67 static TCGv cc_mask;
68
69 static TCGv env_btaken;
70 static TCGv env_btarget;
71 static TCGv env_pc;
72
73 #include "exec/gen-icount.h"
74
75 /* This is the state at translation time. */
76 typedef struct DisasContext {
77 CRISCPU *cpu;
78 target_ulong pc, ppc;
79
80 /* Decoder. */
81 unsigned int (*decoder)(CPUCRISState *env, struct DisasContext *dc);
82 uint32_t ir;
83 uint32_t opcode;
84 unsigned int op1;
85 unsigned int op2;
86 unsigned int zsize, zzsize;
87 unsigned int mode;
88 unsigned int postinc;
89
90 unsigned int size;
91 unsigned int src;
92 unsigned int dst;
93 unsigned int cond;
94
95 int update_cc;
96 int cc_op;
97 int cc_size;
98 uint32_t cc_mask;
99
100 int cc_size_uptodate; /* -1 invalid or last written value. */
101
102 int cc_x_uptodate; /* 1 - ccs, 2 - known | X_FLAG. 0 not uptodate. */
103 int flags_uptodate; /* Wether or not $ccs is uptodate. */
104 int flagx_known; /* Wether or not flags_x has the x flag known at
105 translation time. */
106 int flags_x;
107
108 int clear_x; /* Clear x after this insn? */
109 int clear_prefix; /* Clear prefix after this insn? */
110 int clear_locked_irq; /* Clear the irq lockout. */
111 int cpustate_changed;
112 unsigned int tb_flags; /* tb dependent flags. */
113 int is_jmp;
114
115 #define JMP_NOJMP 0
116 #define JMP_DIRECT 1
117 #define JMP_DIRECT_CC 2
118 #define JMP_INDIRECT 3
119 int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
120 uint32_t jmp_pc;
121
122 int delayed_branch;
123
124 struct TranslationBlock *tb;
125 int singlestep_enabled;
126 } DisasContext;
127
128 static void gen_BUG(DisasContext *dc, const char *file, int line)
129 {
130 printf("BUG: pc=%x %s %d\n", dc->pc, file, line);
131 qemu_log("BUG: pc=%x %s %d\n", dc->pc, file, line);
132 cpu_abort(CPU(dc->cpu), "%s:%d\n", file, line);
133 }
134
135 static const char *regnames[] =
136 {
137 "$r0", "$r1", "$r2", "$r3",
138 "$r4", "$r5", "$r6", "$r7",
139 "$r8", "$r9", "$r10", "$r11",
140 "$r12", "$r13", "$sp", "$acr",
141 };
142 static const char *pregnames[] =
143 {
144 "$bz", "$vr", "$pid", "$srs",
145 "$wz", "$exs", "$eda", "$mof",
146 "$dz", "$ebp", "$erp", "$srp",
147 "$nrp", "$ccs", "$usp", "$spc",
148 };
149
150 /* We need this table to handle preg-moves with implicit width. */
151 static int preg_sizes[] = {
152 1, /* bz. */
153 1, /* vr. */
154 4, /* pid. */
155 1, /* srs. */
156 2, /* wz. */
157 4, 4, 4,
158 4, 4, 4, 4,
159 4, 4, 4, 4,
160 };
161
162 #define t_gen_mov_TN_env(tn, member) \
163 tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member))
164 #define t_gen_mov_env_TN(member, tn) \
165 tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member))
166
167 static inline void t_gen_mov_TN_preg(TCGv tn, int r)
168 {
169 if (r < 0 || r > 15) {
170 fprintf(stderr, "wrong register read $p%d\n", r);
171 }
172 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
173 tcg_gen_mov_tl(tn, tcg_const_tl(0));
174 } else if (r == PR_VR) {
175 tcg_gen_mov_tl(tn, tcg_const_tl(32));
176 } else {
177 tcg_gen_mov_tl(tn, cpu_PR[r]);
178 }
179 }
180 static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
181 {
182 if (r < 0 || r > 15) {
183 fprintf(stderr, "wrong register write $p%d\n", r);
184 }
185 if (r == PR_BZ || r == PR_WZ || r == PR_DZ) {
186 return;
187 } else if (r == PR_SRS) {
188 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
189 } else {
190 if (r == PR_PID) {
191 gen_helper_tlb_flush_pid(cpu_env, tn);
192 }
193 if (dc->tb_flags & S_FLAG && r == PR_SPC) {
194 gen_helper_spc_write(cpu_env, tn);
195 } else if (r == PR_CCS) {
196 dc->cpustate_changed = 1;
197 }
198 tcg_gen_mov_tl(cpu_PR[r], tn);
199 }
200 }
201
202 /* Sign extend at translation time. */
203 static int sign_extend(unsigned int val, unsigned int width)
204 {
205 int sval;
206
207 /* LSL. */
208 val <<= 31 - width;
209 sval = val;
210 /* ASR. */
211 sval >>= 31 - width;
212 return sval;
213 }
214
215 static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr,
216 unsigned int size, unsigned int sign)
217 {
218 int r;
219
220 switch (size) {
221 case 4:
222 {
223 r = cpu_ldl_code(env, addr);
224 break;
225 }
226 case 2:
227 {
228 if (sign) {
229 r = cpu_ldsw_code(env, addr);
230 } else {
231 r = cpu_lduw_code(env, addr);
232 }
233 break;
234 }
235 case 1:
236 {
237 if (sign) {
238 r = cpu_ldsb_code(env, addr);
239 } else {
240 r = cpu_ldub_code(env, addr);
241 }
242 break;
243 }
244 default:
245 cpu_abort(CPU(dc->cpu), "Invalid fetch size %d\n", size);
246 break;
247 }
248 return r;
249 }
250
251 static void cris_lock_irq(DisasContext *dc)
252 {
253 dc->clear_locked_irq = 0;
254 t_gen_mov_env_TN(locked_irq, tcg_const_tl(1));
255 }
256
257 static inline void t_gen_raise_exception(uint32_t index)
258 {
259 TCGv_i32 tmp = tcg_const_i32(index);
260 gen_helper_raise_exception(cpu_env, tmp);
261 tcg_temp_free_i32(tmp);
262 }
263
264 static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
265 {
266 TCGv t0, t_31;
267
268 t0 = tcg_temp_new();
269 t_31 = tcg_const_tl(31);
270 tcg_gen_shl_tl(d, a, b);
271
272 tcg_gen_sub_tl(t0, t_31, b);
273 tcg_gen_sar_tl(t0, t0, t_31);
274 tcg_gen_and_tl(t0, t0, d);
275 tcg_gen_xor_tl(d, d, t0);
276 tcg_temp_free(t0);
277 tcg_temp_free(t_31);
278 }
279
280 static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
281 {
282 TCGv t0, t_31;
283
284 t0 = tcg_temp_new();
285 t_31 = tcg_temp_new();
286 tcg_gen_shr_tl(d, a, b);
287
288 tcg_gen_movi_tl(t_31, 31);
289 tcg_gen_sub_tl(t0, t_31, b);
290 tcg_gen_sar_tl(t0, t0, t_31);
291 tcg_gen_and_tl(t0, t0, d);
292 tcg_gen_xor_tl(d, d, t0);
293 tcg_temp_free(t0);
294 tcg_temp_free(t_31);
295 }
296
297 static void t_gen_asr(TCGv d, TCGv a, TCGv b)
298 {
299 TCGv t0, t_31;
300
301 t0 = tcg_temp_new();
302 t_31 = tcg_temp_new();
303 tcg_gen_sar_tl(d, a, b);
304
305 tcg_gen_movi_tl(t_31, 31);
306 tcg_gen_sub_tl(t0, t_31, b);
307 tcg_gen_sar_tl(t0, t0, t_31);
308 tcg_gen_or_tl(d, d, t0);
309 tcg_temp_free(t0);
310 tcg_temp_free(t_31);
311 }
312
313 static void t_gen_cris_dstep(TCGv d, TCGv a, TCGv b)
314 {
315 int l1;
316
317 l1 = gen_new_label();
318
319 /*
320 * d <<= 1
321 * if (d >= s)
322 * d -= s;
323 */
324 tcg_gen_shli_tl(d, a, 1);
325 tcg_gen_brcond_tl(TCG_COND_LTU, d, b, l1);
326 tcg_gen_sub_tl(d, d, b);
327 gen_set_label(l1);
328 }
329
330 static void t_gen_cris_mstep(TCGv d, TCGv a, TCGv b, TCGv ccs)
331 {
332 TCGv t;
333
334 /*
335 * d <<= 1
336 * if (n)
337 * d += s;
338 */
339 t = tcg_temp_new();
340 tcg_gen_shli_tl(d, a, 1);
341 tcg_gen_shli_tl(t, ccs, 31 - 3);
342 tcg_gen_sari_tl(t, t, 31);
343 tcg_gen_and_tl(t, t, b);
344 tcg_gen_add_tl(d, d, t);
345 tcg_temp_free(t);
346 }
347
348 /* Extended arithmetics on CRIS. */
349 static inline void t_gen_add_flag(TCGv d, int flag)
350 {
351 TCGv c;
352
353 c = tcg_temp_new();
354 t_gen_mov_TN_preg(c, PR_CCS);
355 /* Propagate carry into d. */
356 tcg_gen_andi_tl(c, c, 1 << flag);
357 if (flag) {
358 tcg_gen_shri_tl(c, c, flag);
359 }
360 tcg_gen_add_tl(d, d, c);
361 tcg_temp_free(c);
362 }
363
364 static inline void t_gen_addx_carry(DisasContext *dc, TCGv d)
365 {
366 if (dc->flagx_known) {
367 if (dc->flags_x) {
368 TCGv c;
369
370 c = tcg_temp_new();
371 t_gen_mov_TN_preg(c, PR_CCS);
372 /* C flag is already at bit 0. */
373 tcg_gen_andi_tl(c, c, C_FLAG);
374 tcg_gen_add_tl(d, d, c);
375 tcg_temp_free(c);
376 }
377 } else {
378 TCGv x, c;
379
380 x = tcg_temp_new();
381 c = tcg_temp_new();
382 t_gen_mov_TN_preg(x, PR_CCS);
383 tcg_gen_mov_tl(c, x);
384
385 /* Propagate carry into d if X is set. Branch free. */
386 tcg_gen_andi_tl(c, c, C_FLAG);
387 tcg_gen_andi_tl(x, x, X_FLAG);
388 tcg_gen_shri_tl(x, x, 4);
389
390 tcg_gen_and_tl(x, x, c);
391 tcg_gen_add_tl(d, d, x);
392 tcg_temp_free(x);
393 tcg_temp_free(c);
394 }
395 }
396
397 static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
398 {
399 if (dc->flagx_known) {
400 if (dc->flags_x) {
401 TCGv c;
402
403 c = tcg_temp_new();
404 t_gen_mov_TN_preg(c, PR_CCS);
405 /* C flag is already at bit 0. */
406 tcg_gen_andi_tl(c, c, C_FLAG);
407 tcg_gen_sub_tl(d, d, c);
408 tcg_temp_free(c);
409 }
410 } else {
411 TCGv x, c;
412
413 x = tcg_temp_new();
414 c = tcg_temp_new();
415 t_gen_mov_TN_preg(x, PR_CCS);
416 tcg_gen_mov_tl(c, x);
417
418 /* Propagate carry into d if X is set. Branch free. */
419 tcg_gen_andi_tl(c, c, C_FLAG);
420 tcg_gen_andi_tl(x, x, X_FLAG);
421 tcg_gen_shri_tl(x, x, 4);
422
423 tcg_gen_and_tl(x, x, c);
424 tcg_gen_sub_tl(d, d, x);
425 tcg_temp_free(x);
426 tcg_temp_free(c);
427 }
428 }
429
430 /* Swap the two bytes within each half word of the s operand.
431 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
432 static inline void t_gen_swapb(TCGv d, TCGv s)
433 {
434 TCGv t, org_s;
435
436 t = tcg_temp_new();
437 org_s = tcg_temp_new();
438
439 /* d and s may refer to the same object. */
440 tcg_gen_mov_tl(org_s, s);
441 tcg_gen_shli_tl(t, org_s, 8);
442 tcg_gen_andi_tl(d, t, 0xff00ff00);
443 tcg_gen_shri_tl(t, org_s, 8);
444 tcg_gen_andi_tl(t, t, 0x00ff00ff);
445 tcg_gen_or_tl(d, d, t);
446 tcg_temp_free(t);
447 tcg_temp_free(org_s);
448 }
449
450 /* Swap the halfwords of the s operand. */
451 static inline void t_gen_swapw(TCGv d, TCGv s)
452 {
453 TCGv t;
454 /* d and s refer the same object. */
455 t = tcg_temp_new();
456 tcg_gen_mov_tl(t, s);
457 tcg_gen_shli_tl(d, t, 16);
458 tcg_gen_shri_tl(t, t, 16);
459 tcg_gen_or_tl(d, d, t);
460 tcg_temp_free(t);
461 }
462
463 /* Reverse the within each byte.
464 T0 = (((T0 << 7) & 0x80808080) |
465 ((T0 << 5) & 0x40404040) |
466 ((T0 << 3) & 0x20202020) |
467 ((T0 << 1) & 0x10101010) |
468 ((T0 >> 1) & 0x08080808) |
469 ((T0 >> 3) & 0x04040404) |
470 ((T0 >> 5) & 0x02020202) |
471 ((T0 >> 7) & 0x01010101));
472 */
473 static inline void t_gen_swapr(TCGv d, TCGv s)
474 {
475 struct {
476 int shift; /* LSL when positive, LSR when negative. */
477 uint32_t mask;
478 } bitrev[] = {
479 {7, 0x80808080},
480 {5, 0x40404040},
481 {3, 0x20202020},
482 {1, 0x10101010},
483 {-1, 0x08080808},
484 {-3, 0x04040404},
485 {-5, 0x02020202},
486 {-7, 0x01010101}
487 };
488 int i;
489 TCGv t, org_s;
490
491 /* d and s refer the same object. */
492 t = tcg_temp_new();
493 org_s = tcg_temp_new();
494 tcg_gen_mov_tl(org_s, s);
495
496 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
497 tcg_gen_andi_tl(d, t, bitrev[0].mask);
498 for (i = 1; i < ARRAY_SIZE(bitrev); i++) {
499 if (bitrev[i].shift >= 0) {
500 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
501 } else {
502 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
503 }
504 tcg_gen_andi_tl(t, t, bitrev[i].mask);
505 tcg_gen_or_tl(d, d, t);
506 }
507 tcg_temp_free(t);
508 tcg_temp_free(org_s);
509 }
510
511 static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
512 {
513 int l1;
514
515 l1 = gen_new_label();
516
517 /* Conditional jmp. */
518 tcg_gen_mov_tl(env_pc, pc_false);
519 tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, l1);
520 tcg_gen_mov_tl(env_pc, pc_true);
521 gen_set_label(l1);
522 }
523
524 static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
525 {
526 TranslationBlock *tb;
527 tb = dc->tb;
528 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
529 tcg_gen_goto_tb(n);
530 tcg_gen_movi_tl(env_pc, dest);
531 tcg_gen_exit_tb((uintptr_t)tb + n);
532 } else {
533 tcg_gen_movi_tl(env_pc, dest);
534 tcg_gen_exit_tb(0);
535 }
536 }
537
538 static inline void cris_clear_x_flag(DisasContext *dc)
539 {
540 if (dc->flagx_known && dc->flags_x) {
541 dc->flags_uptodate = 0;
542 }
543
544 dc->flagx_known = 1;
545 dc->flags_x = 0;
546 }
547
548 static void cris_flush_cc_state(DisasContext *dc)
549 {
550 if (dc->cc_size_uptodate != dc->cc_size) {
551 tcg_gen_movi_tl(cc_size, dc->cc_size);
552 dc->cc_size_uptodate = dc->cc_size;
553 }
554 tcg_gen_movi_tl(cc_op, dc->cc_op);
555 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
556 }
557
558 static void cris_evaluate_flags(DisasContext *dc)
559 {
560 if (dc->flags_uptodate) {
561 return;
562 }
563
564 cris_flush_cc_state(dc);
565
566 switch (dc->cc_op) {
567 case CC_OP_MCP:
568 gen_helper_evaluate_flags_mcp(cpu_PR[PR_CCS], cpu_env,
569 cpu_PR[PR_CCS], cc_src,
570 cc_dest, cc_result);
571 break;
572 case CC_OP_MULS:
573 gen_helper_evaluate_flags_muls(cpu_PR[PR_CCS], cpu_env,
574 cpu_PR[PR_CCS], cc_result,
575 cpu_PR[PR_MOF]);
576 break;
577 case CC_OP_MULU:
578 gen_helper_evaluate_flags_mulu(cpu_PR[PR_CCS], cpu_env,
579 cpu_PR[PR_CCS], cc_result,
580 cpu_PR[PR_MOF]);
581 break;
582 case CC_OP_MOVE:
583 case CC_OP_AND:
584 case CC_OP_OR:
585 case CC_OP_XOR:
586 case CC_OP_ASR:
587 case CC_OP_LSR:
588 case CC_OP_LSL:
589 switch (dc->cc_size) {
590 case 4:
591 gen_helper_evaluate_flags_move_4(cpu_PR[PR_CCS],
592 cpu_env, cpu_PR[PR_CCS], cc_result);
593 break;
594 case 2:
595 gen_helper_evaluate_flags_move_2(cpu_PR[PR_CCS],
596 cpu_env, cpu_PR[PR_CCS], cc_result);
597 break;
598 default:
599 gen_helper_evaluate_flags(cpu_env);
600 break;
601 }
602 break;
603 case CC_OP_FLAGS:
604 /* live. */
605 break;
606 case CC_OP_SUB:
607 case CC_OP_CMP:
608 if (dc->cc_size == 4) {
609 gen_helper_evaluate_flags_sub_4(cpu_PR[PR_CCS], cpu_env,
610 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
611 } else {
612 gen_helper_evaluate_flags(cpu_env);
613 }
614
615 break;
616 default:
617 switch (dc->cc_size) {
618 case 4:
619 gen_helper_evaluate_flags_alu_4(cpu_PR[PR_CCS], cpu_env,
620 cpu_PR[PR_CCS], cc_src, cc_dest, cc_result);
621 break;
622 default:
623 gen_helper_evaluate_flags(cpu_env);
624 break;
625 }
626 break;
627 }
628
629 if (dc->flagx_known) {
630 if (dc->flags_x) {
631 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], X_FLAG);
632 } else if (dc->cc_op == CC_OP_FLAGS) {
633 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
634 }
635 }
636 dc->flags_uptodate = 1;
637 }
638
639 static void cris_cc_mask(DisasContext *dc, unsigned int mask)
640 {
641 uint32_t ovl;
642
643 if (!mask) {
644 dc->update_cc = 0;
645 return;
646 }
647
648 /* Check if we need to evaluate the condition codes due to
649 CC overlaying. */
650 ovl = (dc->cc_mask ^ mask) & ~mask;
651 if (ovl) {
652 /* TODO: optimize this case. It trigs all the time. */
653 cris_evaluate_flags(dc);
654 }
655 dc->cc_mask = mask;
656 dc->update_cc = 1;
657 }
658
659 static void cris_update_cc_op(DisasContext *dc, int op, int size)
660 {
661 dc->cc_op = op;
662 dc->cc_size = size;
663 dc->flags_uptodate = 0;
664 }
665
666 static inline void cris_update_cc_x(DisasContext *dc)
667 {
668 /* Save the x flag state at the time of the cc snapshot. */
669 if (dc->flagx_known) {
670 if (dc->cc_x_uptodate == (2 | dc->flags_x)) {
671 return;
672 }
673 tcg_gen_movi_tl(cc_x, dc->flags_x);
674 dc->cc_x_uptodate = 2 | dc->flags_x;
675 } else {
676 tcg_gen_andi_tl(cc_x, cpu_PR[PR_CCS], X_FLAG);
677 dc->cc_x_uptodate = 1;
678 }
679 }
680
681 /* Update cc prior to executing ALU op. Needs source operands untouched. */
682 static void cris_pre_alu_update_cc(DisasContext *dc, int op,
683 TCGv dst, TCGv src, int size)
684 {
685 if (dc->update_cc) {
686 cris_update_cc_op(dc, op, size);
687 tcg_gen_mov_tl(cc_src, src);
688
689 if (op != CC_OP_MOVE
690 && op != CC_OP_AND
691 && op != CC_OP_OR
692 && op != CC_OP_XOR
693 && op != CC_OP_ASR
694 && op != CC_OP_LSR
695 && op != CC_OP_LSL) {
696 tcg_gen_mov_tl(cc_dest, dst);
697 }
698
699 cris_update_cc_x(dc);
700 }
701 }
702
703 /* Update cc after executing ALU op. needs the result. */
704 static inline void cris_update_result(DisasContext *dc, TCGv res)
705 {
706 if (dc->update_cc) {
707 tcg_gen_mov_tl(cc_result, res);
708 }
709 }
710
711 /* Returns one if the write back stage should execute. */
712 static void cris_alu_op_exec(DisasContext *dc, int op,
713 TCGv dst, TCGv a, TCGv b, int size)
714 {
715 /* Emit the ALU insns. */
716 switch (op) {
717 case CC_OP_ADD:
718 tcg_gen_add_tl(dst, a, b);
719 /* Extended arithmetics. */
720 t_gen_addx_carry(dc, dst);
721 break;
722 case CC_OP_ADDC:
723 tcg_gen_add_tl(dst, a, b);
724 t_gen_add_flag(dst, 0); /* C_FLAG. */
725 break;
726 case CC_OP_MCP:
727 tcg_gen_add_tl(dst, a, b);
728 t_gen_add_flag(dst, 8); /* R_FLAG. */
729 break;
730 case CC_OP_SUB:
731 tcg_gen_sub_tl(dst, a, b);
732 /* Extended arithmetics. */
733 t_gen_subx_carry(dc, dst);
734 break;
735 case CC_OP_MOVE:
736 tcg_gen_mov_tl(dst, b);
737 break;
738 case CC_OP_OR:
739 tcg_gen_or_tl(dst, a, b);
740 break;
741 case CC_OP_AND:
742 tcg_gen_and_tl(dst, a, b);
743 break;
744 case CC_OP_XOR:
745 tcg_gen_xor_tl(dst, a, b);
746 break;
747 case CC_OP_LSL:
748 t_gen_lsl(dst, a, b);
749 break;
750 case CC_OP_LSR:
751 t_gen_lsr(dst, a, b);
752 break;
753 case CC_OP_ASR:
754 t_gen_asr(dst, a, b);
755 break;
756 case CC_OP_NEG:
757 tcg_gen_neg_tl(dst, b);
758 /* Extended arithmetics. */
759 t_gen_subx_carry(dc, dst);
760 break;
761 case CC_OP_LZ:
762 gen_helper_lz(dst, b);
763 break;
764 case CC_OP_MULS:
765 tcg_gen_muls2_tl(dst, cpu_PR[PR_MOF], a, b);
766 break;
767 case CC_OP_MULU:
768 tcg_gen_mulu2_tl(dst, cpu_PR[PR_MOF], a, b);
769 break;
770 case CC_OP_DSTEP:
771 t_gen_cris_dstep(dst, a, b);
772 break;
773 case CC_OP_MSTEP:
774 t_gen_cris_mstep(dst, a, b, cpu_PR[PR_CCS]);
775 break;
776 case CC_OP_BOUND:
777 {
778 int l1;
779 l1 = gen_new_label();
780 tcg_gen_mov_tl(dst, a);
781 tcg_gen_brcond_tl(TCG_COND_LEU, a, b, l1);
782 tcg_gen_mov_tl(dst, b);
783 gen_set_label(l1);
784 }
785 break;
786 case CC_OP_CMP:
787 tcg_gen_sub_tl(dst, a, b);
788 /* Extended arithmetics. */
789 t_gen_subx_carry(dc, dst);
790 break;
791 default:
792 qemu_log("illegal ALU op.\n");
793 BUG();
794 break;
795 }
796
797 if (size == 1) {
798 tcg_gen_andi_tl(dst, dst, 0xff);
799 } else if (size == 2) {
800 tcg_gen_andi_tl(dst, dst, 0xffff);
801 }
802 }
803
804 static void cris_alu(DisasContext *dc, int op,
805 TCGv d, TCGv op_a, TCGv op_b, int size)
806 {
807 TCGv tmp;
808 int writeback;
809
810 writeback = 1;
811
812 if (op == CC_OP_CMP) {
813 tmp = tcg_temp_new();
814 writeback = 0;
815 } else if (size == 4) {
816 tmp = d;
817 writeback = 0;
818 } else {
819 tmp = tcg_temp_new();
820 }
821
822
823 cris_pre_alu_update_cc(dc, op, op_a, op_b, size);
824 cris_alu_op_exec(dc, op, tmp, op_a, op_b, size);
825 cris_update_result(dc, tmp);
826
827 /* Writeback. */
828 if (writeback) {
829 if (size == 1) {
830 tcg_gen_andi_tl(d, d, ~0xff);
831 } else {
832 tcg_gen_andi_tl(d, d, ~0xffff);
833 }
834 tcg_gen_or_tl(d, d, tmp);
835 }
836 if (!TCGV_EQUAL(tmp, d)) {
837 tcg_temp_free(tmp);
838 }
839 }
840
841 static int arith_cc(DisasContext *dc)
842 {
843 if (dc->update_cc) {
844 switch (dc->cc_op) {
845 case CC_OP_ADDC: return 1;
846 case CC_OP_ADD: return 1;
847 case CC_OP_SUB: return 1;
848 case CC_OP_DSTEP: return 1;
849 case CC_OP_LSL: return 1;
850 case CC_OP_LSR: return 1;
851 case CC_OP_ASR: return 1;
852 case CC_OP_CMP: return 1;
853 case CC_OP_NEG: return 1;
854 case CC_OP_OR: return 1;
855 case CC_OP_AND: return 1;
856 case CC_OP_XOR: return 1;
857 case CC_OP_MULU: return 1;
858 case CC_OP_MULS: return 1;
859 default:
860 return 0;
861 }
862 }
863 return 0;
864 }
865
866 static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
867 {
868 int arith_opt, move_opt;
869
870 /* TODO: optimize more condition codes. */
871
872 /*
873 * If the flags are live, we've gotta look into the bits of CCS.
874 * Otherwise, if we just did an arithmetic operation we try to
875 * evaluate the condition code faster.
876 *
877 * When this function is done, T0 should be non-zero if the condition
878 * code is true.
879 */
880 arith_opt = arith_cc(dc) && !dc->flags_uptodate;
881 move_opt = (dc->cc_op == CC_OP_MOVE);
882 switch (cond) {
883 case CC_EQ:
884 if ((arith_opt || move_opt)
885 && dc->cc_x_uptodate != (2 | X_FLAG)) {
886 tcg_gen_setcond_tl(TCG_COND_EQ, cc,
887 cc_result, tcg_const_tl(0));
888 } else {
889 cris_evaluate_flags(dc);
890 tcg_gen_andi_tl(cc,
891 cpu_PR[PR_CCS], Z_FLAG);
892 }
893 break;
894 case CC_NE:
895 if ((arith_opt || move_opt)
896 && dc->cc_x_uptodate != (2 | X_FLAG)) {
897 tcg_gen_mov_tl(cc, cc_result);
898 } else {
899 cris_evaluate_flags(dc);
900 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
901 Z_FLAG);
902 tcg_gen_andi_tl(cc, cc, Z_FLAG);
903 }
904 break;
905 case CC_CS:
906 cris_evaluate_flags(dc);
907 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], C_FLAG);
908 break;
909 case CC_CC:
910 cris_evaluate_flags(dc);
911 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS], C_FLAG);
912 tcg_gen_andi_tl(cc, cc, C_FLAG);
913 break;
914 case CC_VS:
915 cris_evaluate_flags(dc);
916 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], V_FLAG);
917 break;
918 case CC_VC:
919 cris_evaluate_flags(dc);
920 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
921 V_FLAG);
922 tcg_gen_andi_tl(cc, cc, V_FLAG);
923 break;
924 case CC_PL:
925 if (arith_opt || move_opt) {
926 int bits = 31;
927
928 if (dc->cc_size == 1) {
929 bits = 7;
930 } else if (dc->cc_size == 2) {
931 bits = 15;
932 }
933
934 tcg_gen_shri_tl(cc, cc_result, bits);
935 tcg_gen_xori_tl(cc, cc, 1);
936 } else {
937 cris_evaluate_flags(dc);
938 tcg_gen_xori_tl(cc, cpu_PR[PR_CCS],
939 N_FLAG);
940 tcg_gen_andi_tl(cc, cc, N_FLAG);
941 }
942 break;
943 case CC_MI:
944 if (arith_opt || move_opt) {
945 int bits = 31;
946
947 if (dc->cc_size == 1) {
948 bits = 7;
949 } else if (dc->cc_size == 2) {
950 bits = 15;
951 }
952
953 tcg_gen_shri_tl(cc, cc_result, bits);
954 tcg_gen_andi_tl(cc, cc, 1);
955 } else {
956 cris_evaluate_flags(dc);
957 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
958 N_FLAG);
959 }
960 break;
961 case CC_LS:
962 cris_evaluate_flags(dc);
963 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS],
964 C_FLAG | Z_FLAG);
965 break;
966 case CC_HI:
967 cris_evaluate_flags(dc);
968 {
969 TCGv tmp;
970
971 tmp = tcg_temp_new();
972 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
973 C_FLAG | Z_FLAG);
974 /* Overlay the C flag on top of the Z. */
975 tcg_gen_shli_tl(cc, tmp, 2);
976 tcg_gen_and_tl(cc, tmp, cc);
977 tcg_gen_andi_tl(cc, cc, Z_FLAG);
978
979 tcg_temp_free(tmp);
980 }
981 break;
982 case CC_GE:
983 cris_evaluate_flags(dc);
984 /* Overlay the V flag on top of the N. */
985 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
986 tcg_gen_xor_tl(cc,
987 cpu_PR[PR_CCS], cc);
988 tcg_gen_andi_tl(cc, cc, N_FLAG);
989 tcg_gen_xori_tl(cc, cc, N_FLAG);
990 break;
991 case CC_LT:
992 cris_evaluate_flags(dc);
993 /* Overlay the V flag on top of the N. */
994 tcg_gen_shli_tl(cc, cpu_PR[PR_CCS], 2);
995 tcg_gen_xor_tl(cc,
996 cpu_PR[PR_CCS], cc);
997 tcg_gen_andi_tl(cc, cc, N_FLAG);
998 break;
999 case CC_GT:
1000 cris_evaluate_flags(dc);
1001 {
1002 TCGv n, z;
1003
1004 n = tcg_temp_new();
1005 z = tcg_temp_new();
1006
1007 /* To avoid a shift we overlay everything on
1008 the V flag. */
1009 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1010 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1011 /* invert Z. */
1012 tcg_gen_xori_tl(z, z, 2);
1013
1014 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1015 tcg_gen_xori_tl(n, n, 2);
1016 tcg_gen_and_tl(cc, z, n);
1017 tcg_gen_andi_tl(cc, cc, 2);
1018
1019 tcg_temp_free(n);
1020 tcg_temp_free(z);
1021 }
1022 break;
1023 case CC_LE:
1024 cris_evaluate_flags(dc);
1025 {
1026 TCGv n, z;
1027
1028 n = tcg_temp_new();
1029 z = tcg_temp_new();
1030
1031 /* To avoid a shift we overlay everything on
1032 the V flag. */
1033 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1034 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1035
1036 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1037 tcg_gen_or_tl(cc, z, n);
1038 tcg_gen_andi_tl(cc, cc, 2);
1039
1040 tcg_temp_free(n);
1041 tcg_temp_free(z);
1042 }
1043 break;
1044 case CC_P:
1045 cris_evaluate_flags(dc);
1046 tcg_gen_andi_tl(cc, cpu_PR[PR_CCS], P_FLAG);
1047 break;
1048 case CC_A:
1049 tcg_gen_movi_tl(cc, 1);
1050 break;
1051 default:
1052 BUG();
1053 break;
1054 };
1055 }
1056
1057 static void cris_store_direct_jmp(DisasContext *dc)
1058 {
1059 /* Store the direct jmp state into the cpu-state. */
1060 if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
1061 if (dc->jmp == JMP_DIRECT) {
1062 tcg_gen_movi_tl(env_btaken, 1);
1063 }
1064 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1065 dc->jmp = JMP_INDIRECT;
1066 }
1067 }
1068
1069 static void cris_prepare_cc_branch (DisasContext *dc,
1070 int offset, int cond)
1071 {
1072 /* This helps us re-schedule the micro-code to insns in delay-slots
1073 before the actual jump. */
1074 dc->delayed_branch = 2;
1075 dc->jmp = JMP_DIRECT_CC;
1076 dc->jmp_pc = dc->pc + offset;
1077
1078 gen_tst_cc(dc, env_btaken, cond);
1079 tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
1080 }
1081
1082
1083 /* jumps, when the dest is in a live reg for example. Direct should be set
1084 when the dest addr is constant to allow tb chaining. */
1085 static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
1086 {
1087 /* This helps us re-schedule the micro-code to insns in delay-slots
1088 before the actual jump. */
1089 dc->delayed_branch = 2;
1090 dc->jmp = type;
1091 if (type == JMP_INDIRECT) {
1092 tcg_gen_movi_tl(env_btaken, 1);
1093 }
1094 }
1095
1096 static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
1097 {
1098 int mem_index = cpu_mmu_index(&dc->cpu->env);
1099
1100 /* If we get a fault on a delayslot we must keep the jmp state in
1101 the cpu-state to be able to re-execute the jmp. */
1102 if (dc->delayed_branch == 1) {
1103 cris_store_direct_jmp(dc);
1104 }
1105
1106 tcg_gen_qemu_ld_i64(dst, addr, mem_index, MO_TEQ);
1107 }
1108
1109 static void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1110 unsigned int size, int sign)
1111 {
1112 int mem_index = cpu_mmu_index(&dc->cpu->env);
1113
1114 /* If we get a fault on a delayslot we must keep the jmp state in
1115 the cpu-state to be able to re-execute the jmp. */
1116 if (dc->delayed_branch == 1) {
1117 cris_store_direct_jmp(dc);
1118 }
1119
1120 tcg_gen_qemu_ld_tl(dst, addr, mem_index,
1121 MO_TE + ctz32(size) + (sign ? MO_SIGN : 0));
1122 }
1123
1124 static void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1125 unsigned int size)
1126 {
1127 int mem_index = cpu_mmu_index(&dc->cpu->env);
1128
1129 /* If we get a fault on a delayslot we must keep the jmp state in
1130 the cpu-state to be able to re-execute the jmp. */
1131 if (dc->delayed_branch == 1) {
1132 cris_store_direct_jmp(dc);
1133 }
1134
1135
1136 /* Conditional writes. We only support the kind were X and P are known
1137 at translation time. */
1138 if (dc->flagx_known && dc->flags_x && (dc->tb_flags & P_FLAG)) {
1139 dc->postinc = 0;
1140 cris_evaluate_flags(dc);
1141 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], C_FLAG);
1142 return;
1143 }
1144
1145 tcg_gen_qemu_st_tl(val, addr, mem_index, MO_TE + ctz32(size));
1146
1147 if (dc->flagx_known && dc->flags_x) {
1148 cris_evaluate_flags(dc);
1149 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~C_FLAG);
1150 }
1151 }
1152
1153 static inline void t_gen_sext(TCGv d, TCGv s, int size)
1154 {
1155 if (size == 1) {
1156 tcg_gen_ext8s_i32(d, s);
1157 } else if (size == 2) {
1158 tcg_gen_ext16s_i32(d, s);
1159 } else if (!TCGV_EQUAL(d, s)) {
1160 tcg_gen_mov_tl(d, s);
1161 }
1162 }
1163
1164 static inline void t_gen_zext(TCGv d, TCGv s, int size)
1165 {
1166 if (size == 1) {
1167 tcg_gen_ext8u_i32(d, s);
1168 } else if (size == 2) {
1169 tcg_gen_ext16u_i32(d, s);
1170 } else if (!TCGV_EQUAL(d, s)) {
1171 tcg_gen_mov_tl(d, s);
1172 }
1173 }
1174
1175 #if DISAS_CRIS
1176 static char memsize_char(int size)
1177 {
1178 switch (size) {
1179 case 1: return 'b'; break;
1180 case 2: return 'w'; break;
1181 case 4: return 'd'; break;
1182 default:
1183 return 'x';
1184 break;
1185 }
1186 }
1187 #endif
1188
1189 static inline unsigned int memsize_z(DisasContext *dc)
1190 {
1191 return dc->zsize + 1;
1192 }
1193
1194 static inline unsigned int memsize_zz(DisasContext *dc)
1195 {
1196 switch (dc->zzsize) {
1197 case 0: return 1;
1198 case 1: return 2;
1199 default:
1200 return 4;
1201 }
1202 }
1203
1204 static inline void do_postinc (DisasContext *dc, int size)
1205 {
1206 if (dc->postinc) {
1207 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
1208 }
1209 }
1210
1211 static inline void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1212 int size, int s_ext, TCGv dst)
1213 {
1214 if (s_ext) {
1215 t_gen_sext(dst, cpu_R[rs], size);
1216 } else {
1217 t_gen_zext(dst, cpu_R[rs], size);
1218 }
1219 }
1220
1221 /* Prepare T0 and T1 for a register alu operation.
1222 s_ext decides if the operand1 should be sign-extended or zero-extended when
1223 needed. */
1224 static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1225 int size, int s_ext, TCGv dst, TCGv src)
1226 {
1227 dec_prep_move_r(dc, rs, rd, size, s_ext, src);
1228
1229 if (s_ext) {
1230 t_gen_sext(dst, cpu_R[rd], size);
1231 } else {
1232 t_gen_zext(dst, cpu_R[rd], size);
1233 }
1234 }
1235
1236 static int dec_prep_move_m(CPUCRISState *env, DisasContext *dc,
1237 int s_ext, int memsize, TCGv dst)
1238 {
1239 unsigned int rs;
1240 uint32_t imm;
1241 int is_imm;
1242 int insn_len = 2;
1243
1244 rs = dc->op1;
1245 is_imm = rs == 15 && dc->postinc;
1246
1247 /* Load [$rs] onto T1. */
1248 if (is_imm) {
1249 insn_len = 2 + memsize;
1250 if (memsize == 1) {
1251 insn_len++;
1252 }
1253
1254 imm = cris_fetch(env, dc, dc->pc + 2, memsize, s_ext);
1255 tcg_gen_movi_tl(dst, imm);
1256 dc->postinc = 0;
1257 } else {
1258 cris_flush_cc_state(dc);
1259 gen_load(dc, dst, cpu_R[rs], memsize, 0);
1260 if (s_ext) {
1261 t_gen_sext(dst, dst, memsize);
1262 } else {
1263 t_gen_zext(dst, dst, memsize);
1264 }
1265 }
1266 return insn_len;
1267 }
1268
1269 /* Prepare T0 and T1 for a memory + alu operation.
1270 s_ext decides if the operand1 should be sign-extended or zero-extended when
1271 needed. */
1272 static int dec_prep_alu_m(CPUCRISState *env, DisasContext *dc,
1273 int s_ext, int memsize, TCGv dst, TCGv src)
1274 {
1275 int insn_len;
1276
1277 insn_len = dec_prep_move_m(env, dc, s_ext, memsize, src);
1278 tcg_gen_mov_tl(dst, cpu_R[dc->op2]);
1279 return insn_len;
1280 }
1281
1282 #if DISAS_CRIS
1283 static const char *cc_name(int cc)
1284 {
1285 static const char *cc_names[16] = {
1286 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1287 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1288 };
1289 assert(cc < 16);
1290 return cc_names[cc];
1291 }
1292 #endif
1293
1294 /* Start of insn decoders. */
1295
1296 static int dec_bccq(CPUCRISState *env, DisasContext *dc)
1297 {
1298 int32_t offset;
1299 int sign;
1300 uint32_t cond = dc->op2;
1301
1302 offset = EXTRACT_FIELD(dc->ir, 1, 7);
1303 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1304
1305 offset *= 2;
1306 offset |= sign << 8;
1307 offset = sign_extend(offset, 8);
1308
1309 LOG_DIS("b%s %x\n", cc_name(cond), dc->pc + offset);
1310
1311 /* op2 holds the condition-code. */
1312 cris_cc_mask(dc, 0);
1313 cris_prepare_cc_branch(dc, offset, cond);
1314 return 2;
1315 }
1316 static int dec_addoq(CPUCRISState *env, DisasContext *dc)
1317 {
1318 int32_t imm;
1319
1320 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1321 imm = sign_extend(dc->op1, 7);
1322
1323 LOG_DIS("addoq %d, $r%u\n", imm, dc->op2);
1324 cris_cc_mask(dc, 0);
1325 /* Fetch register operand, */
1326 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
1327
1328 return 2;
1329 }
1330 static int dec_addq(CPUCRISState *env, DisasContext *dc)
1331 {
1332 LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2);
1333
1334 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1335
1336 cris_cc_mask(dc, CC_MASK_NZVC);
1337
1338 cris_alu(dc, CC_OP_ADD,
1339 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1340 return 2;
1341 }
1342 static int dec_moveq(CPUCRISState *env, DisasContext *dc)
1343 {
1344 uint32_t imm;
1345
1346 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1347 imm = sign_extend(dc->op1, 5);
1348 LOG_DIS("moveq %d, $r%u\n", imm, dc->op2);
1349
1350 tcg_gen_movi_tl(cpu_R[dc->op2], imm);
1351 return 2;
1352 }
1353 static int dec_subq(CPUCRISState *env, DisasContext *dc)
1354 {
1355 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1356
1357 LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2);
1358
1359 cris_cc_mask(dc, CC_MASK_NZVC);
1360 cris_alu(dc, CC_OP_SUB,
1361 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4);
1362 return 2;
1363 }
1364 static int dec_cmpq(CPUCRISState *env, DisasContext *dc)
1365 {
1366 uint32_t imm;
1367 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1368 imm = sign_extend(dc->op1, 5);
1369
1370 LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2);
1371 cris_cc_mask(dc, CC_MASK_NZVC);
1372
1373 cris_alu(dc, CC_OP_CMP,
1374 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1375 return 2;
1376 }
1377 static int dec_andq(CPUCRISState *env, DisasContext *dc)
1378 {
1379 uint32_t imm;
1380 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1381 imm = sign_extend(dc->op1, 5);
1382
1383 LOG_DIS("andq %d, $r%d\n", imm, dc->op2);
1384 cris_cc_mask(dc, CC_MASK_NZ);
1385
1386 cris_alu(dc, CC_OP_AND,
1387 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1388 return 2;
1389 }
1390 static int dec_orq(CPUCRISState *env, DisasContext *dc)
1391 {
1392 uint32_t imm;
1393 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1394 imm = sign_extend(dc->op1, 5);
1395 LOG_DIS("orq %d, $r%d\n", imm, dc->op2);
1396 cris_cc_mask(dc, CC_MASK_NZ);
1397
1398 cris_alu(dc, CC_OP_OR,
1399 cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4);
1400 return 2;
1401 }
1402 static int dec_btstq(CPUCRISState *env, DisasContext *dc)
1403 {
1404 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1405 LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2);
1406
1407 cris_cc_mask(dc, CC_MASK_NZ);
1408 cris_evaluate_flags(dc);
1409 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1410 tcg_const_tl(dc->op1), cpu_PR[PR_CCS]);
1411 cris_alu(dc, CC_OP_MOVE,
1412 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1413 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1414 dc->flags_uptodate = 1;
1415 return 2;
1416 }
1417 static int dec_asrq(CPUCRISState *env, DisasContext *dc)
1418 {
1419 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1420 LOG_DIS("asrq %u, $r%d\n", dc->op1, dc->op2);
1421 cris_cc_mask(dc, CC_MASK_NZ);
1422
1423 tcg_gen_sari_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1424 cris_alu(dc, CC_OP_MOVE,
1425 cpu_R[dc->op2],
1426 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1427 return 2;
1428 }
1429 static int dec_lslq(CPUCRISState *env, DisasContext *dc)
1430 {
1431 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1432 LOG_DIS("lslq %u, $r%d\n", dc->op1, dc->op2);
1433
1434 cris_cc_mask(dc, CC_MASK_NZ);
1435
1436 tcg_gen_shli_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1437
1438 cris_alu(dc, CC_OP_MOVE,
1439 cpu_R[dc->op2],
1440 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1441 return 2;
1442 }
1443 static int dec_lsrq(CPUCRISState *env, DisasContext *dc)
1444 {
1445 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1446 LOG_DIS("lsrq %u, $r%d\n", dc->op1, dc->op2);
1447
1448 cris_cc_mask(dc, CC_MASK_NZ);
1449
1450 tcg_gen_shri_tl(cpu_R[dc->op2], cpu_R[dc->op2], dc->op1);
1451 cris_alu(dc, CC_OP_MOVE,
1452 cpu_R[dc->op2],
1453 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1454 return 2;
1455 }
1456
1457 static int dec_move_r(CPUCRISState *env, DisasContext *dc)
1458 {
1459 int size = memsize_zz(dc);
1460
1461 LOG_DIS("move.%c $r%u, $r%u\n",
1462 memsize_char(size), dc->op1, dc->op2);
1463
1464 cris_cc_mask(dc, CC_MASK_NZ);
1465 if (size == 4) {
1466 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, cpu_R[dc->op2]);
1467 cris_cc_mask(dc, CC_MASK_NZ);
1468 cris_update_cc_op(dc, CC_OP_MOVE, 4);
1469 cris_update_cc_x(dc);
1470 cris_update_result(dc, cpu_R[dc->op2]);
1471 } else {
1472 TCGv t0;
1473
1474 t0 = tcg_temp_new();
1475 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1476 cris_alu(dc, CC_OP_MOVE,
1477 cpu_R[dc->op2],
1478 cpu_R[dc->op2], t0, size);
1479 tcg_temp_free(t0);
1480 }
1481 return 2;
1482 }
1483
1484 static int dec_scc_r(CPUCRISState *env, DisasContext *dc)
1485 {
1486 int cond = dc->op2;
1487
1488 LOG_DIS("s%s $r%u\n",
1489 cc_name(cond), dc->op1);
1490
1491 if (cond != CC_A) {
1492 int l1;
1493
1494 gen_tst_cc(dc, cpu_R[dc->op1], cond);
1495 l1 = gen_new_label();
1496 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_R[dc->op1], 0, l1);
1497 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1498 gen_set_label(l1);
1499 } else {
1500 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1501 }
1502
1503 cris_cc_mask(dc, 0);
1504 return 2;
1505 }
1506
1507 static inline void cris_alu_alloc_temps(DisasContext *dc, int size, TCGv *t)
1508 {
1509 if (size == 4) {
1510 t[0] = cpu_R[dc->op2];
1511 t[1] = cpu_R[dc->op1];
1512 } else {
1513 t[0] = tcg_temp_new();
1514 t[1] = tcg_temp_new();
1515 }
1516 }
1517
1518 static inline void cris_alu_free_temps(DisasContext *dc, int size, TCGv *t)
1519 {
1520 if (size != 4) {
1521 tcg_temp_free(t[0]);
1522 tcg_temp_free(t[1]);
1523 }
1524 }
1525
1526 static int dec_and_r(CPUCRISState *env, DisasContext *dc)
1527 {
1528 TCGv t[2];
1529 int size = memsize_zz(dc);
1530
1531 LOG_DIS("and.%c $r%u, $r%u\n",
1532 memsize_char(size), dc->op1, dc->op2);
1533
1534 cris_cc_mask(dc, CC_MASK_NZ);
1535
1536 cris_alu_alloc_temps(dc, size, t);
1537 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1538 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], size);
1539 cris_alu_free_temps(dc, size, t);
1540 return 2;
1541 }
1542
1543 static int dec_lz_r(CPUCRISState *env, DisasContext *dc)
1544 {
1545 TCGv t0;
1546 LOG_DIS("lz $r%u, $r%u\n",
1547 dc->op1, dc->op2);
1548 cris_cc_mask(dc, CC_MASK_NZ);
1549 t0 = tcg_temp_new();
1550 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0, cpu_R[dc->op2], t0);
1551 cris_alu(dc, CC_OP_LZ, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1552 tcg_temp_free(t0);
1553 return 2;
1554 }
1555
1556 static int dec_lsl_r(CPUCRISState *env, DisasContext *dc)
1557 {
1558 TCGv t[2];
1559 int size = memsize_zz(dc);
1560
1561 LOG_DIS("lsl.%c $r%u, $r%u\n",
1562 memsize_char(size), dc->op1, dc->op2);
1563
1564 cris_cc_mask(dc, CC_MASK_NZ);
1565 cris_alu_alloc_temps(dc, size, t);
1566 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1567 tcg_gen_andi_tl(t[1], t[1], 63);
1568 cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size);
1569 cris_alu_alloc_temps(dc, size, t);
1570 return 2;
1571 }
1572
1573 static int dec_lsr_r(CPUCRISState *env, DisasContext *dc)
1574 {
1575 TCGv t[2];
1576 int size = memsize_zz(dc);
1577
1578 LOG_DIS("lsr.%c $r%u, $r%u\n",
1579 memsize_char(size), dc->op1, dc->op2);
1580
1581 cris_cc_mask(dc, CC_MASK_NZ);
1582 cris_alu_alloc_temps(dc, size, t);
1583 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1584 tcg_gen_andi_tl(t[1], t[1], 63);
1585 cris_alu(dc, CC_OP_LSR, cpu_R[dc->op2], t[0], t[1], size);
1586 cris_alu_free_temps(dc, size, t);
1587 return 2;
1588 }
1589
1590 static int dec_asr_r(CPUCRISState *env, DisasContext *dc)
1591 {
1592 TCGv t[2];
1593 int size = memsize_zz(dc);
1594
1595 LOG_DIS("asr.%c $r%u, $r%u\n",
1596 memsize_char(size), dc->op1, dc->op2);
1597
1598 cris_cc_mask(dc, CC_MASK_NZ);
1599 cris_alu_alloc_temps(dc, size, t);
1600 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1601 tcg_gen_andi_tl(t[1], t[1], 63);
1602 cris_alu(dc, CC_OP_ASR, cpu_R[dc->op2], t[0], t[1], size);
1603 cris_alu_free_temps(dc, size, t);
1604 return 2;
1605 }
1606
1607 static int dec_muls_r(CPUCRISState *env, DisasContext *dc)
1608 {
1609 TCGv t[2];
1610 int size = memsize_zz(dc);
1611
1612 LOG_DIS("muls.%c $r%u, $r%u\n",
1613 memsize_char(size), dc->op1, dc->op2);
1614 cris_cc_mask(dc, CC_MASK_NZV);
1615 cris_alu_alloc_temps(dc, size, t);
1616 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1, t[0], t[1]);
1617
1618 cris_alu(dc, CC_OP_MULS, cpu_R[dc->op2], t[0], t[1], 4);
1619 cris_alu_free_temps(dc, size, t);
1620 return 2;
1621 }
1622
1623 static int dec_mulu_r(CPUCRISState *env, DisasContext *dc)
1624 {
1625 TCGv t[2];
1626 int size = memsize_zz(dc);
1627
1628 LOG_DIS("mulu.%c $r%u, $r%u\n",
1629 memsize_char(size), dc->op1, dc->op2);
1630 cris_cc_mask(dc, CC_MASK_NZV);
1631 cris_alu_alloc_temps(dc, size, t);
1632 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1633
1634 cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4);
1635 cris_alu_alloc_temps(dc, size, t);
1636 return 2;
1637 }
1638
1639
1640 static int dec_dstep_r(CPUCRISState *env, DisasContext *dc)
1641 {
1642 LOG_DIS("dstep $r%u, $r%u\n", dc->op1, dc->op2);
1643 cris_cc_mask(dc, CC_MASK_NZ);
1644 cris_alu(dc, CC_OP_DSTEP,
1645 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1646 return 2;
1647 }
1648
1649 static int dec_xor_r(CPUCRISState *env, DisasContext *dc)
1650 {
1651 TCGv t[2];
1652 int size = memsize_zz(dc);
1653 LOG_DIS("xor.%c $r%u, $r%u\n",
1654 memsize_char(size), dc->op1, dc->op2);
1655 BUG_ON(size != 4); /* xor is dword. */
1656 cris_cc_mask(dc, CC_MASK_NZ);
1657 cris_alu_alloc_temps(dc, size, t);
1658 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1659
1660 cris_alu(dc, CC_OP_XOR, cpu_R[dc->op2], t[0], t[1], 4);
1661 cris_alu_free_temps(dc, size, t);
1662 return 2;
1663 }
1664
1665 static int dec_bound_r(CPUCRISState *env, DisasContext *dc)
1666 {
1667 TCGv l0;
1668 int size = memsize_zz(dc);
1669 LOG_DIS("bound.%c $r%u, $r%u\n",
1670 memsize_char(size), dc->op1, dc->op2);
1671 cris_cc_mask(dc, CC_MASK_NZ);
1672 l0 = tcg_temp_local_new();
1673 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, l0);
1674 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], cpu_R[dc->op2], l0, 4);
1675 tcg_temp_free(l0);
1676 return 2;
1677 }
1678
1679 static int dec_cmp_r(CPUCRISState *env, DisasContext *dc)
1680 {
1681 TCGv t[2];
1682 int size = memsize_zz(dc);
1683 LOG_DIS("cmp.%c $r%u, $r%u\n",
1684 memsize_char(size), dc->op1, dc->op2);
1685 cris_cc_mask(dc, CC_MASK_NZVC);
1686 cris_alu_alloc_temps(dc, size, t);
1687 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1688
1689 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], t[0], t[1], size);
1690 cris_alu_free_temps(dc, size, t);
1691 return 2;
1692 }
1693
1694 static int dec_abs_r(CPUCRISState *env, DisasContext *dc)
1695 {
1696 TCGv t0;
1697
1698 LOG_DIS("abs $r%u, $r%u\n",
1699 dc->op1, dc->op2);
1700 cris_cc_mask(dc, CC_MASK_NZ);
1701
1702 t0 = tcg_temp_new();
1703 tcg_gen_sari_tl(t0, cpu_R[dc->op1], 31);
1704 tcg_gen_xor_tl(cpu_R[dc->op2], cpu_R[dc->op1], t0);
1705 tcg_gen_sub_tl(cpu_R[dc->op2], cpu_R[dc->op2], t0);
1706 tcg_temp_free(t0);
1707
1708 cris_alu(dc, CC_OP_MOVE,
1709 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4);
1710 return 2;
1711 }
1712
1713 static int dec_add_r(CPUCRISState *env, DisasContext *dc)
1714 {
1715 TCGv t[2];
1716 int size = memsize_zz(dc);
1717 LOG_DIS("add.%c $r%u, $r%u\n",
1718 memsize_char(size), dc->op1, dc->op2);
1719 cris_cc_mask(dc, CC_MASK_NZVC);
1720 cris_alu_alloc_temps(dc, size, t);
1721 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1722
1723 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], t[0], t[1], size);
1724 cris_alu_free_temps(dc, size, t);
1725 return 2;
1726 }
1727
1728 static int dec_addc_r(CPUCRISState *env, DisasContext *dc)
1729 {
1730 LOG_DIS("addc $r%u, $r%u\n",
1731 dc->op1, dc->op2);
1732 cris_evaluate_flags(dc);
1733 /* Set for this insn. */
1734 dc->flagx_known = 1;
1735 dc->flags_x = X_FLAG;
1736
1737 cris_cc_mask(dc, CC_MASK_NZVC);
1738 cris_alu(dc, CC_OP_ADDC,
1739 cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op1], 4);
1740 return 2;
1741 }
1742
1743 static int dec_mcp_r(CPUCRISState *env, DisasContext *dc)
1744 {
1745 LOG_DIS("mcp $p%u, $r%u\n",
1746 dc->op2, dc->op1);
1747 cris_evaluate_flags(dc);
1748 cris_cc_mask(dc, CC_MASK_RNZV);
1749 cris_alu(dc, CC_OP_MCP,
1750 cpu_R[dc->op1], cpu_R[dc->op1], cpu_PR[dc->op2], 4);
1751 return 2;
1752 }
1753
1754 #if DISAS_CRIS
1755 static char * swapmode_name(int mode, char *modename) {
1756 int i = 0;
1757 if (mode & 8) {
1758 modename[i++] = 'n';
1759 }
1760 if (mode & 4) {
1761 modename[i++] = 'w';
1762 }
1763 if (mode & 2) {
1764 modename[i++] = 'b';
1765 }
1766 if (mode & 1) {
1767 modename[i++] = 'r';
1768 }
1769 modename[i++] = 0;
1770 return modename;
1771 }
1772 #endif
1773
1774 static int dec_swap_r(CPUCRISState *env, DisasContext *dc)
1775 {
1776 TCGv t0;
1777 #if DISAS_CRIS
1778 char modename[4];
1779 #endif
1780 LOG_DIS("swap%s $r%u\n",
1781 swapmode_name(dc->op2, modename), dc->op1);
1782
1783 cris_cc_mask(dc, CC_MASK_NZ);
1784 t0 = tcg_temp_new();
1785 tcg_gen_mov_tl(t0, cpu_R[dc->op1]);
1786 if (dc->op2 & 8) {
1787 tcg_gen_not_tl(t0, t0);
1788 }
1789 if (dc->op2 & 4) {
1790 t_gen_swapw(t0, t0);
1791 }
1792 if (dc->op2 & 2) {
1793 t_gen_swapb(t0, t0);
1794 }
1795 if (dc->op2 & 1) {
1796 t_gen_swapr(t0, t0);
1797 }
1798 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op1], cpu_R[dc->op1], t0, 4);
1799 tcg_temp_free(t0);
1800 return 2;
1801 }
1802
1803 static int dec_or_r(CPUCRISState *env, DisasContext *dc)
1804 {
1805 TCGv t[2];
1806 int size = memsize_zz(dc);
1807 LOG_DIS("or.%c $r%u, $r%u\n",
1808 memsize_char(size), dc->op1, dc->op2);
1809 cris_cc_mask(dc, CC_MASK_NZ);
1810 cris_alu_alloc_temps(dc, size, t);
1811 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1812 cris_alu(dc, CC_OP_OR, cpu_R[dc->op2], t[0], t[1], size);
1813 cris_alu_free_temps(dc, size, t);
1814 return 2;
1815 }
1816
1817 static int dec_addi_r(CPUCRISState *env, DisasContext *dc)
1818 {
1819 TCGv t0;
1820 LOG_DIS("addi.%c $r%u, $r%u\n",
1821 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1822 cris_cc_mask(dc, 0);
1823 t0 = tcg_temp_new();
1824 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1825 tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0);
1826 tcg_temp_free(t0);
1827 return 2;
1828 }
1829
1830 static int dec_addi_acr(CPUCRISState *env, DisasContext *dc)
1831 {
1832 TCGv t0;
1833 LOG_DIS("addi.%c $r%u, $r%u, $acr\n",
1834 memsize_char(memsize_zz(dc)), dc->op2, dc->op1);
1835 cris_cc_mask(dc, 0);
1836 t0 = tcg_temp_new();
1837 tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize));
1838 tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0);
1839 tcg_temp_free(t0);
1840 return 2;
1841 }
1842
1843 static int dec_neg_r(CPUCRISState *env, DisasContext *dc)
1844 {
1845 TCGv t[2];
1846 int size = memsize_zz(dc);
1847 LOG_DIS("neg.%c $r%u, $r%u\n",
1848 memsize_char(size), dc->op1, dc->op2);
1849 cris_cc_mask(dc, CC_MASK_NZVC);
1850 cris_alu_alloc_temps(dc, size, t);
1851 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1852
1853 cris_alu(dc, CC_OP_NEG, cpu_R[dc->op2], t[0], t[1], size);
1854 cris_alu_free_temps(dc, size, t);
1855 return 2;
1856 }
1857
1858 static int dec_btst_r(CPUCRISState *env, DisasContext *dc)
1859 {
1860 LOG_DIS("btst $r%u, $r%u\n",
1861 dc->op1, dc->op2);
1862 cris_cc_mask(dc, CC_MASK_NZ);
1863 cris_evaluate_flags(dc);
1864 gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2],
1865 cpu_R[dc->op1], cpu_PR[PR_CCS]);
1866 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2],
1867 cpu_R[dc->op2], cpu_R[dc->op2], 4);
1868 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1869 dc->flags_uptodate = 1;
1870 return 2;
1871 }
1872
1873 static int dec_sub_r(CPUCRISState *env, DisasContext *dc)
1874 {
1875 TCGv t[2];
1876 int size = memsize_zz(dc);
1877 LOG_DIS("sub.%c $r%u, $r%u\n",
1878 memsize_char(size), dc->op1, dc->op2);
1879 cris_cc_mask(dc, CC_MASK_NZVC);
1880 cris_alu_alloc_temps(dc, size, t);
1881 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]);
1882 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], size);
1883 cris_alu_free_temps(dc, size, t);
1884 return 2;
1885 }
1886
1887 /* Zero extension. From size to dword. */
1888 static int dec_movu_r(CPUCRISState *env, DisasContext *dc)
1889 {
1890 TCGv t0;
1891 int size = memsize_z(dc);
1892 LOG_DIS("movu.%c $r%u, $r%u\n",
1893 memsize_char(size),
1894 dc->op1, dc->op2);
1895
1896 cris_cc_mask(dc, CC_MASK_NZ);
1897 t0 = tcg_temp_new();
1898 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0, t0);
1899 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1900 tcg_temp_free(t0);
1901 return 2;
1902 }
1903
1904 /* Sign extension. From size to dword. */
1905 static int dec_movs_r(CPUCRISState *env, DisasContext *dc)
1906 {
1907 TCGv t0;
1908 int size = memsize_z(dc);
1909 LOG_DIS("movs.%c $r%u, $r%u\n",
1910 memsize_char(size),
1911 dc->op1, dc->op2);
1912
1913 cris_cc_mask(dc, CC_MASK_NZ);
1914 t0 = tcg_temp_new();
1915 /* Size can only be qi or hi. */
1916 t_gen_sext(t0, cpu_R[dc->op1], size);
1917 cris_alu(dc, CC_OP_MOVE,
1918 cpu_R[dc->op2], cpu_R[dc->op1], t0, 4);
1919 tcg_temp_free(t0);
1920 return 2;
1921 }
1922
1923 /* zero extension. From size to dword. */
1924 static int dec_addu_r(CPUCRISState *env, DisasContext *dc)
1925 {
1926 TCGv t0;
1927 int size = memsize_z(dc);
1928 LOG_DIS("addu.%c $r%u, $r%u\n",
1929 memsize_char(size),
1930 dc->op1, dc->op2);
1931
1932 cris_cc_mask(dc, CC_MASK_NZVC);
1933 t0 = tcg_temp_new();
1934 /* Size can only be qi or hi. */
1935 t_gen_zext(t0, cpu_R[dc->op1], size);
1936 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1937 tcg_temp_free(t0);
1938 return 2;
1939 }
1940
1941 /* Sign extension. From size to dword. */
1942 static int dec_adds_r(CPUCRISState *env, DisasContext *dc)
1943 {
1944 TCGv t0;
1945 int size = memsize_z(dc);
1946 LOG_DIS("adds.%c $r%u, $r%u\n",
1947 memsize_char(size),
1948 dc->op1, dc->op2);
1949
1950 cris_cc_mask(dc, CC_MASK_NZVC);
1951 t0 = tcg_temp_new();
1952 /* Size can only be qi or hi. */
1953 t_gen_sext(t0, cpu_R[dc->op1], size);
1954 cris_alu(dc, CC_OP_ADD,
1955 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1956 tcg_temp_free(t0);
1957 return 2;
1958 }
1959
1960 /* Zero extension. From size to dword. */
1961 static int dec_subu_r(CPUCRISState *env, DisasContext *dc)
1962 {
1963 TCGv t0;
1964 int size = memsize_z(dc);
1965 LOG_DIS("subu.%c $r%u, $r%u\n",
1966 memsize_char(size),
1967 dc->op1, dc->op2);
1968
1969 cris_cc_mask(dc, CC_MASK_NZVC);
1970 t0 = tcg_temp_new();
1971 /* Size can only be qi or hi. */
1972 t_gen_zext(t0, cpu_R[dc->op1], size);
1973 cris_alu(dc, CC_OP_SUB,
1974 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1975 tcg_temp_free(t0);
1976 return 2;
1977 }
1978
1979 /* Sign extension. From size to dword. */
1980 static int dec_subs_r(CPUCRISState *env, DisasContext *dc)
1981 {
1982 TCGv t0;
1983 int size = memsize_z(dc);
1984 LOG_DIS("subs.%c $r%u, $r%u\n",
1985 memsize_char(size),
1986 dc->op1, dc->op2);
1987
1988 cris_cc_mask(dc, CC_MASK_NZVC);
1989 t0 = tcg_temp_new();
1990 /* Size can only be qi or hi. */
1991 t_gen_sext(t0, cpu_R[dc->op1], size);
1992 cris_alu(dc, CC_OP_SUB,
1993 cpu_R[dc->op2], cpu_R[dc->op2], t0, 4);
1994 tcg_temp_free(t0);
1995 return 2;
1996 }
1997
1998 static int dec_setclrf(CPUCRISState *env, DisasContext *dc)
1999 {
2000 uint32_t flags;
2001 int set = (~dc->opcode >> 2) & 1;
2002
2003
2004 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
2005 | EXTRACT_FIELD(dc->ir, 0, 3);
2006 if (set && flags == 0) {
2007 LOG_DIS("nop\n");
2008 return 2;
2009 } else if (!set && (flags & 0x20)) {
2010 LOG_DIS("di\n");
2011 } else {
2012 LOG_DIS("%sf %x\n", set ? "set" : "clr", flags);
2013 }
2014
2015 /* User space is not allowed to touch these. Silently ignore. */
2016 if (dc->tb_flags & U_FLAG) {
2017 flags &= ~(S_FLAG | I_FLAG | U_FLAG);
2018 }
2019
2020 if (flags & X_FLAG) {
2021 dc->flagx_known = 1;
2022 if (set) {
2023 dc->flags_x = X_FLAG;
2024 } else {
2025 dc->flags_x = 0;
2026 }
2027 }
2028
2029 /* Break the TB if any of the SPI flag changes. */
2030 if (flags & (P_FLAG | S_FLAG)) {
2031 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2032 dc->is_jmp = DISAS_UPDATE;
2033 dc->cpustate_changed = 1;
2034 }
2035
2036 /* For the I flag, only act on posedge. */
2037 if ((flags & I_FLAG)) {
2038 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2039 dc->is_jmp = DISAS_UPDATE;
2040 dc->cpustate_changed = 1;
2041 }
2042
2043
2044 /* Simply decode the flags. */
2045 cris_evaluate_flags(dc);
2046 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2047 cris_update_cc_x(dc);
2048 tcg_gen_movi_tl(cc_op, dc->cc_op);
2049
2050 if (set) {
2051 if (!(dc->tb_flags & U_FLAG) && (flags & U_FLAG)) {
2052 /* Enter user mode. */
2053 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
2054 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
2055 dc->cpustate_changed = 1;
2056 }
2057 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
2058 } else {
2059 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
2060 }
2061
2062 dc->flags_uptodate = 1;
2063 dc->clear_x = 0;
2064 return 2;
2065 }
2066
2067 static int dec_move_rs(CPUCRISState *env, DisasContext *dc)
2068 {
2069 LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2);
2070 cris_cc_mask(dc, 0);
2071 gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2),
2072 tcg_const_tl(dc->op1));
2073 return 2;
2074 }
2075 static int dec_move_sr(CPUCRISState *env, DisasContext *dc)
2076 {
2077 LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1);
2078 cris_cc_mask(dc, 0);
2079 gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1),
2080 tcg_const_tl(dc->op2));
2081 return 2;
2082 }
2083
2084 static int dec_move_rp(CPUCRISState *env, DisasContext *dc)
2085 {
2086 TCGv t[2];
2087 LOG_DIS("move $r%u, $p%u\n", dc->op1, dc->op2);
2088 cris_cc_mask(dc, 0);
2089
2090 t[0] = tcg_temp_new();
2091 if (dc->op2 == PR_CCS) {
2092 cris_evaluate_flags(dc);
2093 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2094 if (dc->tb_flags & U_FLAG) {
2095 t[1] = tcg_temp_new();
2096 /* User space is not allowed to touch all flags. */
2097 tcg_gen_andi_tl(t[0], t[0], 0x39f);
2098 tcg_gen_andi_tl(t[1], cpu_PR[PR_CCS], ~0x39f);
2099 tcg_gen_or_tl(t[0], t[1], t[0]);
2100 tcg_temp_free(t[1]);
2101 }
2102 } else {
2103 tcg_gen_mov_tl(t[0], cpu_R[dc->op1]);
2104 }
2105
2106 t_gen_mov_preg_TN(dc, dc->op2, t[0]);
2107 if (dc->op2 == PR_CCS) {
2108 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2109 dc->flags_uptodate = 1;
2110 }
2111 tcg_temp_free(t[0]);
2112 return 2;
2113 }
2114 static int dec_move_pr(CPUCRISState *env, DisasContext *dc)
2115 {
2116 TCGv t0;
2117 LOG_DIS("move $p%u, $r%u\n", dc->op2, dc->op1);
2118 cris_cc_mask(dc, 0);
2119
2120 if (dc->op2 == PR_CCS) {
2121 cris_evaluate_flags(dc);
2122 }
2123
2124 if (dc->op2 == PR_DZ) {
2125 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
2126 } else {
2127 t0 = tcg_temp_new();
2128 t_gen_mov_TN_preg(t0, dc->op2);
2129 cris_alu(dc, CC_OP_MOVE,
2130 cpu_R[dc->op1], cpu_R[dc->op1], t0,
2131 preg_sizes[dc->op2]);
2132 tcg_temp_free(t0);
2133 }
2134 return 2;
2135 }
2136
2137 static int dec_move_mr(CPUCRISState *env, DisasContext *dc)
2138 {
2139 int memsize = memsize_zz(dc);
2140 int insn_len;
2141 LOG_DIS("move.%c [$r%u%s, $r%u\n",
2142 memsize_char(memsize),
2143 dc->op1, dc->postinc ? "+]" : "]",
2144 dc->op2);
2145
2146 if (memsize == 4) {
2147 insn_len = dec_prep_move_m(env, dc, 0, 4, cpu_R[dc->op2]);
2148 cris_cc_mask(dc, CC_MASK_NZ);
2149 cris_update_cc_op(dc, CC_OP_MOVE, 4);
2150 cris_update_cc_x(dc);
2151 cris_update_result(dc, cpu_R[dc->op2]);
2152 } else {
2153 TCGv t0;
2154
2155 t0 = tcg_temp_new();
2156 insn_len = dec_prep_move_m(env, dc, 0, memsize, t0);
2157 cris_cc_mask(dc, CC_MASK_NZ);
2158 cris_alu(dc, CC_OP_MOVE,
2159 cpu_R[dc->op2], cpu_R[dc->op2], t0, memsize);
2160 tcg_temp_free(t0);
2161 }
2162 do_postinc(dc, memsize);
2163 return insn_len;
2164 }
2165
2166 static inline void cris_alu_m_alloc_temps(TCGv *t)
2167 {
2168 t[0] = tcg_temp_new();
2169 t[1] = tcg_temp_new();
2170 }
2171
2172 static inline void cris_alu_m_free_temps(TCGv *t)
2173 {
2174 tcg_temp_free(t[0]);
2175 tcg_temp_free(t[1]);
2176 }
2177
2178 static int dec_movs_m(CPUCRISState *env, DisasContext *dc)
2179 {
2180 TCGv t[2];
2181 int memsize = memsize_z(dc);
2182 int insn_len;
2183 LOG_DIS("movs.%c [$r%u%s, $r%u\n",
2184 memsize_char(memsize),
2185 dc->op1, dc->postinc ? "+]" : "]",
2186 dc->op2);
2187
2188 cris_alu_m_alloc_temps(t);
2189 /* sign extend. */
2190 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2191 cris_cc_mask(dc, CC_MASK_NZ);
2192 cris_alu(dc, CC_OP_MOVE,
2193 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2194 do_postinc(dc, memsize);
2195 cris_alu_m_free_temps(t);
2196 return insn_len;
2197 }
2198
2199 static int dec_addu_m(CPUCRISState *env, DisasContext *dc)
2200 {
2201 TCGv t[2];
2202 int memsize = memsize_z(dc);
2203 int insn_len;
2204 LOG_DIS("addu.%c [$r%u%s, $r%u\n",
2205 memsize_char(memsize),
2206 dc->op1, dc->postinc ? "+]" : "]",
2207 dc->op2);
2208
2209 cris_alu_m_alloc_temps(t);
2210 /* sign extend. */
2211 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2212 cris_cc_mask(dc, CC_MASK_NZVC);
2213 cris_alu(dc, CC_OP_ADD,
2214 cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2215 do_postinc(dc, memsize);
2216 cris_alu_m_free_temps(t);
2217 return insn_len;
2218 }
2219
2220 static int dec_adds_m(CPUCRISState *env, DisasContext *dc)
2221 {
2222 TCGv t[2];
2223 int memsize = memsize_z(dc);
2224 int insn_len;
2225 LOG_DIS("adds.%c [$r%u%s, $r%u\n",
2226 memsize_char(memsize),
2227 dc->op1, dc->postinc ? "+]" : "]",
2228 dc->op2);
2229
2230 cris_alu_m_alloc_temps(t);
2231 /* sign extend. */
2232 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2233 cris_cc_mask(dc, CC_MASK_NZVC);
2234 cris_alu(dc, CC_OP_ADD, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2235 do_postinc(dc, memsize);
2236 cris_alu_m_free_temps(t);
2237 return insn_len;
2238 }
2239
2240 static int dec_subu_m(CPUCRISState *env, DisasContext *dc)
2241 {
2242 TCGv t[2];
2243 int memsize = memsize_z(dc);
2244 int insn_len;
2245 LOG_DIS("subu.%c [$r%u%s, $r%u\n",
2246 memsize_char(memsize),
2247 dc->op1, dc->postinc ? "+]" : "]",
2248 dc->op2);
2249
2250 cris_alu_m_alloc_temps(t);
2251 /* sign extend. */
2252 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2253 cris_cc_mask(dc, CC_MASK_NZVC);
2254 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2255 do_postinc(dc, memsize);
2256 cris_alu_m_free_temps(t);
2257 return insn_len;
2258 }
2259
2260 static int dec_subs_m(CPUCRISState *env, DisasContext *dc)
2261 {
2262 TCGv t[2];
2263 int memsize = memsize_z(dc);
2264 int insn_len;
2265 LOG_DIS("subs.%c [$r%u%s, $r%u\n",
2266 memsize_char(memsize),
2267 dc->op1, dc->postinc ? "+]" : "]",
2268 dc->op2);
2269
2270 cris_alu_m_alloc_temps(t);
2271 /* sign extend. */
2272 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2273 cris_cc_mask(dc, CC_MASK_NZVC);
2274 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2275 do_postinc(dc, memsize);
2276 cris_alu_m_free_temps(t);
2277 return insn_len;
2278 }
2279
2280 static int dec_movu_m(CPUCRISState *env, DisasContext *dc)
2281 {
2282 TCGv t[2];
2283 int memsize = memsize_z(dc);
2284 int insn_len;
2285
2286 LOG_DIS("movu.%c [$r%u%s, $r%u\n",
2287 memsize_char(memsize),
2288 dc->op1, dc->postinc ? "+]" : "]",
2289 dc->op2);
2290
2291 cris_alu_m_alloc_temps(t);
2292 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2293 cris_cc_mask(dc, CC_MASK_NZ);
2294 cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2295 do_postinc(dc, memsize);
2296 cris_alu_m_free_temps(t);
2297 return insn_len;
2298 }
2299
2300 static int dec_cmpu_m(CPUCRISState *env, DisasContext *dc)
2301 {
2302 TCGv t[2];
2303 int memsize = memsize_z(dc);
2304 int insn_len;
2305 LOG_DIS("cmpu.%c [$r%u%s, $r%u\n",
2306 memsize_char(memsize),
2307 dc->op1, dc->postinc ? "+]" : "]",
2308 dc->op2);
2309
2310 cris_alu_m_alloc_temps(t);
2311 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2312 cris_cc_mask(dc, CC_MASK_NZVC);
2313 cris_alu(dc, CC_OP_CMP, cpu_R[dc->op2], cpu_R[dc->op2], t[1], 4);
2314 do_postinc(dc, memsize);
2315 cris_alu_m_free_temps(t);
2316 return insn_len;
2317 }
2318
2319 static int dec_cmps_m(CPUCRISState *env, DisasContext *dc)
2320 {
2321 TCGv t[2];
2322 int memsize = memsize_z(dc);
2323 int insn_len;
2324 LOG_DIS("cmps.%c [$r%u%s, $r%u\n",
2325 memsize_char(memsize),
2326 dc->op1, dc->postinc ? "+]" : "]",
2327 dc->op2);
2328
2329 cris_alu_m_alloc_temps(t);
2330 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2331 cris_cc_mask(dc, CC_MASK_NZVC);
2332 cris_alu(dc, CC_OP_CMP,
2333 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2334 memsize_zz(dc));
2335 do_postinc(dc, memsize);
2336 cris_alu_m_free_temps(t);
2337 return insn_len;
2338 }
2339
2340 static int dec_cmp_m(CPUCRISState *env, DisasContext *dc)
2341 {
2342 TCGv t[2];
2343 int memsize = memsize_zz(dc);
2344 int insn_len;
2345 LOG_DIS("cmp.%c [$r%u%s, $r%u\n",
2346 memsize_char(memsize),
2347 dc->op1, dc->postinc ? "+]" : "]",
2348 dc->op2);
2349
2350 cris_alu_m_alloc_temps(t);
2351 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2352 cris_cc_mask(dc, CC_MASK_NZVC);
2353 cris_alu(dc, CC_OP_CMP,
2354 cpu_R[dc->op2], cpu_R[dc->op2], t[1],
2355 memsize_zz(dc));
2356 do_postinc(dc, memsize);
2357 cris_alu_m_free_temps(t);
2358 return insn_len;
2359 }
2360
2361 static int dec_test_m(CPUCRISState *env, DisasContext *dc)
2362 {
2363 TCGv t[2];
2364 int memsize = memsize_zz(dc);
2365 int insn_len;
2366 LOG_DIS("test.%c [$r%u%s] op2=%x\n",
2367 memsize_char(memsize),
2368 dc->op1, dc->postinc ? "+]" : "]",
2369 dc->op2);
2370
2371 cris_evaluate_flags(dc);
2372
2373 cris_alu_m_alloc_temps(t);
2374 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2375 cris_cc_mask(dc, CC_MASK_NZ);
2376 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
2377
2378 cris_alu(dc, CC_OP_CMP,
2379 cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc));
2380 do_postinc(dc, memsize);
2381 cris_alu_m_free_temps(t);
2382 return insn_len;
2383 }
2384
2385 static int dec_and_m(CPUCRISState *env, DisasContext *dc)
2386 {
2387 TCGv t[2];
2388 int memsize = memsize_zz(dc);
2389 int insn_len;
2390 LOG_DIS("and.%c [$r%u%s, $r%u\n",
2391 memsize_char(memsize),
2392 dc->op1, dc->postinc ? "+]" : "]",
2393 dc->op2);
2394
2395 cris_alu_m_alloc_temps(t);
2396 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2397 cris_cc_mask(dc, CC_MASK_NZ);
2398 cris_alu(dc, CC_OP_AND, cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2399 do_postinc(dc, memsize);
2400 cris_alu_m_free_temps(t);
2401 return insn_len;
2402 }
2403
2404 static int dec_add_m(CPUCRISState *env, DisasContext *dc)
2405 {
2406 TCGv t[2];
2407 int memsize = memsize_zz(dc);
2408 int insn_len;
2409 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2410 memsize_char(memsize),
2411 dc->op1, dc->postinc ? "+]" : "]",
2412 dc->op2);
2413
2414 cris_alu_m_alloc_temps(t);
2415 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2416 cris_cc_mask(dc, CC_MASK_NZVC);
2417 cris_alu(dc, CC_OP_ADD,
2418 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2419 do_postinc(dc, memsize);
2420 cris_alu_m_free_temps(t);
2421 return insn_len;
2422 }
2423
2424 static int dec_addo_m(CPUCRISState *env, DisasContext *dc)
2425 {
2426 TCGv t[2];
2427 int memsize = memsize_zz(dc);
2428 int insn_len;
2429 LOG_DIS("add.%c [$r%u%s, $r%u\n",
2430 memsize_char(memsize),
2431 dc->op1, dc->postinc ? "+]" : "]",
2432 dc->op2);
2433
2434 cris_alu_m_alloc_temps(t);
2435 insn_len = dec_prep_alu_m(env, dc, 1, memsize, t[0], t[1]);
2436 cris_cc_mask(dc, 0);
2437 cris_alu(dc, CC_OP_ADD, cpu_R[R_ACR], t[0], t[1], 4);
2438 do_postinc(dc, memsize);
2439 cris_alu_m_free_temps(t);
2440 return insn_len;
2441 }
2442
2443 static int dec_bound_m(CPUCRISState *env, DisasContext *dc)
2444 {
2445 TCGv l[2];
2446 int memsize = memsize_zz(dc);
2447 int insn_len;
2448 LOG_DIS("bound.%c [$r%u%s, $r%u\n",
2449 memsize_char(memsize),
2450 dc->op1, dc->postinc ? "+]" : "]",
2451 dc->op2);
2452
2453 l[0] = tcg_temp_local_new();
2454 l[1] = tcg_temp_local_new();
2455 insn_len = dec_prep_alu_m(env, dc, 0, memsize, l[0], l[1]);
2456 cris_cc_mask(dc, CC_MASK_NZ);
2457 cris_alu(dc, CC_OP_BOUND, cpu_R[dc->op2], l[0], l[1], 4);
2458 do_postinc(dc, memsize);
2459 tcg_temp_free(l[0]);
2460 tcg_temp_free(l[1]);
2461 return insn_len;
2462 }
2463
2464 static int dec_addc_mr(CPUCRISState *env, DisasContext *dc)
2465 {
2466 TCGv t[2];
2467 int insn_len = 2;
2468 LOG_DIS("addc [$r%u%s, $r%u\n",
2469 dc->op1, dc->postinc ? "+]" : "]",
2470 dc->op2);
2471
2472 cris_evaluate_flags(dc);
2473
2474 /* Set for this insn. */
2475 dc->flagx_known = 1;
2476 dc->flags_x = X_FLAG;
2477
2478 cris_alu_m_alloc_temps(t);
2479 insn_len = dec_prep_alu_m(env, dc, 0, 4, t[0], t[1]);
2480 cris_cc_mask(dc, CC_MASK_NZVC);
2481 cris_alu(dc, CC_OP_ADDC, cpu_R[dc->op2], t[0], t[1], 4);
2482 do_postinc(dc, 4);
2483 cris_alu_m_free_temps(t);
2484 return insn_len;
2485 }
2486
2487 static int dec_sub_m(CPUCRISState *env, DisasContext *dc)
2488 {
2489 TCGv t[2];
2490 int memsize = memsize_zz(dc);
2491 int insn_len;
2492 LOG_DIS("sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2493 memsize_char(memsize),
2494 dc->op1, dc->postinc ? "+]" : "]",
2495 dc->op2, dc->ir, dc->zzsize);
2496
2497 cris_alu_m_alloc_temps(t);
2498 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2499 cris_cc_mask(dc, CC_MASK_NZVC);
2500 cris_alu(dc, CC_OP_SUB, cpu_R[dc->op2], t[0], t[1], memsize);
2501 do_postinc(dc, memsize);
2502 cris_alu_m_free_temps(t);
2503 return insn_len;
2504 }
2505
2506 static int dec_or_m(CPUCRISState *env, DisasContext *dc)
2507 {
2508 TCGv t[2];
2509 int memsize = memsize_zz(dc);
2510 int insn_len;
2511 LOG_DIS("or.%c [$r%u%s, $r%u pc=%x\n",
2512 memsize_char(memsize),
2513 dc->op1, dc->postinc ? "+]" : "]",
2514 dc->op2, dc->pc);
2515
2516 cris_alu_m_alloc_temps(t);
2517 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2518 cris_cc_mask(dc, CC_MASK_NZ);
2519 cris_alu(dc, CC_OP_OR,
2520 cpu_R[dc->op2], t[0], t[1], memsize_zz(dc));
2521 do_postinc(dc, memsize);
2522 cris_alu_m_free_temps(t);
2523 return insn_len;
2524 }
2525
2526 static int dec_move_mp(CPUCRISState *env, DisasContext *dc)
2527 {
2528 TCGv t[2];
2529 int memsize = memsize_zz(dc);
2530 int insn_len = 2;
2531
2532 LOG_DIS("move.%c [$r%u%s, $p%u\n",
2533 memsize_char(memsize),
2534 dc->op1,
2535 dc->postinc ? "+]" : "]",
2536 dc->op2);
2537
2538 cris_alu_m_alloc_temps(t);
2539 insn_len = dec_prep_alu_m(env, dc, 0, memsize, t[0], t[1]);
2540 cris_cc_mask(dc, 0);
2541 if (dc->op2 == PR_CCS) {
2542 cris_evaluate_flags(dc);
2543 if (dc->tb_flags & U_FLAG) {
2544 /* User space is not allowed to touch all flags. */
2545 tcg_gen_andi_tl(t[1], t[1], 0x39f);
2546 tcg_gen_andi_tl(t[0], cpu_PR[PR_CCS], ~0x39f);
2547 tcg_gen_or_tl(t[1], t[0], t[1]);
2548 }
2549 }
2550
2551 t_gen_mov_preg_TN(dc, dc->op2, t[1]);
2552
2553 do_postinc(dc, memsize);
2554 cris_alu_m_free_temps(t);
2555 return insn_len;
2556 }
2557
2558 static int dec_move_pm(CPUCRISState *env, DisasContext *dc)
2559 {
2560 TCGv t0;
2561 int memsize;
2562
2563 memsize = preg_sizes[dc->op2];
2564
2565 LOG_DIS("move.%c $p%u, [$r%u%s\n",
2566 memsize_char(memsize),
2567 dc->op2, dc->op1, dc->postinc ? "+]" : "]");
2568
2569 /* prepare store. Address in T0, value in T1. */
2570 if (dc->op2 == PR_CCS) {
2571 cris_evaluate_flags(dc);
2572 }
2573 t0 = tcg_temp_new();
2574 t_gen_mov_TN_preg(t0, dc->op2);
2575 cris_flush_cc_state(dc);
2576 gen_store(dc, cpu_R[dc->op1], t0, memsize);
2577 tcg_temp_free(t0);
2578
2579 cris_cc_mask(dc, 0);
2580 if (dc->postinc) {
2581 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2582 }
2583 return 2;
2584 }
2585
2586 static int dec_movem_mr(CPUCRISState *env, DisasContext *dc)
2587 {
2588 TCGv_i64 tmp[16];
2589 TCGv tmp32;
2590 TCGv addr;
2591 int i;
2592 int nr = dc->op2 + 1;
2593
2594 LOG_DIS("movem [$r%u%s, $r%u\n", dc->op1,
2595 dc->postinc ? "+]" : "]", dc->op2);
2596
2597 addr = tcg_temp_new();
2598 /* There are probably better ways of doing this. */
2599 cris_flush_cc_state(dc);
2600 for (i = 0; i < (nr >> 1); i++) {
2601 tmp[i] = tcg_temp_new_i64();
2602 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2603 gen_load64(dc, tmp[i], addr);
2604 }
2605 if (nr & 1) {
2606 tmp32 = tcg_temp_new_i32();
2607 tcg_gen_addi_tl(addr, cpu_R[dc->op1], i * 8);
2608 gen_load(dc, tmp32, addr, 4, 0);
2609 } else {
2610 TCGV_UNUSED(tmp32);
2611 }
2612 tcg_temp_free(addr);
2613
2614 for (i = 0; i < (nr >> 1); i++) {
2615 tcg_gen_trunc_i64_i32(cpu_R[i * 2], tmp[i]);
2616 tcg_gen_shri_i64(tmp[i], tmp[i], 32);
2617 tcg_gen_trunc_i64_i32(cpu_R[i * 2 + 1], tmp[i]);
2618 tcg_temp_free_i64(tmp[i]);
2619 }
2620 if (nr & 1) {
2621 tcg_gen_mov_tl(cpu_R[dc->op2], tmp32);
2622 tcg_temp_free(tmp32);
2623 }
2624
2625 /* writeback the updated pointer value. */
2626 if (dc->postinc) {
2627 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], nr * 4);
2628 }
2629
2630 /* gen_load might want to evaluate the previous insns flags. */
2631 cris_cc_mask(dc, 0);
2632 return 2;
2633 }
2634
2635 static int dec_movem_rm(CPUCRISState *env, DisasContext *dc)
2636 {
2637 TCGv tmp;
2638 TCGv addr;
2639 int i;
2640
2641 LOG_DIS("movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2642 dc->postinc ? "+]" : "]");
2643
2644 cris_flush_cc_state(dc);
2645
2646 tmp = tcg_temp_new();
2647 addr = tcg_temp_new();
2648 tcg_gen_movi_tl(tmp, 4);
2649 tcg_gen_mov_tl(addr, cpu_R[dc->op1]);
2650 for (i = 0; i <= dc->op2; i++) {
2651 /* Displace addr. */
2652 /* Perform the store. */
2653 gen_store(dc, addr, cpu_R[i], 4);
2654 tcg_gen_add_tl(addr, addr, tmp);
2655 }
2656 if (dc->postinc) {
2657 tcg_gen_mov_tl(cpu_R[dc->op1], addr);
2658 }
2659 cris_cc_mask(dc, 0);
2660 tcg_temp_free(tmp);
2661 tcg_temp_free(addr);
2662 return 2;
2663 }
2664
2665 static int dec_move_rm(CPUCRISState *env, DisasContext *dc)
2666 {
2667 int memsize;
2668
2669 memsize = memsize_zz(dc);
2670
2671 LOG_DIS("move.%c $r%u, [$r%u]\n",
2672 memsize_char(memsize), dc->op2, dc->op1);
2673
2674 /* prepare store. */
2675 cris_flush_cc_state(dc);
2676 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2677
2678 if (dc->postinc) {
2679 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
2680 }
2681 cris_cc_mask(dc, 0);
2682 return 2;
2683 }
2684
2685 static int dec_lapcq(CPUCRISState *env, DisasContext *dc)
2686 {
2687 LOG_DIS("lapcq %x, $r%u\n",
2688 dc->pc + dc->op1*2, dc->op2);
2689 cris_cc_mask(dc, 0);
2690 tcg_gen_movi_tl(cpu_R[dc->op2], dc->pc + dc->op1 * 2);
2691 return 2;
2692 }
2693
2694 static int dec_lapc_im(CPUCRISState *env, DisasContext *dc)
2695 {
2696 unsigned int rd;
2697 int32_t imm;
2698 int32_t pc;
2699
2700 rd = dc->op2;
2701
2702 cris_cc_mask(dc, 0);
2703 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2704 LOG_DIS("lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2);
2705
2706 pc = dc->pc;
2707 pc += imm;
2708 tcg_gen_movi_tl(cpu_R[rd], pc);
2709 return 6;
2710 }
2711
2712 /* Jump to special reg. */
2713 static int dec_jump_p(CPUCRISState *env, DisasContext *dc)
2714 {
2715 LOG_DIS("jump $p%u\n", dc->op2);
2716
2717 if (dc->op2 == PR_CCS) {
2718 cris_evaluate_flags(dc);
2719 }
2720 t_gen_mov_TN_preg(env_btarget, dc->op2);
2721 /* rete will often have low bit set to indicate delayslot. */
2722 tcg_gen_andi_tl(env_btarget, env_btarget, ~1);
2723 cris_cc_mask(dc, 0);
2724 cris_prepare_jmp(dc, JMP_INDIRECT);
2725 return 2;
2726 }
2727
2728 /* Jump and save. */
2729 static int dec_jas_r(CPUCRISState *env, DisasContext *dc)
2730 {
2731 LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2);
2732 cris_cc_mask(dc, 0);
2733 /* Store the return address in Pd. */
2734 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2735 if (dc->op2 > 15) {
2736 abort();
2737 }
2738 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4));
2739
2740 cris_prepare_jmp(dc, JMP_INDIRECT);
2741 return 2;
2742 }
2743
2744 static int dec_jas_im(CPUCRISState *env, DisasContext *dc)
2745 {
2746 uint32_t imm;
2747
2748 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2749
2750 LOG_DIS("jas 0x%x\n", imm);
2751 cris_cc_mask(dc, 0);
2752 /* Store the return address in Pd. */
2753 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2754
2755 dc->jmp_pc = imm;
2756 cris_prepare_jmp(dc, JMP_DIRECT);
2757 return 6;
2758 }
2759
2760 static int dec_jasc_im(CPUCRISState *env, DisasContext *dc)
2761 {
2762 uint32_t imm;
2763
2764 imm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2765
2766 LOG_DIS("jasc 0x%x\n", imm);
2767 cris_cc_mask(dc, 0);
2768 /* Store the return address in Pd. */
2769 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4));
2770
2771 dc->jmp_pc = imm;
2772 cris_prepare_jmp(dc, JMP_DIRECT);
2773 return 6;
2774 }
2775
2776 static int dec_jasc_r(CPUCRISState *env, DisasContext *dc)
2777 {
2778 LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2);
2779 cris_cc_mask(dc, 0);
2780 /* Store the return address in Pd. */
2781 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2782 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4));
2783 cris_prepare_jmp(dc, JMP_INDIRECT);
2784 return 2;
2785 }
2786
2787 static int dec_bcc_im(CPUCRISState *env, DisasContext *dc)
2788 {
2789 int32_t offset;
2790 uint32_t cond = dc->op2;
2791
2792 offset = cris_fetch(env, dc, dc->pc + 2, 2, 1);
2793
2794 LOG_DIS("b%s %d pc=%x dst=%x\n",
2795 cc_name(cond), offset,
2796 dc->pc, dc->pc + offset);
2797
2798 cris_cc_mask(dc, 0);
2799 /* op2 holds the condition-code. */
2800 cris_prepare_cc_branch(dc, offset, cond);
2801 return 4;
2802 }
2803
2804 static int dec_bas_im(CPUCRISState *env, DisasContext *dc)
2805 {
2806 int32_t simm;
2807
2808 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2809
2810 LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2811 cris_cc_mask(dc, 0);
2812 /* Store the return address in Pd. */
2813 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
2814
2815 dc->jmp_pc = dc->pc + simm;
2816 cris_prepare_jmp(dc, JMP_DIRECT);
2817 return 6;
2818 }
2819
2820 static int dec_basc_im(CPUCRISState *env, DisasContext *dc)
2821 {
2822 int32_t simm;
2823 simm = cris_fetch(env, dc, dc->pc + 2, 4, 0);
2824
2825 LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2);
2826 cris_cc_mask(dc, 0);
2827 /* Store the return address in Pd. */
2828 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12));
2829
2830 dc->jmp_pc = dc->pc + simm;
2831 cris_prepare_jmp(dc, JMP_DIRECT);
2832 return 6;
2833 }
2834
2835 static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc)
2836 {
2837 cris_cc_mask(dc, 0);
2838
2839 if (dc->op2 == 15) {
2840 tcg_gen_st_i32(tcg_const_i32(1), cpu_env,
2841 -offsetof(CRISCPU, env) + offsetof(CPUState, halted));
2842 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2843 t_gen_raise_exception(EXCP_HLT);
2844 return 2;
2845 }
2846
2847 switch (dc->op2 & 7) {
2848 case 2:
2849 /* rfe. */
2850 LOG_DIS("rfe\n");
2851 cris_evaluate_flags(dc);
2852 gen_helper_rfe(cpu_env);
2853 dc->is_jmp = DISAS_UPDATE;
2854 break;
2855 case 5:
2856 /* rfn. */
2857 LOG_DIS("rfn\n");
2858 cris_evaluate_flags(dc);
2859 gen_helper_rfn(cpu_env);
2860 dc->is_jmp = DISAS_UPDATE;
2861 break;
2862 case 6:
2863 LOG_DIS("break %d\n", dc->op1);
2864 cris_evaluate_flags(dc);
2865 /* break. */
2866 tcg_gen_movi_tl(env_pc, dc->pc + 2);
2867
2868 /* Breaks start at 16 in the exception vector. */
2869 t_gen_mov_env_TN(trap_vector,
2870 tcg_const_tl(dc->op1 + 16));
2871 t_gen_raise_exception(EXCP_BREAK);
2872 dc->is_jmp = DISAS_UPDATE;
2873 break;
2874 default:
2875 printf("op2=%x\n", dc->op2);
2876 BUG();
2877 break;
2878
2879 }
2880 return 2;
2881 }
2882
2883 static int dec_ftag_fidx_d_m(CPUCRISState *env, DisasContext *dc)
2884 {
2885 return 2;
2886 }
2887
2888 static int dec_ftag_fidx_i_m(CPUCRISState *env, DisasContext *dc)
2889 {
2890 return 2;
2891 }
2892
2893 static int dec_null(CPUCRISState *env, DisasContext *dc)
2894 {
2895 printf("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2896 dc->pc, dc->opcode, dc->op1, dc->op2);
2897 fflush(NULL);
2898 BUG();
2899 return 2;
2900 }
2901
2902 static struct decoder_info {
2903 struct {
2904 uint32_t bits;
2905 uint32_t mask;
2906 };
2907 int (*dec)(CPUCRISState *env, DisasContext *dc);
2908 } decinfo[] = {
2909 /* Order matters here. */
2910 {DEC_MOVEQ, dec_moveq},
2911 {DEC_BTSTQ, dec_btstq},
2912 {DEC_CMPQ, dec_cmpq},
2913 {DEC_ADDOQ, dec_addoq},
2914 {DEC_ADDQ, dec_addq},
2915 {DEC_SUBQ, dec_subq},
2916 {DEC_ANDQ, dec_andq},
2917 {DEC_ORQ, dec_orq},
2918 {DEC_ASRQ, dec_asrq},
2919 {DEC_LSLQ, dec_lslq},
2920 {DEC_LSRQ, dec_lsrq},
2921 {DEC_BCCQ, dec_bccq},
2922
2923 {DEC_BCC_IM, dec_bcc_im},
2924 {DEC_JAS_IM, dec_jas_im},
2925 {DEC_JAS_R, dec_jas_r},
2926 {DEC_JASC_IM, dec_jasc_im},
2927 {DEC_JASC_R, dec_jasc_r},
2928 {DEC_BAS_IM, dec_bas_im},
2929 {DEC_BASC_IM, dec_basc_im},
2930 {DEC_JUMP_P, dec_jump_p},
2931 {DEC_LAPC_IM, dec_lapc_im},
2932 {DEC_LAPCQ, dec_lapcq},
2933
2934 {DEC_RFE_ETC, dec_rfe_etc},
2935 {DEC_ADDC_MR, dec_addc_mr},
2936
2937 {DEC_MOVE_MP, dec_move_mp},
2938 {DEC_MOVE_PM, dec_move_pm},
2939 {DEC_MOVEM_MR, dec_movem_mr},
2940 {DEC_MOVEM_RM, dec_movem_rm},
2941 {DEC_MOVE_PR, dec_move_pr},
2942 {DEC_SCC_R, dec_scc_r},
2943 {DEC_SETF, dec_setclrf},
2944 {DEC_CLEARF, dec_setclrf},
2945
2946 {DEC_MOVE_SR, dec_move_sr},
2947 {DEC_MOVE_RP, dec_move_rp},
2948 {DEC_SWAP_R, dec_swap_r},
2949 {DEC_ABS_R, dec_abs_r},
2950 {DEC_LZ_R, dec_lz_r},
2951 {DEC_MOVE_RS, dec_move_rs},
2952 {DEC_BTST_R, dec_btst_r},
2953 {DEC_ADDC_R, dec_addc_r},
2954
2955 {DEC_DSTEP_R, dec_dstep_r},
2956 {DEC_XOR_R, dec_xor_r},
2957 {DEC_MCP_R, dec_mcp_r},
2958 {DEC_CMP_R, dec_cmp_r},
2959
2960 {DEC_ADDI_R, dec_addi_r},
2961 {DEC_ADDI_ACR, dec_addi_acr},
2962
2963 {DEC_ADD_R, dec_add_r},
2964 {DEC_SUB_R, dec_sub_r},
2965
2966 {DEC_ADDU_R, dec_addu_r},
2967 {DEC_ADDS_R, dec_adds_r},
2968 {DEC_SUBU_R, dec_subu_r},
2969 {DEC_SUBS_R, dec_subs_r},
2970 {DEC_LSL_R, dec_lsl_r},
2971
2972 {DEC_AND_R, dec_and_r},
2973 {DEC_OR_R, dec_or_r},
2974 {DEC_BOUND_R, dec_bound_r},
2975 {DEC_ASR_R, dec_asr_r},
2976 {DEC_LSR_R, dec_lsr_r},
2977
2978 {DEC_MOVU_R, dec_movu_r},
2979 {DEC_MOVS_R, dec_movs_r},
2980 {DEC_NEG_R, dec_neg_r},
2981 {DEC_MOVE_R, dec_move_r},
2982
2983 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2984 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
2985
2986 {DEC_MULS_R, dec_muls_r},
2987 {DEC_MULU_R, dec_mulu_r},
2988
2989 {DEC_ADDU_M, dec_addu_m},
2990 {DEC_ADDS_M, dec_adds_m},
2991 {DEC_SUBU_M, dec_subu_m},
2992 {DEC_SUBS_M, dec_subs_m},
2993
2994 {DEC_CMPU_M, dec_cmpu_m},
2995 {DEC_CMPS_M, dec_cmps_m},
2996 {DEC_MOVU_M, dec_movu_m},
2997 {DEC_MOVS_M, dec_movs_m},
2998
2999 {DEC_CMP_M, dec_cmp_m},
3000 {DEC_ADDO_M, dec_addo_m},
3001 {DEC_BOUND_M, dec_bound_m},
3002 {DEC_ADD_M, dec_add_m},
3003 {DEC_SUB_M, dec_sub_m},
3004 {DEC_AND_M, dec_and_m},
3005 {DEC_OR_M, dec_or_m},
3006 {DEC_MOVE_RM, dec_move_rm},
3007 {DEC_TEST_M, dec_test_m},
3008 {DEC_MOVE_MR, dec_move_mr},
3009
3010 {{0, 0}, dec_null}
3011 };
3012
3013 static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
3014 {
3015 int insn_len = 2;
3016 int i;
3017
3018 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
3019 tcg_gen_debug_insn_start(dc->pc);
3020 }
3021
3022 /* Load a halfword onto the instruction register. */
3023 dc->ir = cris_fetch(env, dc, dc->pc, 2, 0);
3024
3025 /* Now decode it. */
3026 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
3027 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
3028 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
3029 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
3030 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
3031 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
3032
3033 /* Large switch for all insns. */
3034 for (i = 0; i < ARRAY_SIZE(decinfo); i++) {
3035 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits) {
3036 insn_len = decinfo[i].dec(env, dc);
3037 break;
3038 }
3039 }
3040
3041 #if !defined(CONFIG_USER_ONLY)
3042 /* Single-stepping ? */
3043 if (dc->tb_flags & S_FLAG) {
3044 int l1;
3045
3046 l1 = gen_new_label();
3047 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1);
3048 /* We treat SPC as a break with an odd trap vector. */
3049 cris_evaluate_flags(dc);
3050 t_gen_mov_env_TN(trap_vector, tcg_const_tl(3));
3051 tcg_gen_movi_tl(env_pc, dc->pc + insn_len);
3052 tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len);
3053 t_gen_raise_exception(EXCP_BREAK);
3054 gen_set_label(l1);
3055 }
3056 #endif
3057 return insn_len;
3058 }
3059
3060 static void check_breakpoint(CPUCRISState *env, DisasContext *dc)
3061 {
3062 CPUState *cs = CPU(cris_env_get_cpu(env));
3063 CPUBreakpoint *bp;
3064
3065 if (unlikely(!QTAILQ_EMPTY(&cs->breakpoints))) {
3066 QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
3067 if (bp->pc == dc->pc) {
3068 cris_evaluate_flags(dc);
3069 tcg_gen_movi_tl(env_pc, dc->pc);
3070 t_gen_raise_exception(EXCP_DEBUG);
3071 dc->is_jmp = DISAS_UPDATE;
3072 }
3073 }
3074 }
3075 }
3076
3077 #include "translate_v10.c"
3078
3079 /*
3080 * Delay slots on QEMU/CRIS.
3081 *
3082 * If an exception hits on a delayslot, the core will let ERP (the Exception
3083 * Return Pointer) point to the branch (the previous) insn and set the lsb to
3084 * to give SW a hint that the exception actually hit on the dslot.
3085 *
3086 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
3087 * the core and any jmp to an odd addresses will mask off that lsb. It is
3088 * simply there to let sw know there was an exception on a dslot.
3089 *
3090 * When the software returns from an exception, the branch will re-execute.
3091 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
3092 * and the branch and delayslot dont share pages.
3093 *
3094 * The TB contaning the branch insn will set up env->btarget and evaluate
3095 * env->btaken. When the translation loop exits we will note that the branch
3096 * sequence is broken and let env->dslot be the size of the branch insn (those
3097 * vary in length).
3098 *
3099 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
3100 * set). It will also expect to have env->dslot setup with the size of the
3101 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
3102 * will execute the dslot and take the branch, either to btarget or just one
3103 * insn ahead.
3104 *
3105 * When exceptions occur, we check for env->dslot in do_interrupt to detect
3106 * broken branch sequences and setup $erp accordingly (i.e let it point to the
3107 * branch and set lsb). Then env->dslot gets cleared so that the exception
3108 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
3109 * masked off and we will reexecute the branch insn.
3110 *
3111 */
3112
3113 /* generate intermediate code for basic block 'tb'. */
3114 static inline void
3115 gen_intermediate_code_internal(CRISCPU *cpu, TranslationBlock *tb,
3116 bool search_pc)
3117 {
3118 CPUState *cs = CPU(cpu);
3119 CPUCRISState *env = &cpu->env;
3120 uint16_t *gen_opc_end;
3121 uint32_t pc_start;
3122 unsigned int insn_len;
3123 int j, lj;
3124 struct DisasContext ctx;
3125 struct DisasContext *dc = &ctx;
3126 uint32_t next_page_start;
3127 target_ulong npc;
3128 int num_insns;
3129 int max_insns;
3130
3131 if (env->pregs[PR_VR] == 32) {
3132 dc->decoder = crisv32_decoder;
3133 dc->clear_locked_irq = 0;
3134 } else {
3135 dc->decoder = crisv10_decoder;
3136 dc->clear_locked_irq = 1;
3137 }
3138
3139 /* Odd PC indicates that branch is rexecuting due to exception in the
3140 * delayslot, like in real hw.
3141 */
3142 pc_start = tb->pc & ~1;
3143 dc->cpu = cpu;
3144 dc->tb = tb;
3145
3146 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
3147
3148 dc->is_jmp = DISAS_NEXT;
3149 dc->ppc = pc_start;
3150 dc->pc = pc_start;
3151 dc->singlestep_enabled = cs->singlestep_enabled;
3152 dc->flags_uptodate = 1;
3153 dc->flagx_known = 1;
3154 dc->flags_x = tb->flags & X_FLAG;
3155 dc->cc_x_uptodate = 0;
3156 dc->cc_mask = 0;
3157 dc->update_cc = 0;
3158 dc->clear_prefix = 0;
3159
3160 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
3161 dc->cc_size_uptodate = -1;
3162
3163 /* Decode TB flags. */
3164 dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
3165 | X_FLAG | PFIX_FLAG);
3166 dc->delayed_branch = !!(tb->flags & 7);
3167 if (dc->delayed_branch) {
3168 dc->jmp = JMP_INDIRECT;
3169 } else {
3170 dc->jmp = JMP_NOJMP;
3171 }
3172
3173 dc->cpustate_changed = 0;
3174
3175 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3176 qemu_log(
3177 "srch=%d pc=%x %x flg=%" PRIx64 " bt=%x ds=%u ccs=%x\n"
3178 "pid=%x usp=%x\n"
3179 "%x.%x.%x.%x\n"
3180 "%x.%x.%x.%x\n"
3181 "%x.%x.%x.%x\n"
3182 "%x.%x.%x.%x\n",
3183 search_pc, dc->pc, dc->ppc,
3184 (uint64_t)tb->flags,
3185 env->btarget, (unsigned)tb->flags & 7,
3186 env->pregs[PR_CCS],
3187 env->pregs[PR_PID], env->pregs[PR_USP],
3188 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
3189 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
3190 env->regs[8], env->regs[9],
3191 env->regs[10], env->regs[11],
3192 env->regs[12], env->regs[13],
3193 env->regs[14], env->regs[15]);
3194 qemu_log("--------------\n");
3195 qemu_log("IN: %s\n", lookup_symbol(pc_start));
3196 }
3197
3198 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
3199 lj = -1;
3200 num_insns = 0;
3201 max_insns = tb->cflags & CF_COUNT_MASK;
3202 if (max_insns == 0) {
3203 max_insns = CF_COUNT_MASK;
3204 }
3205
3206 gen_tb_start();
3207 do {
3208 check_breakpoint(env, dc);
3209
3210 if (search_pc) {
3211 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3212 if (lj < j) {
3213 lj++;
3214 while (lj < j) {
3215 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3216 }
3217 }
3218 if (dc->delayed_branch == 1) {
3219 tcg_ctx.gen_opc_pc[lj] = dc->ppc | 1;
3220 } else {
3221 tcg_ctx.gen_opc_pc[lj] = dc->pc;
3222 }
3223 tcg_ctx.gen_opc_instr_start[lj] = 1;
3224 tcg_ctx.gen_opc_icount[lj] = num_insns;
3225 }
3226
3227 /* Pretty disas. */
3228 LOG_DIS("%8.8x:\t", dc->pc);
3229
3230 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) {
3231 gen_io_start();
3232 }
3233 dc->clear_x = 1;
3234
3235 insn_len = dc->decoder(env, dc);
3236 dc->ppc = dc->pc;
3237 dc->pc += insn_len;
3238 if (dc->clear_x) {
3239 cris_clear_x_flag(dc);
3240 }
3241
3242 num_insns++;
3243 /* Check for delayed branches here. If we do it before
3244 actually generating any host code, the simulator will just
3245 loop doing nothing for on this program location. */
3246 if (dc->delayed_branch) {
3247 dc->delayed_branch--;
3248 if (dc->delayed_branch == 0) {
3249 if (tb->flags & 7) {
3250 t_gen_mov_env_TN(dslot, tcg_const_tl(0));
3251 }
3252 if (dc->cpustate_changed || !dc->flagx_known
3253 || (dc->flags_x != (tb->flags & X_FLAG))) {
3254 cris_store_direct_jmp(dc);
3255 }
3256
3257 if (dc->clear_locked_irq) {
3258 dc->clear_locked_irq = 0;
3259 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3260 }
3261
3262 if (dc->jmp == JMP_DIRECT_CC) {
3263 int l1;
3264
3265 l1 = gen_new_label();
3266 cris_evaluate_flags(dc);
3267
3268 /* Conditional jmp. */
3269 tcg_gen_brcondi_tl(TCG_COND_EQ,
3270 env_btaken, 0, l1);
3271 gen_goto_tb(dc, 1, dc->jmp_pc);
3272 gen_set_label(l1);
3273 gen_goto_tb(dc, 0, dc->pc);
3274 dc->is_jmp = DISAS_TB_JUMP;
3275 dc->jmp = JMP_NOJMP;
3276 } else if (dc->jmp == JMP_DIRECT) {
3277 cris_evaluate_flags(dc);
3278 gen_goto_tb(dc, 0, dc->jmp_pc);
3279 dc->is_jmp = DISAS_TB_JUMP;
3280 dc->jmp = JMP_NOJMP;
3281 } else {
3282 t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc));
3283 dc->is_jmp = DISAS_JUMP;
3284 }
3285 break;
3286 }
3287 }
3288
3289 /* If we are rexecuting a branch due to exceptions on
3290 delay slots dont break. */
3291 if (!(tb->pc & 1) && cs->singlestep_enabled) {
3292 break;
3293 }
3294 } while (!dc->is_jmp && !dc->cpustate_changed
3295 && tcg_ctx.gen_opc_ptr < gen_opc_end
3296 && !singlestep
3297 && (dc->pc < next_page_start)
3298 && num_insns < max_insns);
3299
3300 if (dc->clear_locked_irq) {
3301 t_gen_mov_env_TN(locked_irq, tcg_const_tl(0));
3302 }
3303
3304 npc = dc->pc;
3305
3306 if (tb->cflags & CF_LAST_IO)
3307 gen_io_end();
3308 /* Force an update if the per-tb cpu state has changed. */
3309 if (dc->is_jmp == DISAS_NEXT
3310 && (dc->cpustate_changed || !dc->flagx_known
3311 || (dc->flags_x != (tb->flags & X_FLAG)))) {
3312 dc->is_jmp = DISAS_UPDATE;
3313 tcg_gen_movi_tl(env_pc, npc);
3314 }
3315 /* Broken branch+delayslot sequence. */
3316 if (dc->delayed_branch == 1) {
3317 /* Set env->dslot to the size of the branch insn. */
3318 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
3319 cris_store_direct_jmp(dc);
3320 }
3321
3322 cris_evaluate_flags(dc);
3323
3324 if (unlikely(cs->singlestep_enabled)) {
3325 if (dc->is_jmp == DISAS_NEXT) {
3326 tcg_gen_movi_tl(env_pc, npc);
3327 }
3328 t_gen_raise_exception(EXCP_DEBUG);
3329 } else {
3330 switch (dc->is_jmp) {
3331 case DISAS_NEXT:
3332 gen_goto_tb(dc, 1, npc);
3333 break;
3334 default:
3335 case DISAS_JUMP:
3336 case DISAS_UPDATE:
3337 /* indicate that the hash table must be used
3338 to find the next TB */
3339 tcg_gen_exit_tb(0);
3340 break;
3341 case DISAS_SWI:
3342 case DISAS_TB_JUMP:
3343 /* nothing more to generate */
3344 break;
3345 }
3346 }
3347 gen_tb_end(tb, num_insns);
3348 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
3349 if (search_pc) {
3350 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
3351 lj++;
3352 while (lj <= j) {
3353 tcg_ctx.gen_opc_instr_start[lj++] = 0;
3354 }
3355 } else {
3356 tb->size = dc->pc - pc_start;
3357 tb->icount = num_insns;
3358 }
3359
3360 #ifdef DEBUG_DISAS
3361 #if !DISAS_CRIS
3362 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
3363 log_target_disas(env, pc_start, dc->pc - pc_start,
3364 env->pregs[PR_VR]);
3365 qemu_log("\nisize=%d osize=%td\n",
3366 dc->pc - pc_start, tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf);
3367 }
3368 #endif
3369 #endif
3370 }
3371
3372 void gen_intermediate_code (CPUCRISState *env, struct TranslationBlock *tb)
3373 {
3374 gen_intermediate_code_internal(cris_env_get_cpu(env), tb, false);
3375 }
3376
3377 void gen_intermediate_code_pc (CPUCRISState *env, struct TranslationBlock *tb)
3378 {
3379 gen_intermediate_code_internal(cris_env_get_cpu(env), tb, true);
3380 }
3381
3382 void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
3383 int flags)
3384 {
3385 CRISCPU *cpu = CRIS_CPU(cs);
3386 CPUCRISState *env = &cpu->env;
3387 int i;
3388 uint32_t srs;
3389
3390 if (!env || !f) {
3391 return;
3392 }
3393
3394 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
3395 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n",
3396 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
3397 env->cc_op,
3398 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask);
3399
3400
3401 for (i = 0; i < 16; i++) {
3402 cpu_fprintf(f, "%s=%8.8x ", regnames[i], env->regs[i]);
3403 if ((i + 1) % 4 == 0) {
3404 cpu_fprintf(f, "\n");
3405 }
3406 }
3407 cpu_fprintf(f, "\nspecial regs:\n");
3408 for (i = 0; i < 16; i++) {
3409 cpu_fprintf(f, "%s=%8.8x ", pregnames[i], env->pregs[i]);
3410 if ((i + 1) % 4 == 0) {
3411 cpu_fprintf(f, "\n");
3412 }
3413 }
3414 srs = env->pregs[PR_SRS];
3415 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
3416 if (srs < ARRAY_SIZE(env->sregs)) {
3417 for (i = 0; i < 16; i++) {
3418 cpu_fprintf(f, "s%2.2d=%8.8x ",
3419 i, env->sregs[srs][i]);
3420 if ((i + 1) % 4 == 0) {
3421 cpu_fprintf(f, "\n");
3422 }
3423 }
3424 }
3425 cpu_fprintf(f, "\n\n");
3426
3427 }
3428
3429 void cris_initialize_tcg(void)
3430 {
3431 int i;
3432
3433 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
3434 cc_x = tcg_global_mem_new(TCG_AREG0,
3435 offsetof(CPUCRISState, cc_x), "cc_x");
3436 cc_src = tcg_global_mem_new(TCG_AREG0,
3437 offsetof(CPUCRISState, cc_src), "cc_src");
3438 cc_dest = tcg_global_mem_new(TCG_AREG0,
3439 offsetof(CPUCRISState, cc_dest),
3440 "cc_dest");
3441 cc_result = tcg_global_mem_new(TCG_AREG0,
3442 offsetof(CPUCRISState, cc_result),
3443 "cc_result");
3444 cc_op = tcg_global_mem_new(TCG_AREG0,
3445 offsetof(CPUCRISState, cc_op), "cc_op");
3446 cc_size = tcg_global_mem_new(TCG_AREG0,
3447 offsetof(CPUCRISState, cc_size),
3448 "cc_size");
3449 cc_mask = tcg_global_mem_new(TCG_AREG0,
3450 offsetof(CPUCRISState, cc_mask),
3451 "cc_mask");
3452
3453 env_pc = tcg_global_mem_new(TCG_AREG0,
3454 offsetof(CPUCRISState, pc),
3455 "pc");
3456 env_btarget = tcg_global_mem_new(TCG_AREG0,
3457 offsetof(CPUCRISState, btarget),
3458 "btarget");
3459 env_btaken = tcg_global_mem_new(TCG_AREG0,
3460 offsetof(CPUCRISState, btaken),
3461 "btaken");
3462 for (i = 0; i < 16; i++) {
3463 cpu_R[i] = tcg_global_mem_new(TCG_AREG0,
3464 offsetof(CPUCRISState, regs[i]),
3465 regnames[i]);
3466 }
3467 for (i = 0; i < 16; i++) {
3468 cpu_PR[i] = tcg_global_mem_new(TCG_AREG0,
3469 offsetof(CPUCRISState, pregs[i]),
3470 pregnames[i]);
3471 }
3472 }
3473
3474 void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos)
3475 {
3476 env->pc = tcg_ctx.gen_opc_pc[pc_pos];
3477 }
QEmu