hw/net/ne2000.c

   1 /*
   2  * QEMU NE2000 emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "qemu/osdep.h"
  25 #include "hw/hw.h"
  26 #include "hw/pci/pci.h"
  27 #include "net/net.h"
  28 #include "ne2000.h"
  29 #include "hw/loader.h"
  30 #include "sysemu/sysemu.h"
  31
  32 /* debug NE2000 card */
  33 //#define DEBUG_NE2000
  34
  35 #define MAX_ETH_FRAME_SIZE 1514
  36
  37 #define E8390_CMD       0x00  /* The command register (for all pages) */
  38 /* Page 0 register offsets. */
  39 #define EN0_CLDALO      0x01    /* Low byte of current local dma addr  RD */
  40 #define EN0_STARTPG     0x01    /* Starting page of ring bfr WR */
  41 #define EN0_CLDAHI      0x02    /* High byte of current local dma addr  RD */
  42 #define EN0_STOPPG      0x02    /* Ending page +1 of ring bfr WR */
  43 #define EN0_BOUNDARY    0x03    /* Boundary page of ring bfr RD WR */
  44 #define EN0_TSR         0x04    /* Transmit status reg RD */
  45 #define EN0_TPSR        0x04    /* Transmit starting page WR */
  46 #define EN0_NCR         0x05    /* Number of collision reg RD */
  47 #define EN0_TCNTLO      0x05    /* Low  byte of tx byte count WR */
  48 #define EN0_FIFO        0x06    /* FIFO RD */
  49 #define EN0_TCNTHI      0x06    /* High byte of tx byte count WR */
  50 #define EN0_ISR         0x07    /* Interrupt status reg RD WR */
  51 #define EN0_CRDALO      0x08    /* low byte of current remote dma address RD */
  52 #define EN0_RSARLO      0x08    /* Remote start address reg 0 */
  53 #define EN0_CRDAHI      0x09    /* high byte, current remote dma address RD */
  54 #define EN0_RSARHI      0x09    /* Remote start address reg 1 */
  55 #define EN0_RCNTLO      0x0a    /* Remote byte count reg WR */
  56 #define EN0_RTL8029ID0  0x0a    /* Realtek ID byte #1 RD */
  57 #define EN0_RCNTHI      0x0b    /* Remote byte count reg WR */
  58 #define EN0_RTL8029ID1  0x0b    /* Realtek ID byte #2 RD */
  59 #define EN0_RSR         0x0c    /* rx status reg RD */
  60 #define EN0_RXCR        0x0c    /* RX configuration reg WR */
  61 #define EN0_TXCR        0x0d    /* TX configuration reg WR */
  62 #define EN0_COUNTER0    0x0d    /* Rcv alignment error counter RD */
  63 #define EN0_DCFG        0x0e    /* Data configuration reg WR */
  64 #define EN0_COUNTER1    0x0e    /* Rcv CRC error counter RD */
  65 #define EN0_IMR         0x0f    /* Interrupt mask reg WR */
  66 #define EN0_COUNTER2    0x0f    /* Rcv missed frame error counter RD */
  67
  68 #define EN1_PHYS        0x11
  69 #define EN1_CURPAG      0x17
  70 #define EN1_MULT        0x18
  71
  72 #define EN2_STARTPG     0x21    /* Starting page of ring bfr RD */
  73 #define EN2_STOPPG      0x22    /* Ending page +1 of ring bfr RD */
  74
  75 #define EN3_CONFIG0     0x33
  76 #define EN3_CONFIG1     0x34
  77 #define EN3_CONFIG2     0x35
  78 #define EN3_CONFIG3     0x36
  79
  80 /*  Register accessed at EN_CMD, the 8390 base addr.  */
  81 #define E8390_STOP      0x01    /* Stop and reset the chip */
  82 #define E8390_START     0x02    /* Start the chip, clear reset */
  83 #define E8390_TRANS     0x04    /* Transmit a frame */
  84 #define E8390_RREAD     0x08    /* Remote read */
  85 #define E8390_RWRITE    0x10    /* Remote write  */
  86 #define E8390_NODMA     0x20    /* Remote DMA */
  87 #define E8390_PAGE0     0x00    /* Select page chip registers */
  88 #define E8390_PAGE1     0x40    /* using the two high-order bits */
  89 #define E8390_PAGE2     0x80    /* Page 3 is invalid. */
  90
  91 /* Bits in EN0_ISR - Interrupt status register */
  92 #define ENISR_RX        0x01    /* Receiver, no error */
  93 #define ENISR_TX        0x02    /* Transmitter, no error */
  94 #define ENISR_RX_ERR    0x04    /* Receiver, with error */
  95 #define ENISR_TX_ERR    0x08    /* Transmitter, with error */
  96 #define ENISR_OVER      0x10    /* Receiver overwrote the ring */
  97 #define ENISR_COUNTERS  0x20    /* Counters need emptying */
  98 #define ENISR_RDC       0x40    /* remote dma complete */
  99 #define ENISR_RESET     0x80    /* Reset completed */
 100 #define ENISR_ALL       0x3f    /* Interrupts we will enable */
 101
 102 /* Bits in received packet status byte and EN0_RSR*/
 103 #define ENRSR_RXOK      0x01    /* Received a good packet */
 104 #define ENRSR_CRC       0x02    /* CRC error */
 105 #define ENRSR_FAE       0x04    /* frame alignment error */
 106 #define ENRSR_FO        0x08    /* FIFO overrun */
 107 #define ENRSR_MPA       0x10    /* missed pkt */
 108 #define ENRSR_PHY       0x20    /* physical/multicast address */
 109 #define ENRSR_DIS       0x40    /* receiver disable. set in monitor mode */
 110 #define ENRSR_DEF       0x80    /* deferring */
 111
 112 /* Transmitted packet status, EN0_TSR. */
 113 #define ENTSR_PTX 0x01  /* Packet transmitted without error */
 114 #define ENTSR_ND  0x02  /* The transmit wasn't deferred. */
 115 #define ENTSR_COL 0x04  /* The transmit collided at least once. */
 116 #define ENTSR_ABT 0x08  /* The transmit collided 16 times, and was deferred. */
 117 #define ENTSR_CRS 0x10  /* The carrier sense was lost. */
 118 #define ENTSR_FU  0x20  /* A "FIFO underrun" occurred during transmit. */
 119 #define ENTSR_CDH 0x40  /* The collision detect "heartbeat" signal was lost. */
 120 #define ENTSR_OWC 0x80  /* There was an out-of-window collision. */
 121
 122 typedef struct PCINE2000State {
 123     PCIDevice dev;
 124     NE2000State ne2000;
 125 } PCINE2000State;
 126
 127 void ne2000_reset(NE2000State *s)
 128 {
 129     int i;
 130
 131     s->isr = ENISR_RESET;
 132     memcpy(s->mem, &s->c.macaddr, 6);
 133     s->mem[14] = 0x57;
 134     s->mem[15] = 0x57;
 135
 136     /* duplicate prom data */
 137     for(i = 15;i >= 0; i--) {
 138         s->mem[2 * i] = s->mem[i];
 139         s->mem[2 * i + 1] = s->mem[i];
 140     }
 141 }
 142
 143 static void ne2000_update_irq(NE2000State *s)
 144 {
 145     int isr;
 146     isr = (s->isr & s->imr) & 0x7f;
 147 #if defined(DEBUG_NE2000)
 148     printf("NE2000: Set IRQ to %d (%02x %02x)\n",
 149            isr ? 1 : 0, s->isr, s->imr);
 150 #endif
 151     qemu_set_irq(s->irq, (isr != 0));
 152 }
 153
 154 static int ne2000_buffer_full(NE2000State *s)
 155 {
 156     int avail, index, boundary;
 157
 158     index = s->curpag << 8;
 159     boundary = s->boundary << 8;
 160     if (index < boundary)
 161         avail = boundary - index;
 162     else
 163         avail = (s->stop - s->start) - (index - boundary);
 164     if (avail < (MAX_ETH_FRAME_SIZE + 4))
 165         return 1;
 166     return 0;
 167 }
 168
 169 #define MIN_BUF_SIZE 60
 170
 171 ssize_t ne2000_receive(NetClientState *nc, const uint8_t *buf, size_t size_)
 172 {
 173     NE2000State *s = qemu_get_nic_opaque(nc);
 174     int size = size_;
 175     uint8_t *p;
 176     unsigned int total_len, next, avail, len, index, mcast_idx;
 177     uint8_t buf1[60];
 178     static const uint8_t broadcast_macaddr[6] =
 179         { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
 180
 181 #if defined(DEBUG_NE2000)
 182     printf("NE2000: received len=%d\n", size);
 183 #endif
 184
 185     if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
 186         return -1;
 187
 188     /* XXX: check this */
 189     if (s->rxcr & 0x10) {
 190         /* promiscuous: receive all */
 191     } else {
 192         if (!memcmp(buf,  broadcast_macaddr, 6)) {
 193             /* broadcast address */
 194             if (!(s->rxcr & 0x04))
 195                 return size;
 196         } else if (buf[0] & 0x01) {
 197             /* multicast */
 198             if (!(s->rxcr & 0x08))
 199                 return size;
 200             mcast_idx = compute_mcast_idx(buf);
 201             if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
 202                 return size;
 203         } else if (s->mem[0] == buf[0] &&
 204                    s->mem[2] == buf[1] &&
 205                    s->mem[4] == buf[2] &&
 206                    s->mem[6] == buf[3] &&
 207                    s->mem[8] == buf[4] &&
 208                    s->mem[10] == buf[5]) {
 209             /* match */
 210         } else {
 211             return size;
 212         }
 213     }
 214
 215
 216     /* if too small buffer, then expand it */
 217     if (size < MIN_BUF_SIZE) {
 218         memcpy(buf1, buf, size);
 219         memset(buf1 + size, 0, MIN_BUF_SIZE - size);
 220         buf = buf1;
 221         size = MIN_BUF_SIZE;
 222     }
 223
 224     index = s->curpag << 8;
 225     if (index >= NE2000_PMEM_END) {
 226         index = s->start;
 227     }
 228     /* 4 bytes for header */
 229     total_len = size + 4;
 230     /* address for next packet (4 bytes for CRC) */
 231     next = index + ((total_len + 4 + 255) & ~0xff);
 232     if (next >= s->stop)
 233         next -= (s->stop - s->start);
 234     /* prepare packet header */
 235     p = s->mem + index;
 236     s->rsr = ENRSR_RXOK; /* receive status */
 237     /* XXX: check this */
 238     if (buf[0] & 0x01)
 239         s->rsr |= ENRSR_PHY;
 240     p[0] = s->rsr;
 241     p[1] = next >> 8;
 242     p[2] = total_len;
 243     p[3] = total_len >> 8;
 244     index += 4;
 245
 246     /* write packet data */
 247     while (size > 0) {
 248         if (index <= s->stop)
 249             avail = s->stop - index;
 250         else
 251             break;
 252         len = size;
 253         if (len > avail)
 254             len = avail;
 255         memcpy(s->mem + index, buf, len);
 256         buf += len;
 257         index += len;
 258         if (index == s->stop)
 259             index = s->start;
 260         size -= len;
 261     }
 262     s->curpag = next >> 8;
 263
 264     /* now we can signal we have received something */
 265     s->isr |= ENISR_RX;
 266     ne2000_update_irq(s);
 267
 268     return size_;
 269 }
 270
 271 static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 272 {
 273     NE2000State *s = opaque;
 274     int offset, page, index;
 275
 276     addr &= 0xf;
 277 #ifdef DEBUG_NE2000
 278     printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
 279 #endif
 280     if (addr == E8390_CMD) {
 281         /* control register */
 282         s->cmd = val;
 283         if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */
 284             s->isr &= ~ENISR_RESET;
 285             /* test specific case: zero length transfer */
 286             if ((val & (E8390_RREAD | E8390_RWRITE)) &&
 287                 s->rcnt == 0) {
 288                 s->isr |= ENISR_RDC;
 289                 ne2000_update_irq(s);
 290             }
 291             if (val & E8390_TRANS) {
 292                 index = (s->tpsr << 8);
 293                 /* XXX: next 2 lines are a hack to make netware 3.11 work */
 294                 if (index >= NE2000_PMEM_END)
 295                     index -= NE2000_PMEM_SIZE;
 296                 /* fail safe: check range on the transmitted length  */
 297                 if (index + s->tcnt <= NE2000_PMEM_END) {
 298                     qemu_send_packet(qemu_get_queue(s->nic), s->mem + index,
 299                                      s->tcnt);
 300                 }
 301                 /* signal end of transfer */
 302                 s->tsr = ENTSR_PTX;
 303                 s->isr |= ENISR_TX;
 304                 s->cmd &= ~E8390_TRANS;
 305                 ne2000_update_irq(s);
 306             }
 307         }
 308     } else {
 309         page = s->cmd >> 6;
 310         offset = addr | (page << 4);
 311         switch(offset) {
 312         case EN0_STARTPG:
 313             if (val << 8 <= NE2000_PMEM_END) {
 314                 s->start = val << 8;
 315             }
 316             break;
 317         case EN0_STOPPG:
 318             if (val << 8 <= NE2000_PMEM_END) {
 319                 s->stop = val << 8;
 320             }
 321             break;
 322         case EN0_BOUNDARY:
 323             if (val << 8 < NE2000_PMEM_END) {
 324                 s->boundary = val;
 325             }
 326             break;
 327         case EN0_IMR:
 328             s->imr = val;
 329             ne2000_update_irq(s);
 330             break;
 331         case EN0_TPSR:
 332             s->tpsr = val;
 333             break;
 334         case EN0_TCNTLO:
 335             s->tcnt = (s->tcnt & 0xff00) | val;
 336             break;
 337         case EN0_TCNTHI:
 338             s->tcnt = (s->tcnt & 0x00ff) | (val << 8);
 339             break;
 340         case EN0_RSARLO:
 341             s->rsar = (s->rsar & 0xff00) | val;
 342             break;
 343         case EN0_RSARHI:
 344             s->rsar = (s->rsar & 0x00ff) | (val << 8);
 345             break;
 346         case EN0_RCNTLO:
 347             s->rcnt = (s->rcnt & 0xff00) | val;
 348             break;
 349         case EN0_RCNTHI:
 350             s->rcnt = (s->rcnt & 0x00ff) | (val << 8);
 351             break;
 352         case EN0_RXCR:
 353             s->rxcr = val;
 354             break;
 355         case EN0_DCFG:
 356             s->dcfg = val;
 357             break;
 358         case EN0_ISR:
 359             s->isr &= ~(val & 0x7f);
 360             ne2000_update_irq(s);
 361             break;
 362         case EN1_PHYS ... EN1_PHYS + 5:
 363             s->phys[offset - EN1_PHYS] = val;
 364             break;
 365         case EN1_CURPAG:
 366             if (val << 8 < NE2000_PMEM_END) {
 367                 s->curpag = val;
 368             }
 369             break;
 370         case EN1_MULT ... EN1_MULT + 7:
 371             s->mult[offset - EN1_MULT] = val;
 372             break;
 373         }
 374     }
 375 }
 376
 377 static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr)
 378 {
 379     NE2000State *s = opaque;
 380     int offset, page, ret;
 381
 382     addr &= 0xf;
 383     if (addr == E8390_CMD) {
 384         ret = s->cmd;
 385     } else {
 386         page = s->cmd >> 6;
 387         offset = addr | (page << 4);
 388         switch(offset) {
 389         case EN0_TSR:
 390             ret = s->tsr;
 391             break;
 392         case EN0_BOUNDARY:
 393             ret = s->boundary;
 394             break;
 395         case EN0_ISR:
 396             ret = s->isr;
 397             break;
 398         case EN0_RSARLO:
 399             ret = s->rsar & 0x00ff;
 400             break;
 401         case EN0_RSARHI:
 402             ret = s->rsar >> 8;
 403             break;
 404         case EN1_PHYS ... EN1_PHYS + 5:
 405             ret = s->phys[offset - EN1_PHYS];
 406             break;
 407         case EN1_CURPAG:
 408             ret = s->curpag;
 409             break;
 410         case EN1_MULT ... EN1_MULT + 7:
 411             ret = s->mult[offset - EN1_MULT];
 412             break;
 413         case EN0_RSR:
 414             ret = s->rsr;
 415             break;
 416         case EN2_STARTPG:
 417             ret = s->start >> 8;
 418             break;
 419         case EN2_STOPPG:
 420             ret = s->stop >> 8;
 421             break;
 422         case EN0_RTL8029ID0:
 423             ret = 0x50;
 424             break;
 425         case EN0_RTL8029ID1:
 426             ret = 0x43;
 427             break;
 428         case EN3_CONFIG0:
 429             ret = 0;            /* 10baseT media */
 430             break;
 431         case EN3_CONFIG2:
 432             ret = 0x40;         /* 10baseT active */
 433             break;
 434         case EN3_CONFIG3:
 435             ret = 0x40;         /* Full duplex */
 436             break;
 437         default:
 438             ret = 0x00;
 439             break;
 440         }
 441     }
 442 #ifdef DEBUG_NE2000
 443     printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
 444 #endif
 445     return ret;
 446 }
 447
 448 static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr,
 449                                      uint32_t val)
 450 {
 451     if (addr < 32 ||
 452         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 453         s->mem[addr] = val;
 454     }
 455 }
 456
 457 static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr,
 458                                      uint32_t val)
 459 {
 460     addr &= ~1; /* XXX: check exact behaviour if not even */
 461     if (addr < 32 ||
 462         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 463         *(uint16_t *)(s->mem + addr) = cpu_to_le16(val);
 464     }
 465 }
 466
 467 static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr,
 468                                      uint32_t val)
 469 {
 470     addr &= ~1; /* XXX: check exact behaviour if not even */
 471     if (addr < 32
 472         || (addr >= NE2000_PMEM_START
 473             && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
 474         stl_le_p(s->mem + addr, val);
 475     }
 476 }
 477
 478 static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr)
 479 {
 480     if (addr < 32 ||
 481         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 482         return s->mem[addr];
 483     } else {
 484         return 0xff;
 485     }
 486 }
 487
 488 static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr)
 489 {
 490     addr &= ~1; /* XXX: check exact behaviour if not even */
 491     if (addr < 32 ||
 492         (addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
 493         return le16_to_cpu(*(uint16_t *)(s->mem + addr));
 494     } else {
 495         return 0xffff;
 496     }
 497 }
 498
 499 static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr)
 500 {
 501     addr &= ~1; /* XXX: check exact behaviour if not even */
 502     if (addr < 32
 503         || (addr >= NE2000_PMEM_START
 504             && addr + sizeof(uint32_t) <= NE2000_MEM_SIZE)) {
 505         return ldl_le_p(s->mem + addr);
 506     } else {
 507         return 0xffffffff;
 508     }
 509 }
 510
 511 static inline void ne2000_dma_update(NE2000State *s, int len)
 512 {
 513     s->rsar += len;
 514     /* wrap */
 515     /* XXX: check what to do if rsar > stop */
 516     if (s->rsar == s->stop)
 517         s->rsar = s->start;
 518
 519     if (s->rcnt <= len) {
 520         s->rcnt = 0;
 521         /* signal end of transfer */
 522         s->isr |= ENISR_RDC;
 523         ne2000_update_irq(s);
 524     } else {
 525         s->rcnt -= len;
 526     }
 527 }
 528
 529 static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 530 {
 531     NE2000State *s = opaque;
 532
 533 #ifdef DEBUG_NE2000
 534     printf("NE2000: asic write val=0x%04x\n", val);
 535 #endif
 536     if (s->rcnt == 0)
 537         return;
 538     if (s->dcfg & 0x01) {
 539         /* 16 bit access */
 540         ne2000_mem_writew(s, s->rsar, val);
 541         ne2000_dma_update(s, 2);
 542     } else {
 543         /* 8 bit access */
 544         ne2000_mem_writeb(s, s->rsar, val);
 545         ne2000_dma_update(s, 1);
 546     }
 547 }
 548
 549 static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr)
 550 {
 551     NE2000State *s = opaque;
 552     int ret;
 553
 554     if (s->dcfg & 0x01) {
 555         /* 16 bit access */
 556         ret = ne2000_mem_readw(s, s->rsar);
 557         ne2000_dma_update(s, 2);
 558     } else {
 559         /* 8 bit access */
 560         ret = ne2000_mem_readb(s, s->rsar);
 561         ne2000_dma_update(s, 1);
 562     }
 563 #ifdef DEBUG_NE2000
 564     printf("NE2000: asic read val=0x%04x\n", ret);
 565 #endif
 566     return ret;
 567 }
 568
 569 static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 570 {
 571     NE2000State *s = opaque;
 572
 573 #ifdef DEBUG_NE2000
 574     printf("NE2000: asic writel val=0x%04x\n", val);
 575 #endif
 576     if (s->rcnt == 0)
 577         return;
 578     /* 32 bit access */
 579     ne2000_mem_writel(s, s->rsar, val);
 580     ne2000_dma_update(s, 4);
 581 }
 582
 583 static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr)
 584 {
 585     NE2000State *s = opaque;
 586     int ret;
 587
 588     /* 32 bit access */
 589     ret = ne2000_mem_readl(s, s->rsar);
 590     ne2000_dma_update(s, 4);
 591 #ifdef DEBUG_NE2000
 592     printf("NE2000: asic readl val=0x%04x\n", ret);
 593 #endif
 594     return ret;
 595 }
 596
 597 static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 598 {
 599     /* nothing to do (end of reset pulse) */
 600 }
 601
 602 static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr)
 603 {
 604     NE2000State *s = opaque;
 605     ne2000_reset(s);
 606     return 0;
 607 }
 608
 609 static int ne2000_post_load(void* opaque, int version_id)
 610 {
 611     NE2000State* s = opaque;
 612
 613     if (version_id < 2) {
 614         s->rxcr = 0x0c;
 615     }
 616     return 0;
 617 }
 618
 619 const VMStateDescription vmstate_ne2000 = {
 620     .name = "ne2000",
 621     .version_id = 2,
 622     .minimum_version_id = 0,
 623     .post_load = ne2000_post_load,
 624     .fields = (VMStateField[]) {
 625         VMSTATE_UINT8_V(rxcr, NE2000State, 2),
 626         VMSTATE_UINT8(cmd, NE2000State),
 627         VMSTATE_UINT32(start, NE2000State),
 628         VMSTATE_UINT32(stop, NE2000State),
 629         VMSTATE_UINT8(boundary, NE2000State),
 630         VMSTATE_UINT8(tsr, NE2000State),
 631         VMSTATE_UINT8(tpsr, NE2000State),
 632         VMSTATE_UINT16(tcnt, NE2000State),
 633         VMSTATE_UINT16(rcnt, NE2000State),
 634         VMSTATE_UINT32(rsar, NE2000State),
 635         VMSTATE_UINT8(rsr, NE2000State),
 636         VMSTATE_UINT8(isr, NE2000State),
 637         VMSTATE_UINT8(dcfg, NE2000State),
 638         VMSTATE_UINT8(imr, NE2000State),
 639         VMSTATE_BUFFER(phys, NE2000State),
 640         VMSTATE_UINT8(curpag, NE2000State),
 641         VMSTATE_BUFFER(mult, NE2000State),
 642         VMSTATE_UNUSED(4), /* was irq */
 643         VMSTATE_BUFFER(mem, NE2000State),
 644         VMSTATE_END_OF_LIST()
 645     }
 646 };
 647
 648 static const VMStateDescription vmstate_pci_ne2000 = {
 649     .name = "ne2000",
 650     .version_id = 3,
 651     .minimum_version_id = 3,
 652     .fields = (VMStateField[]) {
 653         VMSTATE_PCI_DEVICE(dev, PCINE2000State),
 654         VMSTATE_STRUCT(ne2000, PCINE2000State, 0, vmstate_ne2000, NE2000State),
 655         VMSTATE_END_OF_LIST()
 656     }
 657 };
 658
 659 static uint64_t ne2000_read(void *opaque, hwaddr addr,
 660                             unsigned size)
 661 {
 662     NE2000State *s = opaque;
 663
 664     if (addr < 0x10 && size == 1) {
 665         return ne2000_ioport_read(s, addr);
 666     } else if (addr == 0x10) {
 667         if (size <= 2) {
 668             return ne2000_asic_ioport_read(s, addr);
 669         } else {
 670             return ne2000_asic_ioport_readl(s, addr);
 671         }
 672     } else if (addr == 0x1f && size == 1) {
 673         return ne2000_reset_ioport_read(s, addr);
 674     }
 675     return ((uint64_t)1 << (size * 8)) - 1;
 676 }
 677
 678 static void ne2000_write(void *opaque, hwaddr addr,
 679                          uint64_t data, unsigned size)
 680 {
 681     NE2000State *s = opaque;
 682
 683     if (addr < 0x10 && size == 1) {
 684         ne2000_ioport_write(s, addr, data);
 685     } else if (addr == 0x10) {
 686         if (size <= 2) {
 687             ne2000_asic_ioport_write(s, addr, data);
 688         } else {
 689             ne2000_asic_ioport_writel(s, addr, data);
 690         }
 691     } else if (addr == 0x1f && size == 1) {
 692         ne2000_reset_ioport_write(s, addr, data);
 693     }
 694 }
 695
 696 static const MemoryRegionOps ne2000_ops = {
 697     .read = ne2000_read,
 698     .write = ne2000_write,
 699     .endianness = DEVICE_LITTLE_ENDIAN,
 700 };
 701
 702 /***********************************************************/
 703 /* PCI NE2000 definitions */
 704
 705 void ne2000_setup_io(NE2000State *s, DeviceState *dev, unsigned size)
 706 {
 707     memory_region_init_io(&s->io, OBJECT(dev), &ne2000_ops, s, "ne2000", size);
 708 }
 709
 710 static NetClientInfo net_ne2000_info = {
 711     .type = NET_CLIENT_OPTIONS_KIND_NIC,
 712     .size = sizeof(NICState),
 713     .receive = ne2000_receive,
 714 };
 715
 716 static void pci_ne2000_realize(PCIDevice *pci_dev, Error **errp)
 717 {
 718     PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
 719     NE2000State *s;
 720     uint8_t *pci_conf;
 721
 722     pci_conf = d->dev.config;
 723     pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
 724
 725     s = &d->ne2000;
 726     ne2000_setup_io(s, DEVICE(pci_dev), 0x100);
 727     pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
 728     s->irq = pci_allocate_irq(&d->dev);
 729
 730     qemu_macaddr_default_if_unset(&s->c.macaddr);
 731     ne2000_reset(s);
 732
 733     s->nic = qemu_new_nic(&net_ne2000_info, &s->c,
 734                           object_get_typename(OBJECT(pci_dev)), pci_dev->qdev.id, s);
 735     qemu_format_nic_info_str(qemu_get_queue(s->nic), s->c.macaddr.a);
 736 }
 737
 738 static void pci_ne2000_exit(PCIDevice *pci_dev)
 739 {
 740     PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
 741     NE2000State *s = &d->ne2000;
 742
 743     qemu_del_nic(s->nic);
 744     qemu_free_irq(s->irq);
 745 }
 746
 747 static void ne2000_instance_init(Object *obj)
 748 {
 749     PCIDevice *pci_dev = PCI_DEVICE(obj);
 750     PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev);
 751     NE2000State *s = &d->ne2000;
 752
 753     device_add_bootindex_property(obj, &s->c.bootindex,
 754                                   "bootindex", "/ethernet-phy@0",
 755                                   &pci_dev->qdev, NULL);
 756 }
 757
 758 static Property ne2000_properties[] = {
 759     DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c),
 760     DEFINE_PROP_END_OF_LIST(),
 761 };
 762
 763 static void ne2000_class_init(ObjectClass *klass, void *data)
 764 {
 765     DeviceClass *dc = DEVICE_CLASS(klass);
 766     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 767
 768     k->realize = pci_ne2000_realize;
 769     k->exit = pci_ne2000_exit;
 770     k->romfile = "efi-ne2k_pci.rom",
 771     k->vendor_id = PCI_VENDOR_ID_REALTEK;
 772     k->device_id = PCI_DEVICE_ID_REALTEK_8029;
 773     k->class_id = PCI_CLASS_NETWORK_ETHERNET;
 774     dc->vmsd = &vmstate_pci_ne2000;
 775     dc->props = ne2000_properties;
 776     set_bit(DEVICE_CATEGORY_NETWORK, dc->categories);
 777 }
 778
 779 static const TypeInfo ne2000_info = {
 780     .name          = "ne2k_pci",
 781     .parent        = TYPE_PCI_DEVICE,
 782     .instance_size = sizeof(PCINE2000State),
 783     .class_init    = ne2000_class_init,
 784     .instance_init = ne2000_instance_init,
 785 };
 786
 787 static void ne2000_register_types(void)
 788 {
 789     type_register_static(&ne2000_info);
 790 }
 791
 792 type_init(ne2000_register_types)