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target-tricore: add SWAPMSK instructions of the v1.6.1 ISA
[qemu.git] / target-tricore / translate.c
blobb2e25e7c7fc0e711572668369074f8e8285756a6
1 /*
2 * TriCore emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2013-2014 Bastian Koppelmann C-Lab/University Paderborn
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "exec/cpu_ldst.h"
25
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28
29 #include "tricore-opcodes.h"
30
31 /*
32 * TCG registers
33 */
34 static TCGv cpu_PC;
35 static TCGv cpu_PCXI;
36 static TCGv cpu_PSW;
37 static TCGv cpu_ICR;
38 /* GPR registers */
39 static TCGv cpu_gpr_a[16];
40 static TCGv cpu_gpr_d[16];
41 /* PSW Flag cache */
42 static TCGv cpu_PSW_C;
43 static TCGv cpu_PSW_V;
44 static TCGv cpu_PSW_SV;
45 static TCGv cpu_PSW_AV;
46 static TCGv cpu_PSW_SAV;
47 /* CPU env */
48 static TCGv_ptr cpu_env;
49
50 #include "exec/gen-icount.h"
51
52 static const char *regnames_a[] = {
53 "a0" , "a1" , "a2" , "a3" , "a4" , "a5" ,
54 "a6" , "a7" , "a8" , "a9" , "sp" , "a11" ,
55 "a12" , "a13" , "a14" , "a15",
56 };
57
58 static const char *regnames_d[] = {
59 "d0" , "d1" , "d2" , "d3" , "d4" , "d5" ,
60 "d6" , "d7" , "d8" , "d9" , "d10" , "d11" ,
61 "d12" , "d13" , "d14" , "d15",
62 };
63
64 typedef struct DisasContext {
65 struct TranslationBlock *tb;
66 target_ulong pc, saved_pc, next_pc;
67 uint32_t opcode;
68 int singlestep_enabled;
69 /* Routine used to access memory */
70 int mem_idx;
71 uint32_t hflags, saved_hflags;
72 int bstate;
73 } DisasContext;
74
75 enum {
76
77 BS_NONE = 0,
78 BS_STOP = 1,
79 BS_BRANCH = 2,
80 BS_EXCP = 3,
81 };
82
83 enum {
84 MODE_LL = 0,
85 MODE_LU = 1,
86 MODE_UL = 2,
87 MODE_UU = 3,
88 };
89
90 void tricore_cpu_dump_state(CPUState *cs, FILE *f,
91 fprintf_function cpu_fprintf, int flags)
92 {
93 TriCoreCPU *cpu = TRICORE_CPU(cs);
94 CPUTriCoreState *env = &cpu->env;
95 uint32_t psw;
96 int i;
97
98 psw = psw_read(env);
99
100 cpu_fprintf(f, "PC: " TARGET_FMT_lx, env->PC);
101 cpu_fprintf(f, " PSW: " TARGET_FMT_lx, psw);
102 cpu_fprintf(f, " ICR: " TARGET_FMT_lx, env->ICR);
103 cpu_fprintf(f, "\nPCXI: " TARGET_FMT_lx, env->PCXI);
104 cpu_fprintf(f, " FCX: " TARGET_FMT_lx, env->FCX);
105 cpu_fprintf(f, " LCX: " TARGET_FMT_lx, env->LCX);
106
107 for (i = 0; i < 16; ++i) {
108 if ((i & 3) == 0) {
109 cpu_fprintf(f, "\nGPR A%02d:", i);
110 }
111 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_a[i]);
112 }
113 for (i = 0; i < 16; ++i) {
114 if ((i & 3) == 0) {
115 cpu_fprintf(f, "\nGPR D%02d:", i);
116 }
117 cpu_fprintf(f, " " TARGET_FMT_lx, env->gpr_d[i]);
118 }
119 cpu_fprintf(f, "\n");
120 }
121
122 /*
123 * Functions to generate micro-ops
124 */
125
126 /* Makros for generating helpers */
127
128 #define gen_helper_1arg(name, arg) do { \
129 TCGv_i32 helper_tmp = tcg_const_i32(arg); \
130 gen_helper_##name(cpu_env, helper_tmp); \
131 tcg_temp_free_i32(helper_tmp); \
132 } while (0)
133
134 #define GEN_HELPER_LL(name, ret, arg0, arg1, n) do { \
135 TCGv arg00 = tcg_temp_new(); \
136 TCGv arg01 = tcg_temp_new(); \
137 TCGv arg11 = tcg_temp_new(); \
138 tcg_gen_sari_tl(arg00, arg0, 16); \
139 tcg_gen_ext16s_tl(arg01, arg0); \
140 tcg_gen_ext16s_tl(arg11, arg1); \
141 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
142 tcg_temp_free(arg00); \
143 tcg_temp_free(arg01); \
144 tcg_temp_free(arg11); \
145 } while (0)
146
147 #define GEN_HELPER_LU(name, ret, arg0, arg1, n) do { \
148 TCGv arg00 = tcg_temp_new(); \
149 TCGv arg01 = tcg_temp_new(); \
150 TCGv arg10 = tcg_temp_new(); \
151 TCGv arg11 = tcg_temp_new(); \
152 tcg_gen_sari_tl(arg00, arg0, 16); \
153 tcg_gen_ext16s_tl(arg01, arg0); \
154 tcg_gen_sari_tl(arg11, arg1, 16); \
155 tcg_gen_ext16s_tl(arg10, arg1); \
156 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
157 tcg_temp_free(arg00); \
158 tcg_temp_free(arg01); \
159 tcg_temp_free(arg10); \
160 tcg_temp_free(arg11); \
161 } while (0)
162
163 #define GEN_HELPER_UL(name, ret, arg0, arg1, n) do { \
164 TCGv arg00 = tcg_temp_new(); \
165 TCGv arg01 = tcg_temp_new(); \
166 TCGv arg10 = tcg_temp_new(); \
167 TCGv arg11 = tcg_temp_new(); \
168 tcg_gen_sari_tl(arg00, arg0, 16); \
169 tcg_gen_ext16s_tl(arg01, arg0); \
170 tcg_gen_sari_tl(arg10, arg1, 16); \
171 tcg_gen_ext16s_tl(arg11, arg1); \
172 gen_helper_##name(ret, arg00, arg01, arg10, arg11, n); \
173 tcg_temp_free(arg00); \
174 tcg_temp_free(arg01); \
175 tcg_temp_free(arg10); \
176 tcg_temp_free(arg11); \
177 } while (0)
178
179 #define GEN_HELPER_UU(name, ret, arg0, arg1, n) do { \
180 TCGv arg00 = tcg_temp_new(); \
181 TCGv arg01 = tcg_temp_new(); \
182 TCGv arg11 = tcg_temp_new(); \
183 tcg_gen_sari_tl(arg01, arg0, 16); \
184 tcg_gen_ext16s_tl(arg00, arg0); \
185 tcg_gen_sari_tl(arg11, arg1, 16); \
186 gen_helper_##name(ret, arg00, arg01, arg11, arg11, n); \
187 tcg_temp_free(arg00); \
188 tcg_temp_free(arg01); \
189 tcg_temp_free(arg11); \
190 } while (0)
191
192 #define GEN_HELPER_RRR(name, rl, rh, al1, ah1, arg2) do { \
193 TCGv_i64 ret = tcg_temp_new_i64(); \
194 TCGv_i64 arg1 = tcg_temp_new_i64(); \
195 \
196 tcg_gen_concat_i32_i64(arg1, al1, ah1); \
197 gen_helper_##name(ret, arg1, arg2); \
198 tcg_gen_extr_i64_i32(rl, rh, ret); \
199 \
200 tcg_temp_free_i64(ret); \
201 tcg_temp_free_i64(arg1); \
202 } while (0)
203
204 #define EA_ABS_FORMAT(con) (((con & 0x3C000) << 14) + (con & 0x3FFF))
205 #define EA_B_ABSOLUT(con) (((offset & 0xf00000) << 8) | \
206 ((offset & 0x0fffff) << 1))
207
208 /* Functions for load/save to/from memory */
209
210 static inline void gen_offset_ld(DisasContext *ctx, TCGv r1, TCGv r2,
211 int16_t con, TCGMemOp mop)
212 {
213 TCGv temp = tcg_temp_new();
214 tcg_gen_addi_tl(temp, r2, con);
215 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
216 tcg_temp_free(temp);
217 }
218
219 static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,
220 int16_t con, TCGMemOp mop)
221 {
222 TCGv temp = tcg_temp_new();
223 tcg_gen_addi_tl(temp, r2, con);
224 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
225 tcg_temp_free(temp);
226 }
227
228 static void gen_st_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
229 {
230 TCGv_i64 temp = tcg_temp_new_i64();
231
232 tcg_gen_concat_i32_i64(temp, rl, rh);
233 tcg_gen_qemu_st_i64(temp, address, ctx->mem_idx, MO_LEQ);
234
235 tcg_temp_free_i64(temp);
236 }
237
238 static void gen_offset_st_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
239 DisasContext *ctx)
240 {
241 TCGv temp = tcg_temp_new();
242 tcg_gen_addi_tl(temp, base, con);
243 gen_st_2regs_64(rh, rl, temp, ctx);
244 tcg_temp_free(temp);
245 }
246
247 static void gen_ld_2regs_64(TCGv rh, TCGv rl, TCGv address, DisasContext *ctx)
248 {
249 TCGv_i64 temp = tcg_temp_new_i64();
250
251 tcg_gen_qemu_ld_i64(temp, address, ctx->mem_idx, MO_LEQ);
252 /* write back to two 32 bit regs */
253 tcg_gen_extr_i64_i32(rl, rh, temp);
254
255 tcg_temp_free_i64(temp);
256 }
257
258 static void gen_offset_ld_2regs(TCGv rh, TCGv rl, TCGv base, int16_t con,
259 DisasContext *ctx)
260 {
261 TCGv temp = tcg_temp_new();
262 tcg_gen_addi_tl(temp, base, con);
263 gen_ld_2regs_64(rh, rl, temp, ctx);
264 tcg_temp_free(temp);
265 }
266
267 static void gen_st_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
268 TCGMemOp mop)
269 {
270 TCGv temp = tcg_temp_new();
271 tcg_gen_addi_tl(temp, r2, off);
272 tcg_gen_qemu_st_tl(r1, temp, ctx->mem_idx, mop);
273 tcg_gen_mov_tl(r2, temp);
274 tcg_temp_free(temp);
275 }
276
277 static void gen_ld_preincr(DisasContext *ctx, TCGv r1, TCGv r2, int16_t off,
278 TCGMemOp mop)
279 {
280 TCGv temp = tcg_temp_new();
281 tcg_gen_addi_tl(temp, r2, off);
282 tcg_gen_qemu_ld_tl(r1, temp, ctx->mem_idx, mop);
283 tcg_gen_mov_tl(r2, temp);
284 tcg_temp_free(temp);
285 }
286
287 /* M(EA, word) = (M(EA, word) & ~E[a][63:32]) | (E[a][31:0] & E[a][63:32]); */
288 static void gen_ldmst(DisasContext *ctx, int ereg, TCGv ea)
289 {
290 TCGv temp = tcg_temp_new();
291 TCGv temp2 = tcg_temp_new();
292
293 /* temp = (M(EA, word) */
294 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
295 /* temp = temp & ~E[a][63:32]) */
296 tcg_gen_andc_tl(temp, temp, cpu_gpr_d[ereg+1]);
297 /* temp2 = (E[a][31:0] & E[a][63:32]); */
298 tcg_gen_and_tl(temp2, cpu_gpr_d[ereg], cpu_gpr_d[ereg+1]);
299 /* temp = temp | temp2; */
300 tcg_gen_or_tl(temp, temp, temp2);
301 /* M(EA, word) = temp; */
302 tcg_gen_qemu_st_tl(temp, ea, ctx->mem_idx, MO_LEUL);
303
304 tcg_temp_free(temp);
305 tcg_temp_free(temp2);
306 }
307
308 /* tmp = M(EA, word);
309 M(EA, word) = D[a];
310 D[a] = tmp[31:0];*/
311 static void gen_swap(DisasContext *ctx, int reg, TCGv ea)
312 {
313 TCGv temp = tcg_temp_new();
314
315 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
316 tcg_gen_qemu_st_tl(cpu_gpr_d[reg], ea, ctx->mem_idx, MO_LEUL);
317 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
318
319 tcg_temp_free(temp);
320 }
321
322 static void gen_cmpswap(DisasContext *ctx, int reg, TCGv ea)
323 {
324 TCGv temp = tcg_temp_new();
325 TCGv temp2 = tcg_temp_new();
326 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
327 tcg_gen_movcond_tl(TCG_COND_EQ, temp2, cpu_gpr_d[reg+1], temp,
328 cpu_gpr_d[reg], temp);
329 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
330 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
331
332 tcg_temp_free(temp);
333 tcg_temp_free(temp2);
334 }
335
336 static void gen_swapmsk(DisasContext *ctx, int reg, TCGv ea)
337 {
338 TCGv temp = tcg_temp_new();
339 TCGv temp2 = tcg_temp_new();
340 TCGv temp3 = tcg_temp_new();
341
342 tcg_gen_qemu_ld_tl(temp, ea, ctx->mem_idx, MO_LEUL);
343 tcg_gen_and_tl(temp2, cpu_gpr_d[reg], cpu_gpr_d[reg+1]);
344 tcg_gen_andc_tl(temp3, temp, cpu_gpr_d[reg+1]);
345 tcg_gen_or_tl(temp2, temp2, temp3);
346 tcg_gen_qemu_st_tl(temp2, ea, ctx->mem_idx, MO_LEUL);
347 tcg_gen_mov_tl(cpu_gpr_d[reg], temp);
348
349 tcg_temp_free(temp);
350 tcg_temp_free(temp2);
351 tcg_temp_free(temp3);
352 }
353
354
355 /* We generate loads and store to core special function register (csfr) through
356 the function gen_mfcr and gen_mtcr. To handle access permissions, we use 3
357 makros R, A and E, which allow read-only, all and endinit protected access.
358 These makros also specify in which ISA version the csfr was introduced. */
359 #define R(ADDRESS, REG, FEATURE) \
360 case ADDRESS: \
361 if (tricore_feature(env, FEATURE)) { \
362 tcg_gen_ld_tl(ret, cpu_env, offsetof(CPUTriCoreState, REG)); \
363 } \
364 break;
365 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
366 #define E(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE)
367 static inline void gen_mfcr(CPUTriCoreState *env, TCGv ret, int32_t offset)
368 {
369 /* since we're caching PSW make this a special case */
370 if (offset == 0xfe04) {
371 gen_helper_psw_read(ret, cpu_env);
372 } else {
373 switch (offset) {
374 #include "csfr.def"
375 }
376 }
377 }
378 #undef R
379 #undef A
380 #undef E
381
382 #define R(ADDRESS, REG, FEATURE) /* don't gen writes to read-only reg,
383 since no execption occurs */
384 #define A(ADDRESS, REG, FEATURE) R(ADDRESS, REG, FEATURE) \
385 case ADDRESS: \
386 if (tricore_feature(env, FEATURE)) { \
387 tcg_gen_st_tl(r1, cpu_env, offsetof(CPUTriCoreState, REG)); \
388 } \
389 break;
390 /* Endinit protected registers
391 TODO: Since the endinit bit is in a register of a not yet implemented
392 watchdog device, we handle endinit protected registers like
393 all-access registers for now. */
394 #define E(ADDRESS, REG, FEATURE) A(ADDRESS, REG, FEATURE)
395 static inline void gen_mtcr(CPUTriCoreState *env, DisasContext *ctx, TCGv r1,
396 int32_t offset)
397 {
398 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
399 /* since we're caching PSW make this a special case */
400 if (offset == 0xfe04) {
401 gen_helper_psw_write(cpu_env, r1);
402 } else {
403 switch (offset) {
404 #include "csfr.def"
405 }
406 }
407 } else {
408 /* generate privilege trap */
409 }
410 }
411
412 /* Functions for arithmetic instructions */
413
414 static inline void gen_add_d(TCGv ret, TCGv r1, TCGv r2)
415 {
416 TCGv t0 = tcg_temp_new_i32();
417 TCGv result = tcg_temp_new_i32();
418 /* Addition and set V/SV bits */
419 tcg_gen_add_tl(result, r1, r2);
420 /* calc V bit */
421 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
422 tcg_gen_xor_tl(t0, r1, r2);
423 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
424 /* Calc SV bit */
425 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
426 /* Calc AV/SAV bits */
427 tcg_gen_add_tl(cpu_PSW_AV, result, result);
428 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
429 /* calc SAV */
430 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
431 /* write back result */
432 tcg_gen_mov_tl(ret, result);
433
434 tcg_temp_free(result);
435 tcg_temp_free(t0);
436 }
437
438 static inline void
439 gen_add64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
440 {
441 TCGv temp = tcg_temp_new();
442 TCGv_i64 t0 = tcg_temp_new_i64();
443 TCGv_i64 t1 = tcg_temp_new_i64();
444 TCGv_i64 result = tcg_temp_new_i64();
445
446 tcg_gen_add_i64(result, r1, r2);
447 /* calc v bit */
448 tcg_gen_xor_i64(t1, result, r1);
449 tcg_gen_xor_i64(t0, r1, r2);
450 tcg_gen_andc_i64(t1, t1, t0);
451 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t1, 32);
452 /* calc SV bit */
453 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
454 /* calc AV/SAV bits */
455 tcg_gen_trunc_shr_i64_i32(temp, result, 32);
456 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
457 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
458 /* calc SAV */
459 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
460 /* write back result */
461 tcg_gen_mov_i64(ret, result);
462
463 tcg_temp_free(temp);
464 tcg_temp_free_i64(result);
465 tcg_temp_free_i64(t0);
466 tcg_temp_free_i64(t1);
467 }
468
469 static inline void
470 gen_addsub64_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
471 TCGv r3, void(*op1)(TCGv, TCGv, TCGv),
472 void(*op2)(TCGv, TCGv, TCGv))
473 {
474 TCGv temp = tcg_temp_new();
475 TCGv temp2 = tcg_temp_new();
476 TCGv temp3 = tcg_temp_new();
477 TCGv temp4 = tcg_temp_new();
478
479 (*op1)(temp, r1_low, r2);
480 /* calc V0 bit */
481 tcg_gen_xor_tl(temp2, temp, r1_low);
482 tcg_gen_xor_tl(temp3, r1_low, r2);
483 if (op1 == tcg_gen_add_tl) {
484 tcg_gen_andc_tl(temp2, temp2, temp3);
485 } else {
486 tcg_gen_and_tl(temp2, temp2, temp3);
487 }
488
489 (*op2)(temp3, r1_high, r3);
490 /* calc V1 bit */
491 tcg_gen_xor_tl(cpu_PSW_V, temp3, r1_high);
492 tcg_gen_xor_tl(temp4, r1_high, r3);
493 if (op2 == tcg_gen_add_tl) {
494 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, temp4);
495 } else {
496 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp4);
497 }
498 /* combine V0/V1 bits */
499 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp2);
500 /* calc sv bit */
501 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
502 /* write result */
503 tcg_gen_mov_tl(ret_low, temp);
504 tcg_gen_mov_tl(ret_high, temp3);
505 /* calc AV bit */
506 tcg_gen_add_tl(temp, ret_low, ret_low);
507 tcg_gen_xor_tl(temp, temp, ret_low);
508 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
509 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, ret_high);
510 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
511 /* calc SAV bit */
512 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
513
514 tcg_temp_free(temp);
515 tcg_temp_free(temp2);
516 tcg_temp_free(temp3);
517 tcg_temp_free(temp4);
518 }
519
520 /* ret = r2 + (r1 * r3); */
521 static inline void gen_madd32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
522 {
523 TCGv_i64 t1 = tcg_temp_new_i64();
524 TCGv_i64 t2 = tcg_temp_new_i64();
525 TCGv_i64 t3 = tcg_temp_new_i64();
526
527 tcg_gen_ext_i32_i64(t1, r1);
528 tcg_gen_ext_i32_i64(t2, r2);
529 tcg_gen_ext_i32_i64(t3, r3);
530
531 tcg_gen_mul_i64(t1, t1, t3);
532 tcg_gen_add_i64(t1, t2, t1);
533
534 tcg_gen_trunc_i64_i32(ret, t1);
535 /* calc V
536 t1 > 0x7fffffff */
537 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
538 /* t1 < -0x80000000 */
539 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
540 tcg_gen_or_i64(t2, t2, t3);
541 tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
542 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
543 /* Calc SV bit */
544 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
545 /* Calc AV/SAV bits */
546 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
547 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
548 /* calc SAV */
549 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
550
551 tcg_temp_free_i64(t1);
552 tcg_temp_free_i64(t2);
553 tcg_temp_free_i64(t3);
554 }
555
556 static inline void gen_maddi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
557 {
558 TCGv temp = tcg_const_i32(con);
559 gen_madd32_d(ret, r1, r2, temp);
560 tcg_temp_free(temp);
561 }
562
563 static inline void
564 gen_madd64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
565 TCGv r3)
566 {
567 TCGv t1 = tcg_temp_new();
568 TCGv t2 = tcg_temp_new();
569 TCGv t3 = tcg_temp_new();
570 TCGv t4 = tcg_temp_new();
571
572 tcg_gen_muls2_tl(t1, t2, r1, r3);
573 /* only the add can overflow */
574 tcg_gen_add2_tl(t3, t4, r2_low, r2_high, t1, t2);
575 /* calc V bit */
576 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
577 tcg_gen_xor_tl(t1, r2_high, t2);
578 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t1);
579 /* Calc SV bit */
580 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
581 /* Calc AV/SAV bits */
582 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
583 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
584 /* calc SAV */
585 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
586 /* write back the result */
587 tcg_gen_mov_tl(ret_low, t3);
588 tcg_gen_mov_tl(ret_high, t4);
589
590 tcg_temp_free(t1);
591 tcg_temp_free(t2);
592 tcg_temp_free(t3);
593 tcg_temp_free(t4);
594 }
595
596 static inline void
597 gen_maddu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
598 TCGv r3)
599 {
600 TCGv_i64 t1 = tcg_temp_new_i64();
601 TCGv_i64 t2 = tcg_temp_new_i64();
602 TCGv_i64 t3 = tcg_temp_new_i64();
603
604 tcg_gen_extu_i32_i64(t1, r1);
605 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
606 tcg_gen_extu_i32_i64(t3, r3);
607
608 tcg_gen_mul_i64(t1, t1, t3);
609 tcg_gen_add_i64(t2, t2, t1);
610 /* write back result */
611 tcg_gen_extr_i64_i32(ret_low, ret_high, t2);
612 /* only the add overflows, if t2 < t1
613 calc V bit */
614 tcg_gen_setcond_i64(TCG_COND_LTU, t2, t2, t1);
615 tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
616 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
617 /* Calc SV bit */
618 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
619 /* Calc AV/SAV bits */
620 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
621 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
622 /* calc SAV */
623 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
624
625 tcg_temp_free_i64(t1);
626 tcg_temp_free_i64(t2);
627 tcg_temp_free_i64(t3);
628 }
629
630 static inline void
631 gen_maddi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
632 int32_t con)
633 {
634 TCGv temp = tcg_const_i32(con);
635 gen_madd64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
636 tcg_temp_free(temp);
637 }
638
639 static inline void
640 gen_maddui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
641 int32_t con)
642 {
643 TCGv temp = tcg_const_i32(con);
644 gen_maddu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
645 tcg_temp_free(temp);
646 }
647
648 static inline void
649 gen_madd_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
650 TCGv r3, uint32_t n, uint32_t mode)
651 {
652 TCGv temp = tcg_const_i32(n);
653 TCGv temp2 = tcg_temp_new();
654 TCGv_i64 temp64 = tcg_temp_new_i64();
655 switch (mode) {
656 case MODE_LL:
657 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
658 break;
659 case MODE_LU:
660 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
661 break;
662 case MODE_UL:
663 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
664 break;
665 case MODE_UU:
666 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
667 break;
668 }
669 tcg_gen_extr_i64_i32(temp, temp2, temp64);
670 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
671 tcg_gen_add_tl, tcg_gen_add_tl);
672 tcg_temp_free(temp);
673 tcg_temp_free(temp2);
674 tcg_temp_free_i64(temp64);
675 }
676
677 static inline void
678 gen_maddsu_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
679 TCGv r3, uint32_t n, uint32_t mode)
680 {
681 TCGv temp = tcg_const_i32(n);
682 TCGv temp2 = tcg_temp_new();
683 TCGv_i64 temp64 = tcg_temp_new_i64();
684 switch (mode) {
685 case MODE_LL:
686 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
687 break;
688 case MODE_LU:
689 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
690 break;
691 case MODE_UL:
692 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
693 break;
694 case MODE_UU:
695 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
696 break;
697 }
698 tcg_gen_extr_i64_i32(temp, temp2, temp64);
699 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
700 tcg_gen_sub_tl, tcg_gen_add_tl);
701 tcg_temp_free(temp);
702 tcg_temp_free(temp2);
703 tcg_temp_free_i64(temp64);
704 }
705
706 static inline void
707 gen_maddsum_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
708 TCGv r3, uint32_t n, uint32_t mode)
709 {
710 TCGv temp = tcg_const_i32(n);
711 TCGv_i64 temp64 = tcg_temp_new_i64();
712 TCGv_i64 temp64_2 = tcg_temp_new_i64();
713 TCGv_i64 temp64_3 = tcg_temp_new_i64();
714 switch (mode) {
715 case MODE_LL:
716 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
717 break;
718 case MODE_LU:
719 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
720 break;
721 case MODE_UL:
722 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
723 break;
724 case MODE_UU:
725 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
726 break;
727 }
728 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
729 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
730 tcg_gen_ext32s_i64(temp64, temp64); /* low */
731 tcg_gen_sub_i64(temp64, temp64_2, temp64);
732 tcg_gen_shli_i64(temp64, temp64, 16);
733
734 gen_add64_d(temp64_2, temp64_3, temp64);
735 /* write back result */
736 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
737
738 tcg_temp_free(temp);
739 tcg_temp_free_i64(temp64);
740 tcg_temp_free_i64(temp64_2);
741 tcg_temp_free_i64(temp64_3);
742 }
743
744 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2);
745
746 static inline void
747 gen_madds_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
748 TCGv r3, uint32_t n, uint32_t mode)
749 {
750 TCGv temp = tcg_const_i32(n);
751 TCGv temp2 = tcg_temp_new();
752 TCGv temp3 = tcg_temp_new();
753 TCGv_i64 temp64 = tcg_temp_new_i64();
754
755 switch (mode) {
756 case MODE_LL:
757 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
758 break;
759 case MODE_LU:
760 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
761 break;
762 case MODE_UL:
763 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
764 break;
765 case MODE_UU:
766 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
767 break;
768 }
769 tcg_gen_extr_i64_i32(temp, temp2, temp64);
770 gen_adds(ret_low, r1_low, temp);
771 tcg_gen_mov_tl(temp, cpu_PSW_V);
772 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
773 gen_adds(ret_high, r1_high, temp2);
774 /* combine v bits */
775 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
776 /* combine av bits */
777 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
778
779 tcg_temp_free(temp);
780 tcg_temp_free(temp2);
781 tcg_temp_free(temp3);
782 tcg_temp_free_i64(temp64);
783
784 }
785
786 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2);
787
788 static inline void
789 gen_maddsus_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
790 TCGv r3, uint32_t n, uint32_t mode)
791 {
792 TCGv temp = tcg_const_i32(n);
793 TCGv temp2 = tcg_temp_new();
794 TCGv temp3 = tcg_temp_new();
795 TCGv_i64 temp64 = tcg_temp_new_i64();
796
797 switch (mode) {
798 case MODE_LL:
799 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
800 break;
801 case MODE_LU:
802 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
803 break;
804 case MODE_UL:
805 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
806 break;
807 case MODE_UU:
808 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
809 break;
810 }
811 tcg_gen_extr_i64_i32(temp, temp2, temp64);
812 gen_subs(ret_low, r1_low, temp);
813 tcg_gen_mov_tl(temp, cpu_PSW_V);
814 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
815 gen_adds(ret_high, r1_high, temp2);
816 /* combine v bits */
817 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
818 /* combine av bits */
819 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
820
821 tcg_temp_free(temp);
822 tcg_temp_free(temp2);
823 tcg_temp_free(temp3);
824 tcg_temp_free_i64(temp64);
825
826 }
827
828 static inline void
829 gen_maddsums_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
830 TCGv r3, uint32_t n, uint32_t mode)
831 {
832 TCGv temp = tcg_const_i32(n);
833 TCGv_i64 temp64 = tcg_temp_new_i64();
834 TCGv_i64 temp64_2 = tcg_temp_new_i64();
835
836 switch (mode) {
837 case MODE_LL:
838 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
839 break;
840 case MODE_LU:
841 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
842 break;
843 case MODE_UL:
844 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
845 break;
846 case MODE_UU:
847 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
848 break;
849 }
850 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
851 tcg_gen_ext32s_i64(temp64, temp64); /* low */
852 tcg_gen_sub_i64(temp64, temp64_2, temp64);
853 tcg_gen_shli_i64(temp64, temp64, 16);
854 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
855
856 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
857 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
858
859 tcg_temp_free(temp);
860 tcg_temp_free_i64(temp64);
861 tcg_temp_free_i64(temp64_2);
862 }
863
864
865 static inline void
866 gen_maddm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
867 TCGv r3, uint32_t n, uint32_t mode)
868 {
869 TCGv temp = tcg_const_i32(n);
870 TCGv_i64 temp64 = tcg_temp_new_i64();
871 TCGv_i64 temp64_2 = tcg_temp_new_i64();
872 TCGv_i64 temp64_3 = tcg_temp_new_i64();
873 switch (mode) {
874 case MODE_LL:
875 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
876 break;
877 case MODE_LU:
878 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
879 break;
880 case MODE_UL:
881 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
882 break;
883 case MODE_UU:
884 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
885 break;
886 }
887 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
888 gen_add64_d(temp64_3, temp64_2, temp64);
889 /* write back result */
890 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
891
892 tcg_temp_free(temp);
893 tcg_temp_free_i64(temp64);
894 tcg_temp_free_i64(temp64_2);
895 tcg_temp_free_i64(temp64_3);
896 }
897
898 static inline void
899 gen_maddms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
900 TCGv r3, uint32_t n, uint32_t mode)
901 {
902 TCGv temp = tcg_const_i32(n);
903 TCGv_i64 temp64 = tcg_temp_new_i64();
904 TCGv_i64 temp64_2 = tcg_temp_new_i64();
905 switch (mode) {
906 case MODE_LL:
907 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
908 break;
909 case MODE_LU:
910 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
911 break;
912 case MODE_UL:
913 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
914 break;
915 case MODE_UU:
916 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
917 break;
918 }
919 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
920 gen_helper_add64_ssov(temp64, cpu_env, temp64_2, temp64);
921 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
922
923 tcg_temp_free(temp);
924 tcg_temp_free_i64(temp64);
925 tcg_temp_free_i64(temp64_2);
926 }
927
928 static inline void
929 gen_maddr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
930 uint32_t mode)
931 {
932 TCGv temp = tcg_const_i32(n);
933 TCGv_i64 temp64 = tcg_temp_new_i64();
934 switch (mode) {
935 case MODE_LL:
936 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
937 break;
938 case MODE_LU:
939 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
940 break;
941 case MODE_UL:
942 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
943 break;
944 case MODE_UU:
945 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
946 break;
947 }
948 gen_helper_addr_h(ret, cpu_env, temp64, r1_low, r1_high);
949
950 tcg_temp_free(temp);
951 tcg_temp_free_i64(temp64);
952 }
953
954 static inline void
955 gen_maddr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
956 {
957 TCGv temp = tcg_temp_new();
958 TCGv temp2 = tcg_temp_new();
959
960 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
961 tcg_gen_shli_tl(temp, r1, 16);
962 gen_maddr64_h(ret, temp, temp2, r2, r3, n, mode);
963
964 tcg_temp_free(temp);
965 tcg_temp_free(temp2);
966 }
967
968 static inline void
969 gen_maddsur32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
970 {
971 TCGv temp = tcg_const_i32(n);
972 TCGv temp2 = tcg_temp_new();
973 TCGv_i64 temp64 = tcg_temp_new_i64();
974 switch (mode) {
975 case MODE_LL:
976 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
977 break;
978 case MODE_LU:
979 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
980 break;
981 case MODE_UL:
982 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
983 break;
984 case MODE_UU:
985 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
986 break;
987 }
988 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
989 tcg_gen_shli_tl(temp, r1, 16);
990 gen_helper_addsur_h(ret, cpu_env, temp64, temp, temp2);
991
992 tcg_temp_free(temp);
993 tcg_temp_free(temp2);
994 tcg_temp_free_i64(temp64);
995 }
996
997
998 static inline void
999 gen_maddr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1000 uint32_t n, uint32_t mode)
1001 {
1002 TCGv temp = tcg_const_i32(n);
1003 TCGv_i64 temp64 = tcg_temp_new_i64();
1004 switch (mode) {
1005 case MODE_LL:
1006 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1007 break;
1008 case MODE_LU:
1009 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1010 break;
1011 case MODE_UL:
1012 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1013 break;
1014 case MODE_UU:
1015 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1016 break;
1017 }
1018 gen_helper_addr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1019
1020 tcg_temp_free(temp);
1021 tcg_temp_free_i64(temp64);
1022 }
1023
1024 static inline void
1025 gen_maddr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1026 {
1027 TCGv temp = tcg_temp_new();
1028 TCGv temp2 = tcg_temp_new();
1029
1030 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1031 tcg_gen_shli_tl(temp, r1, 16);
1032 gen_maddr64s_h(ret, temp, temp2, r2, r3, n, mode);
1033
1034 tcg_temp_free(temp);
1035 tcg_temp_free(temp2);
1036 }
1037
1038 static inline void
1039 gen_maddsur32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1040 {
1041 TCGv temp = tcg_const_i32(n);
1042 TCGv temp2 = tcg_temp_new();
1043 TCGv_i64 temp64 = tcg_temp_new_i64();
1044 switch (mode) {
1045 case MODE_LL:
1046 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1047 break;
1048 case MODE_LU:
1049 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1050 break;
1051 case MODE_UL:
1052 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1053 break;
1054 case MODE_UU:
1055 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1056 break;
1057 }
1058 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1059 tcg_gen_shli_tl(temp, r1, 16);
1060 gen_helper_addsur_h_ssov(ret, cpu_env, temp64, temp, temp2);
1061
1062 tcg_temp_free(temp);
1063 tcg_temp_free(temp2);
1064 tcg_temp_free_i64(temp64);
1065 }
1066
1067 static inline void
1068 gen_maddr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1069 {
1070 TCGv temp = tcg_const_i32(n);
1071 gen_helper_maddr_q(ret, cpu_env, r1, r2, r3, temp);
1072 tcg_temp_free(temp);
1073 }
1074
1075 static inline void
1076 gen_maddrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1077 {
1078 TCGv temp = tcg_const_i32(n);
1079 gen_helper_maddr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1080 tcg_temp_free(temp);
1081 }
1082
1083 static inline void
1084 gen_madd32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1085 uint32_t up_shift, CPUTriCoreState *env)
1086 {
1087 TCGv temp = tcg_temp_new();
1088 TCGv temp2 = tcg_temp_new();
1089 TCGv temp3 = tcg_temp_new();
1090 TCGv_i64 t1 = tcg_temp_new_i64();
1091 TCGv_i64 t2 = tcg_temp_new_i64();
1092 TCGv_i64 t3 = tcg_temp_new_i64();
1093
1094 tcg_gen_ext_i32_i64(t2, arg2);
1095 tcg_gen_ext_i32_i64(t3, arg3);
1096
1097 tcg_gen_mul_i64(t2, t2, t3);
1098 tcg_gen_shli_i64(t2, t2, n);
1099
1100 tcg_gen_ext_i32_i64(t1, arg1);
1101 tcg_gen_sari_i64(t2, t2, up_shift);
1102
1103 tcg_gen_add_i64(t3, t1, t2);
1104 tcg_gen_trunc_i64_i32(temp3, t3);
1105 /* calc v bit */
1106 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1107 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1108 tcg_gen_or_i64(t1, t1, t2);
1109 tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
1110 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1111 /* We produce an overflow on the host if the mul before was
1112 (0x80000000 * 0x80000000) << 1). If this is the
1113 case, we negate the ovf. */
1114 if (n == 1) {
1115 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1116 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1117 tcg_gen_and_tl(temp, temp, temp2);
1118 tcg_gen_shli_tl(temp, temp, 31);
1119 /* negate v bit, if special condition */
1120 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1121 }
1122 /* Calc SV bit */
1123 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1124 /* Calc AV/SAV bits */
1125 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1126 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1127 /* calc SAV */
1128 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1129 /* write back result */
1130 tcg_gen_mov_tl(ret, temp3);
1131
1132 tcg_temp_free(temp);
1133 tcg_temp_free(temp2);
1134 tcg_temp_free(temp3);
1135 tcg_temp_free_i64(t1);
1136 tcg_temp_free_i64(t2);
1137 tcg_temp_free_i64(t3);
1138 }
1139
1140 static inline void
1141 gen_m16add32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1142 {
1143 TCGv temp = tcg_temp_new();
1144 TCGv temp2 = tcg_temp_new();
1145 if (n == 0) {
1146 tcg_gen_mul_tl(temp, arg2, arg3);
1147 } else { /* n is expected to be 1 */
1148 tcg_gen_mul_tl(temp, arg2, arg3);
1149 tcg_gen_shli_tl(temp, temp, 1);
1150 /* catch special case r1 = r2 = 0x8000 */
1151 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1152 tcg_gen_sub_tl(temp, temp, temp2);
1153 }
1154 gen_add_d(ret, arg1, temp);
1155
1156 tcg_temp_free(temp);
1157 tcg_temp_free(temp2);
1158 }
1159
1160 static inline void
1161 gen_m16adds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
1162 {
1163 TCGv temp = tcg_temp_new();
1164 TCGv temp2 = tcg_temp_new();
1165 if (n == 0) {
1166 tcg_gen_mul_tl(temp, arg2, arg3);
1167 } else { /* n is expected to be 1 */
1168 tcg_gen_mul_tl(temp, arg2, arg3);
1169 tcg_gen_shli_tl(temp, temp, 1);
1170 /* catch special case r1 = r2 = 0x8000 */
1171 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1172 tcg_gen_sub_tl(temp, temp, temp2);
1173 }
1174 gen_adds(ret, arg1, temp);
1175
1176 tcg_temp_free(temp);
1177 tcg_temp_free(temp2);
1178 }
1179
1180 static inline void
1181 gen_m16add64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1182 TCGv arg3, uint32_t n)
1183 {
1184 TCGv temp = tcg_temp_new();
1185 TCGv temp2 = tcg_temp_new();
1186 TCGv_i64 t1 = tcg_temp_new_i64();
1187 TCGv_i64 t2 = tcg_temp_new_i64();
1188 TCGv_i64 t3 = tcg_temp_new_i64();
1189
1190 if (n == 0) {
1191 tcg_gen_mul_tl(temp, arg2, arg3);
1192 } else { /* n is expected to be 1 */
1193 tcg_gen_mul_tl(temp, arg2, arg3);
1194 tcg_gen_shli_tl(temp, temp, 1);
1195 /* catch special case r1 = r2 = 0x8000 */
1196 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1197 tcg_gen_sub_tl(temp, temp, temp2);
1198 }
1199 tcg_gen_ext_i32_i64(t2, temp);
1200 tcg_gen_shli_i64(t2, t2, 16);
1201 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1202 gen_add64_d(t3, t1, t2);
1203 /* write back result */
1204 tcg_gen_extr_i64_i32(rl, rh, t3);
1205
1206 tcg_temp_free_i64(t1);
1207 tcg_temp_free_i64(t2);
1208 tcg_temp_free_i64(t3);
1209 tcg_temp_free(temp);
1210 tcg_temp_free(temp2);
1211 }
1212
1213 static inline void
1214 gen_m16adds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1215 TCGv arg3, uint32_t n)
1216 {
1217 TCGv temp = tcg_temp_new();
1218 TCGv temp2 = tcg_temp_new();
1219 TCGv_i64 t1 = tcg_temp_new_i64();
1220 TCGv_i64 t2 = tcg_temp_new_i64();
1221
1222 if (n == 0) {
1223 tcg_gen_mul_tl(temp, arg2, arg3);
1224 } else { /* n is expected to be 1 */
1225 tcg_gen_mul_tl(temp, arg2, arg3);
1226 tcg_gen_shli_tl(temp, temp, 1);
1227 /* catch special case r1 = r2 = 0x8000 */
1228 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
1229 tcg_gen_sub_tl(temp, temp, temp2);
1230 }
1231 tcg_gen_ext_i32_i64(t2, temp);
1232 tcg_gen_shli_i64(t2, t2, 16);
1233 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1234
1235 gen_helper_add64_ssov(t1, cpu_env, t1, t2);
1236 tcg_gen_extr_i64_i32(rl, rh, t1);
1237
1238 tcg_temp_free(temp);
1239 tcg_temp_free(temp2);
1240 tcg_temp_free_i64(t1);
1241 tcg_temp_free_i64(t2);
1242 }
1243
1244 static inline void
1245 gen_madd64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1246 TCGv arg3, uint32_t n, CPUTriCoreState *env)
1247 {
1248 TCGv_i64 t1 = tcg_temp_new_i64();
1249 TCGv_i64 t2 = tcg_temp_new_i64();
1250 TCGv_i64 t3 = tcg_temp_new_i64();
1251 TCGv_i64 t4 = tcg_temp_new_i64();
1252 TCGv temp, temp2;
1253
1254 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
1255 tcg_gen_ext_i32_i64(t2, arg2);
1256 tcg_gen_ext_i32_i64(t3, arg3);
1257
1258 tcg_gen_mul_i64(t2, t2, t3);
1259 if (n != 0) {
1260 tcg_gen_shli_i64(t2, t2, 1);
1261 }
1262 tcg_gen_add_i64(t4, t1, t2);
1263 /* calc v bit */
1264 tcg_gen_xor_i64(t3, t4, t1);
1265 tcg_gen_xor_i64(t2, t1, t2);
1266 tcg_gen_andc_i64(t3, t3, t2);
1267 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t3, 32);
1268 /* We produce an overflow on the host if the mul before was
1269 (0x80000000 * 0x80000000) << 1). If this is the
1270 case, we negate the ovf. */
1271 if (n == 1) {
1272 temp = tcg_temp_new();
1273 temp2 = tcg_temp_new();
1274 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1275 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1276 tcg_gen_and_tl(temp, temp, temp2);
1277 tcg_gen_shli_tl(temp, temp, 31);
1278 /* negate v bit, if special condition */
1279 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1280
1281 tcg_temp_free(temp);
1282 tcg_temp_free(temp2);
1283 }
1284 /* write back result */
1285 tcg_gen_extr_i64_i32(rl, rh, t4);
1286 /* Calc SV bit */
1287 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1288 /* Calc AV/SAV bits */
1289 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
1290 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
1291 /* calc SAV */
1292 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1293
1294 tcg_temp_free_i64(t1);
1295 tcg_temp_free_i64(t2);
1296 tcg_temp_free_i64(t3);
1297 tcg_temp_free_i64(t4);
1298 }
1299
1300 static inline void
1301 gen_madds32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1302 uint32_t up_shift)
1303 {
1304 TCGv_i64 t1 = tcg_temp_new_i64();
1305 TCGv_i64 t2 = tcg_temp_new_i64();
1306 TCGv_i64 t3 = tcg_temp_new_i64();
1307
1308 tcg_gen_ext_i32_i64(t1, arg1);
1309 tcg_gen_ext_i32_i64(t2, arg2);
1310 tcg_gen_ext_i32_i64(t3, arg3);
1311
1312 tcg_gen_mul_i64(t2, t2, t3);
1313 tcg_gen_sari_i64(t2, t2, up_shift - n);
1314
1315 gen_helper_madd32_q_add_ssov(ret, cpu_env, t1, t2);
1316
1317 tcg_temp_free_i64(t1);
1318 tcg_temp_free_i64(t2);
1319 tcg_temp_free_i64(t3);
1320 }
1321
1322 static inline void
1323 gen_madds64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
1324 TCGv arg3, uint32_t n)
1325 {
1326 TCGv_i64 r1 = tcg_temp_new_i64();
1327 TCGv temp = tcg_const_i32(n);
1328
1329 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
1330 gen_helper_madd64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
1331 tcg_gen_extr_i64_i32(rl, rh, r1);
1332
1333 tcg_temp_free_i64(r1);
1334 tcg_temp_free(temp);
1335 }
1336 /* ret = r2 - (r1 * r3); */
1337 static inline void gen_msub32_d(TCGv ret, TCGv r1, TCGv r2, TCGv r3)
1338 {
1339 TCGv_i64 t1 = tcg_temp_new_i64();
1340 TCGv_i64 t2 = tcg_temp_new_i64();
1341 TCGv_i64 t3 = tcg_temp_new_i64();
1342
1343 tcg_gen_ext_i32_i64(t1, r1);
1344 tcg_gen_ext_i32_i64(t2, r2);
1345 tcg_gen_ext_i32_i64(t3, r3);
1346
1347 tcg_gen_mul_i64(t1, t1, t3);
1348 tcg_gen_sub_i64(t1, t2, t1);
1349
1350 tcg_gen_trunc_i64_i32(ret, t1);
1351 /* calc V
1352 t2 > 0x7fffffff */
1353 tcg_gen_setcondi_i64(TCG_COND_GT, t3, t1, 0x7fffffffLL);
1354 /* result < -0x80000000 */
1355 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t1, -0x80000000LL);
1356 tcg_gen_or_i64(t2, t2, t3);
1357 tcg_gen_trunc_i64_i32(cpu_PSW_V, t2);
1358 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1359
1360 /* Calc SV bit */
1361 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1362 /* Calc AV/SAV bits */
1363 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
1364 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
1365 /* calc SAV */
1366 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1367
1368 tcg_temp_free_i64(t1);
1369 tcg_temp_free_i64(t2);
1370 tcg_temp_free_i64(t3);
1371 }
1372
1373 static inline void gen_msubi32_d(TCGv ret, TCGv r1, TCGv r2, int32_t con)
1374 {
1375 TCGv temp = tcg_const_i32(con);
1376 gen_msub32_d(ret, r1, r2, temp);
1377 tcg_temp_free(temp);
1378 }
1379
1380 static inline void
1381 gen_msub64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1382 TCGv r3)
1383 {
1384 TCGv t1 = tcg_temp_new();
1385 TCGv t2 = tcg_temp_new();
1386 TCGv t3 = tcg_temp_new();
1387 TCGv t4 = tcg_temp_new();
1388
1389 tcg_gen_muls2_tl(t1, t2, r1, r3);
1390 /* only the sub can overflow */
1391 tcg_gen_sub2_tl(t3, t4, r2_low, r2_high, t1, t2);
1392 /* calc V bit */
1393 tcg_gen_xor_tl(cpu_PSW_V, t4, r2_high);
1394 tcg_gen_xor_tl(t1, r2_high, t2);
1395 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, t1);
1396 /* Calc SV bit */
1397 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1398 /* Calc AV/SAV bits */
1399 tcg_gen_add_tl(cpu_PSW_AV, t4, t4);
1400 tcg_gen_xor_tl(cpu_PSW_AV, t4, cpu_PSW_AV);
1401 /* calc SAV */
1402 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1403 /* write back the result */
1404 tcg_gen_mov_tl(ret_low, t3);
1405 tcg_gen_mov_tl(ret_high, t4);
1406
1407 tcg_temp_free(t1);
1408 tcg_temp_free(t2);
1409 tcg_temp_free(t3);
1410 tcg_temp_free(t4);
1411 }
1412
1413 static inline void
1414 gen_msubi64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1415 int32_t con)
1416 {
1417 TCGv temp = tcg_const_i32(con);
1418 gen_msub64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1419 tcg_temp_free(temp);
1420 }
1421
1422 static inline void
1423 gen_msubu64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1424 TCGv r3)
1425 {
1426 TCGv_i64 t1 = tcg_temp_new_i64();
1427 TCGv_i64 t2 = tcg_temp_new_i64();
1428 TCGv_i64 t3 = tcg_temp_new_i64();
1429
1430 tcg_gen_extu_i32_i64(t1, r1);
1431 tcg_gen_concat_i32_i64(t2, r2_low, r2_high);
1432 tcg_gen_extu_i32_i64(t3, r3);
1433
1434 tcg_gen_mul_i64(t1, t1, t3);
1435 tcg_gen_sub_i64(t3, t2, t1);
1436 tcg_gen_extr_i64_i32(ret_low, ret_high, t3);
1437 /* calc V bit, only the sub can overflow, if t1 > t2 */
1438 tcg_gen_setcond_i64(TCG_COND_GTU, t1, t1, t2);
1439 tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
1440 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1441 /* Calc SV bit */
1442 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1443 /* Calc AV/SAV bits */
1444 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
1445 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
1446 /* calc SAV */
1447 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1448
1449 tcg_temp_free_i64(t1);
1450 tcg_temp_free_i64(t2);
1451 tcg_temp_free_i64(t3);
1452 }
1453
1454 static inline void
1455 gen_msubui64_d(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
1456 int32_t con)
1457 {
1458 TCGv temp = tcg_const_i32(con);
1459 gen_msubu64_d(ret_low, ret_high, r1, r2_low, r2_high, temp);
1460 tcg_temp_free(temp);
1461 }
1462
1463 static inline void gen_addi_d(TCGv ret, TCGv r1, target_ulong r2)
1464 {
1465 TCGv temp = tcg_const_i32(r2);
1466 gen_add_d(ret, r1, temp);
1467 tcg_temp_free(temp);
1468 }
1469 /* calculate the carry bit too */
1470 static inline void gen_add_CC(TCGv ret, TCGv r1, TCGv r2)
1471 {
1472 TCGv t0 = tcg_temp_new_i32();
1473 TCGv result = tcg_temp_new_i32();
1474
1475 tcg_gen_movi_tl(t0, 0);
1476 /* Addition and set C/V/SV bits */
1477 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, r2, t0);
1478 /* calc V bit */
1479 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1480 tcg_gen_xor_tl(t0, r1, r2);
1481 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1482 /* Calc SV bit */
1483 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1484 /* Calc AV/SAV bits */
1485 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1486 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1487 /* calc SAV */
1488 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1489 /* write back result */
1490 tcg_gen_mov_tl(ret, result);
1491
1492 tcg_temp_free(result);
1493 tcg_temp_free(t0);
1494 }
1495
1496 static inline void gen_addi_CC(TCGv ret, TCGv r1, int32_t con)
1497 {
1498 TCGv temp = tcg_const_i32(con);
1499 gen_add_CC(ret, r1, temp);
1500 tcg_temp_free(temp);
1501 }
1502
1503 static inline void gen_addc_CC(TCGv ret, TCGv r1, TCGv r2)
1504 {
1505 TCGv carry = tcg_temp_new_i32();
1506 TCGv t0 = tcg_temp_new_i32();
1507 TCGv result = tcg_temp_new_i32();
1508
1509 tcg_gen_movi_tl(t0, 0);
1510 tcg_gen_setcondi_tl(TCG_COND_NE, carry, cpu_PSW_C, 0);
1511 /* Addition, carry and set C/V/SV bits */
1512 tcg_gen_add2_i32(result, cpu_PSW_C, r1, t0, carry, t0);
1513 tcg_gen_add2_i32(result, cpu_PSW_C, result, cpu_PSW_C, r2, t0);
1514 /* calc V bit */
1515 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1516 tcg_gen_xor_tl(t0, r1, r2);
1517 tcg_gen_andc_tl(cpu_PSW_V, cpu_PSW_V, t0);
1518 /* Calc SV bit */
1519 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1520 /* Calc AV/SAV bits */
1521 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1522 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1523 /* calc SAV */
1524 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1525 /* write back result */
1526 tcg_gen_mov_tl(ret, result);
1527
1528 tcg_temp_free(result);
1529 tcg_temp_free(t0);
1530 tcg_temp_free(carry);
1531 }
1532
1533 static inline void gen_addci_CC(TCGv ret, TCGv r1, int32_t con)
1534 {
1535 TCGv temp = tcg_const_i32(con);
1536 gen_addc_CC(ret, r1, temp);
1537 tcg_temp_free(temp);
1538 }
1539
1540 static inline void gen_cond_add(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1541 TCGv r4)
1542 {
1543 TCGv temp = tcg_temp_new();
1544 TCGv temp2 = tcg_temp_new();
1545 TCGv result = tcg_temp_new();
1546 TCGv mask = tcg_temp_new();
1547 TCGv t0 = tcg_const_i32(0);
1548
1549 /* create mask for sticky bits */
1550 tcg_gen_setcond_tl(cond, mask, r4, t0);
1551 tcg_gen_shli_tl(mask, mask, 31);
1552
1553 tcg_gen_add_tl(result, r1, r2);
1554 /* Calc PSW_V */
1555 tcg_gen_xor_tl(temp, result, r1);
1556 tcg_gen_xor_tl(temp2, r1, r2);
1557 tcg_gen_andc_tl(temp, temp, temp2);
1558 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1559 /* Set PSW_SV */
1560 tcg_gen_and_tl(temp, temp, mask);
1561 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1562 /* calc AV bit */
1563 tcg_gen_add_tl(temp, result, result);
1564 tcg_gen_xor_tl(temp, temp, result);
1565 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1566 /* calc SAV bit */
1567 tcg_gen_and_tl(temp, temp, mask);
1568 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1569 /* write back result */
1570 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1571
1572 tcg_temp_free(t0);
1573 tcg_temp_free(temp);
1574 tcg_temp_free(temp2);
1575 tcg_temp_free(result);
1576 tcg_temp_free(mask);
1577 }
1578
1579 static inline void gen_condi_add(TCGCond cond, TCGv r1, int32_t r2,
1580 TCGv r3, TCGv r4)
1581 {
1582 TCGv temp = tcg_const_i32(r2);
1583 gen_cond_add(cond, r1, temp, r3, r4);
1584 tcg_temp_free(temp);
1585 }
1586
1587 static inline void gen_sub_d(TCGv ret, TCGv r1, TCGv r2)
1588 {
1589 TCGv temp = tcg_temp_new_i32();
1590 TCGv result = tcg_temp_new_i32();
1591
1592 tcg_gen_sub_tl(result, r1, r2);
1593 /* calc V bit */
1594 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1595 tcg_gen_xor_tl(temp, r1, r2);
1596 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1597 /* calc SV bit */
1598 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1599 /* Calc AV bit */
1600 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1601 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1602 /* calc SAV bit */
1603 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1604 /* write back result */
1605 tcg_gen_mov_tl(ret, result);
1606
1607 tcg_temp_free(temp);
1608 tcg_temp_free(result);
1609 }
1610
1611 static inline void
1612 gen_sub64_d(TCGv_i64 ret, TCGv_i64 r1, TCGv_i64 r2)
1613 {
1614 TCGv temp = tcg_temp_new();
1615 TCGv_i64 t0 = tcg_temp_new_i64();
1616 TCGv_i64 t1 = tcg_temp_new_i64();
1617 TCGv_i64 result = tcg_temp_new_i64();
1618
1619 tcg_gen_sub_i64(result, r1, r2);
1620 /* calc v bit */
1621 tcg_gen_xor_i64(t1, result, r1);
1622 tcg_gen_xor_i64(t0, r1, r2);
1623 tcg_gen_and_i64(t1, t1, t0);
1624 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t1, 32);
1625 /* calc SV bit */
1626 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1627 /* calc AV/SAV bits */
1628 tcg_gen_trunc_shr_i64_i32(temp, result, 32);
1629 tcg_gen_add_tl(cpu_PSW_AV, temp, temp);
1630 tcg_gen_xor_tl(cpu_PSW_AV, temp, cpu_PSW_AV);
1631 /* calc SAV */
1632 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1633 /* write back result */
1634 tcg_gen_mov_i64(ret, result);
1635
1636 tcg_temp_free(temp);
1637 tcg_temp_free_i64(result);
1638 tcg_temp_free_i64(t0);
1639 tcg_temp_free_i64(t1);
1640 }
1641
1642 static inline void gen_sub_CC(TCGv ret, TCGv r1, TCGv r2)
1643 {
1644 TCGv result = tcg_temp_new();
1645 TCGv temp = tcg_temp_new();
1646
1647 tcg_gen_sub_tl(result, r1, r2);
1648 /* calc C bit */
1649 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_PSW_C, r1, r2);
1650 /* calc V bit */
1651 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
1652 tcg_gen_xor_tl(temp, r1, r2);
1653 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
1654 /* calc SV bit */
1655 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1656 /* Calc AV bit */
1657 tcg_gen_add_tl(cpu_PSW_AV, result, result);
1658 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
1659 /* calc SAV bit */
1660 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1661 /* write back result */
1662 tcg_gen_mov_tl(ret, result);
1663
1664 tcg_temp_free(result);
1665 tcg_temp_free(temp);
1666 }
1667
1668 static inline void gen_subc_CC(TCGv ret, TCGv r1, TCGv r2)
1669 {
1670 TCGv temp = tcg_temp_new();
1671 tcg_gen_not_tl(temp, r2);
1672 gen_addc_CC(ret, r1, temp);
1673 tcg_temp_free(temp);
1674 }
1675
1676 static inline void gen_cond_sub(TCGCond cond, TCGv r1, TCGv r2, TCGv r3,
1677 TCGv r4)
1678 {
1679 TCGv temp = tcg_temp_new();
1680 TCGv temp2 = tcg_temp_new();
1681 TCGv result = tcg_temp_new();
1682 TCGv mask = tcg_temp_new();
1683 TCGv t0 = tcg_const_i32(0);
1684
1685 /* create mask for sticky bits */
1686 tcg_gen_setcond_tl(cond, mask, r4, t0);
1687 tcg_gen_shli_tl(mask, mask, 31);
1688
1689 tcg_gen_sub_tl(result, r1, r2);
1690 /* Calc PSW_V */
1691 tcg_gen_xor_tl(temp, result, r1);
1692 tcg_gen_xor_tl(temp2, r1, r2);
1693 tcg_gen_and_tl(temp, temp, temp2);
1694 tcg_gen_movcond_tl(cond, cpu_PSW_V, r4, t0, temp, cpu_PSW_V);
1695 /* Set PSW_SV */
1696 tcg_gen_and_tl(temp, temp, mask);
1697 tcg_gen_or_tl(cpu_PSW_SV, temp, cpu_PSW_SV);
1698 /* calc AV bit */
1699 tcg_gen_add_tl(temp, result, result);
1700 tcg_gen_xor_tl(temp, temp, result);
1701 tcg_gen_movcond_tl(cond, cpu_PSW_AV, r4, t0, temp, cpu_PSW_AV);
1702 /* calc SAV bit */
1703 tcg_gen_and_tl(temp, temp, mask);
1704 tcg_gen_or_tl(cpu_PSW_SAV, temp, cpu_PSW_SAV);
1705 /* write back result */
1706 tcg_gen_movcond_tl(cond, r3, r4, t0, result, r1);
1707
1708 tcg_temp_free(t0);
1709 tcg_temp_free(temp);
1710 tcg_temp_free(temp2);
1711 tcg_temp_free(result);
1712 tcg_temp_free(mask);
1713 }
1714
1715 static inline void
1716 gen_msub_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1717 TCGv r3, uint32_t n, uint32_t mode)
1718 {
1719 TCGv temp = tcg_const_i32(n);
1720 TCGv temp2 = tcg_temp_new();
1721 TCGv_i64 temp64 = tcg_temp_new_i64();
1722 switch (mode) {
1723 case MODE_LL:
1724 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1725 break;
1726 case MODE_LU:
1727 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1728 break;
1729 case MODE_UL:
1730 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1731 break;
1732 case MODE_UU:
1733 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1734 break;
1735 }
1736 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1737 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
1738 tcg_gen_sub_tl, tcg_gen_sub_tl);
1739 tcg_temp_free(temp);
1740 tcg_temp_free(temp2);
1741 tcg_temp_free_i64(temp64);
1742 }
1743
1744 static inline void
1745 gen_msubs_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1746 TCGv r3, uint32_t n, uint32_t mode)
1747 {
1748 TCGv temp = tcg_const_i32(n);
1749 TCGv temp2 = tcg_temp_new();
1750 TCGv temp3 = tcg_temp_new();
1751 TCGv_i64 temp64 = tcg_temp_new_i64();
1752
1753 switch (mode) {
1754 case MODE_LL:
1755 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1756 break;
1757 case MODE_LU:
1758 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1759 break;
1760 case MODE_UL:
1761 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1762 break;
1763 case MODE_UU:
1764 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1765 break;
1766 }
1767 tcg_gen_extr_i64_i32(temp, temp2, temp64);
1768 gen_subs(ret_low, r1_low, temp);
1769 tcg_gen_mov_tl(temp, cpu_PSW_V);
1770 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
1771 gen_subs(ret_high, r1_high, temp2);
1772 /* combine v bits */
1773 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
1774 /* combine av bits */
1775 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
1776
1777 tcg_temp_free(temp);
1778 tcg_temp_free(temp2);
1779 tcg_temp_free(temp3);
1780 tcg_temp_free_i64(temp64);
1781 }
1782
1783 static inline void
1784 gen_msubm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1785 TCGv r3, uint32_t n, uint32_t mode)
1786 {
1787 TCGv temp = tcg_const_i32(n);
1788 TCGv_i64 temp64 = tcg_temp_new_i64();
1789 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1790 TCGv_i64 temp64_3 = tcg_temp_new_i64();
1791 switch (mode) {
1792 case MODE_LL:
1793 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
1794 break;
1795 case MODE_LU:
1796 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
1797 break;
1798 case MODE_UL:
1799 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
1800 break;
1801 case MODE_UU:
1802 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
1803 break;
1804 }
1805 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1806 gen_sub64_d(temp64_3, temp64_2, temp64);
1807 /* write back result */
1808 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_3);
1809
1810 tcg_temp_free(temp);
1811 tcg_temp_free_i64(temp64);
1812 tcg_temp_free_i64(temp64_2);
1813 tcg_temp_free_i64(temp64_3);
1814 }
1815
1816 static inline void
1817 gen_msubms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
1818 TCGv r3, uint32_t n, uint32_t mode)
1819 {
1820 TCGv temp = tcg_const_i32(n);
1821 TCGv_i64 temp64 = tcg_temp_new_i64();
1822 TCGv_i64 temp64_2 = tcg_temp_new_i64();
1823 switch (mode) {
1824 case MODE_LL:
1825 GEN_HELPER_LL(mulm_h, temp64, r2, r3, temp);
1826 break;
1827 case MODE_LU:
1828 GEN_HELPER_LU(mulm_h, temp64, r2, r3, temp);
1829 break;
1830 case MODE_UL:
1831 GEN_HELPER_UL(mulm_h, temp64, r2, r3, temp);
1832 break;
1833 case MODE_UU:
1834 GEN_HELPER_UU(mulm_h, temp64, r2, r3, temp);
1835 break;
1836 }
1837 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
1838 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
1839 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
1840
1841 tcg_temp_free(temp);
1842 tcg_temp_free_i64(temp64);
1843 tcg_temp_free_i64(temp64_2);
1844 }
1845
1846 static inline void
1847 gen_msubr64_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3, uint32_t n,
1848 uint32_t mode)
1849 {
1850 TCGv temp = tcg_const_i32(n);
1851 TCGv_i64 temp64 = tcg_temp_new_i64();
1852 switch (mode) {
1853 case MODE_LL:
1854 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1855 break;
1856 case MODE_LU:
1857 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1858 break;
1859 case MODE_UL:
1860 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1861 break;
1862 case MODE_UU:
1863 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1864 break;
1865 }
1866 gen_helper_subr_h(ret, cpu_env, temp64, r1_low, r1_high);
1867
1868 tcg_temp_free(temp);
1869 tcg_temp_free_i64(temp64);
1870 }
1871
1872 static inline void
1873 gen_msubr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1874 {
1875 TCGv temp = tcg_temp_new();
1876 TCGv temp2 = tcg_temp_new();
1877
1878 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1879 tcg_gen_shli_tl(temp, r1, 16);
1880 gen_msubr64_h(ret, temp, temp2, r2, r3, n, mode);
1881
1882 tcg_temp_free(temp);
1883 tcg_temp_free(temp2);
1884 }
1885
1886 static inline void
1887 gen_msubr64s_h(TCGv ret, TCGv r1_low, TCGv r1_high, TCGv r2, TCGv r3,
1888 uint32_t n, uint32_t mode)
1889 {
1890 TCGv temp = tcg_const_i32(n);
1891 TCGv_i64 temp64 = tcg_temp_new_i64();
1892 switch (mode) {
1893 case MODE_LL:
1894 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
1895 break;
1896 case MODE_LU:
1897 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
1898 break;
1899 case MODE_UL:
1900 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
1901 break;
1902 case MODE_UU:
1903 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
1904 break;
1905 }
1906 gen_helper_subr_h_ssov(ret, cpu_env, temp64, r1_low, r1_high);
1907
1908 tcg_temp_free(temp);
1909 tcg_temp_free_i64(temp64);
1910 }
1911
1912 static inline void
1913 gen_msubr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
1914 {
1915 TCGv temp = tcg_temp_new();
1916 TCGv temp2 = tcg_temp_new();
1917
1918 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
1919 tcg_gen_shli_tl(temp, r1, 16);
1920 gen_msubr64s_h(ret, temp, temp2, r2, r3, n, mode);
1921
1922 tcg_temp_free(temp);
1923 tcg_temp_free(temp2);
1924 }
1925
1926 static inline void
1927 gen_msubr_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1928 {
1929 TCGv temp = tcg_const_i32(n);
1930 gen_helper_msubr_q(ret, cpu_env, r1, r2, r3, temp);
1931 tcg_temp_free(temp);
1932 }
1933
1934 static inline void
1935 gen_msubrs_q(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n)
1936 {
1937 TCGv temp = tcg_const_i32(n);
1938 gen_helper_msubr_q_ssov(ret, cpu_env, r1, r2, r3, temp);
1939 tcg_temp_free(temp);
1940 }
1941
1942 static inline void
1943 gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
1944 uint32_t up_shift, CPUTriCoreState *env)
1945 {
1946 TCGv temp = tcg_temp_new();
1947 TCGv temp2 = tcg_temp_new();
1948 TCGv temp3 = tcg_temp_new();
1949 TCGv_i64 t1 = tcg_temp_new_i64();
1950 TCGv_i64 t2 = tcg_temp_new_i64();
1951 TCGv_i64 t3 = tcg_temp_new_i64();
1952 TCGv_i64 t4 = tcg_temp_new_i64();
1953
1954 tcg_gen_ext_i32_i64(t2, arg2);
1955 tcg_gen_ext_i32_i64(t3, arg3);
1956
1957 tcg_gen_mul_i64(t2, t2, t3);
1958
1959 tcg_gen_ext_i32_i64(t1, arg1);
1960 /* if we shift part of the fraction out, we need to round up */
1961 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
1962 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
1963 tcg_gen_sari_i64(t2, t2, up_shift - n);
1964 tcg_gen_add_i64(t2, t2, t4);
1965
1966 tcg_gen_sub_i64(t3, t1, t2);
1967 tcg_gen_trunc_i64_i32(temp3, t3);
1968 /* calc v bit */
1969 tcg_gen_setcondi_i64(TCG_COND_GT, t1, t3, 0x7fffffffLL);
1970 tcg_gen_setcondi_i64(TCG_COND_LT, t2, t3, -0x80000000LL);
1971 tcg_gen_or_i64(t1, t1, t2);
1972 tcg_gen_trunc_i64_i32(cpu_PSW_V, t1);
1973 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
1974 /* We produce an overflow on the host if the mul before was
1975 (0x80000000 * 0x80000000) << 1). If this is the
1976 case, we negate the ovf. */
1977 if (n == 1) {
1978 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
1979 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
1980 tcg_gen_and_tl(temp, temp, temp2);
1981 tcg_gen_shli_tl(temp, temp, 31);
1982 /* negate v bit, if special condition */
1983 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
1984 }
1985 /* Calc SV bit */
1986 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
1987 /* Calc AV/SAV bits */
1988 tcg_gen_add_tl(cpu_PSW_AV, temp3, temp3);
1989 tcg_gen_xor_tl(cpu_PSW_AV, temp3, cpu_PSW_AV);
1990 /* calc SAV */
1991 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
1992 /* write back result */
1993 tcg_gen_mov_tl(ret, temp3);
1994
1995 tcg_temp_free(temp);
1996 tcg_temp_free(temp2);
1997 tcg_temp_free(temp3);
1998 tcg_temp_free_i64(t1);
1999 tcg_temp_free_i64(t2);
2000 tcg_temp_free_i64(t3);
2001 tcg_temp_free_i64(t4);
2002 }
2003
2004 static inline void
2005 gen_m16sub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
2006 {
2007 TCGv temp = tcg_temp_new();
2008 TCGv temp2 = tcg_temp_new();
2009 if (n == 0) {
2010 tcg_gen_mul_tl(temp, arg2, arg3);
2011 } else { /* n is expected to be 1 */
2012 tcg_gen_mul_tl(temp, arg2, arg3);
2013 tcg_gen_shli_tl(temp, temp, 1);
2014 /* catch special case r1 = r2 = 0x8000 */
2015 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2016 tcg_gen_sub_tl(temp, temp, temp2);
2017 }
2018 gen_sub_d(ret, arg1, temp);
2019
2020 tcg_temp_free(temp);
2021 tcg_temp_free(temp2);
2022 }
2023
2024 static inline void
2025 gen_m16subs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n)
2026 {
2027 TCGv temp = tcg_temp_new();
2028 TCGv temp2 = tcg_temp_new();
2029 if (n == 0) {
2030 tcg_gen_mul_tl(temp, arg2, arg3);
2031 } else { /* n is expected to be 1 */
2032 tcg_gen_mul_tl(temp, arg2, arg3);
2033 tcg_gen_shli_tl(temp, temp, 1);
2034 /* catch special case r1 = r2 = 0x8000 */
2035 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2036 tcg_gen_sub_tl(temp, temp, temp2);
2037 }
2038 gen_subs(ret, arg1, temp);
2039
2040 tcg_temp_free(temp);
2041 tcg_temp_free(temp2);
2042 }
2043
2044 static inline void
2045 gen_m16sub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2046 TCGv arg3, uint32_t n)
2047 {
2048 TCGv temp = tcg_temp_new();
2049 TCGv temp2 = tcg_temp_new();
2050 TCGv_i64 t1 = tcg_temp_new_i64();
2051 TCGv_i64 t2 = tcg_temp_new_i64();
2052 TCGv_i64 t3 = tcg_temp_new_i64();
2053
2054 if (n == 0) {
2055 tcg_gen_mul_tl(temp, arg2, arg3);
2056 } else { /* n is expected to be 1 */
2057 tcg_gen_mul_tl(temp, arg2, arg3);
2058 tcg_gen_shli_tl(temp, temp, 1);
2059 /* catch special case r1 = r2 = 0x8000 */
2060 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2061 tcg_gen_sub_tl(temp, temp, temp2);
2062 }
2063 tcg_gen_ext_i32_i64(t2, temp);
2064 tcg_gen_shli_i64(t2, t2, 16);
2065 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2066 gen_sub64_d(t3, t1, t2);
2067 /* write back result */
2068 tcg_gen_extr_i64_i32(rl, rh, t3);
2069
2070 tcg_temp_free_i64(t1);
2071 tcg_temp_free_i64(t2);
2072 tcg_temp_free_i64(t3);
2073 tcg_temp_free(temp);
2074 tcg_temp_free(temp2);
2075 }
2076
2077 static inline void
2078 gen_m16subs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2079 TCGv arg3, uint32_t n)
2080 {
2081 TCGv temp = tcg_temp_new();
2082 TCGv temp2 = tcg_temp_new();
2083 TCGv_i64 t1 = tcg_temp_new_i64();
2084 TCGv_i64 t2 = tcg_temp_new_i64();
2085
2086 if (n == 0) {
2087 tcg_gen_mul_tl(temp, arg2, arg3);
2088 } else { /* n is expected to be 1 */
2089 tcg_gen_mul_tl(temp, arg2, arg3);
2090 tcg_gen_shli_tl(temp, temp, 1);
2091 /* catch special case r1 = r2 = 0x8000 */
2092 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, temp, 0x80000000);
2093 tcg_gen_sub_tl(temp, temp, temp2);
2094 }
2095 tcg_gen_ext_i32_i64(t2, temp);
2096 tcg_gen_shli_i64(t2, t2, 16);
2097 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2098
2099 gen_helper_sub64_ssov(t1, cpu_env, t1, t2);
2100 tcg_gen_extr_i64_i32(rl, rh, t1);
2101
2102 tcg_temp_free(temp);
2103 tcg_temp_free(temp2);
2104 tcg_temp_free_i64(t1);
2105 tcg_temp_free_i64(t2);
2106 }
2107
2108 static inline void
2109 gen_msub64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2110 TCGv arg3, uint32_t n, CPUTriCoreState *env)
2111 {
2112 TCGv_i64 t1 = tcg_temp_new_i64();
2113 TCGv_i64 t2 = tcg_temp_new_i64();
2114 TCGv_i64 t3 = tcg_temp_new_i64();
2115 TCGv_i64 t4 = tcg_temp_new_i64();
2116 TCGv temp, temp2;
2117
2118 tcg_gen_concat_i32_i64(t1, arg1_low, arg1_high);
2119 tcg_gen_ext_i32_i64(t2, arg2);
2120 tcg_gen_ext_i32_i64(t3, arg3);
2121
2122 tcg_gen_mul_i64(t2, t2, t3);
2123 if (n != 0) {
2124 tcg_gen_shli_i64(t2, t2, 1);
2125 }
2126 tcg_gen_sub_i64(t4, t1, t2);
2127 /* calc v bit */
2128 tcg_gen_xor_i64(t3, t4, t1);
2129 tcg_gen_xor_i64(t2, t1, t2);
2130 tcg_gen_and_i64(t3, t3, t2);
2131 tcg_gen_trunc_shr_i64_i32(cpu_PSW_V, t3, 32);
2132 /* We produce an overflow on the host if the mul before was
2133 (0x80000000 * 0x80000000) << 1). If this is the
2134 case, we negate the ovf. */
2135 if (n == 1) {
2136 temp = tcg_temp_new();
2137 temp2 = tcg_temp_new();
2138 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000);
2139 tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3);
2140 tcg_gen_and_tl(temp, temp, temp2);
2141 tcg_gen_shli_tl(temp, temp, 31);
2142 /* negate v bit, if special condition */
2143 tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp);
2144
2145 tcg_temp_free(temp);
2146 tcg_temp_free(temp2);
2147 }
2148 /* write back result */
2149 tcg_gen_extr_i64_i32(rl, rh, t4);
2150 /* Calc SV bit */
2151 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2152 /* Calc AV/SAV bits */
2153 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2154 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2155 /* calc SAV */
2156 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2157
2158 tcg_temp_free_i64(t1);
2159 tcg_temp_free_i64(t2);
2160 tcg_temp_free_i64(t3);
2161 tcg_temp_free_i64(t4);
2162 }
2163
2164 static inline void
2165 gen_msubs32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n,
2166 uint32_t up_shift)
2167 {
2168 TCGv_i64 t1 = tcg_temp_new_i64();
2169 TCGv_i64 t2 = tcg_temp_new_i64();
2170 TCGv_i64 t3 = tcg_temp_new_i64();
2171 TCGv_i64 t4 = tcg_temp_new_i64();
2172
2173 tcg_gen_ext_i32_i64(t1, arg1);
2174 tcg_gen_ext_i32_i64(t2, arg2);
2175 tcg_gen_ext_i32_i64(t3, arg3);
2176
2177 tcg_gen_mul_i64(t2, t2, t3);
2178 /* if we shift part of the fraction out, we need to round up */
2179 tcg_gen_andi_i64(t4, t2, (1ll << (up_shift - n)) - 1);
2180 tcg_gen_setcondi_i64(TCG_COND_NE, t4, t4, 0);
2181 tcg_gen_sari_i64(t3, t2, up_shift - n);
2182 tcg_gen_add_i64(t3, t3, t4);
2183
2184 gen_helper_msub32_q_sub_ssov(ret, cpu_env, t1, t3);
2185
2186 tcg_temp_free_i64(t1);
2187 tcg_temp_free_i64(t2);
2188 tcg_temp_free_i64(t3);
2189 tcg_temp_free_i64(t4);
2190 }
2191
2192 static inline void
2193 gen_msubs64_q(TCGv rl, TCGv rh, TCGv arg1_low, TCGv arg1_high, TCGv arg2,
2194 TCGv arg3, uint32_t n)
2195 {
2196 TCGv_i64 r1 = tcg_temp_new_i64();
2197 TCGv temp = tcg_const_i32(n);
2198
2199 tcg_gen_concat_i32_i64(r1, arg1_low, arg1_high);
2200 gen_helper_msub64_q_ssov(r1, cpu_env, r1, arg2, arg3, temp);
2201 tcg_gen_extr_i64_i32(rl, rh, r1);
2202
2203 tcg_temp_free_i64(r1);
2204 tcg_temp_free(temp);
2205 }
2206
2207 static inline void
2208 gen_msubad_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2209 TCGv r3, uint32_t n, uint32_t mode)
2210 {
2211 TCGv temp = tcg_const_i32(n);
2212 TCGv temp2 = tcg_temp_new();
2213 TCGv_i64 temp64 = tcg_temp_new_i64();
2214 switch (mode) {
2215 case MODE_LL:
2216 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2217 break;
2218 case MODE_LU:
2219 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2220 break;
2221 case MODE_UL:
2222 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2223 break;
2224 case MODE_UU:
2225 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2226 break;
2227 }
2228 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2229 gen_addsub64_h(ret_low, ret_high, r1_low, r1_high, temp, temp2,
2230 tcg_gen_add_tl, tcg_gen_sub_tl);
2231 tcg_temp_free(temp);
2232 tcg_temp_free(temp2);
2233 tcg_temp_free_i64(temp64);
2234 }
2235
2236 static inline void
2237 gen_msubadm_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2238 TCGv r3, uint32_t n, uint32_t mode)
2239 {
2240 TCGv temp = tcg_const_i32(n);
2241 TCGv_i64 temp64 = tcg_temp_new_i64();
2242 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2243 TCGv_i64 temp64_3 = tcg_temp_new_i64();
2244 switch (mode) {
2245 case MODE_LL:
2246 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2247 break;
2248 case MODE_LU:
2249 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2250 break;
2251 case MODE_UL:
2252 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2253 break;
2254 case MODE_UU:
2255 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2256 break;
2257 }
2258 tcg_gen_concat_i32_i64(temp64_3, r1_low, r1_high);
2259 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2260 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2261 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2262 tcg_gen_shli_i64(temp64, temp64, 16);
2263
2264 gen_sub64_d(temp64_2, temp64_3, temp64);
2265 /* write back result */
2266 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64_2);
2267
2268 tcg_temp_free(temp);
2269 tcg_temp_free_i64(temp64);
2270 tcg_temp_free_i64(temp64_2);
2271 tcg_temp_free_i64(temp64_3);
2272 }
2273
2274 static inline void
2275 gen_msubadr32_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2276 {
2277 TCGv temp = tcg_const_i32(n);
2278 TCGv temp2 = tcg_temp_new();
2279 TCGv_i64 temp64 = tcg_temp_new_i64();
2280 switch (mode) {
2281 case MODE_LL:
2282 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2283 break;
2284 case MODE_LU:
2285 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2286 break;
2287 case MODE_UL:
2288 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2289 break;
2290 case MODE_UU:
2291 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2292 break;
2293 }
2294 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2295 tcg_gen_shli_tl(temp, r1, 16);
2296 gen_helper_subadr_h(ret, cpu_env, temp64, temp, temp2);
2297
2298 tcg_temp_free(temp);
2299 tcg_temp_free(temp2);
2300 tcg_temp_free_i64(temp64);
2301 }
2302
2303 static inline void
2304 gen_msubads_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2305 TCGv r3, uint32_t n, uint32_t mode)
2306 {
2307 TCGv temp = tcg_const_i32(n);
2308 TCGv temp2 = tcg_temp_new();
2309 TCGv temp3 = tcg_temp_new();
2310 TCGv_i64 temp64 = tcg_temp_new_i64();
2311
2312 switch (mode) {
2313 case MODE_LL:
2314 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2315 break;
2316 case MODE_LU:
2317 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2318 break;
2319 case MODE_UL:
2320 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2321 break;
2322 case MODE_UU:
2323 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2324 break;
2325 }
2326 tcg_gen_extr_i64_i32(temp, temp2, temp64);
2327 gen_adds(ret_low, r1_low, temp);
2328 tcg_gen_mov_tl(temp, cpu_PSW_V);
2329 tcg_gen_mov_tl(temp3, cpu_PSW_AV);
2330 gen_subs(ret_high, r1_high, temp2);
2331 /* combine v bits */
2332 tcg_gen_or_tl(cpu_PSW_V, cpu_PSW_V, temp);
2333 /* combine av bits */
2334 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp3);
2335
2336 tcg_temp_free(temp);
2337 tcg_temp_free(temp2);
2338 tcg_temp_free(temp3);
2339 tcg_temp_free_i64(temp64);
2340 }
2341
2342 static inline void
2343 gen_msubadms_h(TCGv ret_low, TCGv ret_high, TCGv r1_low, TCGv r1_high, TCGv r2,
2344 TCGv r3, uint32_t n, uint32_t mode)
2345 {
2346 TCGv temp = tcg_const_i32(n);
2347 TCGv_i64 temp64 = tcg_temp_new_i64();
2348 TCGv_i64 temp64_2 = tcg_temp_new_i64();
2349
2350 switch (mode) {
2351 case MODE_LL:
2352 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2353 break;
2354 case MODE_LU:
2355 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2356 break;
2357 case MODE_UL:
2358 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2359 break;
2360 case MODE_UU:
2361 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2362 break;
2363 }
2364 tcg_gen_sari_i64(temp64_2, temp64, 32); /* high */
2365 tcg_gen_ext32s_i64(temp64, temp64); /* low */
2366 tcg_gen_sub_i64(temp64, temp64_2, temp64);
2367 tcg_gen_shli_i64(temp64, temp64, 16);
2368 tcg_gen_concat_i32_i64(temp64_2, r1_low, r1_high);
2369
2370 gen_helper_sub64_ssov(temp64, cpu_env, temp64_2, temp64);
2371 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2372
2373 tcg_temp_free(temp);
2374 tcg_temp_free_i64(temp64);
2375 tcg_temp_free_i64(temp64_2);
2376 }
2377
2378 static inline void
2379 gen_msubadr32s_h(TCGv ret, TCGv r1, TCGv r2, TCGv r3, uint32_t n, uint32_t mode)
2380 {
2381 TCGv temp = tcg_const_i32(n);
2382 TCGv temp2 = tcg_temp_new();
2383 TCGv_i64 temp64 = tcg_temp_new_i64();
2384 switch (mode) {
2385 case MODE_LL:
2386 GEN_HELPER_LL(mul_h, temp64, r2, r3, temp);
2387 break;
2388 case MODE_LU:
2389 GEN_HELPER_LU(mul_h, temp64, r2, r3, temp);
2390 break;
2391 case MODE_UL:
2392 GEN_HELPER_UL(mul_h, temp64, r2, r3, temp);
2393 break;
2394 case MODE_UU:
2395 GEN_HELPER_UU(mul_h, temp64, r2, r3, temp);
2396 break;
2397 }
2398 tcg_gen_andi_tl(temp2, r1, 0xffff0000);
2399 tcg_gen_shli_tl(temp, r1, 16);
2400 gen_helper_subadr_h_ssov(ret, cpu_env, temp64, temp, temp2);
2401
2402 tcg_temp_free(temp);
2403 tcg_temp_free(temp2);
2404 tcg_temp_free_i64(temp64);
2405 }
2406
2407 static inline void gen_abs(TCGv ret, TCGv r1)
2408 {
2409 TCGv temp = tcg_temp_new();
2410 TCGv t0 = tcg_const_i32(0);
2411
2412 tcg_gen_neg_tl(temp, r1);
2413 tcg_gen_movcond_tl(TCG_COND_GE, ret, r1, t0, r1, temp);
2414 /* overflow can only happen, if r1 = 0x80000000 */
2415 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, r1, 0x80000000);
2416 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2417 /* calc SV bit */
2418 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2419 /* Calc AV bit */
2420 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2421 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2422 /* calc SAV bit */
2423 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2424
2425 tcg_temp_free(temp);
2426 tcg_temp_free(t0);
2427 }
2428
2429 static inline void gen_absdif(TCGv ret, TCGv r1, TCGv r2)
2430 {
2431 TCGv temp = tcg_temp_new_i32();
2432 TCGv result = tcg_temp_new_i32();
2433
2434 tcg_gen_sub_tl(result, r1, r2);
2435 tcg_gen_sub_tl(temp, r2, r1);
2436 tcg_gen_movcond_tl(TCG_COND_GT, result, r1, r2, result, temp);
2437
2438 /* calc V bit */
2439 tcg_gen_xor_tl(cpu_PSW_V, result, r1);
2440 tcg_gen_xor_tl(temp, result, r2);
2441 tcg_gen_movcond_tl(TCG_COND_GT, cpu_PSW_V, r1, r2, cpu_PSW_V, temp);
2442 tcg_gen_xor_tl(temp, r1, r2);
2443 tcg_gen_and_tl(cpu_PSW_V, cpu_PSW_V, temp);
2444 /* calc SV bit */
2445 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2446 /* Calc AV bit */
2447 tcg_gen_add_tl(cpu_PSW_AV, result, result);
2448 tcg_gen_xor_tl(cpu_PSW_AV, result, cpu_PSW_AV);
2449 /* calc SAV bit */
2450 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2451 /* write back result */
2452 tcg_gen_mov_tl(ret, result);
2453
2454 tcg_temp_free(temp);
2455 tcg_temp_free(result);
2456 }
2457
2458 static inline void gen_absdifi(TCGv ret, TCGv r1, int32_t con)
2459 {
2460 TCGv temp = tcg_const_i32(con);
2461 gen_absdif(ret, r1, temp);
2462 tcg_temp_free(temp);
2463 }
2464
2465 static inline void gen_absdifsi(TCGv ret, TCGv r1, int32_t con)
2466 {
2467 TCGv temp = tcg_const_i32(con);
2468 gen_helper_absdif_ssov(ret, cpu_env, r1, temp);
2469 tcg_temp_free(temp);
2470 }
2471
2472 static inline void gen_mul_i32s(TCGv ret, TCGv r1, TCGv r2)
2473 {
2474 TCGv high = tcg_temp_new();
2475 TCGv low = tcg_temp_new();
2476
2477 tcg_gen_muls2_tl(low, high, r1, r2);
2478 tcg_gen_mov_tl(ret, low);
2479 /* calc V bit */
2480 tcg_gen_sari_tl(low, low, 31);
2481 tcg_gen_setcond_tl(TCG_COND_NE, cpu_PSW_V, high, low);
2482 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2483 /* calc SV bit */
2484 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2485 /* Calc AV bit */
2486 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2487 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2488 /* calc SAV bit */
2489 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2490
2491 tcg_temp_free(high);
2492 tcg_temp_free(low);
2493 }
2494
2495 static inline void gen_muli_i32s(TCGv ret, TCGv r1, int32_t con)
2496 {
2497 TCGv temp = tcg_const_i32(con);
2498 gen_mul_i32s(ret, r1, temp);
2499 tcg_temp_free(temp);
2500 }
2501
2502 static inline void gen_mul_i64s(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2503 {
2504 tcg_gen_muls2_tl(ret_low, ret_high, r1, r2);
2505 /* clear V bit */
2506 tcg_gen_movi_tl(cpu_PSW_V, 0);
2507 /* calc SV bit */
2508 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2509 /* Calc AV bit */
2510 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2511 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2512 /* calc SAV bit */
2513 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2514 }
2515
2516 static inline void gen_muli_i64s(TCGv ret_low, TCGv ret_high, TCGv r1,
2517 int32_t con)
2518 {
2519 TCGv temp = tcg_const_i32(con);
2520 gen_mul_i64s(ret_low, ret_high, r1, temp);
2521 tcg_temp_free(temp);
2522 }
2523
2524 static inline void gen_mul_i64u(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2)
2525 {
2526 tcg_gen_mulu2_tl(ret_low, ret_high, r1, r2);
2527 /* clear V bit */
2528 tcg_gen_movi_tl(cpu_PSW_V, 0);
2529 /* calc SV bit */
2530 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2531 /* Calc AV bit */
2532 tcg_gen_add_tl(cpu_PSW_AV, ret_high, ret_high);
2533 tcg_gen_xor_tl(cpu_PSW_AV, ret_high, cpu_PSW_AV);
2534 /* calc SAV bit */
2535 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2536 }
2537
2538 static inline void gen_muli_i64u(TCGv ret_low, TCGv ret_high, TCGv r1,
2539 int32_t con)
2540 {
2541 TCGv temp = tcg_const_i32(con);
2542 gen_mul_i64u(ret_low, ret_high, r1, temp);
2543 tcg_temp_free(temp);
2544 }
2545
2546 static inline void gen_mulsi_i32(TCGv ret, TCGv r1, int32_t con)
2547 {
2548 TCGv temp = tcg_const_i32(con);
2549 gen_helper_mul_ssov(ret, cpu_env, r1, temp);
2550 tcg_temp_free(temp);
2551 }
2552
2553 static inline void gen_mulsui_i32(TCGv ret, TCGv r1, int32_t con)
2554 {
2555 TCGv temp = tcg_const_i32(con);
2556 gen_helper_mul_suov(ret, cpu_env, r1, temp);
2557 tcg_temp_free(temp);
2558 }
2559 /* gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9); */
2560 static inline void gen_maddsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2561 {
2562 TCGv temp = tcg_const_i32(con);
2563 gen_helper_madd32_ssov(ret, cpu_env, r1, r2, temp);
2564 tcg_temp_free(temp);
2565 }
2566
2567 static inline void gen_maddsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2568 {
2569 TCGv temp = tcg_const_i32(con);
2570 gen_helper_madd32_suov(ret, cpu_env, r1, r2, temp);
2571 tcg_temp_free(temp);
2572 }
2573
2574 static void
2575 gen_mul_q(TCGv rl, TCGv rh, TCGv arg1, TCGv arg2, uint32_t n, uint32_t up_shift)
2576 {
2577 TCGv temp = tcg_temp_new();
2578 TCGv_i64 temp_64 = tcg_temp_new_i64();
2579 TCGv_i64 temp2_64 = tcg_temp_new_i64();
2580
2581 if (n == 0) {
2582 if (up_shift == 32) {
2583 tcg_gen_muls2_tl(rh, rl, arg1, arg2);
2584 } else if (up_shift == 16) {
2585 tcg_gen_ext_i32_i64(temp_64, arg1);
2586 tcg_gen_ext_i32_i64(temp2_64, arg2);
2587
2588 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2589 tcg_gen_shri_i64(temp_64, temp_64, up_shift);
2590 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2591 } else {
2592 tcg_gen_muls2_tl(rl, rh, arg1, arg2);
2593 }
2594 /* reset v bit */
2595 tcg_gen_movi_tl(cpu_PSW_V, 0);
2596 } else { /* n is expected to be 1 */
2597 tcg_gen_ext_i32_i64(temp_64, arg1);
2598 tcg_gen_ext_i32_i64(temp2_64, arg2);
2599
2600 tcg_gen_mul_i64(temp_64, temp_64, temp2_64);
2601
2602 if (up_shift == 0) {
2603 tcg_gen_shli_i64(temp_64, temp_64, 1);
2604 } else {
2605 tcg_gen_shri_i64(temp_64, temp_64, up_shift - 1);
2606 }
2607 tcg_gen_extr_i64_i32(rl, rh, temp_64);
2608 /* overflow only occurs if r1 = r2 = 0x8000 */
2609 if (up_shift == 0) {/* result is 64 bit */
2610 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rh,
2611 0x80000000);
2612 } else { /* result is 32 bit */
2613 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, rl,
2614 0x80000000);
2615 }
2616 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2617 /* calc sv overflow bit */
2618 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
2619 }
2620 /* calc av overflow bit */
2621 if (up_shift == 0) {
2622 tcg_gen_add_tl(cpu_PSW_AV, rh, rh);
2623 tcg_gen_xor_tl(cpu_PSW_AV, rh, cpu_PSW_AV);
2624 } else {
2625 tcg_gen_add_tl(cpu_PSW_AV, rl, rl);
2626 tcg_gen_xor_tl(cpu_PSW_AV, rl, cpu_PSW_AV);
2627 }
2628 /* calc sav overflow bit */
2629 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2630 tcg_temp_free(temp);
2631 tcg_temp_free_i64(temp_64);
2632 tcg_temp_free_i64(temp2_64);
2633 }
2634
2635 static void
2636 gen_mul_q_16(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2637 {
2638 TCGv temp = tcg_temp_new();
2639 if (n == 0) {
2640 tcg_gen_mul_tl(ret, arg1, arg2);
2641 } else { /* n is expected to be 1 */
2642 tcg_gen_mul_tl(ret, arg1, arg2);
2643 tcg_gen_shli_tl(ret, ret, 1);
2644 /* catch special case r1 = r2 = 0x8000 */
2645 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80000000);
2646 tcg_gen_sub_tl(ret, ret, temp);
2647 }
2648 /* reset v bit */
2649 tcg_gen_movi_tl(cpu_PSW_V, 0);
2650 /* calc av overflow bit */
2651 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2652 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2653 /* calc sav overflow bit */
2654 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2655
2656 tcg_temp_free(temp);
2657 }
2658
2659 static void gen_mulr_q(TCGv ret, TCGv arg1, TCGv arg2, uint32_t n)
2660 {
2661 TCGv temp = tcg_temp_new();
2662 if (n == 0) {
2663 tcg_gen_mul_tl(ret, arg1, arg2);
2664 tcg_gen_addi_tl(ret, ret, 0x8000);
2665 } else {
2666 tcg_gen_mul_tl(ret, arg1, arg2);
2667 tcg_gen_shli_tl(ret, ret, 1);
2668 tcg_gen_addi_tl(ret, ret, 0x8000);
2669 /* catch special case r1 = r2 = 0x8000 */
2670 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, ret, 0x80008000);
2671 tcg_gen_muli_tl(temp, temp, 0x8001);
2672 tcg_gen_sub_tl(ret, ret, temp);
2673 }
2674 /* reset v bit */
2675 tcg_gen_movi_tl(cpu_PSW_V, 0);
2676 /* calc av overflow bit */
2677 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2678 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2679 /* calc sav overflow bit */
2680 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2681 /* cut halfword off */
2682 tcg_gen_andi_tl(ret, ret, 0xffff0000);
2683
2684 tcg_temp_free(temp);
2685 }
2686
2687 static inline void
2688 gen_madds_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2689 TCGv r3)
2690 {
2691 TCGv_i64 temp64 = tcg_temp_new_i64();
2692 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2693 gen_helper_madd64_ssov(temp64, cpu_env, r1, temp64, r3);
2694 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2695 tcg_temp_free_i64(temp64);
2696 }
2697
2698 static inline void
2699 gen_maddsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2700 int32_t con)
2701 {
2702 TCGv temp = tcg_const_i32(con);
2703 gen_madds_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2704 tcg_temp_free(temp);
2705 }
2706
2707 static inline void
2708 gen_maddsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2709 TCGv r3)
2710 {
2711 TCGv_i64 temp64 = tcg_temp_new_i64();
2712 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2713 gen_helper_madd64_suov(temp64, cpu_env, r1, temp64, r3);
2714 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2715 tcg_temp_free_i64(temp64);
2716 }
2717
2718 static inline void
2719 gen_maddsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2720 int32_t con)
2721 {
2722 TCGv temp = tcg_const_i32(con);
2723 gen_maddsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2724 tcg_temp_free(temp);
2725 }
2726
2727 static inline void gen_msubsi_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2728 {
2729 TCGv temp = tcg_const_i32(con);
2730 gen_helper_msub32_ssov(ret, cpu_env, r1, r2, temp);
2731 tcg_temp_free(temp);
2732 }
2733
2734 static inline void gen_msubsui_32(TCGv ret, TCGv r1, TCGv r2, int32_t con)
2735 {
2736 TCGv temp = tcg_const_i32(con);
2737 gen_helper_msub32_suov(ret, cpu_env, r1, r2, temp);
2738 tcg_temp_free(temp);
2739 }
2740
2741 static inline void
2742 gen_msubs_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2743 TCGv r3)
2744 {
2745 TCGv_i64 temp64 = tcg_temp_new_i64();
2746 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2747 gen_helper_msub64_ssov(temp64, cpu_env, r1, temp64, r3);
2748 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2749 tcg_temp_free_i64(temp64);
2750 }
2751
2752 static inline void
2753 gen_msubsi_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2754 int32_t con)
2755 {
2756 TCGv temp = tcg_const_i32(con);
2757 gen_msubs_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2758 tcg_temp_free(temp);
2759 }
2760
2761 static inline void
2762 gen_msubsu_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2763 TCGv r3)
2764 {
2765 TCGv_i64 temp64 = tcg_temp_new_i64();
2766 tcg_gen_concat_i32_i64(temp64, r2_low, r2_high);
2767 gen_helper_msub64_suov(temp64, cpu_env, r1, temp64, r3);
2768 tcg_gen_extr_i64_i32(ret_low, ret_high, temp64);
2769 tcg_temp_free_i64(temp64);
2770 }
2771
2772 static inline void
2773 gen_msubsui_64(TCGv ret_low, TCGv ret_high, TCGv r1, TCGv r2_low, TCGv r2_high,
2774 int32_t con)
2775 {
2776 TCGv temp = tcg_const_i32(con);
2777 gen_msubsu_64(ret_low, ret_high, r1, r2_low, r2_high, temp);
2778 tcg_temp_free(temp);
2779 }
2780
2781 static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
2782 {
2783 TCGv sat_neg = tcg_const_i32(low);
2784 TCGv temp = tcg_const_i32(up);
2785
2786 /* sat_neg = (arg < low ) ? low : arg; */
2787 tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, sat_neg, arg);
2788
2789 /* ret = (sat_neg > up ) ? up : sat_neg; */
2790 tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
2791
2792 tcg_temp_free(sat_neg);
2793 tcg_temp_free(temp);
2794 }
2795
2796 static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
2797 {
2798 TCGv temp = tcg_const_i32(up);
2799 /* sat_neg = (arg > up ) ? up : arg; */
2800 tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
2801 tcg_temp_free(temp);
2802 }
2803
2804 static void gen_shi(TCGv ret, TCGv r1, int32_t shift_count)
2805 {
2806 if (shift_count == -32) {
2807 tcg_gen_movi_tl(ret, 0);
2808 } else if (shift_count >= 0) {
2809 tcg_gen_shli_tl(ret, r1, shift_count);
2810 } else {
2811 tcg_gen_shri_tl(ret, r1, -shift_count);
2812 }
2813 }
2814
2815 static void gen_sh_hi(TCGv ret, TCGv r1, int32_t shiftcount)
2816 {
2817 TCGv temp_low, temp_high;
2818
2819 if (shiftcount == -16) {
2820 tcg_gen_movi_tl(ret, 0);
2821 } else {
2822 temp_high = tcg_temp_new();
2823 temp_low = tcg_temp_new();
2824
2825 tcg_gen_andi_tl(temp_low, r1, 0xffff);
2826 tcg_gen_andi_tl(temp_high, r1, 0xffff0000);
2827 gen_shi(temp_low, temp_low, shiftcount);
2828 gen_shi(ret, temp_high, shiftcount);
2829 tcg_gen_deposit_tl(ret, ret, temp_low, 0, 16);
2830
2831 tcg_temp_free(temp_low);
2832 tcg_temp_free(temp_high);
2833 }
2834 }
2835
2836 static void gen_shaci(TCGv ret, TCGv r1, int32_t shift_count)
2837 {
2838 uint32_t msk, msk_start;
2839 TCGv temp = tcg_temp_new();
2840 TCGv temp2 = tcg_temp_new();
2841 TCGv t_0 = tcg_const_i32(0);
2842
2843 if (shift_count == 0) {
2844 /* Clear PSW.C and PSW.V */
2845 tcg_gen_movi_tl(cpu_PSW_C, 0);
2846 tcg_gen_mov_tl(cpu_PSW_V, cpu_PSW_C);
2847 tcg_gen_mov_tl(ret, r1);
2848 } else if (shift_count == -32) {
2849 /* set PSW.C */
2850 tcg_gen_mov_tl(cpu_PSW_C, r1);
2851 /* fill ret completly with sign bit */
2852 tcg_gen_sari_tl(ret, r1, 31);
2853 /* clear PSW.V */
2854 tcg_gen_movi_tl(cpu_PSW_V, 0);
2855 } else if (shift_count > 0) {
2856 TCGv t_max = tcg_const_i32(0x7FFFFFFF >> shift_count);
2857 TCGv t_min = tcg_const_i32(((int32_t) -0x80000000) >> shift_count);
2858
2859 /* calc carry */
2860 msk_start = 32 - shift_count;
2861 msk = ((1 << shift_count) - 1) << msk_start;
2862 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2863 /* calc v/sv bits */
2864 tcg_gen_setcond_tl(TCG_COND_GT, temp, r1, t_max);
2865 tcg_gen_setcond_tl(TCG_COND_LT, temp2, r1, t_min);
2866 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
2867 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
2868 /* calc sv */
2869 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_V, cpu_PSW_SV);
2870 /* do shift */
2871 tcg_gen_shli_tl(ret, r1, shift_count);
2872
2873 tcg_temp_free(t_max);
2874 tcg_temp_free(t_min);
2875 } else {
2876 /* clear PSW.V */
2877 tcg_gen_movi_tl(cpu_PSW_V, 0);
2878 /* calc carry */
2879 msk = (1 << -shift_count) - 1;
2880 tcg_gen_andi_tl(cpu_PSW_C, r1, msk);
2881 /* do shift */
2882 tcg_gen_sari_tl(ret, r1, -shift_count);
2883 }
2884 /* calc av overflow bit */
2885 tcg_gen_add_tl(cpu_PSW_AV, ret, ret);
2886 tcg_gen_xor_tl(cpu_PSW_AV, ret, cpu_PSW_AV);
2887 /* calc sav overflow bit */
2888 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
2889
2890 tcg_temp_free(temp);
2891 tcg_temp_free(temp2);
2892 tcg_temp_free(t_0);
2893 }
2894
2895 static void gen_shas(TCGv ret, TCGv r1, TCGv r2)
2896 {
2897 gen_helper_sha_ssov(ret, cpu_env, r1, r2);
2898 }
2899
2900 static void gen_shasi(TCGv ret, TCGv r1, int32_t con)
2901 {
2902 TCGv temp = tcg_const_i32(con);
2903 gen_shas(ret, r1, temp);
2904 tcg_temp_free(temp);
2905 }
2906
2907 static void gen_sha_hi(TCGv ret, TCGv r1, int32_t shift_count)
2908 {
2909 TCGv low, high;
2910
2911 if (shift_count == 0) {
2912 tcg_gen_mov_tl(ret, r1);
2913 } else if (shift_count > 0) {
2914 low = tcg_temp_new();
2915 high = tcg_temp_new();
2916
2917 tcg_gen_andi_tl(high, r1, 0xffff0000);
2918 tcg_gen_shli_tl(low, r1, shift_count);
2919 tcg_gen_shli_tl(ret, high, shift_count);
2920 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2921
2922 tcg_temp_free(low);
2923 tcg_temp_free(high);
2924 } else {
2925 low = tcg_temp_new();
2926 high = tcg_temp_new();
2927
2928 tcg_gen_ext16s_tl(low, r1);
2929 tcg_gen_sari_tl(low, low, -shift_count);
2930 tcg_gen_sari_tl(ret, r1, -shift_count);
2931 tcg_gen_deposit_tl(ret, ret, low, 0, 16);
2932
2933 tcg_temp_free(low);
2934 tcg_temp_free(high);
2935 }
2936
2937 }
2938
2939 /* ret = {ret[30:0], (r1 cond r2)}; */
2940 static void gen_sh_cond(int cond, TCGv ret, TCGv r1, TCGv r2)
2941 {
2942 TCGv temp = tcg_temp_new();
2943 TCGv temp2 = tcg_temp_new();
2944
2945 tcg_gen_shli_tl(temp, ret, 1);
2946 tcg_gen_setcond_tl(cond, temp2, r1, r2);
2947 tcg_gen_or_tl(ret, temp, temp2);
2948
2949 tcg_temp_free(temp);
2950 tcg_temp_free(temp2);
2951 }
2952
2953 static void gen_sh_condi(int cond, TCGv ret, TCGv r1, int32_t con)
2954 {
2955 TCGv temp = tcg_const_i32(con);
2956 gen_sh_cond(cond, ret, r1, temp);
2957 tcg_temp_free(temp);
2958 }
2959
2960 static inline void gen_adds(TCGv ret, TCGv r1, TCGv r2)
2961 {
2962 gen_helper_add_ssov(ret, cpu_env, r1, r2);
2963 }
2964
2965 static inline void gen_addsi(TCGv ret, TCGv r1, int32_t con)
2966 {
2967 TCGv temp = tcg_const_i32(con);
2968 gen_helper_add_ssov(ret, cpu_env, r1, temp);
2969 tcg_temp_free(temp);
2970 }
2971
2972 static inline void gen_addsui(TCGv ret, TCGv r1, int32_t con)
2973 {
2974 TCGv temp = tcg_const_i32(con);
2975 gen_helper_add_suov(ret, cpu_env, r1, temp);
2976 tcg_temp_free(temp);
2977 }
2978
2979 static inline void gen_subs(TCGv ret, TCGv r1, TCGv r2)
2980 {
2981 gen_helper_sub_ssov(ret, cpu_env, r1, r2);
2982 }
2983
2984 static inline void gen_subsu(TCGv ret, TCGv r1, TCGv r2)
2985 {
2986 gen_helper_sub_suov(ret, cpu_env, r1, r2);
2987 }
2988
2989 static inline void gen_bit_2op(TCGv ret, TCGv r1, TCGv r2,
2990 int pos1, int pos2,
2991 void(*op1)(TCGv, TCGv, TCGv),
2992 void(*op2)(TCGv, TCGv, TCGv))
2993 {
2994 TCGv temp1, temp2;
2995
2996 temp1 = tcg_temp_new();
2997 temp2 = tcg_temp_new();
2998
2999 tcg_gen_shri_tl(temp2, r2, pos2);
3000 tcg_gen_shri_tl(temp1, r1, pos1);
3001
3002 (*op1)(temp1, temp1, temp2);
3003 (*op2)(temp1 , ret, temp1);
3004
3005 tcg_gen_deposit_tl(ret, ret, temp1, 0, 1);
3006
3007 tcg_temp_free(temp1);
3008 tcg_temp_free(temp2);
3009 }
3010
3011 /* ret = r1[pos1] op1 r2[pos2]; */
3012 static inline void gen_bit_1op(TCGv ret, TCGv r1, TCGv r2,
3013 int pos1, int pos2,
3014 void(*op1)(TCGv, TCGv, TCGv))
3015 {
3016 TCGv temp1, temp2;
3017
3018 temp1 = tcg_temp_new();
3019 temp2 = tcg_temp_new();
3020
3021 tcg_gen_shri_tl(temp2, r2, pos2);
3022 tcg_gen_shri_tl(temp1, r1, pos1);
3023
3024 (*op1)(ret, temp1, temp2);
3025
3026 tcg_gen_andi_tl(ret, ret, 0x1);
3027
3028 tcg_temp_free(temp1);
3029 tcg_temp_free(temp2);
3030 }
3031
3032 static inline void gen_accumulating_cond(int cond, TCGv ret, TCGv r1, TCGv r2,
3033 void(*op)(TCGv, TCGv, TCGv))
3034 {
3035 TCGv temp = tcg_temp_new();
3036 TCGv temp2 = tcg_temp_new();
3037 /* temp = (arg1 cond arg2 )*/
3038 tcg_gen_setcond_tl(cond, temp, r1, r2);
3039 /* temp2 = ret[0]*/
3040 tcg_gen_andi_tl(temp2, ret, 0x1);
3041 /* temp = temp insn temp2 */
3042 (*op)(temp, temp, temp2);
3043 /* ret = {ret[31:1], temp} */
3044 tcg_gen_deposit_tl(ret, ret, temp, 0, 1);
3045
3046 tcg_temp_free(temp);
3047 tcg_temp_free(temp2);
3048 }
3049
3050 static inline void
3051 gen_accumulating_condi(int cond, TCGv ret, TCGv r1, int32_t con,
3052 void(*op)(TCGv, TCGv, TCGv))
3053 {
3054 TCGv temp = tcg_const_i32(con);
3055 gen_accumulating_cond(cond, ret, r1, temp, op);
3056 tcg_temp_free(temp);
3057 }
3058
3059 /* ret = (r1 cond r2) ? 0xFFFFFFFF ? 0x00000000;*/
3060 static inline void gen_cond_w(TCGCond cond, TCGv ret, TCGv r1, TCGv r2)
3061 {
3062 tcg_gen_setcond_tl(cond, ret, r1, r2);
3063 tcg_gen_neg_tl(ret, ret);
3064 }
3065
3066 static inline void gen_eqany_bi(TCGv ret, TCGv r1, int32_t con)
3067 {
3068 TCGv b0 = tcg_temp_new();
3069 TCGv b1 = tcg_temp_new();
3070 TCGv b2 = tcg_temp_new();
3071 TCGv b3 = tcg_temp_new();
3072
3073 /* byte 0 */
3074 tcg_gen_andi_tl(b0, r1, 0xff);
3075 tcg_gen_setcondi_tl(TCG_COND_EQ, b0, b0, con & 0xff);
3076
3077 /* byte 1 */
3078 tcg_gen_andi_tl(b1, r1, 0xff00);
3079 tcg_gen_setcondi_tl(TCG_COND_EQ, b1, b1, con & 0xff00);
3080
3081 /* byte 2 */
3082 tcg_gen_andi_tl(b2, r1, 0xff0000);
3083 tcg_gen_setcondi_tl(TCG_COND_EQ, b2, b2, con & 0xff0000);
3084
3085 /* byte 3 */
3086 tcg_gen_andi_tl(b3, r1, 0xff000000);
3087 tcg_gen_setcondi_tl(TCG_COND_EQ, b3, b3, con & 0xff000000);
3088
3089 /* combine them */
3090 tcg_gen_or_tl(ret, b0, b1);
3091 tcg_gen_or_tl(ret, ret, b2);
3092 tcg_gen_or_tl(ret, ret, b3);
3093
3094 tcg_temp_free(b0);
3095 tcg_temp_free(b1);
3096 tcg_temp_free(b2);
3097 tcg_temp_free(b3);
3098 }
3099
3100 static inline void gen_eqany_hi(TCGv ret, TCGv r1, int32_t con)
3101 {
3102 TCGv h0 = tcg_temp_new();
3103 TCGv h1 = tcg_temp_new();
3104
3105 /* halfword 0 */
3106 tcg_gen_andi_tl(h0, r1, 0xffff);
3107 tcg_gen_setcondi_tl(TCG_COND_EQ, h0, h0, con & 0xffff);
3108
3109 /* halfword 1 */
3110 tcg_gen_andi_tl(h1, r1, 0xffff0000);
3111 tcg_gen_setcondi_tl(TCG_COND_EQ, h1, h1, con & 0xffff0000);
3112
3113 /* combine them */
3114 tcg_gen_or_tl(ret, h0, h1);
3115
3116 tcg_temp_free(h0);
3117 tcg_temp_free(h1);
3118 }
3119 /* mask = ((1 << width) -1) << pos;
3120 ret = (r1 & ~mask) | (r2 << pos) & mask); */
3121 static inline void gen_insert(TCGv ret, TCGv r1, TCGv r2, TCGv width, TCGv pos)
3122 {
3123 TCGv mask = tcg_temp_new();
3124 TCGv temp = tcg_temp_new();
3125 TCGv temp2 = tcg_temp_new();
3126
3127 tcg_gen_movi_tl(mask, 1);
3128 tcg_gen_shl_tl(mask, mask, width);
3129 tcg_gen_subi_tl(mask, mask, 1);
3130 tcg_gen_shl_tl(mask, mask, pos);
3131
3132 tcg_gen_shl_tl(temp, r2, pos);
3133 tcg_gen_and_tl(temp, temp, mask);
3134 tcg_gen_andc_tl(temp2, r1, mask);
3135 tcg_gen_or_tl(ret, temp, temp2);
3136
3137 tcg_temp_free(mask);
3138 tcg_temp_free(temp);
3139 tcg_temp_free(temp2);
3140 }
3141
3142 static inline void gen_bsplit(TCGv rl, TCGv rh, TCGv r1)
3143 {
3144 TCGv_i64 temp = tcg_temp_new_i64();
3145
3146 gen_helper_bsplit(temp, r1);
3147 tcg_gen_extr_i64_i32(rl, rh, temp);
3148
3149 tcg_temp_free_i64(temp);
3150 }
3151
3152 static inline void gen_unpack(TCGv rl, TCGv rh, TCGv r1)
3153 {
3154 TCGv_i64 temp = tcg_temp_new_i64();
3155
3156 gen_helper_unpack(temp, r1);
3157 tcg_gen_extr_i64_i32(rl, rh, temp);
3158
3159 tcg_temp_free_i64(temp);
3160 }
3161
3162 static inline void
3163 gen_dvinit_b(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
3164 {
3165 TCGv_i64 ret = tcg_temp_new_i64();
3166
3167 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
3168 gen_helper_dvinit_b_13(ret, cpu_env, r1, r2);
3169 } else {
3170 gen_helper_dvinit_b_131(ret, cpu_env, r1, r2);
3171 }
3172 tcg_gen_extr_i64_i32(rl, rh, ret);
3173
3174 tcg_temp_free_i64(ret);
3175 }
3176
3177 static inline void
3178 gen_dvinit_h(CPUTriCoreState *env, TCGv rl, TCGv rh, TCGv r1, TCGv r2)
3179 {
3180 TCGv_i64 ret = tcg_temp_new_i64();
3181
3182 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
3183 gen_helper_dvinit_h_13(ret, cpu_env, r1, r2);
3184 } else {
3185 gen_helper_dvinit_h_131(ret, cpu_env, r1, r2);
3186 }
3187 tcg_gen_extr_i64_i32(rl, rh, ret);
3188
3189 tcg_temp_free_i64(ret);
3190 }
3191
3192 static void gen_calc_usb_mul_h(TCGv arg_low, TCGv arg_high)
3193 {
3194 TCGv temp = tcg_temp_new();
3195 /* calc AV bit */
3196 tcg_gen_add_tl(temp, arg_low, arg_low);
3197 tcg_gen_xor_tl(temp, temp, arg_low);
3198 tcg_gen_add_tl(cpu_PSW_AV, arg_high, arg_high);
3199 tcg_gen_xor_tl(cpu_PSW_AV, cpu_PSW_AV, arg_high);
3200 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
3201 /* calc SAV bit */
3202 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3203 tcg_gen_movi_tl(cpu_PSW_V, 0);
3204 tcg_temp_free(temp);
3205 }
3206
3207 static void gen_calc_usb_mulr_h(TCGv arg)
3208 {
3209 TCGv temp = tcg_temp_new();
3210 /* calc AV bit */
3211 tcg_gen_add_tl(temp, arg, arg);
3212 tcg_gen_xor_tl(temp, temp, arg);
3213 tcg_gen_shli_tl(cpu_PSW_AV, temp, 16);
3214 tcg_gen_or_tl(cpu_PSW_AV, cpu_PSW_AV, temp);
3215 /* calc SAV bit */
3216 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3217 /* clear V bit */
3218 tcg_gen_movi_tl(cpu_PSW_V, 0);
3219 tcg_temp_free(temp);
3220 }
3221
3222 /* helpers for generating program flow micro-ops */
3223
3224 static inline void gen_save_pc(target_ulong pc)
3225 {
3226 tcg_gen_movi_tl(cpu_PC, pc);
3227 }
3228
3229 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3230 {
3231 TranslationBlock *tb;
3232 tb = ctx->tb;
3233 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3234 likely(!ctx->singlestep_enabled)) {
3235 tcg_gen_goto_tb(n);
3236 gen_save_pc(dest);
3237 tcg_gen_exit_tb((uintptr_t)tb + n);
3238 } else {
3239 gen_save_pc(dest);
3240 if (ctx->singlestep_enabled) {
3241 /* raise exception debug */
3242 }
3243 tcg_gen_exit_tb(0);
3244 }
3245 }
3246
3247 static inline void gen_branch_cond(DisasContext *ctx, TCGCond cond, TCGv r1,
3248 TCGv r2, int16_t address)
3249 {
3250 TCGLabel *jumpLabel = gen_new_label();
3251 tcg_gen_brcond_tl(cond, r1, r2, jumpLabel);
3252
3253 gen_goto_tb(ctx, 1, ctx->next_pc);
3254
3255 gen_set_label(jumpLabel);
3256 gen_goto_tb(ctx, 0, ctx->pc + address * 2);
3257 }
3258
3259 static inline void gen_branch_condi(DisasContext *ctx, TCGCond cond, TCGv r1,
3260 int r2, int16_t address)
3261 {
3262 TCGv temp = tcg_const_i32(r2);
3263 gen_branch_cond(ctx, cond, r1, temp, address);
3264 tcg_temp_free(temp);
3265 }
3266
3267 static void gen_loop(DisasContext *ctx, int r1, int32_t offset)
3268 {
3269 TCGLabel *l1 = gen_new_label();
3270
3271 tcg_gen_subi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], 1);
3272 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr_a[r1], -1, l1);
3273 gen_goto_tb(ctx, 1, ctx->pc + offset);
3274 gen_set_label(l1);
3275 gen_goto_tb(ctx, 0, ctx->next_pc);
3276 }
3277
3278 static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1,
3279 int r2 , int32_t constant , int32_t offset)
3280 {
3281 TCGv temp, temp2;
3282 int n;
3283
3284 switch (opc) {
3285 /* SB-format jumps */
3286 case OPC1_16_SB_J:
3287 case OPC1_32_B_J:
3288 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3289 break;
3290 case OPC1_32_B_CALL:
3291 case OPC1_16_SB_CALL:
3292 gen_helper_1arg(call, ctx->next_pc);
3293 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3294 break;
3295 case OPC1_16_SB_JZ:
3296 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], 0, offset);
3297 break;
3298 case OPC1_16_SB_JNZ:
3299 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], 0, offset);
3300 break;
3301 /* SBC-format jumps */
3302 case OPC1_16_SBC_JEQ:
3303 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset);
3304 break;
3305 case OPC1_16_SBC_JNE:
3306 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset);
3307 break;
3308 /* SBRN-format jumps */
3309 case OPC1_16_SBRN_JZ_T:
3310 temp = tcg_temp_new();
3311 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
3312 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3313 tcg_temp_free(temp);
3314 break;
3315 case OPC1_16_SBRN_JNZ_T:
3316 temp = tcg_temp_new();
3317 tcg_gen_andi_tl(temp, cpu_gpr_d[15], 0x1u << constant);
3318 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3319 tcg_temp_free(temp);
3320 break;
3321 /* SBR-format jumps */
3322 case OPC1_16_SBR_JEQ:
3323 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15],
3324 offset);
3325 break;
3326 case OPC1_16_SBR_JNE:
3327 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15],
3328 offset);
3329 break;
3330 case OPC1_16_SBR_JNZ:
3331 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], 0, offset);
3332 break;
3333 case OPC1_16_SBR_JNZ_A:
3334 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3335 break;
3336 case OPC1_16_SBR_JGEZ:
3337 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], 0, offset);
3338 break;
3339 case OPC1_16_SBR_JGTZ:
3340 gen_branch_condi(ctx, TCG_COND_GT, cpu_gpr_d[r1], 0, offset);
3341 break;
3342 case OPC1_16_SBR_JLEZ:
3343 gen_branch_condi(ctx, TCG_COND_LE, cpu_gpr_d[r1], 0, offset);
3344 break;
3345 case OPC1_16_SBR_JLTZ:
3346 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], 0, offset);
3347 break;
3348 case OPC1_16_SBR_JZ:
3349 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], 0, offset);
3350 break;
3351 case OPC1_16_SBR_JZ_A:
3352 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3353 break;
3354 case OPC1_16_SBR_LOOP:
3355 gen_loop(ctx, r1, offset * 2 - 32);
3356 break;
3357 /* SR-format jumps */
3358 case OPC1_16_SR_JI:
3359 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
3360 tcg_gen_exit_tb(0);
3361 break;
3362 case OPC2_32_SYS_RET:
3363 case OPC2_16_SR_RET:
3364 gen_helper_ret(cpu_env);
3365 tcg_gen_exit_tb(0);
3366 break;
3367 /* B-format */
3368 case OPC1_32_B_CALLA:
3369 gen_helper_1arg(call, ctx->next_pc);
3370 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3371 break;
3372 case OPC1_32_B_JLA:
3373 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3374 /* fall through */
3375 case OPC1_32_B_JA:
3376 gen_goto_tb(ctx, 0, EA_B_ABSOLUT(offset));
3377 break;
3378 case OPC1_32_B_JL:
3379 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
3380 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3381 break;
3382 /* BOL format */
3383 case OPCM_32_BRC_EQ_NEQ:
3384 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JEQ) {
3385 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[r1], constant, offset);
3386 } else {
3387 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[r1], constant, offset);
3388 }
3389 break;
3390 case OPCM_32_BRC_GE:
3391 if (MASK_OP_BRC_OP2(ctx->opcode) == OP2_32_BRC_JGE) {
3392 gen_branch_condi(ctx, TCG_COND_GE, cpu_gpr_d[r1], constant, offset);
3393 } else {
3394 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3395 gen_branch_condi(ctx, TCG_COND_GEU, cpu_gpr_d[r1], constant,
3396 offset);
3397 }
3398 break;
3399 case OPCM_32_BRC_JLT:
3400 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JLT) {
3401 gen_branch_condi(ctx, TCG_COND_LT, cpu_gpr_d[r1], constant, offset);
3402 } else {
3403 constant = MASK_OP_BRC_CONST4(ctx->opcode);
3404 gen_branch_condi(ctx, TCG_COND_LTU, cpu_gpr_d[r1], constant,
3405 offset);
3406 }
3407 break;
3408 case OPCM_32_BRC_JNE:
3409 temp = tcg_temp_new();
3410 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRC_JNED) {
3411 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3412 /* subi is unconditional */
3413 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3414 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3415 } else {
3416 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3417 /* addi is unconditional */
3418 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3419 gen_branch_condi(ctx, TCG_COND_NE, temp, constant, offset);
3420 }
3421 tcg_temp_free(temp);
3422 break;
3423 /* BRN format */
3424 case OPCM_32_BRN_JTT:
3425 n = MASK_OP_BRN_N(ctx->opcode);
3426
3427 temp = tcg_temp_new();
3428 tcg_gen_andi_tl(temp, cpu_gpr_d[r1], (1 << n));
3429
3430 if (MASK_OP_BRN_OP2(ctx->opcode) == OPC2_32_BRN_JNZ_T) {
3431 gen_branch_condi(ctx, TCG_COND_NE, temp, 0, offset);
3432 } else {
3433 gen_branch_condi(ctx, TCG_COND_EQ, temp, 0, offset);
3434 }
3435 tcg_temp_free(temp);
3436 break;
3437 /* BRR Format */
3438 case OPCM_32_BRR_EQ_NEQ:
3439 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ) {
3440 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2],
3441 offset);
3442 } else {
3443 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3444 offset);
3445 }
3446 break;
3447 case OPCM_32_BRR_ADDR_EQ_NEQ:
3448 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JEQ_A) {
3449 gen_branch_cond(ctx, TCG_COND_EQ, cpu_gpr_a[r1], cpu_gpr_a[r2],
3450 offset);
3451 } else {
3452 gen_branch_cond(ctx, TCG_COND_NE, cpu_gpr_a[r1], cpu_gpr_a[r2],
3453 offset);
3454 }
3455 break;
3456 case OPCM_32_BRR_GE:
3457 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JGE) {
3458 gen_branch_cond(ctx, TCG_COND_GE, cpu_gpr_d[r1], cpu_gpr_d[r2],
3459 offset);
3460 } else {
3461 gen_branch_cond(ctx, TCG_COND_GEU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3462 offset);
3463 }
3464 break;
3465 case OPCM_32_BRR_JLT:
3466 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JLT) {
3467 gen_branch_cond(ctx, TCG_COND_LT, cpu_gpr_d[r1], cpu_gpr_d[r2],
3468 offset);
3469 } else {
3470 gen_branch_cond(ctx, TCG_COND_LTU, cpu_gpr_d[r1], cpu_gpr_d[r2],
3471 offset);
3472 }
3473 break;
3474 case OPCM_32_BRR_LOOP:
3475 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_LOOP) {
3476 gen_loop(ctx, r2, offset * 2);
3477 } else {
3478 /* OPC2_32_BRR_LOOPU */
3479 gen_goto_tb(ctx, 0, ctx->pc + offset * 2);
3480 }
3481 break;
3482 case OPCM_32_BRR_JNE:
3483 temp = tcg_temp_new();
3484 temp2 = tcg_temp_new();
3485 if (MASK_OP_BRC_OP2(ctx->opcode) == OPC2_32_BRR_JNED) {
3486 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3487 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3488 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3489 /* subi is unconditional */
3490 tcg_gen_subi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3491 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3492 } else {
3493 tcg_gen_mov_tl(temp, cpu_gpr_d[r1]);
3494 /* also save r2, in case of r1 == r2, so r2 is not decremented */
3495 tcg_gen_mov_tl(temp2, cpu_gpr_d[r2]);
3496 /* addi is unconditional */
3497 tcg_gen_addi_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 1);
3498 gen_branch_cond(ctx, TCG_COND_NE, temp, temp2, offset);
3499 }
3500 tcg_temp_free(temp);
3501 tcg_temp_free(temp2);
3502 break;
3503 case OPCM_32_BRR_JNZ:
3504 if (MASK_OP_BRR_OP2(ctx->opcode) == OPC2_32_BRR_JNZ_A) {
3505 gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_a[r1], 0, offset);
3506 } else {
3507 gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_a[r1], 0, offset);
3508 }
3509 break;
3510 default:
3511 printf("Branch Error at %x\n", ctx->pc);
3512 }
3513 ctx->bstate = BS_BRANCH;
3514 }
3515
3516
3517 /*
3518 * Functions for decoding instructions
3519 */
3520
3521 static void decode_src_opc(CPUTriCoreState *env, DisasContext *ctx, int op1)
3522 {
3523 int r1;
3524 int32_t const4;
3525 TCGv temp, temp2;
3526
3527 r1 = MASK_OP_SRC_S1D(ctx->opcode);
3528 const4 = MASK_OP_SRC_CONST4_SEXT(ctx->opcode);
3529
3530 switch (op1) {
3531 case OPC1_16_SRC_ADD:
3532 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3533 break;
3534 case OPC1_16_SRC_ADD_A15:
3535 gen_addi_d(cpu_gpr_d[r1], cpu_gpr_d[15], const4);
3536 break;
3537 case OPC1_16_SRC_ADD_15A:
3538 gen_addi_d(cpu_gpr_d[15], cpu_gpr_d[r1], const4);
3539 break;
3540 case OPC1_16_SRC_ADD_A:
3541 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], const4);
3542 break;
3543 case OPC1_16_SRC_CADD:
3544 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3545 cpu_gpr_d[15]);
3546 break;
3547 case OPC1_16_SRC_CADDN:
3548 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const4, cpu_gpr_d[r1],
3549 cpu_gpr_d[15]);
3550 break;
3551 case OPC1_16_SRC_CMOV:
3552 temp = tcg_const_tl(0);
3553 temp2 = tcg_const_tl(const4);
3554 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3555 temp2, cpu_gpr_d[r1]);
3556 tcg_temp_free(temp);
3557 tcg_temp_free(temp2);
3558 break;
3559 case OPC1_16_SRC_CMOVN:
3560 temp = tcg_const_tl(0);
3561 temp2 = tcg_const_tl(const4);
3562 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3563 temp2, cpu_gpr_d[r1]);
3564 tcg_temp_free(temp);
3565 tcg_temp_free(temp2);
3566 break;
3567 case OPC1_16_SRC_EQ:
3568 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3569 const4);
3570 break;
3571 case OPC1_16_SRC_LT:
3572 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3573 const4);
3574 break;
3575 case OPC1_16_SRC_MOV:
3576 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3577 break;
3578 case OPC1_16_SRC_MOV_A:
3579 const4 = MASK_OP_SRC_CONST4(ctx->opcode);
3580 tcg_gen_movi_tl(cpu_gpr_a[r1], const4);
3581 break;
3582 case OPC1_16_SRC_MOV_E:
3583 if (tricore_feature(env, TRICORE_FEATURE_16)) {
3584 tcg_gen_movi_tl(cpu_gpr_d[r1], const4);
3585 tcg_gen_sari_tl(cpu_gpr_d[r1+1], cpu_gpr_d[r1], 31);
3586 } /* TODO: else raise illegal opcode trap */
3587 break;
3588 case OPC1_16_SRC_SH:
3589 gen_shi(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3590 break;
3591 case OPC1_16_SRC_SHA:
3592 gen_shaci(cpu_gpr_d[r1], cpu_gpr_d[r1], const4);
3593 break;
3594 }
3595 }
3596
3597 static void decode_srr_opc(DisasContext *ctx, int op1)
3598 {
3599 int r1, r2;
3600 TCGv temp;
3601
3602 r1 = MASK_OP_SRR_S1D(ctx->opcode);
3603 r2 = MASK_OP_SRR_S2(ctx->opcode);
3604
3605 switch (op1) {
3606 case OPC1_16_SRR_ADD:
3607 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3608 break;
3609 case OPC1_16_SRR_ADD_A15:
3610 gen_add_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3611 break;
3612 case OPC1_16_SRR_ADD_15A:
3613 gen_add_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3614 break;
3615 case OPC1_16_SRR_ADD_A:
3616 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r1], cpu_gpr_a[r2]);
3617 break;
3618 case OPC1_16_SRR_ADDS:
3619 gen_adds(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3620 break;
3621 case OPC1_16_SRR_AND:
3622 tcg_gen_and_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3623 break;
3624 case OPC1_16_SRR_CMOV:
3625 temp = tcg_const_tl(0);
3626 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3627 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3628 tcg_temp_free(temp);
3629 break;
3630 case OPC1_16_SRR_CMOVN:
3631 temp = tcg_const_tl(0);
3632 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[15], temp,
3633 cpu_gpr_d[r2], cpu_gpr_d[r1]);
3634 tcg_temp_free(temp);
3635 break;
3636 case OPC1_16_SRR_EQ:
3637 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[15], cpu_gpr_d[r1],
3638 cpu_gpr_d[r2]);
3639 break;
3640 case OPC1_16_SRR_LT:
3641 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[15], cpu_gpr_d[r1],
3642 cpu_gpr_d[r2]);
3643 break;
3644 case OPC1_16_SRR_MOV:
3645 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_d[r2]);
3646 break;
3647 case OPC1_16_SRR_MOV_A:
3648 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_d[r2]);
3649 break;
3650 case OPC1_16_SRR_MOV_AA:
3651 tcg_gen_mov_tl(cpu_gpr_a[r1], cpu_gpr_a[r2]);
3652 break;
3653 case OPC1_16_SRR_MOV_D:
3654 tcg_gen_mov_tl(cpu_gpr_d[r1], cpu_gpr_a[r2]);
3655 break;
3656 case OPC1_16_SRR_MUL:
3657 gen_mul_i32s(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3658 break;
3659 case OPC1_16_SRR_OR:
3660 tcg_gen_or_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3661 break;
3662 case OPC1_16_SRR_SUB:
3663 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3664 break;
3665 case OPC1_16_SRR_SUB_A15B:
3666 gen_sub_d(cpu_gpr_d[r1], cpu_gpr_d[15], cpu_gpr_d[r2]);
3667 break;
3668 case OPC1_16_SRR_SUB_15AB:
3669 gen_sub_d(cpu_gpr_d[15], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3670 break;
3671 case OPC1_16_SRR_SUBS:
3672 gen_subs(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3673 break;
3674 case OPC1_16_SRR_XOR:
3675 tcg_gen_xor_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], cpu_gpr_d[r2]);
3676 break;
3677 }
3678 }
3679
3680 static void decode_ssr_opc(DisasContext *ctx, int op1)
3681 {
3682 int r1, r2;
3683
3684 r1 = MASK_OP_SSR_S1(ctx->opcode);
3685 r2 = MASK_OP_SSR_S2(ctx->opcode);
3686
3687 switch (op1) {
3688 case OPC1_16_SSR_ST_A:
3689 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3690 break;
3691 case OPC1_16_SSR_ST_A_POSTINC:
3692 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3693 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3694 break;
3695 case OPC1_16_SSR_ST_B:
3696 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3697 break;
3698 case OPC1_16_SSR_ST_B_POSTINC:
3699 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3700 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3701 break;
3702 case OPC1_16_SSR_ST_H:
3703 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3704 break;
3705 case OPC1_16_SSR_ST_H_POSTINC:
3706 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUW);
3707 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3708 break;
3709 case OPC1_16_SSR_ST_W:
3710 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3711 break;
3712 case OPC1_16_SSR_ST_W_POSTINC:
3713 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LEUL);
3714 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3715 break;
3716 }
3717 }
3718
3719 static void decode_sc_opc(DisasContext *ctx, int op1)
3720 {
3721 int32_t const16;
3722
3723 const16 = MASK_OP_SC_CONST8(ctx->opcode);
3724
3725 switch (op1) {
3726 case OPC1_16_SC_AND:
3727 tcg_gen_andi_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3728 break;
3729 case OPC1_16_SC_BISR:
3730 gen_helper_1arg(bisr, const16 & 0xff);
3731 break;
3732 case OPC1_16_SC_LD_A:
3733 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3734 break;
3735 case OPC1_16_SC_LD_W:
3736 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3737 break;
3738 case OPC1_16_SC_MOV:
3739 tcg_gen_movi_tl(cpu_gpr_d[15], const16);
3740 break;
3741 case OPC1_16_SC_OR:
3742 tcg_gen_ori_tl(cpu_gpr_d[15], cpu_gpr_d[15], const16);
3743 break;
3744 case OPC1_16_SC_ST_A:
3745 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3746 break;
3747 case OPC1_16_SC_ST_W:
3748 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[10], const16 * 4, MO_LESL);
3749 break;
3750 case OPC1_16_SC_SUB_A:
3751 tcg_gen_subi_tl(cpu_gpr_a[10], cpu_gpr_a[10], const16);
3752 break;
3753 }
3754 }
3755
3756 static void decode_slr_opc(DisasContext *ctx, int op1)
3757 {
3758 int r1, r2;
3759
3760 r1 = MASK_OP_SLR_D(ctx->opcode);
3761 r2 = MASK_OP_SLR_S2(ctx->opcode);
3762
3763 switch (op1) {
3764 /* SLR-format */
3765 case OPC1_16_SLR_LD_A:
3766 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3767 break;
3768 case OPC1_16_SLR_LD_A_POSTINC:
3769 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3770 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3771 break;
3772 case OPC1_16_SLR_LD_BU:
3773 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3774 break;
3775 case OPC1_16_SLR_LD_BU_POSTINC:
3776 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_UB);
3777 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 1);
3778 break;
3779 case OPC1_16_SLR_LD_H:
3780 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3781 break;
3782 case OPC1_16_SLR_LD_H_POSTINC:
3783 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESW);
3784 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 2);
3785 break;
3786 case OPC1_16_SLR_LD_W:
3787 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3788 break;
3789 case OPC1_16_SLR_LD_W_POSTINC:
3790 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx, MO_LESL);
3791 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], 4);
3792 break;
3793 }
3794 }
3795
3796 static void decode_sro_opc(DisasContext *ctx, int op1)
3797 {
3798 int r2;
3799 int32_t address;
3800
3801 r2 = MASK_OP_SRO_S2(ctx->opcode);
3802 address = MASK_OP_SRO_OFF4(ctx->opcode);
3803
3804 /* SRO-format */
3805 switch (op1) {
3806 case OPC1_16_SRO_LD_A:
3807 gen_offset_ld(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3808 break;
3809 case OPC1_16_SRO_LD_BU:
3810 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3811 break;
3812 case OPC1_16_SRO_LD_H:
3813 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
3814 break;
3815 case OPC1_16_SRO_LD_W:
3816 gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3817 break;
3818 case OPC1_16_SRO_ST_A:
3819 gen_offset_st(ctx, cpu_gpr_a[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3820 break;
3821 case OPC1_16_SRO_ST_B:
3822 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
3823 break;
3824 case OPC1_16_SRO_ST_H:
3825 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
3826 break;
3827 case OPC1_16_SRO_ST_W:
3828 gen_offset_st(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);
3829 break;
3830 }
3831 }
3832
3833 static void decode_sr_system(CPUTriCoreState *env, DisasContext *ctx)
3834 {
3835 uint32_t op2;
3836 op2 = MASK_OP_SR_OP2(ctx->opcode);
3837
3838 switch (op2) {
3839 case OPC2_16_SR_NOP:
3840 break;
3841 case OPC2_16_SR_RET:
3842 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
3843 break;
3844 case OPC2_16_SR_RFE:
3845 gen_helper_rfe(cpu_env);
3846 tcg_gen_exit_tb(0);
3847 ctx->bstate = BS_BRANCH;
3848 break;
3849 case OPC2_16_SR_DEBUG:
3850 /* raise EXCP_DEBUG */
3851 break;
3852 }
3853 }
3854
3855 static void decode_sr_accu(CPUTriCoreState *env, DisasContext *ctx)
3856 {
3857 uint32_t op2;
3858 uint32_t r1;
3859 TCGv temp;
3860
3861 r1 = MASK_OP_SR_S1D(ctx->opcode);
3862 op2 = MASK_OP_SR_OP2(ctx->opcode);
3863
3864 switch (op2) {
3865 case OPC2_16_SR_RSUB:
3866 /* overflow only if r1 = -0x80000000 */
3867 temp = tcg_const_i32(-0x80000000);
3868 /* calc V bit */
3869 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r1], temp);
3870 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
3871 /* calc SV bit */
3872 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
3873 /* sub */
3874 tcg_gen_neg_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
3875 /* calc av */
3876 tcg_gen_add_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_gpr_d[r1]);
3877 tcg_gen_xor_tl(cpu_PSW_AV, cpu_gpr_d[r1], cpu_PSW_AV);
3878 /* calc sav */
3879 tcg_gen_or_tl(cpu_PSW_SAV, cpu_PSW_SAV, cpu_PSW_AV);
3880 tcg_temp_free(temp);
3881 break;
3882 case OPC2_16_SR_SAT_B:
3883 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
3884 break;
3885 case OPC2_16_SR_SAT_BU:
3886 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
3887 break;
3888 case OPC2_16_SR_SAT_H:
3889 gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
3890 break;
3891 case OPC2_16_SR_SAT_HU:
3892 gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
3893 break;
3894 }
3895 }
3896
3897 static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
3898 {
3899 int op1;
3900 int r1, r2;
3901 int32_t const16;
3902 int32_t address;
3903 TCGv temp;
3904
3905 op1 = MASK_OP_MAJOR(ctx->opcode);
3906
3907 /* handle ADDSC.A opcode only being 6 bit long */
3908 if (unlikely((op1 & 0x3f) == OPC1_16_SRRS_ADDSC_A)) {
3909 op1 = OPC1_16_SRRS_ADDSC_A;
3910 }
3911
3912 switch (op1) {
3913 case OPC1_16_SRC_ADD:
3914 case OPC1_16_SRC_ADD_A15:
3915 case OPC1_16_SRC_ADD_15A:
3916 case OPC1_16_SRC_ADD_A:
3917 case OPC1_16_SRC_CADD:
3918 case OPC1_16_SRC_CADDN:
3919 case OPC1_16_SRC_CMOV:
3920 case OPC1_16_SRC_CMOVN:
3921 case OPC1_16_SRC_EQ:
3922 case OPC1_16_SRC_LT:
3923 case OPC1_16_SRC_MOV:
3924 case OPC1_16_SRC_MOV_A:
3925 case OPC1_16_SRC_MOV_E:
3926 case OPC1_16_SRC_SH:
3927 case OPC1_16_SRC_SHA:
3928 decode_src_opc(env, ctx, op1);
3929 break;
3930 /* SRR-format */
3931 case OPC1_16_SRR_ADD:
3932 case OPC1_16_SRR_ADD_A15:
3933 case OPC1_16_SRR_ADD_15A:
3934 case OPC1_16_SRR_ADD_A:
3935 case OPC1_16_SRR_ADDS:
3936 case OPC1_16_SRR_AND:
3937 case OPC1_16_SRR_CMOV:
3938 case OPC1_16_SRR_CMOVN:
3939 case OPC1_16_SRR_EQ:
3940 case OPC1_16_SRR_LT:
3941 case OPC1_16_SRR_MOV:
3942 case OPC1_16_SRR_MOV_A:
3943 case OPC1_16_SRR_MOV_AA:
3944 case OPC1_16_SRR_MOV_D:
3945 case OPC1_16_SRR_MUL:
3946 case OPC1_16_SRR_OR:
3947 case OPC1_16_SRR_SUB:
3948 case OPC1_16_SRR_SUB_A15B:
3949 case OPC1_16_SRR_SUB_15AB:
3950 case OPC1_16_SRR_SUBS:
3951 case OPC1_16_SRR_XOR:
3952 decode_srr_opc(ctx, op1);
3953 break;
3954 /* SSR-format */
3955 case OPC1_16_SSR_ST_A:
3956 case OPC1_16_SSR_ST_A_POSTINC:
3957 case OPC1_16_SSR_ST_B:
3958 case OPC1_16_SSR_ST_B_POSTINC:
3959 case OPC1_16_SSR_ST_H:
3960 case OPC1_16_SSR_ST_H_POSTINC:
3961 case OPC1_16_SSR_ST_W:
3962 case OPC1_16_SSR_ST_W_POSTINC:
3963 decode_ssr_opc(ctx, op1);
3964 break;
3965 /* SRRS-format */
3966 case OPC1_16_SRRS_ADDSC_A:
3967 r2 = MASK_OP_SRRS_S2(ctx->opcode);
3968 r1 = MASK_OP_SRRS_S1D(ctx->opcode);
3969 const16 = MASK_OP_SRRS_N(ctx->opcode);
3970 temp = tcg_temp_new();
3971 tcg_gen_shli_tl(temp, cpu_gpr_d[15], const16);
3972 tcg_gen_add_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], temp);
3973 tcg_temp_free(temp);
3974 break;
3975 /* SLRO-format */
3976 case OPC1_16_SLRO_LD_A:
3977 r1 = MASK_OP_SLRO_D(ctx->opcode);
3978 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3979 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3980 break;
3981 case OPC1_16_SLRO_LD_BU:
3982 r1 = MASK_OP_SLRO_D(ctx->opcode);
3983 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3984 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
3985 break;
3986 case OPC1_16_SLRO_LD_H:
3987 r1 = MASK_OP_SLRO_D(ctx->opcode);
3988 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3989 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
3990 break;
3991 case OPC1_16_SLRO_LD_W:
3992 r1 = MASK_OP_SLRO_D(ctx->opcode);
3993 const16 = MASK_OP_SLRO_OFF4(ctx->opcode);
3994 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
3995 break;
3996 /* SB-format */
3997 case OPC1_16_SB_CALL:
3998 case OPC1_16_SB_J:
3999 case OPC1_16_SB_JNZ:
4000 case OPC1_16_SB_JZ:
4001 address = MASK_OP_SB_DISP8_SEXT(ctx->opcode);
4002 gen_compute_branch(ctx, op1, 0, 0, 0, address);
4003 break;
4004 /* SBC-format */
4005 case OPC1_16_SBC_JEQ:
4006 case OPC1_16_SBC_JNE:
4007 address = MASK_OP_SBC_DISP4(ctx->opcode);
4008 const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode);
4009 gen_compute_branch(ctx, op1, 0, 0, const16, address);
4010 break;
4011 /* SBRN-format */
4012 case OPC1_16_SBRN_JNZ_T:
4013 case OPC1_16_SBRN_JZ_T:
4014 address = MASK_OP_SBRN_DISP4(ctx->opcode);
4015 const16 = MASK_OP_SBRN_N(ctx->opcode);
4016 gen_compute_branch(ctx, op1, 0, 0, const16, address);
4017 break;
4018 /* SBR-format */
4019 case OPC1_16_SBR_JEQ:
4020 case OPC1_16_SBR_JGEZ:
4021 case OPC1_16_SBR_JGTZ:
4022 case OPC1_16_SBR_JLEZ:
4023 case OPC1_16_SBR_JLTZ:
4024 case OPC1_16_SBR_JNE:
4025 case OPC1_16_SBR_JNZ:
4026 case OPC1_16_SBR_JNZ_A:
4027 case OPC1_16_SBR_JZ:
4028 case OPC1_16_SBR_JZ_A:
4029 case OPC1_16_SBR_LOOP:
4030 r1 = MASK_OP_SBR_S2(ctx->opcode);
4031 address = MASK_OP_SBR_DISP4(ctx->opcode);
4032 gen_compute_branch(ctx, op1, r1, 0, 0, address);
4033 break;
4034 /* SC-format */
4035 case OPC1_16_SC_AND:
4036 case OPC1_16_SC_BISR:
4037 case OPC1_16_SC_LD_A:
4038 case OPC1_16_SC_LD_W:
4039 case OPC1_16_SC_MOV:
4040 case OPC1_16_SC_OR:
4041 case OPC1_16_SC_ST_A:
4042 case OPC1_16_SC_ST_W:
4043 case OPC1_16_SC_SUB_A:
4044 decode_sc_opc(ctx, op1);
4045 break;
4046 /* SLR-format */
4047 case OPC1_16_SLR_LD_A:
4048 case OPC1_16_SLR_LD_A_POSTINC:
4049 case OPC1_16_SLR_LD_BU:
4050 case OPC1_16_SLR_LD_BU_POSTINC:
4051 case OPC1_16_SLR_LD_H:
4052 case OPC1_16_SLR_LD_H_POSTINC:
4053 case OPC1_16_SLR_LD_W:
4054 case OPC1_16_SLR_LD_W_POSTINC:
4055 decode_slr_opc(ctx, op1);
4056 break;
4057 /* SRO-format */
4058 case OPC1_16_SRO_LD_A:
4059 case OPC1_16_SRO_LD_BU:
4060 case OPC1_16_SRO_LD_H:
4061 case OPC1_16_SRO_LD_W:
4062 case OPC1_16_SRO_ST_A:
4063 case OPC1_16_SRO_ST_B:
4064 case OPC1_16_SRO_ST_H:
4065 case OPC1_16_SRO_ST_W:
4066 decode_sro_opc(ctx, op1);
4067 break;
4068 /* SSRO-format */
4069 case OPC1_16_SSRO_ST_A:
4070 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4071 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4072 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4073 break;
4074 case OPC1_16_SSRO_ST_B:
4075 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4076 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4077 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16, MO_UB);
4078 break;
4079 case OPC1_16_SSRO_ST_H:
4080 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4081 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4082 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 2, MO_LESW);
4083 break;
4084 case OPC1_16_SSRO_ST_W:
4085 r1 = MASK_OP_SSRO_S1(ctx->opcode);
4086 const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
4087 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
4088 break;
4089 /* SR-format */
4090 case OPCM_16_SR_SYSTEM:
4091 decode_sr_system(env, ctx);
4092 break;
4093 case OPCM_16_SR_ACCU:
4094 decode_sr_accu(env, ctx);
4095 break;
4096 case OPC1_16_SR_JI:
4097 r1 = MASK_OP_SR_S1D(ctx->opcode);
4098 gen_compute_branch(ctx, op1, r1, 0, 0, 0);
4099 break;
4100 case OPC1_16_SR_NOT:
4101 r1 = MASK_OP_SR_S1D(ctx->opcode);
4102 tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
4103 break;
4104 }
4105 }
4106
4107 /*
4108 * 32 bit instructions
4109 */
4110
4111 /* ABS-format */
4112 static void decode_abs_ldw(CPUTriCoreState *env, DisasContext *ctx)
4113 {
4114 int32_t op2;
4115 int32_t r1;
4116 uint32_t address;
4117 TCGv temp;
4118
4119 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4120 address = MASK_OP_ABS_OFF18(ctx->opcode);
4121 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4122
4123 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4124
4125 switch (op2) {
4126 case OPC2_32_ABS_LD_A:
4127 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
4128 break;
4129 case OPC2_32_ABS_LD_D:
4130 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4131 break;
4132 case OPC2_32_ABS_LD_DA:
4133 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4134 break;
4135 case OPC2_32_ABS_LD_W:
4136 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
4137 break;
4138 }
4139
4140 tcg_temp_free(temp);
4141 }
4142
4143 static void decode_abs_ldb(CPUTriCoreState *env, DisasContext *ctx)
4144 {
4145 int32_t op2;
4146 int32_t r1;
4147 uint32_t address;
4148 TCGv temp;
4149
4150 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4151 address = MASK_OP_ABS_OFF18(ctx->opcode);
4152 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4153
4154 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4155
4156 switch (op2) {
4157 case OPC2_32_ABS_LD_B:
4158 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_SB);
4159 break;
4160 case OPC2_32_ABS_LD_BU:
4161 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
4162 break;
4163 case OPC2_32_ABS_LD_H:
4164 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESW);
4165 break;
4166 case OPC2_32_ABS_LD_HU:
4167 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
4168 break;
4169 }
4170
4171 tcg_temp_free(temp);
4172 }
4173
4174 static void decode_abs_ldst_swap(CPUTriCoreState *env, DisasContext *ctx)
4175 {
4176 int32_t op2;
4177 int32_t r1;
4178 uint32_t address;
4179 TCGv temp;
4180
4181 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4182 address = MASK_OP_ABS_OFF18(ctx->opcode);
4183 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4184
4185 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4186
4187 switch (op2) {
4188 case OPC2_32_ABS_LDMST:
4189 gen_ldmst(ctx, r1, temp);
4190 break;
4191 case OPC2_32_ABS_SWAP_W:
4192 gen_swap(ctx, r1, temp);
4193 break;
4194 }
4195
4196 tcg_temp_free(temp);
4197 }
4198
4199 static void decode_abs_ldst_context(CPUTriCoreState *env, DisasContext *ctx)
4200 {
4201 uint32_t op2;
4202 int32_t off18;
4203
4204 off18 = MASK_OP_ABS_OFF18(ctx->opcode);
4205 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4206
4207 switch (op2) {
4208 case OPC2_32_ABS_LDLCX:
4209 gen_helper_1arg(ldlcx, EA_ABS_FORMAT(off18));
4210 break;
4211 case OPC2_32_ABS_LDUCX:
4212 gen_helper_1arg(lducx, EA_ABS_FORMAT(off18));
4213 break;
4214 case OPC2_32_ABS_STLCX:
4215 gen_helper_1arg(stlcx, EA_ABS_FORMAT(off18));
4216 break;
4217 case OPC2_32_ABS_STUCX:
4218 gen_helper_1arg(stucx, EA_ABS_FORMAT(off18));
4219 break;
4220 }
4221 }
4222
4223 static void decode_abs_store(CPUTriCoreState *env, DisasContext *ctx)
4224 {
4225 int32_t op2;
4226 int32_t r1;
4227 uint32_t address;
4228 TCGv temp;
4229
4230 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4231 address = MASK_OP_ABS_OFF18(ctx->opcode);
4232 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4233
4234 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4235
4236 switch (op2) {
4237 case OPC2_32_ABS_ST_A:
4238 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LESL);
4239 break;
4240 case OPC2_32_ABS_ST_D:
4241 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4242 break;
4243 case OPC2_32_ABS_ST_DA:
4244 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4245 break;
4246 case OPC2_32_ABS_ST_W:
4247 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LESL);
4248 break;
4249
4250 }
4251 tcg_temp_free(temp);
4252 }
4253
4254 static void decode_abs_storeb_h(CPUTriCoreState *env, DisasContext *ctx)
4255 {
4256 int32_t op2;
4257 int32_t r1;
4258 uint32_t address;
4259 TCGv temp;
4260
4261 r1 = MASK_OP_ABS_S1D(ctx->opcode);
4262 address = MASK_OP_ABS_OFF18(ctx->opcode);
4263 op2 = MASK_OP_ABS_OP2(ctx->opcode);
4264
4265 temp = tcg_const_i32(EA_ABS_FORMAT(address));
4266
4267 switch (op2) {
4268 case OPC2_32_ABS_ST_B:
4269 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_UB);
4270 break;
4271 case OPC2_32_ABS_ST_H:
4272 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
4273 break;
4274 }
4275 tcg_temp_free(temp);
4276 }
4277
4278 /* Bit-format */
4279
4280 static void decode_bit_andacc(CPUTriCoreState *env, DisasContext *ctx)
4281 {
4282 uint32_t op2;
4283 int r1, r2, r3;
4284 int pos1, pos2;
4285
4286 r1 = MASK_OP_BIT_S1(ctx->opcode);
4287 r2 = MASK_OP_BIT_S2(ctx->opcode);
4288 r3 = MASK_OP_BIT_D(ctx->opcode);
4289 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4290 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4291 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4292
4293
4294 switch (op2) {
4295 case OPC2_32_BIT_AND_AND_T:
4296 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4297 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_and_tl);
4298 break;
4299 case OPC2_32_BIT_AND_ANDN_T:
4300 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4301 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_and_tl);
4302 break;
4303 case OPC2_32_BIT_AND_NOR_T:
4304 if (TCG_TARGET_HAS_andc_i32) {
4305 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4306 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_andc_tl);
4307 } else {
4308 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4309 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_and_tl);
4310 }
4311 break;
4312 case OPC2_32_BIT_AND_OR_T:
4313 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4314 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_and_tl);
4315 break;
4316 }
4317 }
4318
4319 static void decode_bit_logical_t(CPUTriCoreState *env, DisasContext *ctx)
4320 {
4321 uint32_t op2;
4322 int r1, r2, r3;
4323 int pos1, pos2;
4324 r1 = MASK_OP_BIT_S1(ctx->opcode);
4325 r2 = MASK_OP_BIT_S2(ctx->opcode);
4326 r3 = MASK_OP_BIT_D(ctx->opcode);
4327 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4328 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4329 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4330
4331 switch (op2) {
4332 case OPC2_32_BIT_AND_T:
4333 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4334 pos1, pos2, &tcg_gen_and_tl);
4335 break;
4336 case OPC2_32_BIT_ANDN_T:
4337 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4338 pos1, pos2, &tcg_gen_andc_tl);
4339 break;
4340 case OPC2_32_BIT_NOR_T:
4341 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4342 pos1, pos2, &tcg_gen_nor_tl);
4343 break;
4344 case OPC2_32_BIT_OR_T:
4345 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4346 pos1, pos2, &tcg_gen_or_tl);
4347 break;
4348 }
4349 }
4350
4351 static void decode_bit_insert(CPUTriCoreState *env, DisasContext *ctx)
4352 {
4353 uint32_t op2;
4354 int r1, r2, r3;
4355 int pos1, pos2;
4356 TCGv temp;
4357 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4358 r1 = MASK_OP_BIT_S1(ctx->opcode);
4359 r2 = MASK_OP_BIT_S2(ctx->opcode);
4360 r3 = MASK_OP_BIT_D(ctx->opcode);
4361 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4362 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4363
4364 temp = tcg_temp_new();
4365
4366 tcg_gen_shri_tl(temp, cpu_gpr_d[r2], pos2);
4367 if (op2 == OPC2_32_BIT_INSN_T) {
4368 tcg_gen_not_tl(temp, temp);
4369 }
4370 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], temp, pos1, 1);
4371 tcg_temp_free(temp);
4372 }
4373
4374 static void decode_bit_logical_t2(CPUTriCoreState *env, DisasContext *ctx)
4375 {
4376 uint32_t op2;
4377
4378 int r1, r2, r3;
4379 int pos1, pos2;
4380
4381 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4382 r1 = MASK_OP_BIT_S1(ctx->opcode);
4383 r2 = MASK_OP_BIT_S2(ctx->opcode);
4384 r3 = MASK_OP_BIT_D(ctx->opcode);
4385 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4386 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4387
4388 switch (op2) {
4389 case OPC2_32_BIT_NAND_T:
4390 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4391 pos1, pos2, &tcg_gen_nand_tl);
4392 break;
4393 case OPC2_32_BIT_ORN_T:
4394 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4395 pos1, pos2, &tcg_gen_orc_tl);
4396 break;
4397 case OPC2_32_BIT_XNOR_T:
4398 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4399 pos1, pos2, &tcg_gen_eqv_tl);
4400 break;
4401 case OPC2_32_BIT_XOR_T:
4402 gen_bit_1op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4403 pos1, pos2, &tcg_gen_xor_tl);
4404 break;
4405 }
4406 }
4407
4408 static void decode_bit_orand(CPUTriCoreState *env, DisasContext *ctx)
4409 {
4410 uint32_t op2;
4411
4412 int r1, r2, r3;
4413 int pos1, pos2;
4414
4415 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4416 r1 = MASK_OP_BIT_S1(ctx->opcode);
4417 r2 = MASK_OP_BIT_S2(ctx->opcode);
4418 r3 = MASK_OP_BIT_D(ctx->opcode);
4419 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4420 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4421
4422 switch (op2) {
4423 case OPC2_32_BIT_OR_AND_T:
4424 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4425 pos1, pos2, &tcg_gen_and_tl, &tcg_gen_or_tl);
4426 break;
4427 case OPC2_32_BIT_OR_ANDN_T:
4428 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4429 pos1, pos2, &tcg_gen_andc_tl, &tcg_gen_or_tl);
4430 break;
4431 case OPC2_32_BIT_OR_NOR_T:
4432 if (TCG_TARGET_HAS_orc_i32) {
4433 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4434 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_orc_tl);
4435 } else {
4436 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4437 pos1, pos2, &tcg_gen_nor_tl, &tcg_gen_or_tl);
4438 }
4439 break;
4440 case OPC2_32_BIT_OR_OR_T:
4441 gen_bit_2op(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
4442 pos1, pos2, &tcg_gen_or_tl, &tcg_gen_or_tl);
4443 break;
4444 }
4445 }
4446
4447 static void decode_bit_sh_logic1(CPUTriCoreState *env, DisasContext *ctx)
4448 {
4449 uint32_t op2;
4450 int r1, r2, r3;
4451 int pos1, pos2;
4452 TCGv temp;
4453
4454 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4455 r1 = MASK_OP_BIT_S1(ctx->opcode);
4456 r2 = MASK_OP_BIT_S2(ctx->opcode);
4457 r3 = MASK_OP_BIT_D(ctx->opcode);
4458 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4459 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4460
4461 temp = tcg_temp_new();
4462
4463 switch (op2) {
4464 case OPC2_32_BIT_SH_AND_T:
4465 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4466 pos1, pos2, &tcg_gen_and_tl);
4467 break;
4468 case OPC2_32_BIT_SH_ANDN_T:
4469 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4470 pos1, pos2, &tcg_gen_andc_tl);
4471 break;
4472 case OPC2_32_BIT_SH_NOR_T:
4473 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4474 pos1, pos2, &tcg_gen_nor_tl);
4475 break;
4476 case OPC2_32_BIT_SH_OR_T:
4477 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4478 pos1, pos2, &tcg_gen_or_tl);
4479 break;
4480 }
4481 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4482 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4483 tcg_temp_free(temp);
4484 }
4485
4486 static void decode_bit_sh_logic2(CPUTriCoreState *env, DisasContext *ctx)
4487 {
4488 uint32_t op2;
4489 int r1, r2, r3;
4490 int pos1, pos2;
4491 TCGv temp;
4492
4493 op2 = MASK_OP_BIT_OP2(ctx->opcode);
4494 r1 = MASK_OP_BIT_S1(ctx->opcode);
4495 r2 = MASK_OP_BIT_S2(ctx->opcode);
4496 r3 = MASK_OP_BIT_D(ctx->opcode);
4497 pos1 = MASK_OP_BIT_POS1(ctx->opcode);
4498 pos2 = MASK_OP_BIT_POS2(ctx->opcode);
4499
4500 temp = tcg_temp_new();
4501
4502 switch (op2) {
4503 case OPC2_32_BIT_SH_NAND_T:
4504 gen_bit_1op(temp, cpu_gpr_d[r1] , cpu_gpr_d[r2] ,
4505 pos1, pos2, &tcg_gen_nand_tl);
4506 break;
4507 case OPC2_32_BIT_SH_ORN_T:
4508 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4509 pos1, pos2, &tcg_gen_orc_tl);
4510 break;
4511 case OPC2_32_BIT_SH_XNOR_T:
4512 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4513 pos1, pos2, &tcg_gen_eqv_tl);
4514 break;
4515 case OPC2_32_BIT_SH_XOR_T:
4516 gen_bit_1op(temp, cpu_gpr_d[r1], cpu_gpr_d[r2],
4517 pos1, pos2, &tcg_gen_xor_tl);
4518 break;
4519 }
4520 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 1);
4521 tcg_gen_add_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
4522 tcg_temp_free(temp);
4523 }
4524
4525 /* BO-format */
4526
4527
4528 static void decode_bo_addrmode_post_pre_base(CPUTriCoreState *env,
4529 DisasContext *ctx)
4530 {
4531 uint32_t op2;
4532 uint32_t off10;
4533 int32_t r1, r2;
4534 TCGv temp;
4535
4536 r1 = MASK_OP_BO_S1D(ctx->opcode);
4537 r2 = MASK_OP_BO_S2(ctx->opcode);
4538 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4539 op2 = MASK_OP_BO_OP2(ctx->opcode);
4540
4541 switch (op2) {
4542 case OPC2_32_BO_CACHEA_WI_SHORTOFF:
4543 case OPC2_32_BO_CACHEA_W_SHORTOFF:
4544 case OPC2_32_BO_CACHEA_I_SHORTOFF:
4545 /* instruction to access the cache */
4546 break;
4547 case OPC2_32_BO_CACHEA_WI_POSTINC:
4548 case OPC2_32_BO_CACHEA_W_POSTINC:
4549 case OPC2_32_BO_CACHEA_I_POSTINC:
4550 /* instruction to access the cache, but we still need to handle
4551 the addressing mode */
4552 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4553 break;
4554 case OPC2_32_BO_CACHEA_WI_PREINC:
4555 case OPC2_32_BO_CACHEA_W_PREINC:
4556 case OPC2_32_BO_CACHEA_I_PREINC:
4557 /* instruction to access the cache, but we still need to handle
4558 the addressing mode */
4559 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4560 break;
4561 case OPC2_32_BO_CACHEI_WI_SHORTOFF:
4562 case OPC2_32_BO_CACHEI_W_SHORTOFF:
4563 /* TODO: Raise illegal opcode trap,
4564 if !tricore_feature(TRICORE_FEATURE_131) */
4565 break;
4566 case OPC2_32_BO_CACHEI_W_POSTINC:
4567 case OPC2_32_BO_CACHEI_WI_POSTINC:
4568 if (tricore_feature(env, TRICORE_FEATURE_131)) {
4569 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4570 } /* TODO: else raise illegal opcode trap */
4571 break;
4572 case OPC2_32_BO_CACHEI_W_PREINC:
4573 case OPC2_32_BO_CACHEI_WI_PREINC:
4574 if (tricore_feature(env, TRICORE_FEATURE_131)) {
4575 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4576 } /* TODO: else raise illegal opcode trap */
4577 break;
4578 case OPC2_32_BO_ST_A_SHORTOFF:
4579 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4580 break;
4581 case OPC2_32_BO_ST_A_POSTINC:
4582 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4583 MO_LESL);
4584 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4585 break;
4586 case OPC2_32_BO_ST_A_PREINC:
4587 gen_st_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LESL);
4588 break;
4589 case OPC2_32_BO_ST_B_SHORTOFF:
4590 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4591 break;
4592 case OPC2_32_BO_ST_B_POSTINC:
4593 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4594 MO_UB);
4595 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4596 break;
4597 case OPC2_32_BO_ST_B_PREINC:
4598 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4599 break;
4600 case OPC2_32_BO_ST_D_SHORTOFF:
4601 gen_offset_st_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4602 off10, ctx);
4603 break;
4604 case OPC2_32_BO_ST_D_POSTINC:
4605 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4606 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4607 break;
4608 case OPC2_32_BO_ST_D_PREINC:
4609 temp = tcg_temp_new();
4610 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4611 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4612 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4613 tcg_temp_free(temp);
4614 break;
4615 case OPC2_32_BO_ST_DA_SHORTOFF:
4616 gen_offset_st_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4617 off10, ctx);
4618 break;
4619 case OPC2_32_BO_ST_DA_POSTINC:
4620 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4621 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4622 break;
4623 case OPC2_32_BO_ST_DA_PREINC:
4624 temp = tcg_temp_new();
4625 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4626 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4627 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4628 tcg_temp_free(temp);
4629 break;
4630 case OPC2_32_BO_ST_H_SHORTOFF:
4631 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4632 break;
4633 case OPC2_32_BO_ST_H_POSTINC:
4634 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4635 MO_LEUW);
4636 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4637 break;
4638 case OPC2_32_BO_ST_H_PREINC:
4639 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4640 break;
4641 case OPC2_32_BO_ST_Q_SHORTOFF:
4642 temp = tcg_temp_new();
4643 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4644 gen_offset_st(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4645 tcg_temp_free(temp);
4646 break;
4647 case OPC2_32_BO_ST_Q_POSTINC:
4648 temp = tcg_temp_new();
4649 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4650 tcg_gen_qemu_st_tl(temp, cpu_gpr_a[r2], ctx->mem_idx,
4651 MO_LEUW);
4652 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4653 tcg_temp_free(temp);
4654 break;
4655 case OPC2_32_BO_ST_Q_PREINC:
4656 temp = tcg_temp_new();
4657 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4658 gen_st_preincr(ctx, temp, cpu_gpr_a[r2], off10, MO_LEUW);
4659 tcg_temp_free(temp);
4660 break;
4661 case OPC2_32_BO_ST_W_SHORTOFF:
4662 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4663 break;
4664 case OPC2_32_BO_ST_W_POSTINC:
4665 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4666 MO_LEUL);
4667 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4668 break;
4669 case OPC2_32_BO_ST_W_PREINC:
4670 gen_st_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4671 break;
4672 }
4673 }
4674
4675 static void decode_bo_addrmode_bitreverse_circular(CPUTriCoreState *env,
4676 DisasContext *ctx)
4677 {
4678 uint32_t op2;
4679 uint32_t off10;
4680 int32_t r1, r2;
4681 TCGv temp, temp2, temp3;
4682
4683 r1 = MASK_OP_BO_S1D(ctx->opcode);
4684 r2 = MASK_OP_BO_S2(ctx->opcode);
4685 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4686 op2 = MASK_OP_BO_OP2(ctx->opcode);
4687
4688 temp = tcg_temp_new();
4689 temp2 = tcg_temp_new();
4690 temp3 = tcg_const_i32(off10);
4691
4692 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4693 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4694
4695 switch (op2) {
4696 case OPC2_32_BO_CACHEA_WI_BR:
4697 case OPC2_32_BO_CACHEA_W_BR:
4698 case OPC2_32_BO_CACHEA_I_BR:
4699 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4700 break;
4701 case OPC2_32_BO_CACHEA_WI_CIRC:
4702 case OPC2_32_BO_CACHEA_W_CIRC:
4703 case OPC2_32_BO_CACHEA_I_CIRC:
4704 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4705 break;
4706 case OPC2_32_BO_ST_A_BR:
4707 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4708 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4709 break;
4710 case OPC2_32_BO_ST_A_CIRC:
4711 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4712 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4713 break;
4714 case OPC2_32_BO_ST_B_BR:
4715 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4716 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4717 break;
4718 case OPC2_32_BO_ST_B_CIRC:
4719 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4720 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4721 break;
4722 case OPC2_32_BO_ST_D_BR:
4723 gen_st_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4724 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4725 break;
4726 case OPC2_32_BO_ST_D_CIRC:
4727 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4728 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4729 tcg_gen_addi_tl(temp, temp, 4);
4730 tcg_gen_rem_tl(temp, temp, temp2);
4731 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4732 tcg_gen_qemu_st_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4733 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4734 break;
4735 case OPC2_32_BO_ST_DA_BR:
4736 gen_st_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4737 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4738 break;
4739 case OPC2_32_BO_ST_DA_CIRC:
4740 tcg_gen_qemu_st_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4741 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4742 tcg_gen_addi_tl(temp, temp, 4);
4743 tcg_gen_rem_tl(temp, temp, temp2);
4744 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4745 tcg_gen_qemu_st_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4746 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4747 break;
4748 case OPC2_32_BO_ST_H_BR:
4749 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4750 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4751 break;
4752 case OPC2_32_BO_ST_H_CIRC:
4753 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4754 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4755 break;
4756 case OPC2_32_BO_ST_Q_BR:
4757 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4758 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4759 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4760 break;
4761 case OPC2_32_BO_ST_Q_CIRC:
4762 tcg_gen_shri_tl(temp, cpu_gpr_d[r1], 16);
4763 tcg_gen_qemu_st_tl(temp, temp2, ctx->mem_idx, MO_LEUW);
4764 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4765 break;
4766 case OPC2_32_BO_ST_W_BR:
4767 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4768 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4769 break;
4770 case OPC2_32_BO_ST_W_CIRC:
4771 tcg_gen_qemu_st_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4772 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4773 break;
4774 }
4775 tcg_temp_free(temp);
4776 tcg_temp_free(temp2);
4777 tcg_temp_free(temp3);
4778 }
4779
4780 static void decode_bo_addrmode_ld_post_pre_base(CPUTriCoreState *env,
4781 DisasContext *ctx)
4782 {
4783 uint32_t op2;
4784 uint32_t off10;
4785 int32_t r1, r2;
4786 TCGv temp;
4787
4788 r1 = MASK_OP_BO_S1D(ctx->opcode);
4789 r2 = MASK_OP_BO_S2(ctx->opcode);
4790 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4791 op2 = MASK_OP_BO_OP2(ctx->opcode);
4792
4793 switch (op2) {
4794 case OPC2_32_BO_LD_A_SHORTOFF:
4795 gen_offset_ld(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4796 break;
4797 case OPC2_32_BO_LD_A_POSTINC:
4798 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx,
4799 MO_LEUL);
4800 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4801 break;
4802 case OPC2_32_BO_LD_A_PREINC:
4803 gen_ld_preincr(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4804 break;
4805 case OPC2_32_BO_LD_B_SHORTOFF:
4806 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4807 break;
4808 case OPC2_32_BO_LD_B_POSTINC:
4809 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4810 MO_SB);
4811 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4812 break;
4813 case OPC2_32_BO_LD_B_PREINC:
4814 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4815 break;
4816 case OPC2_32_BO_LD_BU_SHORTOFF:
4817 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_UB);
4818 break;
4819 case OPC2_32_BO_LD_BU_POSTINC:
4820 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4821 MO_UB);
4822 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4823 break;
4824 case OPC2_32_BO_LD_BU_PREINC:
4825 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_SB);
4826 break;
4827 case OPC2_32_BO_LD_D_SHORTOFF:
4828 gen_offset_ld_2regs(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2],
4829 off10, ctx);
4830 break;
4831 case OPC2_32_BO_LD_D_POSTINC:
4832 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], cpu_gpr_a[r2], ctx);
4833 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4834 break;
4835 case OPC2_32_BO_LD_D_PREINC:
4836 temp = tcg_temp_new();
4837 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4838 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp, ctx);
4839 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4840 tcg_temp_free(temp);
4841 break;
4842 case OPC2_32_BO_LD_DA_SHORTOFF:
4843 gen_offset_ld_2regs(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2],
4844 off10, ctx);
4845 break;
4846 case OPC2_32_BO_LD_DA_POSTINC:
4847 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], cpu_gpr_a[r2], ctx);
4848 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4849 break;
4850 case OPC2_32_BO_LD_DA_PREINC:
4851 temp = tcg_temp_new();
4852 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
4853 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp, ctx);
4854 tcg_gen_mov_tl(cpu_gpr_a[r2], temp);
4855 tcg_temp_free(temp);
4856 break;
4857 case OPC2_32_BO_LD_H_SHORTOFF:
4858 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4859 break;
4860 case OPC2_32_BO_LD_H_POSTINC:
4861 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4862 MO_LESW);
4863 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4864 break;
4865 case OPC2_32_BO_LD_H_PREINC:
4866 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LESW);
4867 break;
4868 case OPC2_32_BO_LD_HU_SHORTOFF:
4869 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4870 break;
4871 case OPC2_32_BO_LD_HU_POSTINC:
4872 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4873 MO_LEUW);
4874 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4875 break;
4876 case OPC2_32_BO_LD_HU_PREINC:
4877 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4878 break;
4879 case OPC2_32_BO_LD_Q_SHORTOFF:
4880 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4881 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4882 break;
4883 case OPC2_32_BO_LD_Q_POSTINC:
4884 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4885 MO_LEUW);
4886 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4887 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4888 break;
4889 case OPC2_32_BO_LD_Q_PREINC:
4890 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUW);
4891 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4892 break;
4893 case OPC2_32_BO_LD_W_SHORTOFF:
4894 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4895 break;
4896 case OPC2_32_BO_LD_W_POSTINC:
4897 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], cpu_gpr_a[r2], ctx->mem_idx,
4898 MO_LEUL);
4899 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
4900 break;
4901 case OPC2_32_BO_LD_W_PREINC:
4902 gen_ld_preincr(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], off10, MO_LEUL);
4903 break;
4904 }
4905 }
4906
4907 static void decode_bo_addrmode_ld_bitreverse_circular(CPUTriCoreState *env,
4908 DisasContext *ctx)
4909 {
4910 uint32_t op2;
4911 uint32_t off10;
4912 int r1, r2;
4913
4914 TCGv temp, temp2, temp3;
4915
4916 r1 = MASK_OP_BO_S1D(ctx->opcode);
4917 r2 = MASK_OP_BO_S2(ctx->opcode);
4918 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
4919 op2 = MASK_OP_BO_OP2(ctx->opcode);
4920
4921 temp = tcg_temp_new();
4922 temp2 = tcg_temp_new();
4923 temp3 = tcg_const_i32(off10);
4924
4925 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
4926 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4927
4928
4929 switch (op2) {
4930 case OPC2_32_BO_LD_A_BR:
4931 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4932 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4933 break;
4934 case OPC2_32_BO_LD_A_CIRC:
4935 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4936 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4937 break;
4938 case OPC2_32_BO_LD_B_BR:
4939 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4940 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4941 break;
4942 case OPC2_32_BO_LD_B_CIRC:
4943 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_SB);
4944 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4945 break;
4946 case OPC2_32_BO_LD_BU_BR:
4947 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4948 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4949 break;
4950 case OPC2_32_BO_LD_BU_CIRC:
4951 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_UB);
4952 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4953 break;
4954 case OPC2_32_BO_LD_D_BR:
4955 gen_ld_2regs_64(cpu_gpr_d[r1+1], cpu_gpr_d[r1], temp2, ctx);
4956 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4957 break;
4958 case OPC2_32_BO_LD_D_CIRC:
4959 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
4960 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4961 tcg_gen_addi_tl(temp, temp, 4);
4962 tcg_gen_rem_tl(temp, temp, temp2);
4963 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4964 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4965 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4966 break;
4967 case OPC2_32_BO_LD_DA_BR:
4968 gen_ld_2regs_64(cpu_gpr_a[r1+1], cpu_gpr_a[r1], temp2, ctx);
4969 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4970 break;
4971 case OPC2_32_BO_LD_DA_CIRC:
4972 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp2, ctx->mem_idx, MO_LEUL);
4973 tcg_gen_shri_tl(temp2, cpu_gpr_a[r2+1], 16);
4974 tcg_gen_addi_tl(temp, temp, 4);
4975 tcg_gen_rem_tl(temp, temp, temp2);
4976 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
4977 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1+1], temp2, ctx->mem_idx, MO_LEUL);
4978 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4979 break;
4980 case OPC2_32_BO_LD_H_BR:
4981 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4982 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4983 break;
4984 case OPC2_32_BO_LD_H_CIRC:
4985 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LESW);
4986 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4987 break;
4988 case OPC2_32_BO_LD_HU_BR:
4989 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4990 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
4991 break;
4992 case OPC2_32_BO_LD_HU_CIRC:
4993 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4994 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
4995 break;
4996 case OPC2_32_BO_LD_Q_BR:
4997 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
4998 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
4999 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5000 break;
5001 case OPC2_32_BO_LD_Q_CIRC:
5002 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUW);
5003 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
5004 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5005 break;
5006 case OPC2_32_BO_LD_W_BR:
5007 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
5008 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5009 break;
5010 case OPC2_32_BO_LD_W_CIRC:
5011 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp2, ctx->mem_idx, MO_LEUL);
5012 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5013 break;
5014 }
5015 tcg_temp_free(temp);
5016 tcg_temp_free(temp2);
5017 tcg_temp_free(temp3);
5018 }
5019
5020 static void decode_bo_addrmode_stctx_post_pre_base(CPUTriCoreState *env,
5021 DisasContext *ctx)
5022 {
5023 uint32_t op2;
5024 uint32_t off10;
5025 int r1, r2;
5026
5027 TCGv temp, temp2;
5028
5029 r1 = MASK_OP_BO_S1D(ctx->opcode);
5030 r2 = MASK_OP_BO_S2(ctx->opcode);
5031 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
5032 op2 = MASK_OP_BO_OP2(ctx->opcode);
5033
5034
5035 temp = tcg_temp_new();
5036 temp2 = tcg_temp_new();
5037
5038 switch (op2) {
5039 case OPC2_32_BO_LDLCX_SHORTOFF:
5040 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5041 gen_helper_ldlcx(cpu_env, temp);
5042 break;
5043 case OPC2_32_BO_LDMST_SHORTOFF:
5044 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5045 gen_ldmst(ctx, r1, temp);
5046 break;
5047 case OPC2_32_BO_LDMST_POSTINC:
5048 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
5049 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5050 break;
5051 case OPC2_32_BO_LDMST_PREINC:
5052 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5053 gen_ldmst(ctx, r1, cpu_gpr_a[r2]);
5054 break;
5055 case OPC2_32_BO_LDUCX_SHORTOFF:
5056 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5057 gen_helper_lducx(cpu_env, temp);
5058 break;
5059 case OPC2_32_BO_LEA_SHORTOFF:
5060 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], off10);
5061 break;
5062 case OPC2_32_BO_STLCX_SHORTOFF:
5063 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5064 gen_helper_stlcx(cpu_env, temp);
5065 break;
5066 case OPC2_32_BO_STUCX_SHORTOFF:
5067 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5068 gen_helper_stucx(cpu_env, temp);
5069 break;
5070 case OPC2_32_BO_SWAP_W_SHORTOFF:
5071 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5072 gen_swap(ctx, r1, temp);
5073 break;
5074 case OPC2_32_BO_SWAP_W_POSTINC:
5075 gen_swap(ctx, r1, cpu_gpr_a[r2]);
5076 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5077 break;
5078 case OPC2_32_BO_SWAP_W_PREINC:
5079 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5080 gen_swap(ctx, r1, cpu_gpr_a[r2]);
5081 break;
5082 case OPC2_32_BO_CMPSWAP_W_SHORTOFF:
5083 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5084 gen_cmpswap(ctx, r1, temp);
5085 break;
5086 case OPC2_32_BO_CMPSWAP_W_POSTINC:
5087 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
5088 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5089 break;
5090 case OPC2_32_BO_CMPSWAP_W_PREINC:
5091 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5092 gen_cmpswap(ctx, r1, cpu_gpr_a[r2]);
5093 break;
5094 case OPC2_32_BO_SWAPMSK_W_SHORTOFF:
5095 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], off10);
5096 gen_swapmsk(ctx, r1, temp);
5097 break;
5098 case OPC2_32_BO_SWAPMSK_W_POSTINC:
5099 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
5100 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5101 break;
5102 case OPC2_32_BO_SWAPMSK_W_PREINC:
5103 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10);
5104 gen_swapmsk(ctx, r1, cpu_gpr_a[r2]);
5105 break;
5106 }
5107 tcg_temp_free(temp);
5108 tcg_temp_free(temp2);
5109 }
5110
5111 static void decode_bo_addrmode_ldmst_bitreverse_circular(CPUTriCoreState *env,
5112 DisasContext *ctx)
5113 {
5114 uint32_t op2;
5115 uint32_t off10;
5116 int r1, r2;
5117
5118 TCGv temp, temp2, temp3;
5119
5120 r1 = MASK_OP_BO_S1D(ctx->opcode);
5121 r2 = MASK_OP_BO_S2(ctx->opcode);
5122 off10 = MASK_OP_BO_OFF10_SEXT(ctx->opcode);
5123 op2 = MASK_OP_BO_OP2(ctx->opcode);
5124
5125 temp = tcg_temp_new();
5126 temp2 = tcg_temp_new();
5127 temp3 = tcg_const_i32(off10);
5128
5129 tcg_gen_ext16u_tl(temp, cpu_gpr_a[r2+1]);
5130 tcg_gen_add_tl(temp2, cpu_gpr_a[r2], temp);
5131
5132 switch (op2) {
5133 case OPC2_32_BO_LDMST_BR:
5134 gen_ldmst(ctx, r1, temp2);
5135 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5136 break;
5137 case OPC2_32_BO_LDMST_CIRC:
5138 gen_ldmst(ctx, r1, temp2);
5139 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5140 break;
5141 case OPC2_32_BO_SWAP_W_BR:
5142 gen_swap(ctx, r1, temp2);
5143 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5144 break;
5145 case OPC2_32_BO_SWAP_W_CIRC:
5146 gen_swap(ctx, r1, temp2);
5147 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5148 break;
5149 case OPC2_32_BO_CMPSWAP_W_BR:
5150 gen_cmpswap(ctx, r1, temp2);
5151 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5152 break;
5153 case OPC2_32_BO_CMPSWAP_W_CIRC:
5154 gen_cmpswap(ctx, r1, temp2);
5155 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5156 break;
5157 case OPC2_32_BO_SWAPMSK_W_BR:
5158 gen_swapmsk(ctx, r1, temp2);
5159 gen_helper_br_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1]);
5160 break;
5161 case OPC2_32_BO_SWAPMSK_W_CIRC:
5162 gen_swapmsk(ctx, r1, temp2);
5163 gen_helper_circ_update(cpu_gpr_a[r2+1], cpu_gpr_a[r2+1], temp3);
5164 break;
5165 }
5166
5167 tcg_temp_free(temp);
5168 tcg_temp_free(temp2);
5169 tcg_temp_free(temp3);
5170 }
5171
5172 static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1)
5173 {
5174 int r1, r2;
5175 int32_t address;
5176 TCGv temp;
5177
5178 r1 = MASK_OP_BOL_S1D(ctx->opcode);
5179 r2 = MASK_OP_BOL_S2(ctx->opcode);
5180 address = MASK_OP_BOL_OFF16_SEXT(ctx->opcode);
5181
5182 switch (op1) {
5183 case OPC1_32_BOL_LD_A_LONGOFF:
5184 temp = tcg_temp_new();
5185 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
5186 tcg_gen_qemu_ld_tl(cpu_gpr_a[r1], temp, ctx->mem_idx, MO_LEUL);
5187 tcg_temp_free(temp);
5188 break;
5189 case OPC1_32_BOL_LD_W_LONGOFF:
5190 temp = tcg_temp_new();
5191 tcg_gen_addi_tl(temp, cpu_gpr_a[r2], address);
5192 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUL);
5193 tcg_temp_free(temp);
5194 break;
5195 case OPC1_32_BOL_LEA_LONGOFF:
5196 tcg_gen_addi_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], address);
5197 break;
5198 case OPC1_32_BOL_ST_A_LONGOFF:
5199 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5200 gen_offset_st(ctx, cpu_gpr_a[r1], cpu_gpr_a[r2], address, MO_LEUL);
5201 } else {
5202 /* raise illegal opcode trap */
5203 }
5204 break;
5205 case OPC1_32_BOL_ST_W_LONGOFF:
5206 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUL);
5207 break;
5208 case OPC1_32_BOL_LD_B_LONGOFF:
5209 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5210 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
5211 } else {
5212 /* raise illegal opcode trap */
5213 }
5214 break;
5215 case OPC1_32_BOL_LD_BU_LONGOFF:
5216 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5217 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_UB);
5218 } else {
5219 /* raise illegal opcode trap */
5220 }
5221 break;
5222 case OPC1_32_BOL_LD_H_LONGOFF:
5223 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5224 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
5225 } else {
5226 /* raise illegal opcode trap */
5227 }
5228 break;
5229 case OPC1_32_BOL_LD_HU_LONGOFF:
5230 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5231 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LEUW);
5232 } else {
5233 /* raise illegal opcode trap */
5234 }
5235 break;
5236 case OPC1_32_BOL_ST_B_LONGOFF:
5237 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5238 gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_SB);
5239 } else {
5240 /* raise illegal opcode trap */
5241 }
5242 break;
5243 case OPC1_32_BOL_ST_H_LONGOFF:
5244 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5245 gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW);
5246 } else {
5247 /* raise illegal opcode trap */
5248 }
5249 break;
5250 }
5251 }
5252
5253 /* RC format */
5254 static void decode_rc_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
5255 {
5256 uint32_t op2;
5257 int r1, r2;
5258 int32_t const9;
5259 TCGv temp;
5260
5261 r2 = MASK_OP_RC_D(ctx->opcode);
5262 r1 = MASK_OP_RC_S1(ctx->opcode);
5263 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5264 op2 = MASK_OP_RC_OP2(ctx->opcode);
5265
5266 temp = tcg_temp_new();
5267
5268 switch (op2) {
5269 case OPC2_32_RC_AND:
5270 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5271 break;
5272 case OPC2_32_RC_ANDN:
5273 tcg_gen_andi_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
5274 break;
5275 case OPC2_32_RC_NAND:
5276 tcg_gen_movi_tl(temp, const9);
5277 tcg_gen_nand_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
5278 break;
5279 case OPC2_32_RC_NOR:
5280 tcg_gen_movi_tl(temp, const9);
5281 tcg_gen_nor_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp);
5282 break;
5283 case OPC2_32_RC_OR:
5284 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5285 break;
5286 case OPC2_32_RC_ORN:
5287 tcg_gen_ori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], ~const9);
5288 break;
5289 case OPC2_32_RC_SH:
5290 const9 = sextract32(const9, 0, 6);
5291 gen_shi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5292 break;
5293 case OPC2_32_RC_SH_H:
5294 const9 = sextract32(const9, 0, 5);
5295 gen_sh_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5296 break;
5297 case OPC2_32_RC_SHA:
5298 const9 = sextract32(const9, 0, 6);
5299 gen_shaci(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5300 break;
5301 case OPC2_32_RC_SHA_H:
5302 const9 = sextract32(const9, 0, 5);
5303 gen_sha_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5304 break;
5305 case OPC2_32_RC_SHAS:
5306 gen_shasi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5307 break;
5308 case OPC2_32_RC_XNOR:
5309 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5310 tcg_gen_not_tl(cpu_gpr_d[r2], cpu_gpr_d[r2]);
5311 break;
5312 case OPC2_32_RC_XOR:
5313 tcg_gen_xori_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5314 break;
5315 }
5316 tcg_temp_free(temp);
5317 }
5318
5319 static void decode_rc_accumulator(CPUTriCoreState *env, DisasContext *ctx)
5320 {
5321 uint32_t op2;
5322 int r1, r2;
5323 int16_t const9;
5324
5325 TCGv temp;
5326
5327 r2 = MASK_OP_RC_D(ctx->opcode);
5328 r1 = MASK_OP_RC_S1(ctx->opcode);
5329 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5330
5331 op2 = MASK_OP_RC_OP2(ctx->opcode);
5332
5333 temp = tcg_temp_new();
5334
5335 switch (op2) {
5336 case OPC2_32_RC_ABSDIF:
5337 gen_absdifi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5338 break;
5339 case OPC2_32_RC_ABSDIFS:
5340 gen_absdifsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5341 break;
5342 case OPC2_32_RC_ADD:
5343 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5344 break;
5345 case OPC2_32_RC_ADDC:
5346 gen_addci_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5347 break;
5348 case OPC2_32_RC_ADDS:
5349 gen_addsi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5350 break;
5351 case OPC2_32_RC_ADDS_U:
5352 gen_addsui(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5353 break;
5354 case OPC2_32_RC_ADDX:
5355 gen_addi_CC(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5356 break;
5357 case OPC2_32_RC_AND_EQ:
5358 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5359 const9, &tcg_gen_and_tl);
5360 break;
5361 case OPC2_32_RC_AND_GE:
5362 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5363 const9, &tcg_gen_and_tl);
5364 break;
5365 case OPC2_32_RC_AND_GE_U:
5366 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5367 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5368 const9, &tcg_gen_and_tl);
5369 break;
5370 case OPC2_32_RC_AND_LT:
5371 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5372 const9, &tcg_gen_and_tl);
5373 break;
5374 case OPC2_32_RC_AND_LT_U:
5375 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5376 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5377 const9, &tcg_gen_and_tl);
5378 break;
5379 case OPC2_32_RC_AND_NE:
5380 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5381 const9, &tcg_gen_and_tl);
5382 break;
5383 case OPC2_32_RC_EQ:
5384 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5385 break;
5386 case OPC2_32_RC_EQANY_B:
5387 gen_eqany_bi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5388 break;
5389 case OPC2_32_RC_EQANY_H:
5390 gen_eqany_hi(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5391 break;
5392 case OPC2_32_RC_GE:
5393 tcg_gen_setcondi_tl(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5394 break;
5395 case OPC2_32_RC_GE_U:
5396 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5397 tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5398 break;
5399 case OPC2_32_RC_LT:
5400 tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5401 break;
5402 case OPC2_32_RC_LT_U:
5403 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5404 tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5405 break;
5406 case OPC2_32_RC_MAX:
5407 tcg_gen_movi_tl(temp, const9);
5408 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5409 cpu_gpr_d[r1], temp);
5410 break;
5411 case OPC2_32_RC_MAX_U:
5412 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5413 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5414 cpu_gpr_d[r1], temp);
5415 break;
5416 case OPC2_32_RC_MIN:
5417 tcg_gen_movi_tl(temp, const9);
5418 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5419 cpu_gpr_d[r1], temp);
5420 break;
5421 case OPC2_32_RC_MIN_U:
5422 tcg_gen_movi_tl(temp, MASK_OP_RC_CONST9(ctx->opcode));
5423 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], temp,
5424 cpu_gpr_d[r1], temp);
5425 break;
5426 case OPC2_32_RC_NE:
5427 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5428 break;
5429 case OPC2_32_RC_OR_EQ:
5430 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5431 const9, &tcg_gen_or_tl);
5432 break;
5433 case OPC2_32_RC_OR_GE:
5434 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5435 const9, &tcg_gen_or_tl);
5436 break;
5437 case OPC2_32_RC_OR_GE_U:
5438 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5439 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5440 const9, &tcg_gen_or_tl);
5441 break;
5442 case OPC2_32_RC_OR_LT:
5443 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5444 const9, &tcg_gen_or_tl);
5445 break;
5446 case OPC2_32_RC_OR_LT_U:
5447 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5448 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5449 const9, &tcg_gen_or_tl);
5450 break;
5451 case OPC2_32_RC_OR_NE:
5452 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5453 const9, &tcg_gen_or_tl);
5454 break;
5455 case OPC2_32_RC_RSUB:
5456 tcg_gen_movi_tl(temp, const9);
5457 gen_sub_d(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5458 break;
5459 case OPC2_32_RC_RSUBS:
5460 tcg_gen_movi_tl(temp, const9);
5461 gen_subs(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5462 break;
5463 case OPC2_32_RC_RSUBS_U:
5464 tcg_gen_movi_tl(temp, const9);
5465 gen_subsu(cpu_gpr_d[r2], temp, cpu_gpr_d[r1]);
5466 break;
5467 case OPC2_32_RC_SH_EQ:
5468 gen_sh_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5469 break;
5470 case OPC2_32_RC_SH_GE:
5471 gen_sh_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5472 break;
5473 case OPC2_32_RC_SH_GE_U:
5474 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5475 gen_sh_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5476 break;
5477 case OPC2_32_RC_SH_LT:
5478 gen_sh_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5479 break;
5480 case OPC2_32_RC_SH_LT_U:
5481 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5482 gen_sh_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5483 break;
5484 case OPC2_32_RC_SH_NE:
5485 gen_sh_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5486 break;
5487 case OPC2_32_RC_XOR_EQ:
5488 gen_accumulating_condi(TCG_COND_EQ, cpu_gpr_d[r2], cpu_gpr_d[r1],
5489 const9, &tcg_gen_xor_tl);
5490 break;
5491 case OPC2_32_RC_XOR_GE:
5492 gen_accumulating_condi(TCG_COND_GE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5493 const9, &tcg_gen_xor_tl);
5494 break;
5495 case OPC2_32_RC_XOR_GE_U:
5496 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5497 gen_accumulating_condi(TCG_COND_GEU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5498 const9, &tcg_gen_xor_tl);
5499 break;
5500 case OPC2_32_RC_XOR_LT:
5501 gen_accumulating_condi(TCG_COND_LT, cpu_gpr_d[r2], cpu_gpr_d[r1],
5502 const9, &tcg_gen_xor_tl);
5503 break;
5504 case OPC2_32_RC_XOR_LT_U:
5505 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5506 gen_accumulating_condi(TCG_COND_LTU, cpu_gpr_d[r2], cpu_gpr_d[r1],
5507 const9, &tcg_gen_xor_tl);
5508 break;
5509 case OPC2_32_RC_XOR_NE:
5510 gen_accumulating_condi(TCG_COND_NE, cpu_gpr_d[r2], cpu_gpr_d[r1],
5511 const9, &tcg_gen_xor_tl);
5512 break;
5513 }
5514 tcg_temp_free(temp);
5515 }
5516
5517 static void decode_rc_serviceroutine(CPUTriCoreState *env, DisasContext *ctx)
5518 {
5519 uint32_t op2;
5520 uint32_t const9;
5521
5522 op2 = MASK_OP_RC_OP2(ctx->opcode);
5523 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5524
5525 switch (op2) {
5526 case OPC2_32_RC_BISR:
5527 gen_helper_1arg(bisr, const9);
5528 break;
5529 case OPC2_32_RC_SYSCALL:
5530 /* TODO: Add exception generation */
5531 break;
5532 }
5533 }
5534
5535 static void decode_rc_mul(CPUTriCoreState *env, DisasContext *ctx)
5536 {
5537 uint32_t op2;
5538 int r1, r2;
5539 int16_t const9;
5540
5541 r2 = MASK_OP_RC_D(ctx->opcode);
5542 r1 = MASK_OP_RC_S1(ctx->opcode);
5543 const9 = MASK_OP_RC_CONST9_SEXT(ctx->opcode);
5544
5545 op2 = MASK_OP_RC_OP2(ctx->opcode);
5546
5547 switch (op2) {
5548 case OPC2_32_RC_MUL_32:
5549 gen_muli_i32s(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5550 break;
5551 case OPC2_32_RC_MUL_64:
5552 gen_muli_i64s(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5553 break;
5554 case OPC2_32_RC_MULS_32:
5555 gen_mulsi_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5556 break;
5557 case OPC2_32_RC_MUL_U_64:
5558 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5559 gen_muli_i64u(cpu_gpr_d[r2], cpu_gpr_d[r2+1], cpu_gpr_d[r1], const9);
5560 break;
5561 case OPC2_32_RC_MULS_U_32:
5562 const9 = MASK_OP_RC_CONST9(ctx->opcode);
5563 gen_mulsui_i32(cpu_gpr_d[r2], cpu_gpr_d[r1], const9);
5564 break;
5565 }
5566 }
5567
5568 /* RCPW format */
5569 static void decode_rcpw_insert(CPUTriCoreState *env, DisasContext *ctx)
5570 {
5571 uint32_t op2;
5572 int r1, r2;
5573 int32_t pos, width, const4;
5574
5575 TCGv temp;
5576
5577 op2 = MASK_OP_RCPW_OP2(ctx->opcode);
5578 r1 = MASK_OP_RCPW_S1(ctx->opcode);
5579 r2 = MASK_OP_RCPW_D(ctx->opcode);
5580 const4 = MASK_OP_RCPW_CONST4(ctx->opcode);
5581 width = MASK_OP_RCPW_WIDTH(ctx->opcode);
5582 pos = MASK_OP_RCPW_POS(ctx->opcode);
5583
5584 switch (op2) {
5585 case OPC2_32_RCPW_IMASK:
5586 /* if pos + width > 31 undefined result */
5587 if (pos + width <= 31) {
5588 tcg_gen_movi_tl(cpu_gpr_d[r2+1], ((1u << width) - 1) << pos);
5589 tcg_gen_movi_tl(cpu_gpr_d[r2], (const4 << pos));
5590 }
5591 break;
5592 case OPC2_32_RCPW_INSERT:
5593 /* if pos + width > 32 undefined result */
5594 if (pos + width <= 32) {
5595 temp = tcg_const_i32(const4);
5596 tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
5597 tcg_temp_free(temp);
5598 }
5599 break;
5600 }
5601 }
5602
5603 /* RCRW format */
5604
5605 static void decode_rcrw_insert(CPUTriCoreState *env, DisasContext *ctx)
5606 {
5607 uint32_t op2;
5608 int r1, r3, r4;
5609 int32_t width, const4;
5610
5611 TCGv temp, temp2, temp3;
5612
5613 op2 = MASK_OP_RCRW_OP2(ctx->opcode);
5614 r1 = MASK_OP_RCRW_S1(ctx->opcode);
5615 r3 = MASK_OP_RCRW_S3(ctx->opcode);
5616 r4 = MASK_OP_RCRW_D(ctx->opcode);
5617 width = MASK_OP_RCRW_WIDTH(ctx->opcode);
5618 const4 = MASK_OP_RCRW_CONST4(ctx->opcode);
5619
5620 temp = tcg_temp_new();
5621 temp2 = tcg_temp_new();
5622
5623 switch (op2) {
5624 case OPC2_32_RCRW_IMASK:
5625 tcg_gen_andi_tl(temp, cpu_gpr_d[r4], 0x1f);
5626 tcg_gen_movi_tl(temp2, (1 << width) - 1);
5627 tcg_gen_shl_tl(cpu_gpr_d[r3 + 1], temp2, temp);
5628 tcg_gen_movi_tl(temp2, const4);
5629 tcg_gen_shl_tl(cpu_gpr_d[r3], temp2, temp);
5630 break;
5631 case OPC2_32_RCRW_INSERT:
5632 temp3 = tcg_temp_new();
5633
5634 tcg_gen_movi_tl(temp, width);
5635 tcg_gen_movi_tl(temp2, const4);
5636 tcg_gen_andi_tl(temp3, cpu_gpr_d[r4], 0x1f);
5637 gen_insert(cpu_gpr_d[r3], cpu_gpr_d[r1], temp2, temp, temp3);
5638
5639 tcg_temp_free(temp3);
5640 break;
5641 }
5642 tcg_temp_free(temp);
5643 tcg_temp_free(temp2);
5644 }
5645
5646 /* RCR format */
5647
5648 static void decode_rcr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
5649 {
5650 uint32_t op2;
5651 int r1, r3, r4;
5652 int32_t const9;
5653
5654 TCGv temp, temp2;
5655
5656 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5657 r1 = MASK_OP_RCR_S1(ctx->opcode);
5658 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5659 r3 = MASK_OP_RCR_S3(ctx->opcode);
5660 r4 = MASK_OP_RCR_D(ctx->opcode);
5661
5662 switch (op2) {
5663 case OPC2_32_RCR_CADD:
5664 gen_condi_add(TCG_COND_NE, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
5665 cpu_gpr_d[r4]);
5666 break;
5667 case OPC2_32_RCR_CADDN:
5668 gen_condi_add(TCG_COND_EQ, cpu_gpr_d[r1], const9, cpu_gpr_d[r3],
5669 cpu_gpr_d[r4]);
5670 break;
5671 case OPC2_32_RCR_SEL:
5672 temp = tcg_const_i32(0);
5673 temp2 = tcg_const_i32(const9);
5674 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5675 cpu_gpr_d[r1], temp2);
5676 tcg_temp_free(temp);
5677 tcg_temp_free(temp2);
5678 break;
5679 case OPC2_32_RCR_SELN:
5680 temp = tcg_const_i32(0);
5681 temp2 = tcg_const_i32(const9);
5682 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
5683 cpu_gpr_d[r1], temp2);
5684 tcg_temp_free(temp);
5685 tcg_temp_free(temp2);
5686 break;
5687 }
5688 }
5689
5690 static void decode_rcr_madd(CPUTriCoreState *env, DisasContext *ctx)
5691 {
5692 uint32_t op2;
5693 int r1, r3, r4;
5694 int32_t const9;
5695
5696
5697 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5698 r1 = MASK_OP_RCR_S1(ctx->opcode);
5699 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5700 r3 = MASK_OP_RCR_S3(ctx->opcode);
5701 r4 = MASK_OP_RCR_D(ctx->opcode);
5702
5703 switch (op2) {
5704 case OPC2_32_RCR_MADD_32:
5705 gen_maddi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5706 break;
5707 case OPC2_32_RCR_MADD_64:
5708 gen_maddi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5709 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5710 break;
5711 case OPC2_32_RCR_MADDS_32:
5712 gen_maddsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5713 break;
5714 case OPC2_32_RCR_MADDS_64:
5715 gen_maddsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5716 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5717 break;
5718 case OPC2_32_RCR_MADD_U_64:
5719 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5720 gen_maddui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5721 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5722 break;
5723 case OPC2_32_RCR_MADDS_U_32:
5724 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5725 gen_maddsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5726 break;
5727 case OPC2_32_RCR_MADDS_U_64:
5728 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5729 gen_maddsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5730 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5731 break;
5732 }
5733 }
5734
5735 static void decode_rcr_msub(CPUTriCoreState *env, DisasContext *ctx)
5736 {
5737 uint32_t op2;
5738 int r1, r3, r4;
5739 int32_t const9;
5740
5741
5742 op2 = MASK_OP_RCR_OP2(ctx->opcode);
5743 r1 = MASK_OP_RCR_S1(ctx->opcode);
5744 const9 = MASK_OP_RCR_CONST9_SEXT(ctx->opcode);
5745 r3 = MASK_OP_RCR_S3(ctx->opcode);
5746 r4 = MASK_OP_RCR_D(ctx->opcode);
5747
5748 switch (op2) {
5749 case OPC2_32_RCR_MSUB_32:
5750 gen_msubi32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5751 break;
5752 case OPC2_32_RCR_MSUB_64:
5753 gen_msubi64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5754 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5755 break;
5756 case OPC2_32_RCR_MSUBS_32:
5757 gen_msubsi_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5758 break;
5759 case OPC2_32_RCR_MSUBS_64:
5760 gen_msubsi_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5761 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5762 break;
5763 case OPC2_32_RCR_MSUB_U_64:
5764 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5765 gen_msubui64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5766 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5767 break;
5768 case OPC2_32_RCR_MSUBS_U_32:
5769 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5770 gen_msubsui_32(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3], const9);
5771 break;
5772 case OPC2_32_RCR_MSUBS_U_64:
5773 const9 = MASK_OP_RCR_CONST9(ctx->opcode);
5774 gen_msubsui_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
5775 cpu_gpr_d[r3], cpu_gpr_d[r3+1], const9);
5776 break;
5777 }
5778 }
5779
5780 /* RLC format */
5781
5782 static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx,
5783 uint32_t op1)
5784 {
5785 int32_t const16;
5786 int r1, r2;
5787
5788 const16 = MASK_OP_RLC_CONST16_SEXT(ctx->opcode);
5789 r1 = MASK_OP_RLC_S1(ctx->opcode);
5790 r2 = MASK_OP_RLC_D(ctx->opcode);
5791
5792 switch (op1) {
5793 case OPC1_32_RLC_ADDI:
5794 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16);
5795 break;
5796 case OPC1_32_RLC_ADDIH:
5797 gen_addi_d(cpu_gpr_d[r2], cpu_gpr_d[r1], const16 << 16);
5798 break;
5799 case OPC1_32_RLC_ADDIH_A:
5800 tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r1], const16 << 16);
5801 break;
5802 case OPC1_32_RLC_MFCR:
5803 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5804 gen_mfcr(env, cpu_gpr_d[r2], const16);
5805 break;
5806 case OPC1_32_RLC_MOV:
5807 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5808 break;
5809 case OPC1_32_RLC_MOV_64:
5810 if (tricore_feature(env, TRICORE_FEATURE_16)) {
5811 if ((r2 & 0x1) != 0) {
5812 /* TODO: raise OPD trap */
5813 }
5814 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5815 tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15);
5816 } else {
5817 /* TODO: raise illegal opcode trap */
5818 }
5819 break;
5820 case OPC1_32_RLC_MOV_U:
5821 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5822 tcg_gen_movi_tl(cpu_gpr_d[r2], const16);
5823 break;
5824 case OPC1_32_RLC_MOV_H:
5825 tcg_gen_movi_tl(cpu_gpr_d[r2], const16 << 16);
5826 break;
5827 case OPC1_32_RLC_MOVH_A:
5828 tcg_gen_movi_tl(cpu_gpr_a[r2], const16 << 16);
5829 break;
5830 case OPC1_32_RLC_MTCR:
5831 const16 = MASK_OP_RLC_CONST16(ctx->opcode);
5832 gen_mtcr(env, ctx, cpu_gpr_d[r1], const16);
5833 break;
5834 }
5835 }
5836
5837 /* RR format */
5838 static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx)
5839 {
5840 uint32_t op2;
5841 int r3, r2, r1;
5842
5843 r3 = MASK_OP_RR_D(ctx->opcode);
5844 r2 = MASK_OP_RR_S2(ctx->opcode);
5845 r1 = MASK_OP_RR_S1(ctx->opcode);
5846 op2 = MASK_OP_RR_OP2(ctx->opcode);
5847
5848 switch (op2) {
5849 case OPC2_32_RR_ABS:
5850 gen_abs(cpu_gpr_d[r3], cpu_gpr_d[r2]);
5851 break;
5852 case OPC2_32_RR_ABS_B:
5853 gen_helper_abs_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5854 break;
5855 case OPC2_32_RR_ABS_H:
5856 gen_helper_abs_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5857 break;
5858 case OPC2_32_RR_ABSDIF:
5859 gen_absdif(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5860 break;
5861 case OPC2_32_RR_ABSDIF_B:
5862 gen_helper_absdif_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5863 cpu_gpr_d[r2]);
5864 break;
5865 case OPC2_32_RR_ABSDIF_H:
5866 gen_helper_absdif_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5867 cpu_gpr_d[r2]);
5868 break;
5869 case OPC2_32_RR_ABSDIFS:
5870 gen_helper_absdif_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5871 cpu_gpr_d[r2]);
5872 break;
5873 case OPC2_32_RR_ABSDIFS_H:
5874 gen_helper_absdif_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5875 cpu_gpr_d[r2]);
5876 break;
5877 case OPC2_32_RR_ABSS:
5878 gen_helper_abs_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5879 break;
5880 case OPC2_32_RR_ABSS_H:
5881 gen_helper_abs_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r2]);
5882 break;
5883 case OPC2_32_RR_ADD:
5884 gen_add_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5885 break;
5886 case OPC2_32_RR_ADD_B:
5887 gen_helper_add_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5888 break;
5889 case OPC2_32_RR_ADD_H:
5890 gen_helper_add_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
5891 break;
5892 case OPC2_32_RR_ADDC:
5893 gen_addc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5894 break;
5895 case OPC2_32_RR_ADDS:
5896 gen_adds(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5897 break;
5898 case OPC2_32_RR_ADDS_H:
5899 gen_helper_add_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5900 cpu_gpr_d[r2]);
5901 break;
5902 case OPC2_32_RR_ADDS_HU:
5903 gen_helper_add_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5904 cpu_gpr_d[r2]);
5905 break;
5906 case OPC2_32_RR_ADDS_U:
5907 gen_helper_add_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
5908 cpu_gpr_d[r2]);
5909 break;
5910 case OPC2_32_RR_ADDX:
5911 gen_add_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5912 break;
5913 case OPC2_32_RR_AND_EQ:
5914 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5915 cpu_gpr_d[r2], &tcg_gen_and_tl);
5916 break;
5917 case OPC2_32_RR_AND_GE:
5918 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5919 cpu_gpr_d[r2], &tcg_gen_and_tl);
5920 break;
5921 case OPC2_32_RR_AND_GE_U:
5922 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5923 cpu_gpr_d[r2], &tcg_gen_and_tl);
5924 break;
5925 case OPC2_32_RR_AND_LT:
5926 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5927 cpu_gpr_d[r2], &tcg_gen_and_tl);
5928 break;
5929 case OPC2_32_RR_AND_LT_U:
5930 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5931 cpu_gpr_d[r2], &tcg_gen_and_tl);
5932 break;
5933 case OPC2_32_RR_AND_NE:
5934 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5935 cpu_gpr_d[r2], &tcg_gen_and_tl);
5936 break;
5937 case OPC2_32_RR_EQ:
5938 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
5939 cpu_gpr_d[r2]);
5940 break;
5941 case OPC2_32_RR_EQ_B:
5942 gen_helper_eq_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5943 break;
5944 case OPC2_32_RR_EQ_H:
5945 gen_helper_eq_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5946 break;
5947 case OPC2_32_RR_EQ_W:
5948 gen_cond_w(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5949 break;
5950 case OPC2_32_RR_EQANY_B:
5951 gen_helper_eqany_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5952 break;
5953 case OPC2_32_RR_EQANY_H:
5954 gen_helper_eqany_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5955 break;
5956 case OPC2_32_RR_GE:
5957 tcg_gen_setcond_tl(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
5958 cpu_gpr_d[r2]);
5959 break;
5960 case OPC2_32_RR_GE_U:
5961 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5962 cpu_gpr_d[r2]);
5963 break;
5964 case OPC2_32_RR_LT:
5965 tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5966 cpu_gpr_d[r2]);
5967 break;
5968 case OPC2_32_RR_LT_U:
5969 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5970 cpu_gpr_d[r2]);
5971 break;
5972 case OPC2_32_RR_LT_B:
5973 gen_helper_lt_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5974 break;
5975 case OPC2_32_RR_LT_BU:
5976 gen_helper_lt_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5977 break;
5978 case OPC2_32_RR_LT_H:
5979 gen_helper_lt_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5980 break;
5981 case OPC2_32_RR_LT_HU:
5982 gen_helper_lt_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5983 break;
5984 case OPC2_32_RR_LT_W:
5985 gen_cond_w(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5986 break;
5987 case OPC2_32_RR_LT_WU:
5988 gen_cond_w(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5989 break;
5990 case OPC2_32_RR_MAX:
5991 tcg_gen_movcond_tl(TCG_COND_GT, cpu_gpr_d[r3], cpu_gpr_d[r1],
5992 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5993 break;
5994 case OPC2_32_RR_MAX_U:
5995 tcg_gen_movcond_tl(TCG_COND_GTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
5996 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
5997 break;
5998 case OPC2_32_RR_MAX_B:
5999 gen_helper_max_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6000 break;
6001 case OPC2_32_RR_MAX_BU:
6002 gen_helper_max_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6003 break;
6004 case OPC2_32_RR_MAX_H:
6005 gen_helper_max_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6006 break;
6007 case OPC2_32_RR_MAX_HU:
6008 gen_helper_max_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6009 break;
6010 case OPC2_32_RR_MIN:
6011 tcg_gen_movcond_tl(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6012 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6013 break;
6014 case OPC2_32_RR_MIN_U:
6015 tcg_gen_movcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6016 cpu_gpr_d[r2], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6017 break;
6018 case OPC2_32_RR_MIN_B:
6019 gen_helper_min_b(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6020 break;
6021 case OPC2_32_RR_MIN_BU:
6022 gen_helper_min_bu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6023 break;
6024 case OPC2_32_RR_MIN_H:
6025 gen_helper_min_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6026 break;
6027 case OPC2_32_RR_MIN_HU:
6028 gen_helper_min_hu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6029 break;
6030 case OPC2_32_RR_MOV:
6031 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]);
6032 break;
6033 case OPC2_32_RR_NE:
6034 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6035 cpu_gpr_d[r2]);
6036 break;
6037 case OPC2_32_RR_OR_EQ:
6038 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6039 cpu_gpr_d[r2], &tcg_gen_or_tl);
6040 break;
6041 case OPC2_32_RR_OR_GE:
6042 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6043 cpu_gpr_d[r2], &tcg_gen_or_tl);
6044 break;
6045 case OPC2_32_RR_OR_GE_U:
6046 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6047 cpu_gpr_d[r2], &tcg_gen_or_tl);
6048 break;
6049 case OPC2_32_RR_OR_LT:
6050 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6051 cpu_gpr_d[r2], &tcg_gen_or_tl);
6052 break;
6053 case OPC2_32_RR_OR_LT_U:
6054 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6055 cpu_gpr_d[r2], &tcg_gen_or_tl);
6056 break;
6057 case OPC2_32_RR_OR_NE:
6058 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6059 cpu_gpr_d[r2], &tcg_gen_or_tl);
6060 break;
6061 case OPC2_32_RR_SAT_B:
6062 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7f, -0x80);
6063 break;
6064 case OPC2_32_RR_SAT_BU:
6065 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xff);
6066 break;
6067 case OPC2_32_RR_SAT_H:
6068 gen_saturate(cpu_gpr_d[r3], cpu_gpr_d[r1], 0x7fff, -0x8000);
6069 break;
6070 case OPC2_32_RR_SAT_HU:
6071 gen_saturate_u(cpu_gpr_d[r3], cpu_gpr_d[r1], 0xffff);
6072 break;
6073 case OPC2_32_RR_SH_EQ:
6074 gen_sh_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6075 cpu_gpr_d[r2]);
6076 break;
6077 case OPC2_32_RR_SH_GE:
6078 gen_sh_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6079 cpu_gpr_d[r2]);
6080 break;
6081 case OPC2_32_RR_SH_GE_U:
6082 gen_sh_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6083 cpu_gpr_d[r2]);
6084 break;
6085 case OPC2_32_RR_SH_LT:
6086 gen_sh_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6087 cpu_gpr_d[r2]);
6088 break;
6089 case OPC2_32_RR_SH_LT_U:
6090 gen_sh_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6091 cpu_gpr_d[r2]);
6092 break;
6093 case OPC2_32_RR_SH_NE:
6094 gen_sh_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6095 cpu_gpr_d[r2]);
6096 break;
6097 case OPC2_32_RR_SUB:
6098 gen_sub_d(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6099 break;
6100 case OPC2_32_RR_SUB_B:
6101 gen_helper_sub_b(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6102 break;
6103 case OPC2_32_RR_SUB_H:
6104 gen_helper_sub_h(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6105 break;
6106 case OPC2_32_RR_SUBC:
6107 gen_subc_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6108 break;
6109 case OPC2_32_RR_SUBS:
6110 gen_subs(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6111 break;
6112 case OPC2_32_RR_SUBS_U:
6113 gen_subsu(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6114 break;
6115 case OPC2_32_RR_SUBS_H:
6116 gen_helper_sub_h_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6117 cpu_gpr_d[r2]);
6118 break;
6119 case OPC2_32_RR_SUBS_HU:
6120 gen_helper_sub_h_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6121 cpu_gpr_d[r2]);
6122 break;
6123 case OPC2_32_RR_SUBX:
6124 gen_sub_CC(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6125 break;
6126 case OPC2_32_RR_XOR_EQ:
6127 gen_accumulating_cond(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_d[r1],
6128 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6129 break;
6130 case OPC2_32_RR_XOR_GE:
6131 gen_accumulating_cond(TCG_COND_GE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6132 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6133 break;
6134 case OPC2_32_RR_XOR_GE_U:
6135 gen_accumulating_cond(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6136 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6137 break;
6138 case OPC2_32_RR_XOR_LT:
6139 gen_accumulating_cond(TCG_COND_LT, cpu_gpr_d[r3], cpu_gpr_d[r1],
6140 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6141 break;
6142 case OPC2_32_RR_XOR_LT_U:
6143 gen_accumulating_cond(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_d[r1],
6144 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6145 break;
6146 case OPC2_32_RR_XOR_NE:
6147 gen_accumulating_cond(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1],
6148 cpu_gpr_d[r2], &tcg_gen_xor_tl);
6149 break;
6150 }
6151 }
6152
6153 static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx)
6154 {
6155 uint32_t op2;
6156 int r3, r2, r1;
6157 TCGv temp;
6158
6159 r3 = MASK_OP_RR_D(ctx->opcode);
6160 r2 = MASK_OP_RR_S2(ctx->opcode);
6161 r1 = MASK_OP_RR_S1(ctx->opcode);
6162
6163 temp = tcg_temp_new();
6164 op2 = MASK_OP_RR_OP2(ctx->opcode);
6165
6166 switch (op2) {
6167 case OPC2_32_RR_AND:
6168 tcg_gen_and_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6169 break;
6170 case OPC2_32_RR_ANDN:
6171 tcg_gen_andc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6172 break;
6173 case OPC2_32_RR_CLO:
6174 gen_helper_clo(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6175 break;
6176 case OPC2_32_RR_CLO_H:
6177 gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6178 break;
6179 case OPC2_32_RR_CLS:
6180 gen_helper_cls(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6181 break;
6182 case OPC2_32_RR_CLS_H:
6183 gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6184 break;
6185 case OPC2_32_RR_CLZ:
6186 gen_helper_clz(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6187 break;
6188 case OPC2_32_RR_CLZ_H:
6189 gen_helper_clz_h(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6190 break;
6191 case OPC2_32_RR_NAND:
6192 tcg_gen_nand_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6193 break;
6194 case OPC2_32_RR_NOR:
6195 tcg_gen_nor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6196 break;
6197 case OPC2_32_RR_OR:
6198 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6199 break;
6200 case OPC2_32_RR_ORN:
6201 tcg_gen_orc_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6202 break;
6203 case OPC2_32_RR_SH:
6204 gen_helper_sh(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6205 break;
6206 case OPC2_32_RR_SH_H:
6207 gen_helper_sh_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6208 break;
6209 case OPC2_32_RR_SHA:
6210 gen_helper_sha(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
6211 break;
6212 case OPC2_32_RR_SHA_H:
6213 gen_helper_sha_h(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6214 break;
6215 case OPC2_32_RR_SHAS:
6216 gen_shas(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6217 break;
6218 case OPC2_32_RR_XNOR:
6219 tcg_gen_eqv_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6220 break;
6221 case OPC2_32_RR_XOR:
6222 tcg_gen_xor_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6223 break;
6224 }
6225 tcg_temp_free(temp);
6226 }
6227
6228 static void decode_rr_address(CPUTriCoreState *env, DisasContext *ctx)
6229 {
6230 uint32_t op2, n;
6231 int r1, r2, r3;
6232 TCGv temp;
6233
6234 op2 = MASK_OP_RR_OP2(ctx->opcode);
6235 r3 = MASK_OP_RR_D(ctx->opcode);
6236 r2 = MASK_OP_RR_S2(ctx->opcode);
6237 r1 = MASK_OP_RR_S1(ctx->opcode);
6238 n = MASK_OP_RR_N(ctx->opcode);
6239
6240 switch (op2) {
6241 case OPC2_32_RR_ADD_A:
6242 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6243 break;
6244 case OPC2_32_RR_ADDSC_A:
6245 temp = tcg_temp_new();
6246 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], n);
6247 tcg_gen_add_tl(cpu_gpr_a[r3], cpu_gpr_a[r2], temp);
6248 tcg_temp_free(temp);
6249 break;
6250 case OPC2_32_RR_ADDSC_AT:
6251 temp = tcg_temp_new();
6252 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 3);
6253 tcg_gen_add_tl(temp, cpu_gpr_a[r2], temp);
6254 tcg_gen_andi_tl(cpu_gpr_a[r3], temp, 0xFFFFFFFC);
6255 tcg_temp_free(temp);
6256 break;
6257 case OPC2_32_RR_EQ_A:
6258 tcg_gen_setcond_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1],
6259 cpu_gpr_a[r2]);
6260 break;
6261 case OPC2_32_RR_EQZ:
6262 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6263 break;
6264 case OPC2_32_RR_GE_A:
6265 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6266 cpu_gpr_a[r2]);
6267 break;
6268 case OPC2_32_RR_LT_A:
6269 tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr_d[r3], cpu_gpr_a[r1],
6270 cpu_gpr_a[r2]);
6271 break;
6272 case OPC2_32_RR_MOV_A:
6273 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_d[r2]);
6274 break;
6275 case OPC2_32_RR_MOV_AA:
6276 tcg_gen_mov_tl(cpu_gpr_a[r3], cpu_gpr_a[r2]);
6277 break;
6278 case OPC2_32_RR_MOV_D:
6279 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_a[r2]);
6280 break;
6281 case OPC2_32_RR_NE_A:
6282 tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1],
6283 cpu_gpr_a[r2]);
6284 break;
6285 case OPC2_32_RR_NEZ_A:
6286 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_a[r1], 0);
6287 break;
6288 case OPC2_32_RR_SUB_A:
6289 tcg_gen_sub_tl(cpu_gpr_a[r3], cpu_gpr_a[r1], cpu_gpr_a[r2]);
6290 break;
6291 }
6292 }
6293
6294 static void decode_rr_idirect(CPUTriCoreState *env, DisasContext *ctx)
6295 {
6296 uint32_t op2;
6297 int r1;
6298
6299 op2 = MASK_OP_RR_OP2(ctx->opcode);
6300 r1 = MASK_OP_RR_S1(ctx->opcode);
6301
6302 switch (op2) {
6303 case OPC2_32_RR_JI:
6304 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6305 break;
6306 case OPC2_32_RR_JLI:
6307 tcg_gen_movi_tl(cpu_gpr_a[11], ctx->next_pc);
6308 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6309 break;
6310 case OPC2_32_RR_CALLI:
6311 gen_helper_1arg(call, ctx->next_pc);
6312 tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], ~0x1);
6313 break;
6314 }
6315 tcg_gen_exit_tb(0);
6316 ctx->bstate = BS_BRANCH;
6317 }
6318
6319 static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx)
6320 {
6321 uint32_t op2;
6322 int r1, r2, r3;
6323
6324 TCGv temp, temp2, temp3;
6325
6326 op2 = MASK_OP_RR_OP2(ctx->opcode);
6327 r3 = MASK_OP_RR_D(ctx->opcode);
6328 r2 = MASK_OP_RR_S2(ctx->opcode);
6329 r1 = MASK_OP_RR_S1(ctx->opcode);
6330
6331 switch (op2) {
6332 case OPC2_32_RR_BMERGE:
6333 gen_helper_bmerge(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6334 break;
6335 case OPC2_32_RR_BSPLIT:
6336 gen_bsplit(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6337 break;
6338 case OPC2_32_RR_DVINIT_B:
6339 gen_dvinit_b(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6340 cpu_gpr_d[r2]);
6341 break;
6342 case OPC2_32_RR_DVINIT_BU:
6343 temp = tcg_temp_new();
6344 temp2 = tcg_temp_new();
6345 temp3 = tcg_temp_new();
6346
6347 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 8);
6348 /* reset av */
6349 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6350 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
6351 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6352 tcg_gen_neg_tl(temp, temp3);
6353 /* use cpu_PSW_AV to compare against 0 */
6354 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
6355 temp, temp3);
6356 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
6357 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
6358 temp2, cpu_gpr_d[r2]);
6359 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6360 } else {
6361 /* overflow = (D[b] == 0) */
6362 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6363 }
6364 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6365 /* sv */
6366 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6367 /* write result */
6368 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 24);
6369 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6370
6371 tcg_temp_free(temp);
6372 tcg_temp_free(temp2);
6373 tcg_temp_free(temp3);
6374 break;
6375 case OPC2_32_RR_DVINIT_H:
6376 gen_dvinit_h(env, cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6377 cpu_gpr_d[r2]);
6378 break;
6379 case OPC2_32_RR_DVINIT_HU:
6380 temp = tcg_temp_new();
6381 temp2 = tcg_temp_new();
6382 temp3 = tcg_temp_new();
6383
6384 tcg_gen_shri_tl(temp3, cpu_gpr_d[r1], 16);
6385 /* reset av */
6386 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6387 if (!tricore_feature(env, TRICORE_FEATURE_131)) {
6388 /* overflow = (abs(D[r3+1]) >= abs(D[r2])) */
6389 tcg_gen_neg_tl(temp, temp3);
6390 /* use cpu_PSW_AV to compare against 0 */
6391 tcg_gen_movcond_tl(TCG_COND_LT, temp, temp3, cpu_PSW_AV,
6392 temp, temp3);
6393 tcg_gen_neg_tl(temp2, cpu_gpr_d[r2]);
6394 tcg_gen_movcond_tl(TCG_COND_LT, temp2, cpu_gpr_d[r2], cpu_PSW_AV,
6395 temp2, cpu_gpr_d[r2]);
6396 tcg_gen_setcond_tl(TCG_COND_GE, cpu_PSW_V, temp, temp2);
6397 } else {
6398 /* overflow = (D[b] == 0) */
6399 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6400 }
6401 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6402 /* sv */
6403 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6404 /* write result */
6405 tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3);
6406 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16);
6407 tcg_temp_free(temp);
6408 tcg_temp_free(temp2);
6409 tcg_temp_free(temp3);
6410 break;
6411 case OPC2_32_RR_DVINIT:
6412 temp = tcg_temp_new();
6413 temp2 = tcg_temp_new();
6414 /* overflow = ((D[b] == 0) ||
6415 ((D[b] == 0xFFFFFFFF) && (D[a] == 0x80000000))) */
6416 tcg_gen_setcondi_tl(TCG_COND_EQ, temp, cpu_gpr_d[r2], 0xffffffff);
6417 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r1], 0x80000000);
6418 tcg_gen_and_tl(temp, temp, temp2);
6419 tcg_gen_setcondi_tl(TCG_COND_EQ, temp2, cpu_gpr_d[r2], 0);
6420 tcg_gen_or_tl(cpu_PSW_V, temp, temp2);
6421 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6422 /* sv */
6423 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6424 /* reset av */
6425 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6426 /* write result */
6427 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6428 /* sign extend to high reg */
6429 tcg_gen_sari_tl(cpu_gpr_d[r3+1], cpu_gpr_d[r1], 31);
6430 tcg_temp_free(temp);
6431 tcg_temp_free(temp2);
6432 break;
6433 case OPC2_32_RR_DVINIT_U:
6434 /* overflow = (D[b] == 0) */
6435 tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_PSW_V, cpu_gpr_d[r2], 0);
6436 tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31);
6437 /* sv */
6438 tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V);
6439 /* reset av */
6440 tcg_gen_movi_tl(cpu_PSW_AV, 0);
6441 /* write result */
6442 tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6443 /* zero extend to high reg*/
6444 tcg_gen_movi_tl(cpu_gpr_d[r3+1], 0);
6445 break;
6446 case OPC2_32_RR_PARITY:
6447 gen_helper_parity(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6448 break;
6449 case OPC2_32_RR_UNPACK:
6450 gen_unpack(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6451 break;
6452 }
6453 }
6454
6455 /* RR1 Format */
6456 static void decode_rr1_mul(CPUTriCoreState *env, DisasContext *ctx)
6457 {
6458 uint32_t op2;
6459
6460 int r1, r2, r3;
6461 TCGv n;
6462 TCGv_i64 temp64;
6463
6464 r1 = MASK_OP_RR1_S1(ctx->opcode);
6465 r2 = MASK_OP_RR1_S2(ctx->opcode);
6466 r3 = MASK_OP_RR1_D(ctx->opcode);
6467 n = tcg_const_i32(MASK_OP_RR1_N(ctx->opcode));
6468 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6469
6470 switch (op2) {
6471 case OPC2_32_RR1_MUL_H_32_LL:
6472 temp64 = tcg_temp_new_i64();
6473 GEN_HELPER_LL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6474 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6475 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6476 tcg_temp_free_i64(temp64);
6477 break;
6478 case OPC2_32_RR1_MUL_H_32_LU:
6479 temp64 = tcg_temp_new_i64();
6480 GEN_HELPER_LU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6481 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6482 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6483 tcg_temp_free_i64(temp64);
6484 break;
6485 case OPC2_32_RR1_MUL_H_32_UL:
6486 temp64 = tcg_temp_new_i64();
6487 GEN_HELPER_UL(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6488 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6489 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6490 tcg_temp_free_i64(temp64);
6491 break;
6492 case OPC2_32_RR1_MUL_H_32_UU:
6493 temp64 = tcg_temp_new_i64();
6494 GEN_HELPER_UU(mul_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6495 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6496 gen_calc_usb_mul_h(cpu_gpr_d[r3], cpu_gpr_d[r3+1]);
6497 tcg_temp_free_i64(temp64);
6498 break;
6499 case OPC2_32_RR1_MULM_H_64_LL:
6500 temp64 = tcg_temp_new_i64();
6501 GEN_HELPER_LL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6502 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6503 /* reset V bit */
6504 tcg_gen_movi_tl(cpu_PSW_V, 0);
6505 /* reset AV bit */
6506 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6507 tcg_temp_free_i64(temp64);
6508 break;
6509 case OPC2_32_RR1_MULM_H_64_LU:
6510 temp64 = tcg_temp_new_i64();
6511 GEN_HELPER_LU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6512 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6513 /* reset V bit */
6514 tcg_gen_movi_tl(cpu_PSW_V, 0);
6515 /* reset AV bit */
6516 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6517 tcg_temp_free_i64(temp64);
6518 break;
6519 case OPC2_32_RR1_MULM_H_64_UL:
6520 temp64 = tcg_temp_new_i64();
6521 GEN_HELPER_UL(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6522 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6523 /* reset V bit */
6524 tcg_gen_movi_tl(cpu_PSW_V, 0);
6525 /* reset AV bit */
6526 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6527 tcg_temp_free_i64(temp64);
6528 break;
6529 case OPC2_32_RR1_MULM_H_64_UU:
6530 temp64 = tcg_temp_new_i64();
6531 GEN_HELPER_UU(mulm_h, temp64, cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6532 tcg_gen_extr_i64_i32(cpu_gpr_d[r3], cpu_gpr_d[r3+1], temp64);
6533 /* reset V bit */
6534 tcg_gen_movi_tl(cpu_PSW_V, 0);
6535 /* reset AV bit */
6536 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
6537 tcg_temp_free_i64(temp64);
6538
6539 break;
6540 case OPC2_32_RR1_MULR_H_16_LL:
6541 GEN_HELPER_LL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6542 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6543 break;
6544 case OPC2_32_RR1_MULR_H_16_LU:
6545 GEN_HELPER_LU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6546 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6547 break;
6548 case OPC2_32_RR1_MULR_H_16_UL:
6549 GEN_HELPER_UL(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6550 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6551 break;
6552 case OPC2_32_RR1_MULR_H_16_UU:
6553 GEN_HELPER_UU(mulr_h, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2], n);
6554 gen_calc_usb_mulr_h(cpu_gpr_d[r3]);
6555 break;
6556 }
6557 tcg_temp_free(n);
6558 }
6559
6560 static void decode_rr1_mulq(CPUTriCoreState *env, DisasContext *ctx)
6561 {
6562 uint32_t op2;
6563 int r1, r2, r3;
6564 uint32_t n;
6565
6566 TCGv temp, temp2;
6567
6568 r1 = MASK_OP_RR1_S1(ctx->opcode);
6569 r2 = MASK_OP_RR1_S2(ctx->opcode);
6570 r3 = MASK_OP_RR1_D(ctx->opcode);
6571 n = MASK_OP_RR1_N(ctx->opcode);
6572 op2 = MASK_OP_RR1_OP2(ctx->opcode);
6573
6574 temp = tcg_temp_new();
6575 temp2 = tcg_temp_new();
6576
6577 switch (op2) {
6578 case OPC2_32_RR1_MUL_Q_32:
6579 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], cpu_gpr_d[r2], n, 32);
6580 break;
6581 case OPC2_32_RR1_MUL_Q_64:
6582 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
6583 n, 0);
6584 break;
6585 case OPC2_32_RR1_MUL_Q_32_L:
6586 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6587 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6588 break;
6589 case OPC2_32_RR1_MUL_Q_64_L:
6590 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
6591 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6592 break;
6593 case OPC2_32_RR1_MUL_Q_32_U:
6594 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6595 gen_mul_q(cpu_gpr_d[r3], temp, cpu_gpr_d[r1], temp, n, 16);
6596 break;
6597 case OPC2_32_RR1_MUL_Q_64_U:
6598 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
6599 gen_mul_q(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp, n, 0);
6600 break;
6601 case OPC2_32_RR1_MUL_Q_32_LL:
6602 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6603 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6604 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6605 break;
6606 case OPC2_32_RR1_MUL_Q_32_UU:
6607 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6608 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6609 gen_mul_q_16(cpu_gpr_d[r3], temp, temp2, n);
6610 break;
6611 case OPC2_32_RR1_MULR_Q_32_L:
6612 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
6613 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
6614 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6615 break;
6616 case OPC2_32_RR1_MULR_Q_32_U:
6617 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
6618 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
6619 gen_mulr_q(cpu_gpr_d[r3], temp, temp2, n);
6620 break;
6621 }
6622 tcg_temp_free(temp);
6623 tcg_temp_free(temp2);
6624 }
6625
6626 /* RR2 format */
6627 static void decode_rr2_mul(CPUTriCoreState *env, DisasContext *ctx)
6628 {
6629 uint32_t op2;
6630 int r1, r2, r3;
6631
6632 op2 = MASK_OP_RR2_OP2(ctx->opcode);
6633 r1 = MASK_OP_RR2_S1(ctx->opcode);
6634 r2 = MASK_OP_RR2_S2(ctx->opcode);
6635 r3 = MASK_OP_RR2_D(ctx->opcode);
6636 switch (op2) {
6637 case OPC2_32_RR2_MUL_32:
6638 gen_mul_i32s(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]);
6639 break;
6640 case OPC2_32_RR2_MUL_64:
6641 gen_mul_i64s(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6642 cpu_gpr_d[r2]);
6643 break;
6644 case OPC2_32_RR2_MULS_32:
6645 gen_helper_mul_ssov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6646 cpu_gpr_d[r2]);
6647 break;
6648 case OPC2_32_RR2_MUL_U_64:
6649 gen_mul_i64u(cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r1],
6650 cpu_gpr_d[r2]);
6651 break;
6652 case OPC2_32_RR2_MULS_U_32:
6653 gen_helper_mul_suov(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1],
6654 cpu_gpr_d[r2]);
6655 break;
6656 }
6657 }
6658
6659 /* RRPW format */
6660 static void decode_rrpw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
6661 {
6662 uint32_t op2;
6663 int r1, r2, r3;
6664 int32_t pos, width;
6665
6666 op2 = MASK_OP_RRPW_OP2(ctx->opcode);
6667 r1 = MASK_OP_RRPW_S1(ctx->opcode);
6668 r2 = MASK_OP_RRPW_S2(ctx->opcode);
6669 r3 = MASK_OP_RRPW_D(ctx->opcode);
6670 pos = MASK_OP_RRPW_POS(ctx->opcode);
6671 width = MASK_OP_RRPW_WIDTH(ctx->opcode);
6672
6673 switch (op2) {
6674 case OPC2_32_RRPW_EXTR:
6675 if (pos + width <= 31) {
6676 /* optimize special cases */
6677 if ((pos == 0) && (width == 8)) {
6678 tcg_gen_ext8s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6679 } else if ((pos == 0) && (width == 16)) {
6680 tcg_gen_ext16s_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
6681 } else {
6682 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 32 - pos - width);
6683 tcg_gen_sari_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], 32 - width);
6684 }
6685 }
6686 break;
6687 case OPC2_32_RRPW_EXTR_U:
6688 if (width == 0) {
6689 tcg_gen_movi_tl(cpu_gpr_d[r3], 0);
6690 } else {
6691 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], pos);
6692 tcg_gen_andi_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], ~0u >> (32-width));
6693 }
6694 break;
6695 case OPC2_32_RRPW_IMASK:
6696 if (pos + width <= 31) {
6697 tcg_gen_movi_tl(cpu_gpr_d[r3+1], ((1u << width) - 1) << pos);
6698 tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], pos);
6699 }
6700 break;
6701 case OPC2_32_RRPW_INSERT:
6702 if (pos + width <= 31) {
6703 tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
6704 width, pos);
6705 }
6706 break;
6707 }
6708 }
6709
6710 /* RRR format */
6711 static void decode_rrr_cond_select(CPUTriCoreState *env, DisasContext *ctx)
6712 {
6713 uint32_t op2;
6714 int r1, r2, r3, r4;
6715 TCGv temp;
6716
6717 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6718 r1 = MASK_OP_RRR_S1(ctx->opcode);
6719 r2 = MASK_OP_RRR_S2(ctx->opcode);
6720 r3 = MASK_OP_RRR_S3(ctx->opcode);
6721 r4 = MASK_OP_RRR_D(ctx->opcode);
6722
6723 switch (op2) {
6724 case OPC2_32_RRR_CADD:
6725 gen_cond_add(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2],
6726 cpu_gpr_d[r4], cpu_gpr_d[r3]);
6727 break;
6728 case OPC2_32_RRR_CADDN:
6729 gen_cond_add(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6730 cpu_gpr_d[r3]);
6731 break;
6732 case OPC2_32_RRR_CSUB:
6733 gen_cond_sub(TCG_COND_NE, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6734 cpu_gpr_d[r3]);
6735 break;
6736 case OPC2_32_RRR_CSUBN:
6737 gen_cond_sub(TCG_COND_EQ, cpu_gpr_d[r1], cpu_gpr_d[r2], cpu_gpr_d[r4],
6738 cpu_gpr_d[r3]);
6739 break;
6740 case OPC2_32_RRR_SEL:
6741 temp = tcg_const_i32(0);
6742 tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6743 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6744 tcg_temp_free(temp);
6745 break;
6746 case OPC2_32_RRR_SELN:
6747 temp = tcg_const_i32(0);
6748 tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr_d[r4], cpu_gpr_d[r3], temp,
6749 cpu_gpr_d[r1], cpu_gpr_d[r2]);
6750 tcg_temp_free(temp);
6751 break;
6752 }
6753 }
6754
6755 static void decode_rrr_divide(CPUTriCoreState *env, DisasContext *ctx)
6756 {
6757 uint32_t op2;
6758
6759 int r1, r2, r3, r4;
6760
6761 op2 = MASK_OP_RRR_OP2(ctx->opcode);
6762 r1 = MASK_OP_RRR_S1(ctx->opcode);
6763 r2 = MASK_OP_RRR_S2(ctx->opcode);
6764 r3 = MASK_OP_RRR_S3(ctx->opcode);
6765 r4 = MASK_OP_RRR_D(ctx->opcode);
6766
6767 switch (op2) {
6768 case OPC2_32_RRR_DVADJ:
6769 GEN_HELPER_RRR(dvadj, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6770 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6771 break;
6772 case OPC2_32_RRR_DVSTEP:
6773 GEN_HELPER_RRR(dvstep, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6774 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6775 break;
6776 case OPC2_32_RRR_DVSTEP_U:
6777 GEN_HELPER_RRR(dvstep_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6778 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6779 break;
6780 case OPC2_32_RRR_IXMAX:
6781 GEN_HELPER_RRR(ixmax, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6782 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6783 break;
6784 case OPC2_32_RRR_IXMAX_U:
6785 GEN_HELPER_RRR(ixmax_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6786 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6787 break;
6788 case OPC2_32_RRR_IXMIN:
6789 GEN_HELPER_RRR(ixmin, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6790 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6791 break;
6792 case OPC2_32_RRR_IXMIN_U:
6793 GEN_HELPER_RRR(ixmin_u, cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6794 cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6795 break;
6796 case OPC2_32_RRR_PACK:
6797 gen_helper_pack(cpu_gpr_d[r4], cpu_PSW_C, cpu_gpr_d[r3],
6798 cpu_gpr_d[r3+1], cpu_gpr_d[r1]);
6799 break;
6800 }
6801 }
6802
6803 /* RRR2 format */
6804 static void decode_rrr2_madd(CPUTriCoreState *env, DisasContext *ctx)
6805 {
6806 uint32_t op2;
6807 uint32_t r1, r2, r3, r4;
6808
6809 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6810 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6811 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6812 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6813 r4 = MASK_OP_RRR2_D(ctx->opcode);
6814 switch (op2) {
6815 case OPC2_32_RRR2_MADD_32:
6816 gen_madd32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6817 cpu_gpr_d[r2]);
6818 break;
6819 case OPC2_32_RRR2_MADD_64:
6820 gen_madd64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6821 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6822 break;
6823 case OPC2_32_RRR2_MADDS_32:
6824 gen_helper_madd32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6825 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6826 break;
6827 case OPC2_32_RRR2_MADDS_64:
6828 gen_madds_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6829 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6830 break;
6831 case OPC2_32_RRR2_MADD_U_64:
6832 gen_maddu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6833 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6834 break;
6835 case OPC2_32_RRR2_MADDS_U_32:
6836 gen_helper_madd32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6837 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6838 break;
6839 case OPC2_32_RRR2_MADDS_U_64:
6840 gen_maddsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6841 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6842 break;
6843 }
6844 }
6845
6846 static void decode_rrr2_msub(CPUTriCoreState *env, DisasContext *ctx)
6847 {
6848 uint32_t op2;
6849 uint32_t r1, r2, r3, r4;
6850
6851 op2 = MASK_OP_RRR2_OP2(ctx->opcode);
6852 r1 = MASK_OP_RRR2_S1(ctx->opcode);
6853 r2 = MASK_OP_RRR2_S2(ctx->opcode);
6854 r3 = MASK_OP_RRR2_S3(ctx->opcode);
6855 r4 = MASK_OP_RRR2_D(ctx->opcode);
6856
6857 switch (op2) {
6858 case OPC2_32_RRR2_MSUB_32:
6859 gen_msub32_d(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r3],
6860 cpu_gpr_d[r2]);
6861 break;
6862 case OPC2_32_RRR2_MSUB_64:
6863 gen_msub64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6864 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6865 break;
6866 case OPC2_32_RRR2_MSUBS_32:
6867 gen_helper_msub32_ssov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6868 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6869 break;
6870 case OPC2_32_RRR2_MSUBS_64:
6871 gen_msubs_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6872 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6873 break;
6874 case OPC2_32_RRR2_MSUB_U_64:
6875 gen_msubu64_d(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6876 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6877 break;
6878 case OPC2_32_RRR2_MSUBS_U_32:
6879 gen_helper_msub32_suov(cpu_gpr_d[r4], cpu_env, cpu_gpr_d[r1],
6880 cpu_gpr_d[r3], cpu_gpr_d[r2]);
6881 break;
6882 case OPC2_32_RRR2_MSUBS_U_64:
6883 gen_msubsu_64(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r1],
6884 cpu_gpr_d[r3], cpu_gpr_d[r3+1], cpu_gpr_d[r2]);
6885 break;
6886 }
6887 }
6888
6889 /* RRR1 format */
6890 static void decode_rrr1_madd(CPUTriCoreState *env, DisasContext *ctx)
6891 {
6892 uint32_t op2;
6893 uint32_t r1, r2, r3, r4, n;
6894
6895 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
6896 r1 = MASK_OP_RRR1_S1(ctx->opcode);
6897 r2 = MASK_OP_RRR1_S2(ctx->opcode);
6898 r3 = MASK_OP_RRR1_S3(ctx->opcode);
6899 r4 = MASK_OP_RRR1_D(ctx->opcode);
6900 n = MASK_OP_RRR1_N(ctx->opcode);
6901
6902 switch (op2) {
6903 case OPC2_32_RRR1_MADD_H_LL:
6904 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6905 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6906 break;
6907 case OPC2_32_RRR1_MADD_H_LU:
6908 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6909 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6910 break;
6911 case OPC2_32_RRR1_MADD_H_UL:
6912 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6913 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6914 break;
6915 case OPC2_32_RRR1_MADD_H_UU:
6916 gen_madd_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6917 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6918 break;
6919 case OPC2_32_RRR1_MADDS_H_LL:
6920 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6921 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6922 break;
6923 case OPC2_32_RRR1_MADDS_H_LU:
6924 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6925 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6926 break;
6927 case OPC2_32_RRR1_MADDS_H_UL:
6928 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6929 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6930 break;
6931 case OPC2_32_RRR1_MADDS_H_UU:
6932 gen_madds_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6933 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6934 break;
6935 case OPC2_32_RRR1_MADDM_H_LL:
6936 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6937 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6938 break;
6939 case OPC2_32_RRR1_MADDM_H_LU:
6940 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6941 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6942 break;
6943 case OPC2_32_RRR1_MADDM_H_UL:
6944 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6945 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6946 break;
6947 case OPC2_32_RRR1_MADDM_H_UU:
6948 gen_maddm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6949 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6950 break;
6951 case OPC2_32_RRR1_MADDMS_H_LL:
6952 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6953 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
6954 break;
6955 case OPC2_32_RRR1_MADDMS_H_LU:
6956 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6957 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
6958 break;
6959 case OPC2_32_RRR1_MADDMS_H_UL:
6960 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6961 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
6962 break;
6963 case OPC2_32_RRR1_MADDMS_H_UU:
6964 gen_maddms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
6965 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
6966 break;
6967 case OPC2_32_RRR1_MADDR_H_LL:
6968 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6969 cpu_gpr_d[r2], n, MODE_LL);
6970 break;
6971 case OPC2_32_RRR1_MADDR_H_LU:
6972 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6973 cpu_gpr_d[r2], n, MODE_LU);
6974 break;
6975 case OPC2_32_RRR1_MADDR_H_UL:
6976 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6977 cpu_gpr_d[r2], n, MODE_UL);
6978 break;
6979 case OPC2_32_RRR1_MADDR_H_UU:
6980 gen_maddr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6981 cpu_gpr_d[r2], n, MODE_UU);
6982 break;
6983 case OPC2_32_RRR1_MADDRS_H_LL:
6984 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6985 cpu_gpr_d[r2], n, MODE_LL);
6986 break;
6987 case OPC2_32_RRR1_MADDRS_H_LU:
6988 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6989 cpu_gpr_d[r2], n, MODE_LU);
6990 break;
6991 case OPC2_32_RRR1_MADDRS_H_UL:
6992 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6993 cpu_gpr_d[r2], n, MODE_UL);
6994 break;
6995 case OPC2_32_RRR1_MADDRS_H_UU:
6996 gen_maddr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
6997 cpu_gpr_d[r2], n, MODE_UU);
6998 break;
6999 }
7000 }
7001
7002 static void decode_rrr1_maddq_h(CPUTriCoreState *env, DisasContext *ctx)
7003 {
7004 uint32_t op2;
7005 uint32_t r1, r2, r3, r4, n;
7006 TCGv temp, temp2;
7007
7008 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7009 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7010 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7011 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7012 r4 = MASK_OP_RRR1_D(ctx->opcode);
7013 n = MASK_OP_RRR1_N(ctx->opcode);
7014
7015 temp = tcg_const_i32(n);
7016 temp2 = tcg_temp_new();
7017
7018 switch (op2) {
7019 case OPC2_32_RRR1_MADD_Q_32:
7020 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7021 cpu_gpr_d[r2], n, 32, env);
7022 break;
7023 case OPC2_32_RRR1_MADD_Q_64:
7024 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7025 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7026 n, env);
7027 break;
7028 case OPC2_32_RRR1_MADD_Q_32_L:
7029 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7030 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7031 temp, n, 16, env);
7032 break;
7033 case OPC2_32_RRR1_MADD_Q_64_L:
7034 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7035 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7036 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7037 n, env);
7038 break;
7039 case OPC2_32_RRR1_MADD_Q_32_U:
7040 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7041 gen_madd32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7042 temp, n, 16, env);
7043 break;
7044 case OPC2_32_RRR1_MADD_Q_64_U:
7045 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7046 gen_madd64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7047 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7048 n, env);
7049 break;
7050 case OPC2_32_RRR1_MADD_Q_32_LL:
7051 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7052 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7053 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7054 break;
7055 case OPC2_32_RRR1_MADD_Q_64_LL:
7056 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7057 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7058 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7059 cpu_gpr_d[r3+1], temp, temp2, n);
7060 break;
7061 case OPC2_32_RRR1_MADD_Q_32_UU:
7062 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7063 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7064 gen_m16add32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7065 break;
7066 case OPC2_32_RRR1_MADD_Q_64_UU:
7067 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7068 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7069 gen_m16add64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7070 cpu_gpr_d[r3+1], temp, temp2, n);
7071 break;
7072 case OPC2_32_RRR1_MADDS_Q_32:
7073 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7074 cpu_gpr_d[r2], n, 32);
7075 break;
7076 case OPC2_32_RRR1_MADDS_Q_64:
7077 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7078 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7079 n);
7080 break;
7081 case OPC2_32_RRR1_MADDS_Q_32_L:
7082 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7083 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7084 temp, n, 16);
7085 break;
7086 case OPC2_32_RRR1_MADDS_Q_64_L:
7087 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7088 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7089 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7090 n);
7091 break;
7092 case OPC2_32_RRR1_MADDS_Q_32_U:
7093 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7094 gen_madds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7095 temp, n, 16);
7096 break;
7097 case OPC2_32_RRR1_MADDS_Q_64_U:
7098 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7099 gen_madds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7100 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7101 n);
7102 break;
7103 case OPC2_32_RRR1_MADDS_Q_32_LL:
7104 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7105 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7106 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7107 break;
7108 case OPC2_32_RRR1_MADDS_Q_64_LL:
7109 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7110 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7111 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7112 cpu_gpr_d[r3+1], temp, temp2, n);
7113 break;
7114 case OPC2_32_RRR1_MADDS_Q_32_UU:
7115 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7116 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7117 gen_m16adds32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7118 break;
7119 case OPC2_32_RRR1_MADDS_Q_64_UU:
7120 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7121 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7122 gen_m16adds64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7123 cpu_gpr_d[r3+1], temp, temp2, n);
7124 break;
7125 case OPC2_32_RRR1_MADDR_H_64_UL:
7126 gen_maddr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7127 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7128 break;
7129 case OPC2_32_RRR1_MADDRS_H_64_UL:
7130 gen_maddr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7131 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7132 break;
7133 case OPC2_32_RRR1_MADDR_Q_32_LL:
7134 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7135 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7136 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7137 break;
7138 case OPC2_32_RRR1_MADDR_Q_32_UU:
7139 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7140 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7141 gen_maddr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7142 break;
7143 case OPC2_32_RRR1_MADDRS_Q_32_LL:
7144 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7145 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7146 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7147 break;
7148 case OPC2_32_RRR1_MADDRS_Q_32_UU:
7149 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7150 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7151 gen_maddrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7152 break;
7153 }
7154 tcg_temp_free(temp);
7155 tcg_temp_free(temp2);
7156 }
7157
7158 static void decode_rrr1_maddsu_h(CPUTriCoreState *env, DisasContext *ctx)
7159 {
7160 uint32_t op2;
7161 uint32_t r1, r2, r3, r4, n;
7162
7163 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7164 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7165 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7166 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7167 r4 = MASK_OP_RRR1_D(ctx->opcode);
7168 n = MASK_OP_RRR1_N(ctx->opcode);
7169
7170 switch (op2) {
7171 case OPC2_32_RRR1_MADDSU_H_32_LL:
7172 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7173 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7174 break;
7175 case OPC2_32_RRR1_MADDSU_H_32_LU:
7176 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7177 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7178 break;
7179 case OPC2_32_RRR1_MADDSU_H_32_UL:
7180 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7181 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7182 break;
7183 case OPC2_32_RRR1_MADDSU_H_32_UU:
7184 gen_maddsu_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7185 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7186 break;
7187 case OPC2_32_RRR1_MADDSUS_H_32_LL:
7188 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7189 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7190 n, MODE_LL);
7191 break;
7192 case OPC2_32_RRR1_MADDSUS_H_32_LU:
7193 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7194 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7195 n, MODE_LU);
7196 break;
7197 case OPC2_32_RRR1_MADDSUS_H_32_UL:
7198 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7199 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7200 n, MODE_UL);
7201 break;
7202 case OPC2_32_RRR1_MADDSUS_H_32_UU:
7203 gen_maddsus_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7204 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7205 n, MODE_UU);
7206 break;
7207 case OPC2_32_RRR1_MADDSUM_H_64_LL:
7208 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7209 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7210 n, MODE_LL);
7211 break;
7212 case OPC2_32_RRR1_MADDSUM_H_64_LU:
7213 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7214 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7215 n, MODE_LU);
7216 break;
7217 case OPC2_32_RRR1_MADDSUM_H_64_UL:
7218 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7219 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7220 n, MODE_UL);
7221 break;
7222 case OPC2_32_RRR1_MADDSUM_H_64_UU:
7223 gen_maddsum_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7224 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7225 n, MODE_UU);
7226 break;
7227 case OPC2_32_RRR1_MADDSUMS_H_64_LL:
7228 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7229 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7230 n, MODE_LL);
7231 break;
7232 case OPC2_32_RRR1_MADDSUMS_H_64_LU:
7233 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7234 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7235 n, MODE_LU);
7236 break;
7237 case OPC2_32_RRR1_MADDSUMS_H_64_UL:
7238 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7239 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7240 n, MODE_UL);
7241 break;
7242 case OPC2_32_RRR1_MADDSUMS_H_64_UU:
7243 gen_maddsums_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7244 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7245 n, MODE_UU);
7246 break;
7247 case OPC2_32_RRR1_MADDSUR_H_16_LL:
7248 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7249 cpu_gpr_d[r2], n, MODE_LL);
7250 break;
7251 case OPC2_32_RRR1_MADDSUR_H_16_LU:
7252 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7253 cpu_gpr_d[r2], n, MODE_LU);
7254 break;
7255 case OPC2_32_RRR1_MADDSUR_H_16_UL:
7256 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7257 cpu_gpr_d[r2], n, MODE_UL);
7258 break;
7259 case OPC2_32_RRR1_MADDSUR_H_16_UU:
7260 gen_maddsur32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7261 cpu_gpr_d[r2], n, MODE_UU);
7262 break;
7263 case OPC2_32_RRR1_MADDSURS_H_16_LL:
7264 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7265 cpu_gpr_d[r2], n, MODE_LL);
7266 break;
7267 case OPC2_32_RRR1_MADDSURS_H_16_LU:
7268 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7269 cpu_gpr_d[r2], n, MODE_LU);
7270 break;
7271 case OPC2_32_RRR1_MADDSURS_H_16_UL:
7272 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7273 cpu_gpr_d[r2], n, MODE_UL);
7274 break;
7275 case OPC2_32_RRR1_MADDSURS_H_16_UU:
7276 gen_maddsur32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7277 cpu_gpr_d[r2], n, MODE_UU);
7278 break;
7279 }
7280 }
7281
7282 static void decode_rrr1_msub(CPUTriCoreState *env, DisasContext *ctx)
7283 {
7284 uint32_t op2;
7285 uint32_t r1, r2, r3, r4, n;
7286
7287 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7288 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7289 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7290 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7291 r4 = MASK_OP_RRR1_D(ctx->opcode);
7292 n = MASK_OP_RRR1_N(ctx->opcode);
7293
7294 switch (op2) {
7295 case OPC2_32_RRR1_MSUB_H_LL:
7296 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7297 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7298 break;
7299 case OPC2_32_RRR1_MSUB_H_LU:
7300 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7301 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7302 break;
7303 case OPC2_32_RRR1_MSUB_H_UL:
7304 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7305 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7306 break;
7307 case OPC2_32_RRR1_MSUB_H_UU:
7308 gen_msub_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7309 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7310 break;
7311 case OPC2_32_RRR1_MSUBS_H_LL:
7312 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7313 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7314 break;
7315 case OPC2_32_RRR1_MSUBS_H_LU:
7316 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7317 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7318 break;
7319 case OPC2_32_RRR1_MSUBS_H_UL:
7320 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7321 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7322 break;
7323 case OPC2_32_RRR1_MSUBS_H_UU:
7324 gen_msubs_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7325 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7326 break;
7327 case OPC2_32_RRR1_MSUBM_H_LL:
7328 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7329 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7330 break;
7331 case OPC2_32_RRR1_MSUBM_H_LU:
7332 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7333 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7334 break;
7335 case OPC2_32_RRR1_MSUBM_H_UL:
7336 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7337 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7338 break;
7339 case OPC2_32_RRR1_MSUBM_H_UU:
7340 gen_msubm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7341 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7342 break;
7343 case OPC2_32_RRR1_MSUBMS_H_LL:
7344 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7345 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7346 break;
7347 case OPC2_32_RRR1_MSUBMS_H_LU:
7348 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7349 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7350 break;
7351 case OPC2_32_RRR1_MSUBMS_H_UL:
7352 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7353 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7354 break;
7355 case OPC2_32_RRR1_MSUBMS_H_UU:
7356 gen_msubms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7357 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7358 break;
7359 case OPC2_32_RRR1_MSUBR_H_LL:
7360 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7361 cpu_gpr_d[r2], n, MODE_LL);
7362 break;
7363 case OPC2_32_RRR1_MSUBR_H_LU:
7364 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7365 cpu_gpr_d[r2], n, MODE_LU);
7366 break;
7367 case OPC2_32_RRR1_MSUBR_H_UL:
7368 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7369 cpu_gpr_d[r2], n, MODE_UL);
7370 break;
7371 case OPC2_32_RRR1_MSUBR_H_UU:
7372 gen_msubr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7373 cpu_gpr_d[r2], n, MODE_UU);
7374 break;
7375 case OPC2_32_RRR1_MSUBRS_H_LL:
7376 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7377 cpu_gpr_d[r2], n, MODE_LL);
7378 break;
7379 case OPC2_32_RRR1_MSUBRS_H_LU:
7380 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7381 cpu_gpr_d[r2], n, MODE_LU);
7382 break;
7383 case OPC2_32_RRR1_MSUBRS_H_UL:
7384 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7385 cpu_gpr_d[r2], n, MODE_UL);
7386 break;
7387 case OPC2_32_RRR1_MSUBRS_H_UU:
7388 gen_msubr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7389 cpu_gpr_d[r2], n, MODE_UU);
7390 break;
7391 }
7392 }
7393
7394 static void decode_rrr1_msubq_h(CPUTriCoreState *env, DisasContext *ctx)
7395 {
7396 uint32_t op2;
7397 uint32_t r1, r2, r3, r4, n;
7398 TCGv temp, temp2;
7399
7400 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7401 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7402 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7403 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7404 r4 = MASK_OP_RRR1_D(ctx->opcode);
7405 n = MASK_OP_RRR1_N(ctx->opcode);
7406
7407 temp = tcg_const_i32(n);
7408 temp2 = tcg_temp_new();
7409
7410 switch (op2) {
7411 case OPC2_32_RRR1_MSUB_Q_32:
7412 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7413 cpu_gpr_d[r2], n, 32, env);
7414 break;
7415 case OPC2_32_RRR1_MSUB_Q_64:
7416 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7417 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7418 n, env);
7419 break;
7420 case OPC2_32_RRR1_MSUB_Q_32_L:
7421 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7422 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7423 temp, n, 16, env);
7424 break;
7425 case OPC2_32_RRR1_MSUB_Q_64_L:
7426 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7427 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7428 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7429 n, env);
7430 break;
7431 case OPC2_32_RRR1_MSUB_Q_32_U:
7432 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7433 gen_msub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7434 temp, n, 16, env);
7435 break;
7436 case OPC2_32_RRR1_MSUB_Q_64_U:
7437 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7438 gen_msub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7439 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7440 n, env);
7441 break;
7442 case OPC2_32_RRR1_MSUB_Q_32_LL:
7443 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7444 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7445 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7446 break;
7447 case OPC2_32_RRR1_MSUB_Q_64_LL:
7448 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7449 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7450 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7451 cpu_gpr_d[r3+1], temp, temp2, n);
7452 break;
7453 case OPC2_32_RRR1_MSUB_Q_32_UU:
7454 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7455 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7456 gen_m16sub32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7457 break;
7458 case OPC2_32_RRR1_MSUB_Q_64_UU:
7459 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7460 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7461 gen_m16sub64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7462 cpu_gpr_d[r3+1], temp, temp2, n);
7463 break;
7464 case OPC2_32_RRR1_MSUBS_Q_32:
7465 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7466 cpu_gpr_d[r2], n, 32);
7467 break;
7468 case OPC2_32_RRR1_MSUBS_Q_64:
7469 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7470 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7471 n);
7472 break;
7473 case OPC2_32_RRR1_MSUBS_Q_32_L:
7474 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7475 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7476 temp, n, 16);
7477 break;
7478 case OPC2_32_RRR1_MSUBS_Q_64_L:
7479 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r2]);
7480 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7481 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7482 n);
7483 break;
7484 case OPC2_32_RRR1_MSUBS_Q_32_U:
7485 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7486 gen_msubs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7487 temp, n, 16);
7488 break;
7489 case OPC2_32_RRR1_MSUBS_Q_64_U:
7490 tcg_gen_sari_tl(temp, cpu_gpr_d[r2], 16);
7491 gen_msubs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7492 cpu_gpr_d[r3+1], cpu_gpr_d[r1], temp,
7493 n);
7494 break;
7495 case OPC2_32_RRR1_MSUBS_Q_32_LL:
7496 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7497 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7498 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7499 break;
7500 case OPC2_32_RRR1_MSUBS_Q_64_LL:
7501 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7502 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7503 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7504 cpu_gpr_d[r3+1], temp, temp2, n);
7505 break;
7506 case OPC2_32_RRR1_MSUBS_Q_32_UU:
7507 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7508 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7509 gen_m16subs32_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7510 break;
7511 case OPC2_32_RRR1_MSUBS_Q_64_UU:
7512 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7513 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7514 gen_m16subs64_q(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7515 cpu_gpr_d[r3+1], temp, temp2, n);
7516 break;
7517 case OPC2_32_RRR1_MSUBR_H_64_UL:
7518 gen_msubr64_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7519 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7520 break;
7521 case OPC2_32_RRR1_MSUBRS_H_64_UL:
7522 gen_msubr64s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r3+1],
7523 cpu_gpr_d[r1], cpu_gpr_d[r2], n, 2);
7524 break;
7525 case OPC2_32_RRR1_MSUBR_Q_32_LL:
7526 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7527 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7528 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7529 break;
7530 case OPC2_32_RRR1_MSUBR_Q_32_UU:
7531 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7532 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7533 gen_msubr_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7534 break;
7535 case OPC2_32_RRR1_MSUBRS_Q_32_LL:
7536 tcg_gen_ext16s_tl(temp, cpu_gpr_d[r1]);
7537 tcg_gen_ext16s_tl(temp2, cpu_gpr_d[r2]);
7538 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7539 break;
7540 case OPC2_32_RRR1_MSUBRS_Q_32_UU:
7541 tcg_gen_sari_tl(temp, cpu_gpr_d[r1], 16);
7542 tcg_gen_sari_tl(temp2, cpu_gpr_d[r2], 16);
7543 gen_msubrs_q(cpu_gpr_d[r4], cpu_gpr_d[r3], temp, temp2, n);
7544 break;
7545 }
7546 tcg_temp_free(temp);
7547 tcg_temp_free(temp2);
7548 }
7549
7550 static void decode_rrr1_msubad_h(CPUTriCoreState *env, DisasContext *ctx)
7551 {
7552 uint32_t op2;
7553 uint32_t r1, r2, r3, r4, n;
7554
7555 op2 = MASK_OP_RRR1_OP2(ctx->opcode);
7556 r1 = MASK_OP_RRR1_S1(ctx->opcode);
7557 r2 = MASK_OP_RRR1_S2(ctx->opcode);
7558 r3 = MASK_OP_RRR1_S3(ctx->opcode);
7559 r4 = MASK_OP_RRR1_D(ctx->opcode);
7560 n = MASK_OP_RRR1_N(ctx->opcode);
7561
7562 switch (op2) {
7563 case OPC2_32_RRR1_MSUBAD_H_32_LL:
7564 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7565 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LL);
7566 break;
7567 case OPC2_32_RRR1_MSUBAD_H_32_LU:
7568 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7569 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_LU);
7570 break;
7571 case OPC2_32_RRR1_MSUBAD_H_32_UL:
7572 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7573 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UL);
7574 break;
7575 case OPC2_32_RRR1_MSUBAD_H_32_UU:
7576 gen_msubad_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7577 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2], n, MODE_UU);
7578 break;
7579 case OPC2_32_RRR1_MSUBADS_H_32_LL:
7580 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7581 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7582 n, MODE_LL);
7583 break;
7584 case OPC2_32_RRR1_MSUBADS_H_32_LU:
7585 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7586 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7587 n, MODE_LU);
7588 break;
7589 case OPC2_32_RRR1_MSUBADS_H_32_UL:
7590 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7591 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7592 n, MODE_UL);
7593 break;
7594 case OPC2_32_RRR1_MSUBADS_H_32_UU:
7595 gen_msubads_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7596 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7597 n, MODE_UU);
7598 break;
7599 case OPC2_32_RRR1_MSUBADM_H_64_LL:
7600 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7601 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7602 n, MODE_LL);
7603 break;
7604 case OPC2_32_RRR1_MSUBADM_H_64_LU:
7605 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7606 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7607 n, MODE_LU);
7608 break;
7609 case OPC2_32_RRR1_MSUBADM_H_64_UL:
7610 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7611 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7612 n, MODE_UL);
7613 break;
7614 case OPC2_32_RRR1_MSUBADM_H_64_UU:
7615 gen_msubadm_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7616 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7617 n, MODE_UU);
7618 break;
7619 case OPC2_32_RRR1_MSUBADMS_H_64_LL:
7620 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7621 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7622 n, MODE_LL);
7623 break;
7624 case OPC2_32_RRR1_MSUBADMS_H_64_LU:
7625 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7626 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7627 n, MODE_LU);
7628 break;
7629 case OPC2_32_RRR1_MSUBADMS_H_64_UL:
7630 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7631 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7632 n, MODE_UL);
7633 break;
7634 case OPC2_32_RRR1_MSUBADMS_H_64_UU:
7635 gen_msubadms_h(cpu_gpr_d[r4], cpu_gpr_d[r4+1], cpu_gpr_d[r3],
7636 cpu_gpr_d[r3+1], cpu_gpr_d[r1], cpu_gpr_d[r2],
7637 n, MODE_UU);
7638 break;
7639 case OPC2_32_RRR1_MSUBADR_H_16_LL:
7640 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7641 cpu_gpr_d[r2], n, MODE_LL);
7642 break;
7643 case OPC2_32_RRR1_MSUBADR_H_16_LU:
7644 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7645 cpu_gpr_d[r2], n, MODE_LU);
7646 break;
7647 case OPC2_32_RRR1_MSUBADR_H_16_UL:
7648 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7649 cpu_gpr_d[r2], n, MODE_UL);
7650 break;
7651 case OPC2_32_RRR1_MSUBADR_H_16_UU:
7652 gen_msubadr32_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7653 cpu_gpr_d[r2], n, MODE_UU);
7654 break;
7655 case OPC2_32_RRR1_MSUBADRS_H_16_LL:
7656 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7657 cpu_gpr_d[r2], n, MODE_LL);
7658 break;
7659 case OPC2_32_RRR1_MSUBADRS_H_16_LU:
7660 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7661 cpu_gpr_d[r2], n, MODE_LU);
7662 break;
7663 case OPC2_32_RRR1_MSUBADRS_H_16_UL:
7664 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7665 cpu_gpr_d[r2], n, MODE_UL);
7666 break;
7667 case OPC2_32_RRR1_MSUBADRS_H_16_UU:
7668 gen_msubadr32s_h(cpu_gpr_d[r4], cpu_gpr_d[r3], cpu_gpr_d[r1],
7669 cpu_gpr_d[r2], n, MODE_UU);
7670 break;
7671 }
7672 }
7673
7674 /* RRRR format */
7675 static void decode_rrrr_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
7676 {
7677 uint32_t op2;
7678 int r1, r2, r3, r4;
7679 TCGv tmp_width, tmp_pos;
7680
7681 r1 = MASK_OP_RRRR_S1(ctx->opcode);
7682 r2 = MASK_OP_RRRR_S2(ctx->opcode);
7683 r3 = MASK_OP_RRRR_S3(ctx->opcode);
7684 r4 = MASK_OP_RRRR_D(ctx->opcode);
7685 op2 = MASK_OP_RRRR_OP2(ctx->opcode);
7686
7687 tmp_pos = tcg_temp_new();
7688 tmp_width = tcg_temp_new();
7689
7690 switch (op2) {
7691 case OPC2_32_RRRR_DEXTR:
7692 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7693 if (r1 == r2) {
7694 tcg_gen_rotl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7695 } else {
7696 tcg_gen_shl_tl(tmp_width, cpu_gpr_d[r1], tmp_pos);
7697 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
7698 tcg_gen_shr_tl(tmp_pos, cpu_gpr_d[r2], tmp_pos);
7699 tcg_gen_or_tl(cpu_gpr_d[r4], tmp_width, tmp_pos);
7700 }
7701 break;
7702 case OPC2_32_RRRR_EXTR:
7703 case OPC2_32_RRRR_EXTR_U:
7704 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7705 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7706 tcg_gen_add_tl(tmp_pos, tmp_pos, tmp_width);
7707 tcg_gen_subfi_tl(tmp_pos, 32, tmp_pos);
7708 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], tmp_pos);
7709 tcg_gen_subfi_tl(tmp_width, 32, tmp_width);
7710 if (op2 == OPC2_32_RRRR_EXTR) {
7711 tcg_gen_sar_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7712 } else {
7713 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], tmp_width);
7714 }
7715 break;
7716 case OPC2_32_RRRR_INSERT:
7717 tcg_gen_andi_tl(tmp_width, cpu_gpr_d[r3+1], 0x1f);
7718 tcg_gen_andi_tl(tmp_pos, cpu_gpr_d[r3], 0x1f);
7719 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], tmp_width,
7720 tmp_pos);
7721 break;
7722 }
7723 tcg_temp_free(tmp_pos);
7724 tcg_temp_free(tmp_width);
7725 }
7726
7727 /* RRRW format */
7728 static void decode_rrrw_extract_insert(CPUTriCoreState *env, DisasContext *ctx)
7729 {
7730 uint32_t op2;
7731 int r1, r2, r3, r4;
7732 int32_t width;
7733
7734 TCGv temp, temp2;
7735
7736 op2 = MASK_OP_RRRW_OP2(ctx->opcode);
7737 r1 = MASK_OP_RRRW_S1(ctx->opcode);
7738 r2 = MASK_OP_RRRW_S2(ctx->opcode);
7739 r3 = MASK_OP_RRRW_S3(ctx->opcode);
7740 r4 = MASK_OP_RRRW_D(ctx->opcode);
7741 width = MASK_OP_RRRW_WIDTH(ctx->opcode);
7742
7743 temp = tcg_temp_new();
7744
7745 switch (op2) {
7746 case OPC2_32_RRRW_EXTR:
7747 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7748 tcg_gen_addi_tl(temp, temp, width);
7749 tcg_gen_subfi_tl(temp, 32, temp);
7750 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7751 tcg_gen_sari_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], 32 - width);
7752 break;
7753 case OPC2_32_RRRW_EXTR_U:
7754 if (width == 0) {
7755 tcg_gen_movi_tl(cpu_gpr_d[r4], 0);
7756 } else {
7757 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7758 tcg_gen_shr_tl(cpu_gpr_d[r4], cpu_gpr_d[r1], temp);
7759 tcg_gen_andi_tl(cpu_gpr_d[r4], cpu_gpr_d[r4], ~0u >> (32-width));
7760 }
7761 break;
7762 case OPC2_32_RRRW_IMASK:
7763 temp2 = tcg_temp_new();
7764
7765 tcg_gen_andi_tl(temp, cpu_gpr_d[r3], 0x1f);
7766 tcg_gen_movi_tl(temp2, (1 << width) - 1);
7767 tcg_gen_shl_tl(temp2, temp2, temp);
7768 tcg_gen_shl_tl(cpu_gpr_d[r4], cpu_gpr_d[r2], temp);
7769 tcg_gen_mov_tl(cpu_gpr_d[r4+1], temp2);
7770
7771 tcg_temp_free(temp2);
7772 break;
7773 case OPC2_32_RRRW_INSERT:
7774 temp2 = tcg_temp_new();
7775
7776 tcg_gen_movi_tl(temp, width);
7777 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3], 0x1f);
7778 gen_insert(cpu_gpr_d[r4], cpu_gpr_d[r1], cpu_gpr_d[r2], temp, temp2);
7779
7780 tcg_temp_free(temp2);
7781 break;
7782 }
7783 tcg_temp_free(temp);
7784 }
7785
7786 /* SYS Format*/
7787 static void decode_sys_interrupts(CPUTriCoreState *env, DisasContext *ctx)
7788 {
7789 uint32_t op2;
7790 TCGLabel *l1;
7791 TCGv tmp;
7792
7793 op2 = MASK_OP_SYS_OP2(ctx->opcode);
7794
7795 switch (op2) {
7796 case OPC2_32_SYS_DEBUG:
7797 /* raise EXCP_DEBUG */
7798 break;
7799 case OPC2_32_SYS_DISABLE:
7800 tcg_gen_andi_tl(cpu_ICR, cpu_ICR, ~MASK_ICR_IE);
7801 break;
7802 case OPC2_32_SYS_DSYNC:
7803 break;
7804 case OPC2_32_SYS_ENABLE:
7805 tcg_gen_ori_tl(cpu_ICR, cpu_ICR, MASK_ICR_IE);
7806 break;
7807 case OPC2_32_SYS_ISYNC:
7808 break;
7809 case OPC2_32_SYS_NOP:
7810 break;
7811 case OPC2_32_SYS_RET:
7812 gen_compute_branch(ctx, op2, 0, 0, 0, 0);
7813 break;
7814 case OPC2_32_SYS_RFE:
7815 gen_helper_rfe(cpu_env);
7816 tcg_gen_exit_tb(0);
7817 ctx->bstate = BS_BRANCH;
7818 break;
7819 case OPC2_32_SYS_RFM:
7820 if ((ctx->hflags & TRICORE_HFLAG_KUU) == TRICORE_HFLAG_SM) {
7821 tmp = tcg_temp_new();
7822 l1 = gen_new_label();
7823
7824 tcg_gen_ld32u_tl(tmp, cpu_env, offsetof(CPUTriCoreState, DBGSR));
7825 tcg_gen_andi_tl(tmp, tmp, MASK_DBGSR_DE);
7826 tcg_gen_brcondi_tl(TCG_COND_NE, tmp, 1, l1);
7827 gen_helper_rfm(cpu_env);
7828 gen_set_label(l1);
7829 tcg_gen_exit_tb(0);
7830 ctx->bstate = BS_BRANCH;
7831 tcg_temp_free(tmp);
7832 } else {
7833 /* generate privilege trap */
7834 }
7835 break;
7836 case OPC2_32_SYS_RSLCX:
7837 gen_helper_rslcx(cpu_env);
7838 break;
7839 case OPC2_32_SYS_SVLCX:
7840 gen_helper_svlcx(cpu_env);
7841 break;
7842 case OPC2_32_SYS_TRAPSV:
7843 /* TODO: raise sticky overflow trap */
7844 break;
7845 case OPC2_32_SYS_TRAPV:
7846 /* TODO: raise overflow trap */
7847 break;
7848 }
7849 }
7850
7851 static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx)
7852 {
7853 int op1;
7854 int32_t r1, r2, r3;
7855 int32_t address, const16;
7856 int8_t b, const4;
7857 int32_t bpos;
7858 TCGv temp, temp2, temp3;
7859
7860 op1 = MASK_OP_MAJOR(ctx->opcode);
7861
7862 /* handle JNZ.T opcode only being 7 bit long */
7863 if (unlikely((op1 & 0x7f) == OPCM_32_BRN_JTT)) {
7864 op1 = OPCM_32_BRN_JTT;
7865 }
7866
7867 switch (op1) {
7868 /* ABS-format */
7869 case OPCM_32_ABS_LDW:
7870 decode_abs_ldw(env, ctx);
7871 break;
7872 case OPCM_32_ABS_LDB:
7873 decode_abs_ldb(env, ctx);
7874 break;
7875 case OPCM_32_ABS_LDMST_SWAP:
7876 decode_abs_ldst_swap(env, ctx);
7877 break;
7878 case OPCM_32_ABS_LDST_CONTEXT:
7879 decode_abs_ldst_context(env, ctx);
7880 break;
7881 case OPCM_32_ABS_STORE:
7882 decode_abs_store(env, ctx);
7883 break;
7884 case OPCM_32_ABS_STOREB_H:
7885 decode_abs_storeb_h(env, ctx);
7886 break;
7887 case OPC1_32_ABS_STOREQ:
7888 address = MASK_OP_ABS_OFF18(ctx->opcode);
7889 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7890 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7891 temp2 = tcg_temp_new();
7892
7893 tcg_gen_shri_tl(temp2, cpu_gpr_d[r1], 16);
7894 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_LEUW);
7895
7896 tcg_temp_free(temp2);
7897 tcg_temp_free(temp);
7898 break;
7899 case OPC1_32_ABS_LD_Q:
7900 address = MASK_OP_ABS_OFF18(ctx->opcode);
7901 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7902 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7903
7904 tcg_gen_qemu_ld_tl(cpu_gpr_d[r1], temp, ctx->mem_idx, MO_LEUW);
7905 tcg_gen_shli_tl(cpu_gpr_d[r1], cpu_gpr_d[r1], 16);
7906
7907 tcg_temp_free(temp);
7908 break;
7909 case OPC1_32_ABS_LEA:
7910 address = MASK_OP_ABS_OFF18(ctx->opcode);
7911 r1 = MASK_OP_ABS_S1D(ctx->opcode);
7912 tcg_gen_movi_tl(cpu_gpr_a[r1], EA_ABS_FORMAT(address));
7913 break;
7914 /* ABSB-format */
7915 case OPC1_32_ABSB_ST_T:
7916 address = MASK_OP_ABS_OFF18(ctx->opcode);
7917 b = MASK_OP_ABSB_B(ctx->opcode);
7918 bpos = MASK_OP_ABSB_BPOS(ctx->opcode);
7919
7920 temp = tcg_const_i32(EA_ABS_FORMAT(address));
7921 temp2 = tcg_temp_new();
7922
7923 tcg_gen_qemu_ld_tl(temp2, temp, ctx->mem_idx, MO_UB);
7924 tcg_gen_andi_tl(temp2, temp2, ~(0x1u << bpos));
7925 tcg_gen_ori_tl(temp2, temp2, (b << bpos));
7926 tcg_gen_qemu_st_tl(temp2, temp, ctx->mem_idx, MO_UB);
7927
7928 tcg_temp_free(temp);
7929 tcg_temp_free(temp2);
7930 break;
7931 /* B-format */
7932 case OPC1_32_B_CALL:
7933 case OPC1_32_B_CALLA:
7934 case OPC1_32_B_J:
7935 case OPC1_32_B_JA:
7936 case OPC1_32_B_JL:
7937 case OPC1_32_B_JLA:
7938 address = MASK_OP_B_DISP24_SEXT(ctx->opcode);
7939 gen_compute_branch(ctx, op1, 0, 0, 0, address);
7940 break;
7941 /* Bit-format */
7942 case OPCM_32_BIT_ANDACC:
7943 decode_bit_andacc(env, ctx);
7944 break;
7945 case OPCM_32_BIT_LOGICAL_T1:
7946 decode_bit_logical_t(env, ctx);
7947 break;
7948 case OPCM_32_BIT_INSERT:
7949 decode_bit_insert(env, ctx);
7950 break;
7951 case OPCM_32_BIT_LOGICAL_T2:
7952 decode_bit_logical_t2(env, ctx);
7953 break;
7954 case OPCM_32_BIT_ORAND:
7955 decode_bit_orand(env, ctx);
7956 break;
7957 case OPCM_32_BIT_SH_LOGIC1:
7958 decode_bit_sh_logic1(env, ctx);
7959 break;
7960 case OPCM_32_BIT_SH_LOGIC2:
7961 decode_bit_sh_logic2(env, ctx);
7962 break;
7963 /* BO Format */
7964 case OPCM_32_BO_ADDRMODE_POST_PRE_BASE:
7965 decode_bo_addrmode_post_pre_base(env, ctx);
7966 break;
7967 case OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR:
7968 decode_bo_addrmode_bitreverse_circular(env, ctx);
7969 break;
7970 case OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE:
7971 decode_bo_addrmode_ld_post_pre_base(env, ctx);
7972 break;
7973 case OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR:
7974 decode_bo_addrmode_ld_bitreverse_circular(env, ctx);
7975 break;
7976 case OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE:
7977 decode_bo_addrmode_stctx_post_pre_base(env, ctx);
7978 break;
7979 case OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR:
7980 decode_bo_addrmode_ldmst_bitreverse_circular(env, ctx);
7981 break;
7982 /* BOL-format */
7983 case OPC1_32_BOL_LD_A_LONGOFF:
7984 case OPC1_32_BOL_LD_W_LONGOFF:
7985 case OPC1_32_BOL_LEA_LONGOFF:
7986 case OPC1_32_BOL_ST_W_LONGOFF:
7987 case OPC1_32_BOL_ST_A_LONGOFF:
7988 case OPC1_32_BOL_LD_B_LONGOFF:
7989 case OPC1_32_BOL_LD_BU_LONGOFF:
7990 case OPC1_32_BOL_LD_H_LONGOFF:
7991 case OPC1_32_BOL_LD_HU_LONGOFF:
7992 case OPC1_32_BOL_ST_B_LONGOFF:
7993 case OPC1_32_BOL_ST_H_LONGOFF:
7994 decode_bol_opc(env, ctx, op1);
7995 break;
7996 /* BRC Format */
7997 case OPCM_32_BRC_EQ_NEQ:
7998 case OPCM_32_BRC_GE:
7999 case OPCM_32_BRC_JLT:
8000 case OPCM_32_BRC_JNE:
8001 const4 = MASK_OP_BRC_CONST4_SEXT(ctx->opcode);
8002 address = MASK_OP_BRC_DISP15_SEXT(ctx->opcode);
8003 r1 = MASK_OP_BRC_S1(ctx->opcode);
8004 gen_compute_branch(ctx, op1, r1, 0, const4, address);
8005 break;
8006 /* BRN Format */
8007 case OPCM_32_BRN_JTT:
8008 address = MASK_OP_BRN_DISP15_SEXT(ctx->opcode);
8009 r1 = MASK_OP_BRN_S1(ctx->opcode);
8010 gen_compute_branch(ctx, op1, r1, 0, 0, address);
8011 break;
8012 /* BRR Format */
8013 case OPCM_32_BRR_EQ_NEQ:
8014 case OPCM_32_BRR_ADDR_EQ_NEQ:
8015 case OPCM_32_BRR_GE:
8016 case OPCM_32_BRR_JLT:
8017 case OPCM_32_BRR_JNE:
8018 case OPCM_32_BRR_JNZ:
8019 case OPCM_32_BRR_LOOP:
8020 address = MASK_OP_BRR_DISP15_SEXT(ctx->opcode);
8021 r2 = MASK_OP_BRR_S2(ctx->opcode);
8022 r1 = MASK_OP_BRR_S1(ctx->opcode);
8023 gen_compute_branch(ctx, op1, r1, r2, 0, address);
8024 break;
8025 /* RC Format */
8026 case OPCM_32_RC_LOGICAL_SHIFT:
8027 decode_rc_logical_shift(env, ctx);
8028 break;
8029 case OPCM_32_RC_ACCUMULATOR:
8030 decode_rc_accumulator(env, ctx);
8031 break;
8032 case OPCM_32_RC_SERVICEROUTINE:
8033 decode_rc_serviceroutine(env, ctx);
8034 break;
8035 case OPCM_32_RC_MUL:
8036 decode_rc_mul(env, ctx);
8037 break;
8038 /* RCPW Format */
8039 case OPCM_32_RCPW_MASK_INSERT:
8040 decode_rcpw_insert(env, ctx);
8041 break;
8042 /* RCRR Format */
8043 case OPC1_32_RCRR_INSERT:
8044 r1 = MASK_OP_RCRR_S1(ctx->opcode);
8045 r2 = MASK_OP_RCRR_S3(ctx->opcode);
8046 r3 = MASK_OP_RCRR_D(ctx->opcode);
8047 const16 = MASK_OP_RCRR_CONST4(ctx->opcode);
8048 temp = tcg_const_i32(const16);
8049 temp2 = tcg_temp_new(); /* width*/
8050 temp3 = tcg_temp_new(); /* pos */
8051
8052 tcg_gen_andi_tl(temp2, cpu_gpr_d[r3+1], 0x1f);
8053 tcg_gen_andi_tl(temp3, cpu_gpr_d[r3], 0x1f);
8054
8055 gen_insert(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, temp2, temp3);
8056
8057 tcg_temp_free(temp);
8058 tcg_temp_free(temp2);
8059 tcg_temp_free(temp3);
8060 break;
8061 /* RCRW Format */
8062 case OPCM_32_RCRW_MASK_INSERT:
8063 decode_rcrw_insert(env, ctx);
8064 break;
8065 /* RCR Format */
8066 case OPCM_32_RCR_COND_SELECT:
8067 decode_rcr_cond_select(env, ctx);
8068 break;
8069 case OPCM_32_RCR_MADD:
8070 decode_rcr_madd(env, ctx);
8071 break;
8072 case OPCM_32_RCR_MSUB:
8073 decode_rcr_msub(env, ctx);
8074 break;
8075 /* RLC Format */
8076 case OPC1_32_RLC_ADDI:
8077 case OPC1_32_RLC_ADDIH:
8078 case OPC1_32_RLC_ADDIH_A:
8079 case OPC1_32_RLC_MFCR:
8080 case OPC1_32_RLC_MOV:
8081 case OPC1_32_RLC_MOV_64:
8082 case OPC1_32_RLC_MOV_U:
8083 case OPC1_32_RLC_MOV_H:
8084 case OPC1_32_RLC_MOVH_A:
8085 case OPC1_32_RLC_MTCR:
8086 decode_rlc_opc(env, ctx, op1);
8087 break;
8088 /* RR Format */
8089 case OPCM_32_RR_ACCUMULATOR:
8090 decode_rr_accumulator(env, ctx);
8091 break;
8092 case OPCM_32_RR_LOGICAL_SHIFT:
8093 decode_rr_logical_shift(env, ctx);
8094 break;
8095 case OPCM_32_RR_ADDRESS:
8096 decode_rr_address(env, ctx);
8097 break;
8098 case OPCM_32_RR_IDIRECT:
8099 decode_rr_idirect(env, ctx);
8100 break;
8101 case OPCM_32_RR_DIVIDE:
8102 decode_rr_divide(env, ctx);
8103 break;
8104 /* RR1 Format */
8105 case OPCM_32_RR1_MUL:
8106 decode_rr1_mul(env, ctx);
8107 break;
8108 case OPCM_32_RR1_MULQ:
8109 decode_rr1_mulq(env, ctx);
8110 break;
8111 /* RR2 format */
8112 case OPCM_32_RR2_MUL:
8113 decode_rr2_mul(env, ctx);
8114 break;
8115 /* RRPW format */
8116 case OPCM_32_RRPW_EXTRACT_INSERT:
8117 decode_rrpw_extract_insert(env, ctx);
8118 break;
8119 case OPC1_32_RRPW_DEXTR:
8120 r1 = MASK_OP_RRPW_S1(ctx->opcode);
8121 r2 = MASK_OP_RRPW_S2(ctx->opcode);
8122 r3 = MASK_OP_RRPW_D(ctx->opcode);
8123 const16 = MASK_OP_RRPW_POS(ctx->opcode);
8124 if (r1 == r2) {
8125 tcg_gen_rotli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], const16);
8126 } else {
8127 temp = tcg_temp_new();
8128 tcg_gen_shli_tl(temp, cpu_gpr_d[r1], const16);
8129 tcg_gen_shri_tl(cpu_gpr_d[r3], cpu_gpr_d[r2], 32 - const16);
8130 tcg_gen_or_tl(cpu_gpr_d[r3], cpu_gpr_d[r3], temp);
8131 tcg_temp_free(temp);
8132 }
8133 break;
8134 /* RRR Format */
8135 case OPCM_32_RRR_COND_SELECT:
8136 decode_rrr_cond_select(env, ctx);
8137 break;
8138 case OPCM_32_RRR_DIVIDE:
8139 decode_rrr_divide(env, ctx);
8140 /* RRR2 Format */
8141 case OPCM_32_RRR2_MADD:
8142 decode_rrr2_madd(env, ctx);
8143 break;
8144 case OPCM_32_RRR2_MSUB:
8145 decode_rrr2_msub(env, ctx);
8146 break;
8147 /* RRR1 format */
8148 case OPCM_32_RRR1_MADD:
8149 decode_rrr1_madd(env, ctx);
8150 break;
8151 case OPCM_32_RRR1_MADDQ_H:
8152 decode_rrr1_maddq_h(env, ctx);
8153 break;
8154 case OPCM_32_RRR1_MADDSU_H:
8155 decode_rrr1_maddsu_h(env, ctx);
8156 break;
8157 case OPCM_32_RRR1_MSUB_H:
8158 decode_rrr1_msub(env, ctx);
8159 break;
8160 case OPCM_32_RRR1_MSUB_Q:
8161 decode_rrr1_msubq_h(env, ctx);
8162 break;
8163 case OPCM_32_RRR1_MSUBAD_H:
8164 decode_rrr1_msubad_h(env, ctx);
8165 break;
8166 /* RRRR format */
8167 case OPCM_32_RRRR_EXTRACT_INSERT:
8168 decode_rrrr_extract_insert(env, ctx);
8169 /* RRRW format */
8170 case OPCM_32_RRRW_EXTRACT_INSERT:
8171 decode_rrrw_extract_insert(env, ctx);
8172 break;
8173 /* SYS format */
8174 case OPCM_32_SYS_INTERRUPTS:
8175 decode_sys_interrupts(env, ctx);
8176 break;
8177 case OPC1_32_SYS_RSTV:
8178 tcg_gen_movi_tl(cpu_PSW_V, 0);
8179 tcg_gen_mov_tl(cpu_PSW_SV, cpu_PSW_V);
8180 tcg_gen_mov_tl(cpu_PSW_AV, cpu_PSW_V);
8181 tcg_gen_mov_tl(cpu_PSW_SAV, cpu_PSW_V);
8182 break;
8183 }
8184 }
8185
8186 static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
8187 {
8188 /* 16-Bit Instruction */
8189 if ((ctx->opcode & 0x1) == 0) {
8190 ctx->next_pc = ctx->pc + 2;
8191 decode_16Bit_opc(env, ctx);
8192 /* 32-Bit Instruction */
8193 } else {
8194 ctx->next_pc = ctx->pc + 4;
8195 decode_32Bit_opc(env, ctx);
8196 }
8197 }
8198
8199 static inline void
8200 gen_intermediate_code_internal(TriCoreCPU *cpu, struct TranslationBlock *tb,
8201 int search_pc)
8202 {
8203 CPUState *cs = CPU(cpu);
8204 CPUTriCoreState *env = &cpu->env;
8205 DisasContext ctx;
8206 target_ulong pc_start;
8207 int num_insns;
8208
8209 if (search_pc) {
8210 qemu_log("search pc %d\n", search_pc);
8211 }
8212
8213 num_insns = 0;
8214 pc_start = tb->pc;
8215 ctx.pc = pc_start;
8216 ctx.saved_pc = -1;
8217 ctx.tb = tb;
8218 ctx.singlestep_enabled = cs->singlestep_enabled;
8219 ctx.bstate = BS_NONE;
8220 ctx.mem_idx = cpu_mmu_index(env);
8221
8222 tcg_clear_temp_count();
8223 gen_tb_start(tb);
8224 while (ctx.bstate == BS_NONE) {
8225 ctx.opcode = cpu_ldl_code(env, ctx.pc);
8226 decode_opc(env, &ctx, 0);
8227
8228 num_insns++;
8229
8230 if (tcg_op_buf_full()) {
8231 gen_save_pc(ctx.next_pc);
8232 tcg_gen_exit_tb(0);
8233 break;
8234 }
8235 if (singlestep) {
8236 gen_save_pc(ctx.next_pc);
8237 tcg_gen_exit_tb(0);
8238 break;
8239 }
8240 ctx.pc = ctx.next_pc;
8241 }
8242
8243 gen_tb_end(tb, num_insns);
8244 if (search_pc) {
8245 printf("done_generating search pc\n");
8246 } else {
8247 tb->size = ctx.pc - pc_start;
8248 tb->icount = num_insns;
8249 }
8250 if (tcg_check_temp_count()) {
8251 printf("LEAK at %08x\n", env->PC);
8252 }
8253
8254 #ifdef DEBUG_DISAS
8255 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8256 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8257 log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
8258 qemu_log("\n");
8259 }
8260 #endif
8261 }
8262
8263 void
8264 gen_intermediate_code(CPUTriCoreState *env, struct TranslationBlock *tb)
8265 {
8266 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, false);
8267 }
8268
8269 void
8270 gen_intermediate_code_pc(CPUTriCoreState *env, struct TranslationBlock *tb)
8271 {
8272 gen_intermediate_code_internal(tricore_env_get_cpu(env), tb, true);
8273 }
8274
8275 void
8276 restore_state_to_opc(CPUTriCoreState *env, TranslationBlock *tb, int pc_pos)
8277 {
8278 env->PC = tcg_ctx.gen_opc_pc[pc_pos];
8279 }
8280 /*
8281 *
8282 * Initialization
8283 *
8284 */
8285
8286 void cpu_state_reset(CPUTriCoreState *env)
8287 {
8288 /* Reset Regs to Default Value */
8289 env->PSW = 0xb80;
8290 }
8291
8292 static void tricore_tcg_init_csfr(void)
8293 {
8294 cpu_PCXI = tcg_global_mem_new(TCG_AREG0,
8295 offsetof(CPUTriCoreState, PCXI), "PCXI");
8296 cpu_PSW = tcg_global_mem_new(TCG_AREG0,
8297 offsetof(CPUTriCoreState, PSW), "PSW");
8298 cpu_PC = tcg_global_mem_new(TCG_AREG0,
8299 offsetof(CPUTriCoreState, PC), "PC");
8300 cpu_ICR = tcg_global_mem_new(TCG_AREG0,
8301 offsetof(CPUTriCoreState, ICR), "ICR");
8302 }
8303
8304 void tricore_tcg_init(void)
8305 {
8306 int i;
8307 static int inited;
8308 if (inited) {
8309 return;
8310 }
8311 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
8312 /* reg init */
8313 for (i = 0 ; i < 16 ; i++) {
8314 cpu_gpr_a[i] = tcg_global_mem_new(TCG_AREG0,
8315 offsetof(CPUTriCoreState, gpr_a[i]),
8316 regnames_a[i]);
8317 }
8318 for (i = 0 ; i < 16 ; i++) {
8319 cpu_gpr_d[i] = tcg_global_mem_new(TCG_AREG0,
8320 offsetof(CPUTriCoreState, gpr_d[i]),
8321 regnames_d[i]);
8322 }
8323 tricore_tcg_init_csfr();
8324 /* init PSW flag cache */
8325 cpu_PSW_C = tcg_global_mem_new(TCG_AREG0,
8326 offsetof(CPUTriCoreState, PSW_USB_C),
8327 "PSW_C");
8328 cpu_PSW_V = tcg_global_mem_new(TCG_AREG0,
8329 offsetof(CPUTriCoreState, PSW_USB_V),
8330 "PSW_V");
8331 cpu_PSW_SV = tcg_global_mem_new(TCG_AREG0,
8332 offsetof(CPUTriCoreState, PSW_USB_SV),
8333 "PSW_SV");
8334 cpu_PSW_AV = tcg_global_mem_new(TCG_AREG0,
8335 offsetof(CPUTriCoreState, PSW_USB_AV),
8336 "PSW_AV");
8337 cpu_PSW_SAV = tcg_global_mem_new(TCG_AREG0,
8338 offsetof(CPUTriCoreState, PSW_USB_SAV),
8339 "PSW_SAV");
8340 }
QEmu