hw/mips_r4k.c

   1 /*
   2  * QEMU/MIPS pseudo-board
   3  *
   4  * emulates a simple machine with ISA-like bus.
   5  * ISA IO space mapped to the 0x14000000 (PHYS) and
   6  * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
   7  * All peripherial devices are attached to this "bus" with
   8  * the standard PC ISA addresses.
   9 */
  10 #include "hw.h"
  11 #include "mips.h"
  12 #include "pc.h"
  13 #include "isa.h"
  14 #include "net.h"
  15 #include "sysemu.h"
  16 #include "boards.h"
  17 #include "flash.h"
  18 #include "qemu-log.h"
  19 #include "mips-bios.h"
  20 #include "ide.h"
  21 #include "loader.h"
  22 #include "elf.h"
  23
  24 #define MAX_IDE_BUS 2
  25
  26 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  27 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  28 static const int ide_irq[2] = { 14, 15 };
  29
  30 static PITState *pit; /* PIT i8254 */
  31
  32 /* i8254 PIT is attached to the IRQ0 at PIC i8259 */
  33
  34 static struct _loaderparams {
  35     int ram_size;
  36     const char *kernel_filename;
  37     const char *kernel_cmdline;
  38     const char *initrd_filename;
  39 } loaderparams;
  40
  41 static void mips_qemu_writel (void *opaque, target_phys_addr_t addr,
  42                               uint32_t val)
  43 {
  44     if ((addr & 0xffff) == 0 && val == 42)
  45         qemu_system_reset_request ();
  46     else if ((addr & 0xffff) == 4 && val == 42)
  47         qemu_system_shutdown_request ();
  48 }
  49
  50 static uint32_t mips_qemu_readl (void *opaque, target_phys_addr_t addr)
  51 {
  52     return 0;
  53 }
  54
  55 static CPUWriteMemoryFunc * const mips_qemu_write[] = {
  56     &mips_qemu_writel,
  57     &mips_qemu_writel,
  58     &mips_qemu_writel,
  59 };
  60
  61 static CPUReadMemoryFunc * const mips_qemu_read[] = {
  62     &mips_qemu_readl,
  63     &mips_qemu_readl,
  64     &mips_qemu_readl,
  65 };
  66
  67 static int mips_qemu_iomemtype = 0;
  68
  69 typedef struct ResetData {
  70     CPUState *env;
  71     uint64_t vector;
  72 } ResetData;
  73
  74 static int64_t load_kernel(void)
  75 {
  76     int64_t entry, kernel_high;
  77     long kernel_size, initrd_size, params_size;
  78     ram_addr_t initrd_offset;
  79     uint32_t *params_buf;
  80     int big_endian;
  81
  82 #ifdef TARGET_WORDS_BIGENDIAN
  83     big_endian = 1;
  84 #else
  85     big_endian = 0;
  86 #endif
  87     kernel_size = load_elf(loaderparams.kernel_filename, cpu_mips_kseg0_to_phys,
  88                            NULL, (uint64_t *)&entry, NULL,
  89                            (uint64_t *)&kernel_high, big_endian,
  90                            ELF_MACHINE, 1);
  91     if (kernel_size >= 0) {
  92         if ((entry & ~0x7fffffffULL) == 0x80000000)
  93             entry = (int32_t)entry;
  94     } else {
  95         fprintf(stderr, "qemu: could not load kernel '%s'\n",
  96                 loaderparams.kernel_filename);
  97         exit(1);
  98     }
  99
 100     /* load initrd */
 101     initrd_size = 0;
 102     initrd_offset = 0;
 103     if (loaderparams.initrd_filename) {
 104         initrd_size = get_image_size (loaderparams.initrd_filename);
 105         if (initrd_size > 0) {
 106             initrd_offset = (kernel_high + ~TARGET_PAGE_MASK) & TARGET_PAGE_MASK;
 107             if (initrd_offset + initrd_size > ram_size) {
 108                 fprintf(stderr,
 109                         "qemu: memory too small for initial ram disk '%s'\n",
 110                         loaderparams.initrd_filename);
 111                 exit(1);
 112             }
 113             initrd_size = load_image_targphys(loaderparams.initrd_filename,
 114                                               initrd_offset,
 115                                               ram_size - initrd_offset);
 116         }
 117         if (initrd_size == (target_ulong) -1) {
 118             fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 119                     loaderparams.initrd_filename);
 120             exit(1);
 121         }
 122     }
 123
 124     /* Store command line.  */
 125     params_size = 264;
 126     params_buf = qemu_malloc(params_size);
 127
 128     params_buf[0] = tswap32(ram_size);
 129     params_buf[1] = tswap32(0x12345678);
 130
 131     if (initrd_size > 0) {
 132         snprintf((char *)params_buf + 8, 256, "rd_start=0x%" PRIx64 " rd_size=%li %s",
 133                  cpu_mips_phys_to_kseg0(NULL, initrd_offset),
 134                  initrd_size, loaderparams.kernel_cmdline);
 135     } else {
 136         snprintf((char *)params_buf + 8, 256, "%s", loaderparams.kernel_cmdline);
 137     }
 138
 139     rom_add_blob_fixed("params", params_buf, params_size,
 140                        (16 << 20) - 264);
 141
 142     return entry;
 143 }
 144
 145 static void main_cpu_reset(void *opaque)
 146 {
 147     ResetData *s = (ResetData *)opaque;
 148     CPUState *env = s->env;
 149
 150     cpu_reset(env);
 151     env->active_tc.PC = s->vector;
 152 }
 153
 154 static const int sector_len = 32 * 1024;
 155 static
 156 void mips_r4k_init (ram_addr_t ram_size,
 157                     const char *boot_device,
 158                     const char *kernel_filename, const char *kernel_cmdline,
 159                     const char *initrd_filename, const char *cpu_model)
 160 {
 161     char *filename;
 162     ram_addr_t ram_offset;
 163     ram_addr_t bios_offset;
 164     int bios_size;
 165     CPUState *env;
 166     ResetData *reset_info;
 167     RTCState *rtc_state;
 168     int i;
 169     qemu_irq *i8259;
 170     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 171     DriveInfo *dinfo;
 172
 173     /* init CPUs */
 174     if (cpu_model == NULL) {
 175 #ifdef TARGET_MIPS64
 176         cpu_model = "R4000";
 177 #else
 178         cpu_model = "24Kf";
 179 #endif
 180     }
 181     env = cpu_init(cpu_model);
 182     if (!env) {
 183         fprintf(stderr, "Unable to find CPU definition\n");
 184         exit(1);
 185     }
 186     reset_info = qemu_mallocz(sizeof(ResetData));
 187     reset_info->env = env;
 188     reset_info->vector = env->active_tc.PC;
 189     qemu_register_reset(main_cpu_reset, reset_info);
 190
 191     /* allocate RAM */
 192     if (ram_size > (256 << 20)) {
 193         fprintf(stderr,
 194                 "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
 195                 ((unsigned int)ram_size / (1 << 20)));
 196         exit(1);
 197     }
 198     ram_offset = qemu_ram_alloc(ram_size);
 199
 200     cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
 201
 202     if (!mips_qemu_iomemtype) {
 203         mips_qemu_iomemtype = cpu_register_io_memory(mips_qemu_read,
 204                                                      mips_qemu_write, NULL);
 205     }
 206     cpu_register_physical_memory(0x1fbf0000, 0x10000, mips_qemu_iomemtype);
 207
 208     /* Try to load a BIOS image. If this fails, we continue regardless,
 209        but initialize the hardware ourselves. When a kernel gets
 210        preloaded we also initialize the hardware, since the BIOS wasn't
 211        run. */
 212     if (bios_name == NULL)
 213         bios_name = BIOS_FILENAME;
 214     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 215     if (filename) {
 216         bios_size = get_image_size(filename);
 217     } else {
 218         bios_size = -1;
 219     }
 220     if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
 221         bios_offset = qemu_ram_alloc(BIOS_SIZE);
 222         cpu_register_physical_memory(0x1fc00000, BIOS_SIZE,
 223                                      bios_offset | IO_MEM_ROM);
 224
 225         load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
 226     } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) {
 227         uint32_t mips_rom = 0x00400000;
 228         bios_offset = qemu_ram_alloc(mips_rom);
 229         if (!pflash_cfi01_register(0x1fc00000, bios_offset,
 230             dinfo->bdrv, sector_len, mips_rom / sector_len,
 231             4, 0, 0, 0, 0)) {
 232             fprintf(stderr, "qemu: Error registering flash memory.\n");
 233         }
 234     }
 235     else {
 236         /* not fatal */
 237         fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
 238                 bios_name);
 239     }
 240     if (filename) {
 241         qemu_free(filename);
 242     }
 243
 244     if (kernel_filename) {
 245         loaderparams.ram_size = ram_size;
 246         loaderparams.kernel_filename = kernel_filename;
 247         loaderparams.kernel_cmdline = kernel_cmdline;
 248         loaderparams.initrd_filename = initrd_filename;
 249         reset_info->vector = load_kernel();
 250     }
 251
 252     /* Init CPU internal devices */
 253     cpu_mips_irq_init_cpu(env);
 254     cpu_mips_clock_init(env);
 255
 256     /* The PIC is attached to the MIPS CPU INT0 pin */
 257     i8259 = i8259_init(env->irq[2]);
 258     isa_bus_new(NULL);
 259     isa_bus_irqs(i8259);
 260
 261     rtc_state = rtc_init(2000);
 262
 263     /* Register 64 KB of ISA IO space at 0x14000000 */
 264     isa_mmio_init(0x14000000, 0x00010000);
 265     isa_mem_base = 0x10000000;
 266
 267     pit = pit_init(0x40, i8259[0]);
 268
 269     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 270         if (serial_hds[i]) {
 271             serial_isa_init(i, serial_hds[i]);
 272         }
 273     }
 274
 275     isa_vga_init();
 276
 277     if (nd_table[0].vlan)
 278         isa_ne2000_init(0x300, 9, &nd_table[0]);
 279
 280     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 281         fprintf(stderr, "qemu: too many IDE bus\n");
 282         exit(1);
 283     }
 284
 285     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 286         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
 287     }
 288
 289     for(i = 0; i < MAX_IDE_BUS; i++)
 290         isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
 291                      hd[MAX_IDE_DEVS * i],
 292                      hd[MAX_IDE_DEVS * i + 1]);
 293
 294     isa_create_simple("i8042");
 295 }
 296
 297 static QEMUMachine mips_machine = {
 298     .name = "mips",
 299     .desc = "mips r4k platform",
 300     .init = mips_r4k_init,
 301 };
 302
 303 static void mips_machine_init(void)
 304 {
 305     qemu_register_machine(&mips_machine);
 306 }
 307
 308 machine_init(mips_machine_init);