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pcihp: compose PCNT callchain right before its user _GPE._E01
[qemu.git] / target / arm / cpu_tcg.c
blobccde5080eb708bbddca51fde502c2dba58c1af85
1 /*
2 * QEMU ARM TCG CPUs.
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This code is licensed under the GNU GPL v2 or later.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
9 */
10
11 #include "qemu/osdep.h"
12 #include "cpu.h"
13 #ifdef CONFIG_TCG
14 #include "hw/core/tcg-cpu-ops.h"
15 #endif /* CONFIG_TCG */
16 #include "internals.h"
17 #include "target/arm/idau.h"
18 #if !defined(CONFIG_USER_ONLY)
19 #include "hw/boards.h"
20 #endif
21 #include "cpregs.h"
22
23
24 /* Share AArch32 -cpu max features with AArch64. */
25 void aa32_max_features(ARMCPU *cpu)
26 {
27 uint32_t t;
28
29 /* Add additional features supported by QEMU */
30 t = cpu->isar.id_isar5;
31 t = FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */
32 t = FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */
33 t = FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */
34 t = FIELD_DP32(t, ID_ISAR5, CRC32, 1);
35 t = FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */
36 t = FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */
37 cpu->isar.id_isar5 = t;
38
39 t = cpu->isar.id_isar6;
40 t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */
41 t = FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */
42 t = FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */
43 t = FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */
44 t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */
45 t = FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */
46 t = FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */
47 cpu->isar.id_isar6 = t;
48
49 t = cpu->isar.mvfr1;
50 t = FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */
51 t = FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */
52 cpu->isar.mvfr1 = t;
53
54 t = cpu->isar.mvfr2;
55 t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
56 t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
57 cpu->isar.mvfr2 = t;
58
59 t = cpu->isar.id_mmfr3;
60 t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */
61 cpu->isar.id_mmfr3 = t;
62
63 t = cpu->isar.id_mmfr4;
64 t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */
65 t = FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */
66 t = FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */
67 t = FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX */
68 t = FIELD_DP32(t, ID_MMFR4, EVT, 2); /* FEAT_EVT */
69 cpu->isar.id_mmfr4 = t;
70
71 t = cpu->isar.id_mmfr5;
72 t = FIELD_DP32(t, ID_MMFR5, ETS, 1); /* FEAT_ETS */
73 cpu->isar.id_mmfr5 = t;
74
75 t = cpu->isar.id_pfr0;
76 t = FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */
77 t = FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */
78 t = FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */
79 cpu->isar.id_pfr0 = t;
80
81 t = cpu->isar.id_pfr2;
82 t = FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */
83 t = FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */
84 cpu->isar.id_pfr2 = t;
85
86 t = cpu->isar.id_dfr0;
87 t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */
88 t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */
89 t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */
90 cpu->isar.id_dfr0 = t;
91 }
92
93 #ifndef CONFIG_USER_ONLY
94 static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
95 {
96 ARMCPU *cpu = env_archcpu(env);
97
98 /* Number of cores is in [25:24]; otherwise we RAZ */
99 return (cpu->core_count - 1) << 24;
100 }
101
102 static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] = {
103 { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
104 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
105 .access = PL1_RW, .readfn = l2ctlr_read,
106 .writefn = arm_cp_write_ignore },
107 { .name = "L2CTLR",
108 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
109 .access = PL1_RW, .readfn = l2ctlr_read,
110 .writefn = arm_cp_write_ignore },
111 { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
112 .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
113 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
114 { .name = "L2ECTLR",
115 .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
116 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
117 { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
118 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
119 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
120 { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
121 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
122 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
123 { .name = "CPUACTLR",
124 .cp = 15, .opc1 = 0, .crm = 15,
125 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
126 { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
127 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
128 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
129 { .name = "CPUECTLR",
130 .cp = 15, .opc1 = 1, .crm = 15,
131 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
132 { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
133 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
134 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
135 { .name = "CPUMERRSR",
136 .cp = 15, .opc1 = 2, .crm = 15,
137 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
138 { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
139 .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
140 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
141 { .name = "L2MERRSR",
142 .cp = 15, .opc1 = 3, .crm = 15,
143 .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
144 };
145
146 void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
147 {
148 define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
149 }
150 #endif /* !CONFIG_USER_ONLY */
151
152 /* CPU models. These are not needed for the AArch64 linux-user build. */
153 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
154
155 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
156 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
157 {
158 CPUClass *cc = CPU_GET_CLASS(cs);
159 ARMCPU *cpu = ARM_CPU(cs);
160 CPUARMState *env = &cpu->env;
161 bool ret = false;
162
163 /*
164 * ARMv7-M interrupt masking works differently than -A or -R.
165 * There is no FIQ/IRQ distinction. Instead of I and F bits
166 * masking FIQ and IRQ interrupts, an exception is taken only
167 * if it is higher priority than the current execution priority
168 * (which depends on state like BASEPRI, FAULTMASK and the
169 * currently active exception).
170 */
171 if (interrupt_request & CPU_INTERRUPT_HARD
172 && (armv7m_nvic_can_take_pending_exception(env->nvic))) {
173 cs->exception_index = EXCP_IRQ;
174 cc->tcg_ops->do_interrupt(cs);
175 ret = true;
176 }
177 return ret;
178 }
179 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */
180
181 static void arm926_initfn(Object *obj)
182 {
183 ARMCPU *cpu = ARM_CPU(obj);
184
185 cpu->dtb_compatible = "arm,arm926";
186 set_feature(&cpu->env, ARM_FEATURE_V5);
187 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
188 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
189 cpu->midr = 0x41069265;
190 cpu->reset_fpsid = 0x41011090;
191 cpu->ctr = 0x1dd20d2;
192 cpu->reset_sctlr = 0x00090078;
193
194 /*
195 * ARMv5 does not have the ID_ISAR registers, but we can still
196 * set the field to indicate Jazelle support within QEMU.
197 */
198 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
199 /*
200 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
201 * support even though ARMv5 doesn't have this register.
202 */
203 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
204 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
205 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
206 }
207
208 static void arm946_initfn(Object *obj)
209 {
210 ARMCPU *cpu = ARM_CPU(obj);
211
212 cpu->dtb_compatible = "arm,arm946";
213 set_feature(&cpu->env, ARM_FEATURE_V5);
214 set_feature(&cpu->env, ARM_FEATURE_PMSA);
215 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
216 cpu->midr = 0x41059461;
217 cpu->ctr = 0x0f004006;
218 cpu->reset_sctlr = 0x00000078;
219 }
220
221 static void arm1026_initfn(Object *obj)
222 {
223 ARMCPU *cpu = ARM_CPU(obj);
224
225 cpu->dtb_compatible = "arm,arm1026";
226 set_feature(&cpu->env, ARM_FEATURE_V5);
227 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
228 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
229 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
230 cpu->midr = 0x4106a262;
231 cpu->reset_fpsid = 0x410110a0;
232 cpu->ctr = 0x1dd20d2;
233 cpu->reset_sctlr = 0x00090078;
234 cpu->reset_auxcr = 1;
235
236 /*
237 * ARMv5 does not have the ID_ISAR registers, but we can still
238 * set the field to indicate Jazelle support within QEMU.
239 */
240 cpu->isar.id_isar1 = FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELLE, 1);
241 /*
242 * Similarly, we need to set MVFR0 fields to enable vfp and short vector
243 * support even though ARMv5 doesn't have this register.
244 */
245 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
246 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1);
247 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1);
248
249 {
250 /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
251 ARMCPRegInfo ifar = {
252 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
253 .access = PL1_RW,
254 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
255 .resetvalue = 0
256 };
257 define_one_arm_cp_reg(cpu, &ifar);
258 }
259 }
260
261 static void arm1136_r2_initfn(Object *obj)
262 {
263 ARMCPU *cpu = ARM_CPU(obj);
264 /*
265 * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
266 * older core than plain "arm1136". In particular this does not
267 * have the v6K features.
268 * These ID register values are correct for 1136 but may be wrong
269 * for 1136_r2 (in particular r0p2 does not actually implement most
270 * of the ID registers).
271 */
272
273 cpu->dtb_compatible = "arm,arm1136";
274 set_feature(&cpu->env, ARM_FEATURE_V6);
275 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
276 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
277 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
278 cpu->midr = 0x4107b362;
279 cpu->reset_fpsid = 0x410120b4;
280 cpu->isar.mvfr0 = 0x11111111;
281 cpu->isar.mvfr1 = 0x00000000;
282 cpu->ctr = 0x1dd20d2;
283 cpu->reset_sctlr = 0x00050078;
284 cpu->isar.id_pfr0 = 0x111;
285 cpu->isar.id_pfr1 = 0x1;
286 cpu->isar.id_dfr0 = 0x2;
287 cpu->id_afr0 = 0x3;
288 cpu->isar.id_mmfr0 = 0x01130003;
289 cpu->isar.id_mmfr1 = 0x10030302;
290 cpu->isar.id_mmfr2 = 0x01222110;
291 cpu->isar.id_isar0 = 0x00140011;
292 cpu->isar.id_isar1 = 0x12002111;
293 cpu->isar.id_isar2 = 0x11231111;
294 cpu->isar.id_isar3 = 0x01102131;
295 cpu->isar.id_isar4 = 0x141;
296 cpu->reset_auxcr = 7;
297 }
298
299 static void arm1136_initfn(Object *obj)
300 {
301 ARMCPU *cpu = ARM_CPU(obj);
302
303 cpu->dtb_compatible = "arm,arm1136";
304 set_feature(&cpu->env, ARM_FEATURE_V6K);
305 set_feature(&cpu->env, ARM_FEATURE_V6);
306 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
307 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
308 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
309 cpu->midr = 0x4117b363;
310 cpu->reset_fpsid = 0x410120b4;
311 cpu->isar.mvfr0 = 0x11111111;
312 cpu->isar.mvfr1 = 0x00000000;
313 cpu->ctr = 0x1dd20d2;
314 cpu->reset_sctlr = 0x00050078;
315 cpu->isar.id_pfr0 = 0x111;
316 cpu->isar.id_pfr1 = 0x1;
317 cpu->isar.id_dfr0 = 0x2;
318 cpu->id_afr0 = 0x3;
319 cpu->isar.id_mmfr0 = 0x01130003;
320 cpu->isar.id_mmfr1 = 0x10030302;
321 cpu->isar.id_mmfr2 = 0x01222110;
322 cpu->isar.id_isar0 = 0x00140011;
323 cpu->isar.id_isar1 = 0x12002111;
324 cpu->isar.id_isar2 = 0x11231111;
325 cpu->isar.id_isar3 = 0x01102131;
326 cpu->isar.id_isar4 = 0x141;
327 cpu->reset_auxcr = 7;
328 }
329
330 static void arm1176_initfn(Object *obj)
331 {
332 ARMCPU *cpu = ARM_CPU(obj);
333
334 cpu->dtb_compatible = "arm,arm1176";
335 set_feature(&cpu->env, ARM_FEATURE_V6K);
336 set_feature(&cpu->env, ARM_FEATURE_VAPA);
337 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
338 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
339 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
340 set_feature(&cpu->env, ARM_FEATURE_EL3);
341 cpu->midr = 0x410fb767;
342 cpu->reset_fpsid = 0x410120b5;
343 cpu->isar.mvfr0 = 0x11111111;
344 cpu->isar.mvfr1 = 0x00000000;
345 cpu->ctr = 0x1dd20d2;
346 cpu->reset_sctlr = 0x00050078;
347 cpu->isar.id_pfr0 = 0x111;
348 cpu->isar.id_pfr1 = 0x11;
349 cpu->isar.id_dfr0 = 0x33;
350 cpu->id_afr0 = 0;
351 cpu->isar.id_mmfr0 = 0x01130003;
352 cpu->isar.id_mmfr1 = 0x10030302;
353 cpu->isar.id_mmfr2 = 0x01222100;
354 cpu->isar.id_isar0 = 0x0140011;
355 cpu->isar.id_isar1 = 0x12002111;
356 cpu->isar.id_isar2 = 0x11231121;
357 cpu->isar.id_isar3 = 0x01102131;
358 cpu->isar.id_isar4 = 0x01141;
359 cpu->reset_auxcr = 7;
360 }
361
362 static void arm11mpcore_initfn(Object *obj)
363 {
364 ARMCPU *cpu = ARM_CPU(obj);
365
366 cpu->dtb_compatible = "arm,arm11mpcore";
367 set_feature(&cpu->env, ARM_FEATURE_V6K);
368 set_feature(&cpu->env, ARM_FEATURE_VAPA);
369 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
370 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
371 cpu->midr = 0x410fb022;
372 cpu->reset_fpsid = 0x410120b4;
373 cpu->isar.mvfr0 = 0x11111111;
374 cpu->isar.mvfr1 = 0x00000000;
375 cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
376 cpu->isar.id_pfr0 = 0x111;
377 cpu->isar.id_pfr1 = 0x1;
378 cpu->isar.id_dfr0 = 0;
379 cpu->id_afr0 = 0x2;
380 cpu->isar.id_mmfr0 = 0x01100103;
381 cpu->isar.id_mmfr1 = 0x10020302;
382 cpu->isar.id_mmfr2 = 0x01222000;
383 cpu->isar.id_isar0 = 0x00100011;
384 cpu->isar.id_isar1 = 0x12002111;
385 cpu->isar.id_isar2 = 0x11221011;
386 cpu->isar.id_isar3 = 0x01102131;
387 cpu->isar.id_isar4 = 0x141;
388 cpu->reset_auxcr = 1;
389 }
390
391 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
392 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
393 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
394 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
395 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
396 };
397
398 static void cortex_a8_initfn(Object *obj)
399 {
400 ARMCPU *cpu = ARM_CPU(obj);
401
402 cpu->dtb_compatible = "arm,cortex-a8";
403 set_feature(&cpu->env, ARM_FEATURE_V7);
404 set_feature(&cpu->env, ARM_FEATURE_NEON);
405 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
406 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
407 set_feature(&cpu->env, ARM_FEATURE_EL3);
408 cpu->midr = 0x410fc080;
409 cpu->reset_fpsid = 0x410330c0;
410 cpu->isar.mvfr0 = 0x11110222;
411 cpu->isar.mvfr1 = 0x00011111;
412 cpu->ctr = 0x82048004;
413 cpu->reset_sctlr = 0x00c50078;
414 cpu->isar.id_pfr0 = 0x1031;
415 cpu->isar.id_pfr1 = 0x11;
416 cpu->isar.id_dfr0 = 0x400;
417 cpu->id_afr0 = 0;
418 cpu->isar.id_mmfr0 = 0x31100003;
419 cpu->isar.id_mmfr1 = 0x20000000;
420 cpu->isar.id_mmfr2 = 0x01202000;
421 cpu->isar.id_mmfr3 = 0x11;
422 cpu->isar.id_isar0 = 0x00101111;
423 cpu->isar.id_isar1 = 0x12112111;
424 cpu->isar.id_isar2 = 0x21232031;
425 cpu->isar.id_isar3 = 0x11112131;
426 cpu->isar.id_isar4 = 0x00111142;
427 cpu->isar.dbgdidr = 0x15141000;
428 cpu->clidr = (1 << 27) | (2 << 24) | 3;
429 cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
430 cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
431 cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
432 cpu->reset_auxcr = 2;
433 cpu->isar.reset_pmcr_el0 = 0x41002000;
434 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
435 }
436
437 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
438 /*
439 * power_control should be set to maximum latency. Again,
440 * default to 0 and set by private hook
441 */
442 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
443 .access = PL1_RW, .resetvalue = 0,
444 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
445 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
446 .access = PL1_RW, .resetvalue = 0,
447 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
448 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
449 .access = PL1_RW, .resetvalue = 0,
450 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
451 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
452 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
453 /* TLB lockdown control */
454 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
455 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
456 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
457 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
458 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
459 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
460 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
461 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
462 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
463 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
464 };
465
466 static void cortex_a9_initfn(Object *obj)
467 {
468 ARMCPU *cpu = ARM_CPU(obj);
469
470 cpu->dtb_compatible = "arm,cortex-a9";
471 set_feature(&cpu->env, ARM_FEATURE_V7);
472 set_feature(&cpu->env, ARM_FEATURE_NEON);
473 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
474 set_feature(&cpu->env, ARM_FEATURE_EL3);
475 /*
476 * Note that A9 supports the MP extensions even for
477 * A9UP and single-core A9MP (which are both different
478 * and valid configurations; we don't model A9UP).
479 */
480 set_feature(&cpu->env, ARM_FEATURE_V7MP);
481 set_feature(&cpu->env, ARM_FEATURE_CBAR);
482 cpu->midr = 0x410fc090;
483 cpu->reset_fpsid = 0x41033090;
484 cpu->isar.mvfr0 = 0x11110222;
485 cpu->isar.mvfr1 = 0x01111111;
486 cpu->ctr = 0x80038003;
487 cpu->reset_sctlr = 0x00c50078;
488 cpu->isar.id_pfr0 = 0x1031;
489 cpu->isar.id_pfr1 = 0x11;
490 cpu->isar.id_dfr0 = 0x000;
491 cpu->id_afr0 = 0;
492 cpu->isar.id_mmfr0 = 0x00100103;
493 cpu->isar.id_mmfr1 = 0x20000000;
494 cpu->isar.id_mmfr2 = 0x01230000;
495 cpu->isar.id_mmfr3 = 0x00002111;
496 cpu->isar.id_isar0 = 0x00101111;
497 cpu->isar.id_isar1 = 0x13112111;
498 cpu->isar.id_isar2 = 0x21232041;
499 cpu->isar.id_isar3 = 0x11112131;
500 cpu->isar.id_isar4 = 0x00111142;
501 cpu->isar.dbgdidr = 0x35141000;
502 cpu->clidr = (1 << 27) | (1 << 24) | 3;
503 cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
504 cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
505 cpu->isar.reset_pmcr_el0 = 0x41093000;
506 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
507 }
508
509 #ifndef CONFIG_USER_ONLY
510 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
511 {
512 MachineState *ms = MACHINE(qdev_get_machine());
513
514 /*
515 * Linux wants the number of processors from here.
516 * Might as well set the interrupt-controller bit too.
517 */
518 return ((ms->smp.cpus - 1) << 24) | (1 << 23);
519 }
520 #endif
521
522 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
523 #ifndef CONFIG_USER_ONLY
524 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
525 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
526 .writefn = arm_cp_write_ignore, },
527 #endif
528 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
529 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
530 };
531
532 static void cortex_a7_initfn(Object *obj)
533 {
534 ARMCPU *cpu = ARM_CPU(obj);
535
536 cpu->dtb_compatible = "arm,cortex-a7";
537 set_feature(&cpu->env, ARM_FEATURE_V7VE);
538 set_feature(&cpu->env, ARM_FEATURE_NEON);
539 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
540 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
541 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
542 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
543 set_feature(&cpu->env, ARM_FEATURE_EL2);
544 set_feature(&cpu->env, ARM_FEATURE_EL3);
545 set_feature(&cpu->env, ARM_FEATURE_PMU);
546 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
547 cpu->midr = 0x410fc075;
548 cpu->reset_fpsid = 0x41023075;
549 cpu->isar.mvfr0 = 0x10110222;
550 cpu->isar.mvfr1 = 0x11111111;
551 cpu->ctr = 0x84448003;
552 cpu->reset_sctlr = 0x00c50078;
553 cpu->isar.id_pfr0 = 0x00001131;
554 cpu->isar.id_pfr1 = 0x00011011;
555 cpu->isar.id_dfr0 = 0x02010555;
556 cpu->id_afr0 = 0x00000000;
557 cpu->isar.id_mmfr0 = 0x10101105;
558 cpu->isar.id_mmfr1 = 0x40000000;
559 cpu->isar.id_mmfr2 = 0x01240000;
560 cpu->isar.id_mmfr3 = 0x02102211;
561 /*
562 * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
563 * table 4-41 gives 0x02101110, which includes the arm div insns.
564 */
565 cpu->isar.id_isar0 = 0x02101110;
566 cpu->isar.id_isar1 = 0x13112111;
567 cpu->isar.id_isar2 = 0x21232041;
568 cpu->isar.id_isar3 = 0x11112131;
569 cpu->isar.id_isar4 = 0x10011142;
570 cpu->isar.dbgdidr = 0x3515f005;
571 cpu->isar.dbgdevid = 0x01110f13;
572 cpu->isar.dbgdevid1 = 0x1;
573 cpu->clidr = 0x0a200023;
574 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
575 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
576 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
577 cpu->isar.reset_pmcr_el0 = 0x41072000;
578 define_arm_cp_regs(cpu, cortexa15_cp_reginfo); /* Same as A15 */
579 }
580
581 static void cortex_a15_initfn(Object *obj)
582 {
583 ARMCPU *cpu = ARM_CPU(obj);
584
585 cpu->dtb_compatible = "arm,cortex-a15";
586 set_feature(&cpu->env, ARM_FEATURE_V7VE);
587 set_feature(&cpu->env, ARM_FEATURE_NEON);
588 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
589 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
590 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
591 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
592 set_feature(&cpu->env, ARM_FEATURE_EL2);
593 set_feature(&cpu->env, ARM_FEATURE_EL3);
594 set_feature(&cpu->env, ARM_FEATURE_PMU);
595 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
596 /* r4p0 cpu, not requiring expensive tlb flush errata */
597 cpu->midr = 0x414fc0f0;
598 cpu->revidr = 0x0;
599 cpu->reset_fpsid = 0x410430f0;
600 cpu->isar.mvfr0 = 0x10110222;
601 cpu->isar.mvfr1 = 0x11111111;
602 cpu->ctr = 0x8444c004;
603 cpu->reset_sctlr = 0x00c50078;
604 cpu->isar.id_pfr0 = 0x00001131;
605 cpu->isar.id_pfr1 = 0x00011011;
606 cpu->isar.id_dfr0 = 0x02010555;
607 cpu->id_afr0 = 0x00000000;
608 cpu->isar.id_mmfr0 = 0x10201105;
609 cpu->isar.id_mmfr1 = 0x20000000;
610 cpu->isar.id_mmfr2 = 0x01240000;
611 cpu->isar.id_mmfr3 = 0x02102211;
612 cpu->isar.id_isar0 = 0x02101110;
613 cpu->isar.id_isar1 = 0x13112111;
614 cpu->isar.id_isar2 = 0x21232041;
615 cpu->isar.id_isar3 = 0x11112131;
616 cpu->isar.id_isar4 = 0x10011142;
617 cpu->isar.dbgdidr = 0x3515f021;
618 cpu->isar.dbgdevid = 0x01110f13;
619 cpu->isar.dbgdevid1 = 0x0;
620 cpu->clidr = 0x0a200023;
621 cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
622 cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
623 cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
624 cpu->isar.reset_pmcr_el0 = 0x410F3000;
625 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
626 }
627
628 static void cortex_m0_initfn(Object *obj)
629 {
630 ARMCPU *cpu = ARM_CPU(obj);
631 set_feature(&cpu->env, ARM_FEATURE_V6);
632 set_feature(&cpu->env, ARM_FEATURE_M);
633
634 cpu->midr = 0x410cc200;
635
636 /*
637 * These ID register values are not guest visible, because
638 * we do not implement the Main Extension. They must be set
639 * to values corresponding to the Cortex-M0's implemented
640 * features, because QEMU generally controls its emulation
641 * by looking at ID register fields. We use the same values as
642 * for the M3.
643 */
644 cpu->isar.id_pfr0 = 0x00000030;
645 cpu->isar.id_pfr1 = 0x00000200;
646 cpu->isar.id_dfr0 = 0x00100000;
647 cpu->id_afr0 = 0x00000000;
648 cpu->isar.id_mmfr0 = 0x00000030;
649 cpu->isar.id_mmfr1 = 0x00000000;
650 cpu->isar.id_mmfr2 = 0x00000000;
651 cpu->isar.id_mmfr3 = 0x00000000;
652 cpu->isar.id_isar0 = 0x01141110;
653 cpu->isar.id_isar1 = 0x02111000;
654 cpu->isar.id_isar2 = 0x21112231;
655 cpu->isar.id_isar3 = 0x01111110;
656 cpu->isar.id_isar4 = 0x01310102;
657 cpu->isar.id_isar5 = 0x00000000;
658 cpu->isar.id_isar6 = 0x00000000;
659 }
660
661 static void cortex_m3_initfn(Object *obj)
662 {
663 ARMCPU *cpu = ARM_CPU(obj);
664 set_feature(&cpu->env, ARM_FEATURE_V7);
665 set_feature(&cpu->env, ARM_FEATURE_M);
666 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
667 cpu->midr = 0x410fc231;
668 cpu->pmsav7_dregion = 8;
669 cpu->isar.id_pfr0 = 0x00000030;
670 cpu->isar.id_pfr1 = 0x00000200;
671 cpu->isar.id_dfr0 = 0x00100000;
672 cpu->id_afr0 = 0x00000000;
673 cpu->isar.id_mmfr0 = 0x00000030;
674 cpu->isar.id_mmfr1 = 0x00000000;
675 cpu->isar.id_mmfr2 = 0x00000000;
676 cpu->isar.id_mmfr3 = 0x00000000;
677 cpu->isar.id_isar0 = 0x01141110;
678 cpu->isar.id_isar1 = 0x02111000;
679 cpu->isar.id_isar2 = 0x21112231;
680 cpu->isar.id_isar3 = 0x01111110;
681 cpu->isar.id_isar4 = 0x01310102;
682 cpu->isar.id_isar5 = 0x00000000;
683 cpu->isar.id_isar6 = 0x00000000;
684 }
685
686 static void cortex_m4_initfn(Object *obj)
687 {
688 ARMCPU *cpu = ARM_CPU(obj);
689
690 set_feature(&cpu->env, ARM_FEATURE_V7);
691 set_feature(&cpu->env, ARM_FEATURE_M);
692 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
693 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
694 cpu->midr = 0x410fc240; /* r0p0 */
695 cpu->pmsav7_dregion = 8;
696 cpu->isar.mvfr0 = 0x10110021;
697 cpu->isar.mvfr1 = 0x11000011;
698 cpu->isar.mvfr2 = 0x00000000;
699 cpu->isar.id_pfr0 = 0x00000030;
700 cpu->isar.id_pfr1 = 0x00000200;
701 cpu->isar.id_dfr0 = 0x00100000;
702 cpu->id_afr0 = 0x00000000;
703 cpu->isar.id_mmfr0 = 0x00000030;
704 cpu->isar.id_mmfr1 = 0x00000000;
705 cpu->isar.id_mmfr2 = 0x00000000;
706 cpu->isar.id_mmfr3 = 0x00000000;
707 cpu->isar.id_isar0 = 0x01141110;
708 cpu->isar.id_isar1 = 0x02111000;
709 cpu->isar.id_isar2 = 0x21112231;
710 cpu->isar.id_isar3 = 0x01111110;
711 cpu->isar.id_isar4 = 0x01310102;
712 cpu->isar.id_isar5 = 0x00000000;
713 cpu->isar.id_isar6 = 0x00000000;
714 }
715
716 static void cortex_m7_initfn(Object *obj)
717 {
718 ARMCPU *cpu = ARM_CPU(obj);
719
720 set_feature(&cpu->env, ARM_FEATURE_V7);
721 set_feature(&cpu->env, ARM_FEATURE_M);
722 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
723 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
724 cpu->midr = 0x411fc272; /* r1p2 */
725 cpu->pmsav7_dregion = 8;
726 cpu->isar.mvfr0 = 0x10110221;
727 cpu->isar.mvfr1 = 0x12000011;
728 cpu->isar.mvfr2 = 0x00000040;
729 cpu->isar.id_pfr0 = 0x00000030;
730 cpu->isar.id_pfr1 = 0x00000200;
731 cpu->isar.id_dfr0 = 0x00100000;
732 cpu->id_afr0 = 0x00000000;
733 cpu->isar.id_mmfr0 = 0x00100030;
734 cpu->isar.id_mmfr1 = 0x00000000;
735 cpu->isar.id_mmfr2 = 0x01000000;
736 cpu->isar.id_mmfr3 = 0x00000000;
737 cpu->isar.id_isar0 = 0x01101110;
738 cpu->isar.id_isar1 = 0x02112000;
739 cpu->isar.id_isar2 = 0x20232231;
740 cpu->isar.id_isar3 = 0x01111131;
741 cpu->isar.id_isar4 = 0x01310132;
742 cpu->isar.id_isar5 = 0x00000000;
743 cpu->isar.id_isar6 = 0x00000000;
744 }
745
746 static void cortex_m33_initfn(Object *obj)
747 {
748 ARMCPU *cpu = ARM_CPU(obj);
749
750 set_feature(&cpu->env, ARM_FEATURE_V8);
751 set_feature(&cpu->env, ARM_FEATURE_M);
752 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
753 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
754 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
755 cpu->midr = 0x410fd213; /* r0p3 */
756 cpu->pmsav7_dregion = 16;
757 cpu->sau_sregion = 8;
758 cpu->isar.mvfr0 = 0x10110021;
759 cpu->isar.mvfr1 = 0x11000011;
760 cpu->isar.mvfr2 = 0x00000040;
761 cpu->isar.id_pfr0 = 0x00000030;
762 cpu->isar.id_pfr1 = 0x00000210;
763 cpu->isar.id_dfr0 = 0x00200000;
764 cpu->id_afr0 = 0x00000000;
765 cpu->isar.id_mmfr0 = 0x00101F40;
766 cpu->isar.id_mmfr1 = 0x00000000;
767 cpu->isar.id_mmfr2 = 0x01000000;
768 cpu->isar.id_mmfr3 = 0x00000000;
769 cpu->isar.id_isar0 = 0x01101110;
770 cpu->isar.id_isar1 = 0x02212000;
771 cpu->isar.id_isar2 = 0x20232232;
772 cpu->isar.id_isar3 = 0x01111131;
773 cpu->isar.id_isar4 = 0x01310132;
774 cpu->isar.id_isar5 = 0x00000000;
775 cpu->isar.id_isar6 = 0x00000000;
776 cpu->clidr = 0x00000000;
777 cpu->ctr = 0x8000c000;
778 }
779
780 static void cortex_m55_initfn(Object *obj)
781 {
782 ARMCPU *cpu = ARM_CPU(obj);
783
784 set_feature(&cpu->env, ARM_FEATURE_V8);
785 set_feature(&cpu->env, ARM_FEATURE_V8_1M);
786 set_feature(&cpu->env, ARM_FEATURE_M);
787 set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
788 set_feature(&cpu->env, ARM_FEATURE_M_SECURITY);
789 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
790 cpu->midr = 0x410fd221; /* r0p1 */
791 cpu->revidr = 0;
792 cpu->pmsav7_dregion = 16;
793 cpu->sau_sregion = 8;
794 /* These are the MVFR* values for the FPU + full MVE configuration */
795 cpu->isar.mvfr0 = 0x10110221;
796 cpu->isar.mvfr1 = 0x12100211;
797 cpu->isar.mvfr2 = 0x00000040;
798 cpu->isar.id_pfr0 = 0x20000030;
799 cpu->isar.id_pfr1 = 0x00000230;
800 cpu->isar.id_dfr0 = 0x10200000;
801 cpu->id_afr0 = 0x00000000;
802 cpu->isar.id_mmfr0 = 0x00111040;
803 cpu->isar.id_mmfr1 = 0x00000000;
804 cpu->isar.id_mmfr2 = 0x01000000;
805 cpu->isar.id_mmfr3 = 0x00000011;
806 cpu->isar.id_isar0 = 0x01103110;
807 cpu->isar.id_isar1 = 0x02212000;
808 cpu->isar.id_isar2 = 0x20232232;
809 cpu->isar.id_isar3 = 0x01111131;
810 cpu->isar.id_isar4 = 0x01310132;
811 cpu->isar.id_isar5 = 0x00000000;
812 cpu->isar.id_isar6 = 0x00000000;
813 cpu->clidr = 0x00000000; /* caches not implemented */
814 cpu->ctr = 0x8303c003;
815 }
816
817 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
818 /* Dummy the TCM region regs for the moment */
819 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
820 .access = PL1_RW, .type = ARM_CP_CONST },
821 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
822 .access = PL1_RW, .type = ARM_CP_CONST },
823 { .name = "DCACHE_INVAL", .cp = 15, .opc1 = 0, .crn = 15, .crm = 5,
824 .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP },
825 };
826
827 static void cortex_r5_initfn(Object *obj)
828 {
829 ARMCPU *cpu = ARM_CPU(obj);
830
831 set_feature(&cpu->env, ARM_FEATURE_V7);
832 set_feature(&cpu->env, ARM_FEATURE_V7MP);
833 set_feature(&cpu->env, ARM_FEATURE_PMSA);
834 set_feature(&cpu->env, ARM_FEATURE_PMU);
835 cpu->midr = 0x411fc153; /* r1p3 */
836 cpu->isar.id_pfr0 = 0x0131;
837 cpu->isar.id_pfr1 = 0x001;
838 cpu->isar.id_dfr0 = 0x010400;
839 cpu->id_afr0 = 0x0;
840 cpu->isar.id_mmfr0 = 0x0210030;
841 cpu->isar.id_mmfr1 = 0x00000000;
842 cpu->isar.id_mmfr2 = 0x01200000;
843 cpu->isar.id_mmfr3 = 0x0211;
844 cpu->isar.id_isar0 = 0x02101111;
845 cpu->isar.id_isar1 = 0x13112111;
846 cpu->isar.id_isar2 = 0x21232141;
847 cpu->isar.id_isar3 = 0x01112131;
848 cpu->isar.id_isar4 = 0x0010142;
849 cpu->isar.id_isar5 = 0x0;
850 cpu->isar.id_isar6 = 0x0;
851 cpu->mp_is_up = true;
852 cpu->pmsav7_dregion = 16;
853 cpu->isar.reset_pmcr_el0 = 0x41151800;
854 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
855 }
856
857 static void cortex_r52_initfn(Object *obj)
858 {
859 ARMCPU *cpu = ARM_CPU(obj);
860
861 set_feature(&cpu->env, ARM_FEATURE_V8);
862 set_feature(&cpu->env, ARM_FEATURE_EL2);
863 set_feature(&cpu->env, ARM_FEATURE_PMSA);
864 set_feature(&cpu->env, ARM_FEATURE_NEON);
865 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
866 cpu->midr = 0x411fd133; /* r1p3 */
867 cpu->revidr = 0x00000000;
868 cpu->reset_fpsid = 0x41034023;
869 cpu->isar.mvfr0 = 0x10110222;
870 cpu->isar.mvfr1 = 0x12111111;
871 cpu->isar.mvfr2 = 0x00000043;
872 cpu->ctr = 0x8144c004;
873 cpu->reset_sctlr = 0x30c50838;
874 cpu->isar.id_pfr0 = 0x00000131;
875 cpu->isar.id_pfr1 = 0x10111001;
876 cpu->isar.id_dfr0 = 0x03010006;
877 cpu->id_afr0 = 0x00000000;
878 cpu->isar.id_mmfr0 = 0x00211040;
879 cpu->isar.id_mmfr1 = 0x40000000;
880 cpu->isar.id_mmfr2 = 0x01200000;
881 cpu->isar.id_mmfr3 = 0xf0102211;
882 cpu->isar.id_mmfr4 = 0x00000010;
883 cpu->isar.id_isar0 = 0x02101110;
884 cpu->isar.id_isar1 = 0x13112111;
885 cpu->isar.id_isar2 = 0x21232142;
886 cpu->isar.id_isar3 = 0x01112131;
887 cpu->isar.id_isar4 = 0x00010142;
888 cpu->isar.id_isar5 = 0x00010001;
889 cpu->isar.dbgdidr = 0x77168000;
890 cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
891 cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
892 cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
893
894 cpu->pmsav7_dregion = 16;
895 cpu->pmsav8r_hdregion = 16;
896 }
897
898 static void cortex_r5f_initfn(Object *obj)
899 {
900 ARMCPU *cpu = ARM_CPU(obj);
901
902 cortex_r5_initfn(obj);
903 cpu->isar.mvfr0 = 0x10110221;
904 cpu->isar.mvfr1 = 0x00000011;
905 }
906
907 static void ti925t_initfn(Object *obj)
908 {
909 ARMCPU *cpu = ARM_CPU(obj);
910 set_feature(&cpu->env, ARM_FEATURE_V4T);
911 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
912 cpu->midr = ARM_CPUID_TI925T;
913 cpu->ctr = 0x5109149;
914 cpu->reset_sctlr = 0x00000070;
915 }
916
917 static void sa1100_initfn(Object *obj)
918 {
919 ARMCPU *cpu = ARM_CPU(obj);
920
921 cpu->dtb_compatible = "intel,sa1100";
922 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
923 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
924 cpu->midr = 0x4401A11B;
925 cpu->reset_sctlr = 0x00000070;
926 }
927
928 static void sa1110_initfn(Object *obj)
929 {
930 ARMCPU *cpu = ARM_CPU(obj);
931 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
932 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
933 cpu->midr = 0x6901B119;
934 cpu->reset_sctlr = 0x00000070;
935 }
936
937 static void pxa250_initfn(Object *obj)
938 {
939 ARMCPU *cpu = ARM_CPU(obj);
940
941 cpu->dtb_compatible = "marvell,xscale";
942 set_feature(&cpu->env, ARM_FEATURE_V5);
943 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
944 cpu->midr = 0x69052100;
945 cpu->ctr = 0xd172172;
946 cpu->reset_sctlr = 0x00000078;
947 }
948
949 static void pxa255_initfn(Object *obj)
950 {
951 ARMCPU *cpu = ARM_CPU(obj);
952
953 cpu->dtb_compatible = "marvell,xscale";
954 set_feature(&cpu->env, ARM_FEATURE_V5);
955 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
956 cpu->midr = 0x69052d00;
957 cpu->ctr = 0xd172172;
958 cpu->reset_sctlr = 0x00000078;
959 }
960
961 static void pxa260_initfn(Object *obj)
962 {
963 ARMCPU *cpu = ARM_CPU(obj);
964
965 cpu->dtb_compatible = "marvell,xscale";
966 set_feature(&cpu->env, ARM_FEATURE_V5);
967 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
968 cpu->midr = 0x69052903;
969 cpu->ctr = 0xd172172;
970 cpu->reset_sctlr = 0x00000078;
971 }
972
973 static void pxa261_initfn(Object *obj)
974 {
975 ARMCPU *cpu = ARM_CPU(obj);
976
977 cpu->dtb_compatible = "marvell,xscale";
978 set_feature(&cpu->env, ARM_FEATURE_V5);
979 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
980 cpu->midr = 0x69052d05;
981 cpu->ctr = 0xd172172;
982 cpu->reset_sctlr = 0x00000078;
983 }
984
985 static void pxa262_initfn(Object *obj)
986 {
987 ARMCPU *cpu = ARM_CPU(obj);
988
989 cpu->dtb_compatible = "marvell,xscale";
990 set_feature(&cpu->env, ARM_FEATURE_V5);
991 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
992 cpu->midr = 0x69052d06;
993 cpu->ctr = 0xd172172;
994 cpu->reset_sctlr = 0x00000078;
995 }
996
997 static void pxa270a0_initfn(Object *obj)
998 {
999 ARMCPU *cpu = ARM_CPU(obj);
1000
1001 cpu->dtb_compatible = "marvell,xscale";
1002 set_feature(&cpu->env, ARM_FEATURE_V5);
1003 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1004 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1005 cpu->midr = 0x69054110;
1006 cpu->ctr = 0xd172172;
1007 cpu->reset_sctlr = 0x00000078;
1008 }
1009
1010 static void pxa270a1_initfn(Object *obj)
1011 {
1012 ARMCPU *cpu = ARM_CPU(obj);
1013
1014 cpu->dtb_compatible = "marvell,xscale";
1015 set_feature(&cpu->env, ARM_FEATURE_V5);
1016 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1017 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1018 cpu->midr = 0x69054111;
1019 cpu->ctr = 0xd172172;
1020 cpu->reset_sctlr = 0x00000078;
1021 }
1022
1023 static void pxa270b0_initfn(Object *obj)
1024 {
1025 ARMCPU *cpu = ARM_CPU(obj);
1026
1027 cpu->dtb_compatible = "marvell,xscale";
1028 set_feature(&cpu->env, ARM_FEATURE_V5);
1029 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1030 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1031 cpu->midr = 0x69054112;
1032 cpu->ctr = 0xd172172;
1033 cpu->reset_sctlr = 0x00000078;
1034 }
1035
1036 static void pxa270b1_initfn(Object *obj)
1037 {
1038 ARMCPU *cpu = ARM_CPU(obj);
1039
1040 cpu->dtb_compatible = "marvell,xscale";
1041 set_feature(&cpu->env, ARM_FEATURE_V5);
1042 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1043 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1044 cpu->midr = 0x69054113;
1045 cpu->ctr = 0xd172172;
1046 cpu->reset_sctlr = 0x00000078;
1047 }
1048
1049 static void pxa270c0_initfn(Object *obj)
1050 {
1051 ARMCPU *cpu = ARM_CPU(obj);
1052
1053 cpu->dtb_compatible = "marvell,xscale";
1054 set_feature(&cpu->env, ARM_FEATURE_V5);
1055 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1056 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1057 cpu->midr = 0x69054114;
1058 cpu->ctr = 0xd172172;
1059 cpu->reset_sctlr = 0x00000078;
1060 }
1061
1062 static void pxa270c5_initfn(Object *obj)
1063 {
1064 ARMCPU *cpu = ARM_CPU(obj);
1065
1066 cpu->dtb_compatible = "marvell,xscale";
1067 set_feature(&cpu->env, ARM_FEATURE_V5);
1068 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1069 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1070 cpu->midr = 0x69054117;
1071 cpu->ctr = 0xd172172;
1072 cpu->reset_sctlr = 0x00000078;
1073 }
1074
1075 #ifdef CONFIG_TCG
1076 static const struct TCGCPUOps arm_v7m_tcg_ops = {
1077 .initialize = arm_translate_init,
1078 .synchronize_from_tb = arm_cpu_synchronize_from_tb,
1079 .debug_excp_handler = arm_debug_excp_handler,
1080 .restore_state_to_opc = arm_restore_state_to_opc,
1081
1082 #ifdef CONFIG_USER_ONLY
1083 .record_sigsegv = arm_cpu_record_sigsegv,
1084 .record_sigbus = arm_cpu_record_sigbus,
1085 #else
1086 .tlb_fill = arm_cpu_tlb_fill,
1087 .cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt,
1088 .do_interrupt = arm_v7m_cpu_do_interrupt,
1089 .do_transaction_failed = arm_cpu_do_transaction_failed,
1090 .do_unaligned_access = arm_cpu_do_unaligned_access,
1091 .adjust_watchpoint_address = arm_adjust_watchpoint_address,
1092 .debug_check_watchpoint = arm_debug_check_watchpoint,
1093 .debug_check_breakpoint = arm_debug_check_breakpoint,
1094 #endif /* !CONFIG_USER_ONLY */
1095 };
1096 #endif /* CONFIG_TCG */
1097
1098 static void arm_v7m_class_init(ObjectClass *oc, void *data)
1099 {
1100 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1101 CPUClass *cc = CPU_CLASS(oc);
1102
1103 acc->info = data;
1104 #ifdef CONFIG_TCG
1105 cc->tcg_ops = &arm_v7m_tcg_ops;
1106 #endif /* CONFIG_TCG */
1107
1108 cc->gdb_core_xml_file = "arm-m-profile.xml";
1109 }
1110
1111 #ifndef TARGET_AARCH64
1112 /*
1113 * -cpu max: a CPU with as many features enabled as our emulation supports.
1114 * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
1115 * this only needs to handle 32 bits, and need not care about KVM.
1116 */
1117 static void arm_max_initfn(Object *obj)
1118 {
1119 ARMCPU *cpu = ARM_CPU(obj);
1120
1121 /* aarch64_a57_initfn, advertising none of the aarch64 features */
1122 cpu->dtb_compatible = "arm,cortex-a57";
1123 set_feature(&cpu->env, ARM_FEATURE_V8);
1124 set_feature(&cpu->env, ARM_FEATURE_NEON);
1125 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1126 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1127 set_feature(&cpu->env, ARM_FEATURE_EL2);
1128 set_feature(&cpu->env, ARM_FEATURE_EL3);
1129 set_feature(&cpu->env, ARM_FEATURE_PMU);
1130 cpu->midr = 0x411fd070;
1131 cpu->revidr = 0x00000000;
1132 cpu->reset_fpsid = 0x41034070;
1133 cpu->isar.mvfr0 = 0x10110222;
1134 cpu->isar.mvfr1 = 0x12111111;
1135 cpu->isar.mvfr2 = 0x00000043;
1136 cpu->ctr = 0x8444c004;
1137 cpu->reset_sctlr = 0x00c50838;
1138 cpu->isar.id_pfr0 = 0x00000131;
1139 cpu->isar.id_pfr1 = 0x00011011;
1140 cpu->isar.id_dfr0 = 0x03010066;
1141 cpu->id_afr0 = 0x00000000;
1142 cpu->isar.id_mmfr0 = 0x10101105;
1143 cpu->isar.id_mmfr1 = 0x40000000;
1144 cpu->isar.id_mmfr2 = 0x01260000;
1145 cpu->isar.id_mmfr3 = 0x02102211;
1146 cpu->isar.id_isar0 = 0x02101110;
1147 cpu->isar.id_isar1 = 0x13112111;
1148 cpu->isar.id_isar2 = 0x21232042;
1149 cpu->isar.id_isar3 = 0x01112131;
1150 cpu->isar.id_isar4 = 0x00011142;
1151 cpu->isar.id_isar5 = 0x00011121;
1152 cpu->isar.id_isar6 = 0;
1153 cpu->isar.dbgdidr = 0x3516d000;
1154 cpu->isar.dbgdevid = 0x00110f13;
1155 cpu->isar.dbgdevid1 = 0x2;
1156 cpu->isar.reset_pmcr_el0 = 0x41013000;
1157 cpu->clidr = 0x0a200023;
1158 cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
1159 cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
1160 cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
1161 define_cortex_a72_a57_a53_cp_reginfo(cpu);
1162
1163 aa32_max_features(cpu);
1164
1165 #ifdef CONFIG_USER_ONLY
1166 /*
1167 * Break with true ARMv8 and add back old-style VFP short-vector support.
1168 * Only do this for user-mode, where -cpu max is the default, so that
1169 * older v6 and v7 programs are more likely to work without adjustment.
1170 */
1171 cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
1172 #endif
1173 }
1174 #endif /* !TARGET_AARCH64 */
1175
1176 static const ARMCPUInfo arm_tcg_cpus[] = {
1177 { .name = "arm926", .initfn = arm926_initfn },
1178 { .name = "arm946", .initfn = arm946_initfn },
1179 { .name = "arm1026", .initfn = arm1026_initfn },
1180 /*
1181 * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1182 * older core than plain "arm1136". In particular this does not
1183 * have the v6K features.
1184 */
1185 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1186 { .name = "arm1136", .initfn = arm1136_initfn },
1187 { .name = "arm1176", .initfn = arm1176_initfn },
1188 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1189 { .name = "cortex-a7", .initfn = cortex_a7_initfn },
1190 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1191 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1192 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1193 { .name = "cortex-m0", .initfn = cortex_m0_initfn,
1194 .class_init = arm_v7m_class_init },
1195 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1196 .class_init = arm_v7m_class_init },
1197 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1198 .class_init = arm_v7m_class_init },
1199 { .name = "cortex-m7", .initfn = cortex_m7_initfn,
1200 .class_init = arm_v7m_class_init },
1201 { .name = "cortex-m33", .initfn = cortex_m33_initfn,
1202 .class_init = arm_v7m_class_init },
1203 { .name = "cortex-m55", .initfn = cortex_m55_initfn,
1204 .class_init = arm_v7m_class_init },
1205 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1206 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1207 { .name = "cortex-r52", .initfn = cortex_r52_initfn },
1208 { .name = "ti925t", .initfn = ti925t_initfn },
1209 { .name = "sa1100", .initfn = sa1100_initfn },
1210 { .name = "sa1110", .initfn = sa1110_initfn },
1211 { .name = "pxa250", .initfn = pxa250_initfn },
1212 { .name = "pxa255", .initfn = pxa255_initfn },
1213 { .name = "pxa260", .initfn = pxa260_initfn },
1214 { .name = "pxa261", .initfn = pxa261_initfn },
1215 { .name = "pxa262", .initfn = pxa262_initfn },
1216 /* "pxa270" is an alias for "pxa270-a0" */
1217 { .name = "pxa270", .initfn = pxa270a0_initfn },
1218 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1219 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1220 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1221 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1222 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1223 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1224 #ifndef TARGET_AARCH64
1225 { .name = "max", .initfn = arm_max_initfn },
1226 #endif
1227 #ifdef CONFIG_USER_ONLY
1228 { .name = "any", .initfn = arm_max_initfn },
1229 #endif
1230 };
1231
1232 static const TypeInfo idau_interface_type_info = {
1233 .name = TYPE_IDAU_INTERFACE,
1234 .parent = TYPE_INTERFACE,
1235 .class_size = sizeof(IDAUInterfaceClass),
1236 };
1237
1238 static void arm_tcg_cpu_register_types(void)
1239 {
1240 size_t i;
1241
1242 type_register_static(&idau_interface_type_info);
1243 for (i = 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) {
1244 arm_cpu_register(&arm_tcg_cpus[i]);
1245 }
1246 }
1247
1248 type_init(arm_tcg_cpu_register_types)
1249
1250 #endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */
QEmu