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pc: acpi: mark all possible CPUs as enabled in SRAT
[qemu.git] / hw / ppc / e500.c
blob2832fc0da444d89737768f7c4dcb0638e2625750
1 /*
2 * QEMU PowerPC e500-based platforms
3 *
4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author: Yu Liu, <yu.liu@freescale.com>
7 *
8 * This file is derived from hw/ppc440_bamboo.c,
9 * the copyright for that material belongs to the original owners.
10 *
11 * This is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17 #include "config.h"
18 #include "qemu-common.h"
19 #include "e500.h"
20 #include "e500-ccsr.h"
21 #include "net/net.h"
22 #include "qemu/config-file.h"
23 #include "hw/hw.h"
24 #include "hw/char/serial.h"
25 #include "hw/pci/pci.h"
26 #include "hw/boards.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/kvm.h"
29 #include "kvm_ppc.h"
30 #include "sysemu/device_tree.h"
31 #include "hw/ppc/openpic.h"
32 #include "hw/ppc/ppc.h"
33 #include "hw/loader.h"
34 #include "elf.h"
35 #include "hw/sysbus.h"
36 #include "exec/address-spaces.h"
37 #include "qemu/host-utils.h"
38 #include "hw/pci-host/ppce500.h"
39 #include "qemu/error-report.h"
40 #include "hw/platform-bus.h"
41 #include "hw/net/fsl_etsec/etsec.h"
42
43 #define EPAPR_MAGIC (0x45504150)
44 #define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
45 #define DTC_LOAD_PAD 0x1800000
46 #define DTC_PAD_MASK 0xFFFFF
47 #define DTB_MAX_SIZE (8 * 1024 * 1024)
48 #define INITRD_LOAD_PAD 0x2000000
49 #define INITRD_PAD_MASK 0xFFFFFF
50
51 #define RAM_SIZES_ALIGN (64UL << 20)
52
53 /* TODO: parameterize */
54 #define MPC8544_CCSRBAR_BASE 0xE0000000ULL
55 #define MPC8544_CCSRBAR_SIZE 0x00100000ULL
56 #define MPC8544_MPIC_REGS_OFFSET 0x40000ULL
57 #define MPC8544_MSI_REGS_OFFSET 0x41600ULL
58 #define MPC8544_SERIAL0_REGS_OFFSET 0x4500ULL
59 #define MPC8544_SERIAL1_REGS_OFFSET 0x4600ULL
60 #define MPC8544_PCI_REGS_OFFSET 0x8000ULL
61 #define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + \
62 MPC8544_PCI_REGS_OFFSET)
63 #define MPC8544_PCI_REGS_SIZE 0x1000ULL
64 #define MPC8544_PCI_IO 0xE1000000ULL
65 #define MPC8544_UTIL_OFFSET 0xe0000ULL
66 #define MPC8544_SPIN_BASE 0xEF000000ULL
67 #define MPC8XXX_GPIO_OFFSET 0x000FF000ULL
68 #define MPC8XXX_GPIO_IRQ 43
69
70 struct boot_info
71 {
72 uint32_t dt_base;
73 uint32_t dt_size;
74 uint32_t entry;
75 };
76
77 static uint32_t *pci_map_create(void *fdt, uint32_t mpic, int first_slot,
78 int nr_slots, int *len)
79 {
80 int i = 0;
81 int slot;
82 int pci_irq;
83 int host_irq;
84 int last_slot = first_slot + nr_slots;
85 uint32_t *pci_map;
86
87 *len = nr_slots * 4 * 7 * sizeof(uint32_t);
88 pci_map = g_malloc(*len);
89
90 for (slot = first_slot; slot < last_slot; slot++) {
91 for (pci_irq = 0; pci_irq < 4; pci_irq++) {
92 pci_map[i++] = cpu_to_be32(slot << 11);
93 pci_map[i++] = cpu_to_be32(0x0);
94 pci_map[i++] = cpu_to_be32(0x0);
95 pci_map[i++] = cpu_to_be32(pci_irq + 1);
96 pci_map[i++] = cpu_to_be32(mpic);
97 host_irq = ppce500_pci_map_irq_slot(slot, pci_irq);
98 pci_map[i++] = cpu_to_be32(host_irq + 1);
99 pci_map[i++] = cpu_to_be32(0x1);
100 }
101 }
102
103 assert((i * sizeof(uint32_t)) == *len);
104
105 return pci_map;
106 }
107
108 static void dt_serial_create(void *fdt, unsigned long long offset,
109 const char *soc, const char *mpic,
110 const char *alias, int idx, bool defcon)
111 {
112 char ser[128];
113
114 snprintf(ser, sizeof(ser), "%s/serial@%llx", soc, offset);
115 qemu_fdt_add_subnode(fdt, ser);
116 qemu_fdt_setprop_string(fdt, ser, "device_type", "serial");
117 qemu_fdt_setprop_string(fdt, ser, "compatible", "ns16550");
118 qemu_fdt_setprop_cells(fdt, ser, "reg", offset, 0x100);
119 qemu_fdt_setprop_cell(fdt, ser, "cell-index", idx);
120 qemu_fdt_setprop_cell(fdt, ser, "clock-frequency", 0);
121 qemu_fdt_setprop_cells(fdt, ser, "interrupts", 42, 2);
122 qemu_fdt_setprop_phandle(fdt, ser, "interrupt-parent", mpic);
123 qemu_fdt_setprop_string(fdt, "/aliases", alias, ser);
124
125 if (defcon) {
126 qemu_fdt_setprop_string(fdt, "/chosen", "linux,stdout-path", ser);
127 }
128 }
129
130 static void create_dt_mpc8xxx_gpio(void *fdt, const char *soc, const char *mpic)
131 {
132 hwaddr mmio0 = MPC8XXX_GPIO_OFFSET;
133 int irq0 = MPC8XXX_GPIO_IRQ;
134 gchar *node = g_strdup_printf("%s/gpio@%"PRIx64, soc, mmio0);
135 gchar *poweroff = g_strdup_printf("%s/power-off", soc);
136 int gpio_ph;
137
138 qemu_fdt_add_subnode(fdt, node);
139 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,qoriq-gpio");
140 qemu_fdt_setprop_cells(fdt, node, "reg", mmio0, 0x1000);
141 qemu_fdt_setprop_cells(fdt, node, "interrupts", irq0, 0x2);
142 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
143 qemu_fdt_setprop_cells(fdt, node, "#gpio-cells", 2);
144 qemu_fdt_setprop(fdt, node, "gpio-controller", NULL, 0);
145 gpio_ph = qemu_fdt_alloc_phandle(fdt);
146 qemu_fdt_setprop_cell(fdt, node, "phandle", gpio_ph);
147 qemu_fdt_setprop_cell(fdt, node, "linux,phandle", gpio_ph);
148
149 /* Power Off Pin */
150 qemu_fdt_add_subnode(fdt, poweroff);
151 qemu_fdt_setprop_string(fdt, poweroff, "compatible", "gpio-poweroff");
152 qemu_fdt_setprop_cells(fdt, poweroff, "gpios", gpio_ph, 0, 0);
153
154 g_free(node);
155 g_free(poweroff);
156 }
157
158 typedef struct PlatformDevtreeData {
159 void *fdt;
160 const char *mpic;
161 int irq_start;
162 const char *node;
163 PlatformBusDevice *pbus;
164 } PlatformDevtreeData;
165
166 static int create_devtree_etsec(SysBusDevice *sbdev, PlatformDevtreeData *data)
167 {
168 eTSEC *etsec = ETSEC_COMMON(sbdev);
169 PlatformBusDevice *pbus = data->pbus;
170 hwaddr mmio0 = platform_bus_get_mmio_addr(pbus, sbdev, 0);
171 int irq0 = platform_bus_get_irqn(pbus, sbdev, 0);
172 int irq1 = platform_bus_get_irqn(pbus, sbdev, 1);
173 int irq2 = platform_bus_get_irqn(pbus, sbdev, 2);
174 gchar *node = g_strdup_printf("/platform/ethernet@%"PRIx64, mmio0);
175 gchar *group = g_strdup_printf("%s/queue-group", node);
176 void *fdt = data->fdt;
177
178 assert((int64_t)mmio0 >= 0);
179 assert(irq0 >= 0);
180 assert(irq1 >= 0);
181 assert(irq2 >= 0);
182
183 qemu_fdt_add_subnode(fdt, node);
184 qemu_fdt_setprop_string(fdt, node, "device_type", "network");
185 qemu_fdt_setprop_string(fdt, node, "compatible", "fsl,etsec2");
186 qemu_fdt_setprop_string(fdt, node, "model", "eTSEC");
187 qemu_fdt_setprop(fdt, node, "local-mac-address", etsec->conf.macaddr.a, 6);
188 qemu_fdt_setprop_cells(fdt, node, "fixed-link", 0, 1, 1000, 0, 0);
189
190 qemu_fdt_add_subnode(fdt, group);
191 qemu_fdt_setprop_cells(fdt, group, "reg", mmio0, 0x1000);
192 qemu_fdt_setprop_cells(fdt, group, "interrupts",
193 data->irq_start + irq0, 0x2,
194 data->irq_start + irq1, 0x2,
195 data->irq_start + irq2, 0x2);
196
197 g_free(node);
198 g_free(group);
199
200 return 0;
201 }
202
203 static int sysbus_device_create_devtree(SysBusDevice *sbdev, void *opaque)
204 {
205 PlatformDevtreeData *data = opaque;
206 bool matched = false;
207
208 if (object_dynamic_cast(OBJECT(sbdev), TYPE_ETSEC_COMMON)) {
209 create_devtree_etsec(sbdev, data);
210 matched = true;
211 }
212
213 if (!matched) {
214 error_report("Device %s is not supported by this machine yet.",
215 qdev_fw_name(DEVICE(sbdev)));
216 exit(1);
217 }
218
219 return 0;
220 }
221
222 static void platform_bus_create_devtree(PPCE500Params *params, void *fdt,
223 const char *mpic)
224 {
225 gchar *node = g_strdup_printf("/platform@%"PRIx64, params->platform_bus_base);
226 const char platcomp[] = "qemu,platform\0simple-bus";
227 uint64_t addr = params->platform_bus_base;
228 uint64_t size = params->platform_bus_size;
229 int irq_start = params->platform_bus_first_irq;
230 PlatformBusDevice *pbus;
231 DeviceState *dev;
232
233 /* Create a /platform node that we can put all devices into */
234
235 qemu_fdt_add_subnode(fdt, node);
236 qemu_fdt_setprop(fdt, node, "compatible", platcomp, sizeof(platcomp));
237
238 /* Our platform bus region is less than 32bit big, so 1 cell is enough for
239 address and size */
240 qemu_fdt_setprop_cells(fdt, node, "#size-cells", 1);
241 qemu_fdt_setprop_cells(fdt, node, "#address-cells", 1);
242 qemu_fdt_setprop_cells(fdt, node, "ranges", 0, addr >> 32, addr, size);
243
244 qemu_fdt_setprop_phandle(fdt, node, "interrupt-parent", mpic);
245
246 dev = qdev_find_recursive(sysbus_get_default(), TYPE_PLATFORM_BUS_DEVICE);
247 pbus = PLATFORM_BUS_DEVICE(dev);
248
249 /* We can only create dt nodes for dynamic devices when they're ready */
250 if (pbus->done_gathering) {
251 PlatformDevtreeData data = {
252 .fdt = fdt,
253 .mpic = mpic,
254 .irq_start = irq_start,
255 .node = node,
256 .pbus = pbus,
257 };
258
259 /* Loop through all dynamic sysbus devices and create nodes for them */
260 foreach_dynamic_sysbus_device(sysbus_device_create_devtree, &data);
261 }
262
263 g_free(node);
264 }
265
266 static int ppce500_load_device_tree(MachineState *machine,
267 PPCE500Params *params,
268 hwaddr addr,
269 hwaddr initrd_base,
270 hwaddr initrd_size,
271 hwaddr kernel_base,
272 hwaddr kernel_size,
273 bool dry_run)
274 {
275 CPUPPCState *env = first_cpu->env_ptr;
276 int ret = -1;
277 uint64_t mem_reg_property[] = { 0, cpu_to_be64(machine->ram_size) };
278 int fdt_size;
279 void *fdt;
280 uint8_t hypercall[16];
281 uint32_t clock_freq = 400000000;
282 uint32_t tb_freq = 400000000;
283 int i;
284 char compatible_sb[] = "fsl,mpc8544-immr\0simple-bus";
285 char soc[128];
286 char mpic[128];
287 uint32_t mpic_ph;
288 uint32_t msi_ph;
289 char gutil[128];
290 char pci[128];
291 char msi[128];
292 uint32_t *pci_map = NULL;
293 int len;
294 uint32_t pci_ranges[14] =
295 {
296 0x2000000, 0x0, 0xc0000000,
297 0x0, 0xc0000000,
298 0x0, 0x20000000,
299
300 0x1000000, 0x0, 0x0,
301 0x0, 0xe1000000,
302 0x0, 0x10000,
303 };
304 QemuOpts *machine_opts = qemu_get_machine_opts();
305 const char *dtb_file = qemu_opt_get(machine_opts, "dtb");
306 const char *toplevel_compat = qemu_opt_get(machine_opts, "dt_compatible");
307
308 if (dtb_file) {
309 char *filename;
310 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, dtb_file);
311 if (!filename) {
312 goto out;
313 }
314
315 fdt = load_device_tree(filename, &fdt_size);
316 if (!fdt) {
317 goto out;
318 }
319 goto done;
320 }
321
322 fdt = create_device_tree(&fdt_size);
323 if (fdt == NULL) {
324 goto out;
325 }
326
327 /* Manipulate device tree in memory. */
328 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 2);
329 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 2);
330
331 qemu_fdt_add_subnode(fdt, "/memory");
332 qemu_fdt_setprop_string(fdt, "/memory", "device_type", "memory");
333 qemu_fdt_setprop(fdt, "/memory", "reg", mem_reg_property,
334 sizeof(mem_reg_property));
335
336 qemu_fdt_add_subnode(fdt, "/chosen");
337 if (initrd_size) {
338 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-start",
339 initrd_base);
340 if (ret < 0) {
341 fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
342 }
343
344 ret = qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end",
345 (initrd_base + initrd_size));
346 if (ret < 0) {
347 fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
348 }
349
350 }
351
352 if (kernel_base != -1ULL) {
353 qemu_fdt_setprop_cells(fdt, "/chosen", "qemu,boot-kernel",
354 kernel_base >> 32, kernel_base,
355 kernel_size >> 32, kernel_size);
356 }
357
358 ret = qemu_fdt_setprop_string(fdt, "/chosen", "bootargs",
359 machine->kernel_cmdline);
360 if (ret < 0)
361 fprintf(stderr, "couldn't set /chosen/bootargs\n");
362
363 if (kvm_enabled()) {
364 /* Read out host's frequencies */
365 clock_freq = kvmppc_get_clockfreq();
366 tb_freq = kvmppc_get_tbfreq();
367
368 /* indicate KVM hypercall interface */
369 qemu_fdt_add_subnode(fdt, "/hypervisor");
370 qemu_fdt_setprop_string(fdt, "/hypervisor", "compatible",
371 "linux,kvm");
372 kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
373 qemu_fdt_setprop(fdt, "/hypervisor", "hcall-instructions",
374 hypercall, sizeof(hypercall));
375 /* if KVM supports the idle hcall, set property indicating this */
376 if (kvmppc_get_hasidle(env)) {
377 qemu_fdt_setprop(fdt, "/hypervisor", "has-idle", NULL, 0);
378 }
379 }
380
381 /* Create CPU nodes */
382 qemu_fdt_add_subnode(fdt, "/cpus");
383 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 1);
384 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0);
385
386 /* We need to generate the cpu nodes in reverse order, so Linux can pick
387 the first node as boot node and be happy */
388 for (i = smp_cpus - 1; i >= 0; i--) {
389 CPUState *cpu;
390 PowerPCCPU *pcpu;
391 char cpu_name[128];
392 uint64_t cpu_release_addr = MPC8544_SPIN_BASE + (i * 0x20);
393
394 cpu = qemu_get_cpu(i);
395 if (cpu == NULL) {
396 continue;
397 }
398 env = cpu->env_ptr;
399 pcpu = POWERPC_CPU(cpu);
400
401 snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x",
402 ppc_get_vcpu_dt_id(pcpu));
403 qemu_fdt_add_subnode(fdt, cpu_name);
404 qemu_fdt_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
405 qemu_fdt_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
406 qemu_fdt_setprop_string(fdt, cpu_name, "device_type", "cpu");
407 qemu_fdt_setprop_cell(fdt, cpu_name, "reg",
408 ppc_get_vcpu_dt_id(pcpu));
409 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-line-size",
410 env->dcache_line_size);
411 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-line-size",
412 env->icache_line_size);
413 qemu_fdt_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
414 qemu_fdt_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
415 qemu_fdt_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
416 if (cpu->cpu_index) {
417 qemu_fdt_setprop_string(fdt, cpu_name, "status", "disabled");
418 qemu_fdt_setprop_string(fdt, cpu_name, "enable-method",
419 "spin-table");
420 qemu_fdt_setprop_u64(fdt, cpu_name, "cpu-release-addr",
421 cpu_release_addr);
422 } else {
423 qemu_fdt_setprop_string(fdt, cpu_name, "status", "okay");
424 }
425 }
426
427 qemu_fdt_add_subnode(fdt, "/aliases");
428 /* XXX These should go into their respective devices' code */
429 snprintf(soc, sizeof(soc), "/soc@%llx", MPC8544_CCSRBAR_BASE);
430 qemu_fdt_add_subnode(fdt, soc);
431 qemu_fdt_setprop_string(fdt, soc, "device_type", "soc");
432 qemu_fdt_setprop(fdt, soc, "compatible", compatible_sb,
433 sizeof(compatible_sb));
434 qemu_fdt_setprop_cell(fdt, soc, "#address-cells", 1);
435 qemu_fdt_setprop_cell(fdt, soc, "#size-cells", 1);
436 qemu_fdt_setprop_cells(fdt, soc, "ranges", 0x0,
437 MPC8544_CCSRBAR_BASE >> 32, MPC8544_CCSRBAR_BASE,
438 MPC8544_CCSRBAR_SIZE);
439 /* XXX should contain a reasonable value */
440 qemu_fdt_setprop_cell(fdt, soc, "bus-frequency", 0);
441
442 snprintf(mpic, sizeof(mpic), "%s/pic@%llx", soc, MPC8544_MPIC_REGS_OFFSET);
443 qemu_fdt_add_subnode(fdt, mpic);
444 qemu_fdt_setprop_string(fdt, mpic, "device_type", "open-pic");
445 qemu_fdt_setprop_string(fdt, mpic, "compatible", "fsl,mpic");
446 qemu_fdt_setprop_cells(fdt, mpic, "reg", MPC8544_MPIC_REGS_OFFSET,
447 0x40000);
448 qemu_fdt_setprop_cell(fdt, mpic, "#address-cells", 0);
449 qemu_fdt_setprop_cell(fdt, mpic, "#interrupt-cells", 2);
450 mpic_ph = qemu_fdt_alloc_phandle(fdt);
451 qemu_fdt_setprop_cell(fdt, mpic, "phandle", mpic_ph);
452 qemu_fdt_setprop_cell(fdt, mpic, "linux,phandle", mpic_ph);
453 qemu_fdt_setprop(fdt, mpic, "interrupt-controller", NULL, 0);
454
455 /*
456 * We have to generate ser1 first, because Linux takes the first
457 * device it finds in the dt as serial output device. And we generate
458 * devices in reverse order to the dt.
459 */
460 if (serial_hds[1]) {
461 dt_serial_create(fdt, MPC8544_SERIAL1_REGS_OFFSET,
462 soc, mpic, "serial1", 1, false);
463 }
464
465 if (serial_hds[0]) {
466 dt_serial_create(fdt, MPC8544_SERIAL0_REGS_OFFSET,
467 soc, mpic, "serial0", 0, true);
468 }
469
470 snprintf(gutil, sizeof(gutil), "%s/global-utilities@%llx", soc,
471 MPC8544_UTIL_OFFSET);
472 qemu_fdt_add_subnode(fdt, gutil);
473 qemu_fdt_setprop_string(fdt, gutil, "compatible", "fsl,mpc8544-guts");
474 qemu_fdt_setprop_cells(fdt, gutil, "reg", MPC8544_UTIL_OFFSET, 0x1000);
475 qemu_fdt_setprop(fdt, gutil, "fsl,has-rstcr", NULL, 0);
476
477 snprintf(msi, sizeof(msi), "/%s/msi@%llx", soc, MPC8544_MSI_REGS_OFFSET);
478 qemu_fdt_add_subnode(fdt, msi);
479 qemu_fdt_setprop_string(fdt, msi, "compatible", "fsl,mpic-msi");
480 qemu_fdt_setprop_cells(fdt, msi, "reg", MPC8544_MSI_REGS_OFFSET, 0x200);
481 msi_ph = qemu_fdt_alloc_phandle(fdt);
482 qemu_fdt_setprop_cells(fdt, msi, "msi-available-ranges", 0x0, 0x100);
483 qemu_fdt_setprop_phandle(fdt, msi, "interrupt-parent", mpic);
484 qemu_fdt_setprop_cells(fdt, msi, "interrupts",
485 0xe0, 0x0,
486 0xe1, 0x0,
487 0xe2, 0x0,
488 0xe3, 0x0,
489 0xe4, 0x0,
490 0xe5, 0x0,
491 0xe6, 0x0,
492 0xe7, 0x0);
493 qemu_fdt_setprop_cell(fdt, msi, "phandle", msi_ph);
494 qemu_fdt_setprop_cell(fdt, msi, "linux,phandle", msi_ph);
495
496 snprintf(pci, sizeof(pci), "/pci@%llx", MPC8544_PCI_REGS_BASE);
497 qemu_fdt_add_subnode(fdt, pci);
498 qemu_fdt_setprop_cell(fdt, pci, "cell-index", 0);
499 qemu_fdt_setprop_string(fdt, pci, "compatible", "fsl,mpc8540-pci");
500 qemu_fdt_setprop_string(fdt, pci, "device_type", "pci");
501 qemu_fdt_setprop_cells(fdt, pci, "interrupt-map-mask", 0xf800, 0x0,
502 0x0, 0x7);
503 pci_map = pci_map_create(fdt, qemu_fdt_get_phandle(fdt, mpic),
504 params->pci_first_slot, params->pci_nr_slots,
505 &len);
506 qemu_fdt_setprop(fdt, pci, "interrupt-map", pci_map, len);
507 qemu_fdt_setprop_phandle(fdt, pci, "interrupt-parent", mpic);
508 qemu_fdt_setprop_cells(fdt, pci, "interrupts", 24, 2);
509 qemu_fdt_setprop_cells(fdt, pci, "bus-range", 0, 255);
510 for (i = 0; i < 14; i++) {
511 pci_ranges[i] = cpu_to_be32(pci_ranges[i]);
512 }
513 qemu_fdt_setprop_cell(fdt, pci, "fsl,msi", msi_ph);
514 qemu_fdt_setprop(fdt, pci, "ranges", pci_ranges, sizeof(pci_ranges));
515 qemu_fdt_setprop_cells(fdt, pci, "reg", MPC8544_PCI_REGS_BASE >> 32,
516 MPC8544_PCI_REGS_BASE, 0, 0x1000);
517 qemu_fdt_setprop_cell(fdt, pci, "clock-frequency", 66666666);
518 qemu_fdt_setprop_cell(fdt, pci, "#interrupt-cells", 1);
519 qemu_fdt_setprop_cell(fdt, pci, "#size-cells", 2);
520 qemu_fdt_setprop_cell(fdt, pci, "#address-cells", 3);
521 qemu_fdt_setprop_string(fdt, "/aliases", "pci0", pci);
522
523 if (params->has_mpc8xxx_gpio) {
524 create_dt_mpc8xxx_gpio(fdt, soc, mpic);
525 }
526
527 if (params->has_platform_bus) {
528 platform_bus_create_devtree(params, fdt, mpic);
529 }
530
531 params->fixup_devtree(params, fdt);
532
533 if (toplevel_compat) {
534 qemu_fdt_setprop(fdt, "/", "compatible", toplevel_compat,
535 strlen(toplevel_compat) + 1);
536 }
537
538 done:
539 if (!dry_run) {
540 qemu_fdt_dumpdtb(fdt, fdt_size);
541 cpu_physical_memory_write(addr, fdt, fdt_size);
542 }
543 ret = fdt_size;
544
545 out:
546 g_free(pci_map);
547
548 return ret;
549 }
550
551 typedef struct DeviceTreeParams {
552 MachineState *machine;
553 PPCE500Params params;
554 hwaddr addr;
555 hwaddr initrd_base;
556 hwaddr initrd_size;
557 hwaddr kernel_base;
558 hwaddr kernel_size;
559 Notifier notifier;
560 } DeviceTreeParams;
561
562 static void ppce500_reset_device_tree(void *opaque)
563 {
564 DeviceTreeParams *p = opaque;
565 ppce500_load_device_tree(p->machine, &p->params, p->addr, p->initrd_base,
566 p->initrd_size, p->kernel_base, p->kernel_size,
567 false);
568 }
569
570 static void ppce500_init_notify(Notifier *notifier, void *data)
571 {
572 DeviceTreeParams *p = container_of(notifier, DeviceTreeParams, notifier);
573 ppce500_reset_device_tree(p);
574 }
575
576 static int ppce500_prep_device_tree(MachineState *machine,
577 PPCE500Params *params,
578 hwaddr addr,
579 hwaddr initrd_base,
580 hwaddr initrd_size,
581 hwaddr kernel_base,
582 hwaddr kernel_size)
583 {
584 DeviceTreeParams *p = g_new(DeviceTreeParams, 1);
585 p->machine = machine;
586 p->params = *params;
587 p->addr = addr;
588 p->initrd_base = initrd_base;
589 p->initrd_size = initrd_size;
590 p->kernel_base = kernel_base;
591 p->kernel_size = kernel_size;
592
593 qemu_register_reset(ppce500_reset_device_tree, p);
594 p->notifier.notify = ppce500_init_notify;
595 qemu_add_machine_init_done_notifier(&p->notifier);
596
597 /* Issue the device tree loader once, so that we get the size of the blob */
598 return ppce500_load_device_tree(machine, params, addr, initrd_base,
599 initrd_size, kernel_base, kernel_size,
600 true);
601 }
602
603 /* Create -kernel TLB entries for BookE. */
604 static inline hwaddr booke206_page_size_to_tlb(uint64_t size)
605 {
606 return 63 - clz64(size >> 10);
607 }
608
609 static int booke206_initial_map_tsize(CPUPPCState *env)
610 {
611 struct boot_info *bi = env->load_info;
612 hwaddr dt_end;
613 int ps;
614
615 /* Our initial TLB entry needs to cover everything from 0 to
616 the device tree top */
617 dt_end = bi->dt_base + bi->dt_size;
618 ps = booke206_page_size_to_tlb(dt_end) + 1;
619 if (ps & 1) {
620 /* e500v2 can only do even TLB size bits */
621 ps++;
622 }
623 return ps;
624 }
625
626 static uint64_t mmubooke_initial_mapsize(CPUPPCState *env)
627 {
628 int tsize;
629
630 tsize = booke206_initial_map_tsize(env);
631 return (1ULL << 10 << tsize);
632 }
633
634 static void mmubooke_create_initial_mapping(CPUPPCState *env)
635 {
636 ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
637 hwaddr size;
638 int ps;
639
640 ps = booke206_initial_map_tsize(env);
641 size = (ps << MAS1_TSIZE_SHIFT);
642 tlb->mas1 = MAS1_VALID | size;
643 tlb->mas2 = 0;
644 tlb->mas7_3 = 0;
645 tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
646
647 env->tlb_dirty = true;
648 }
649
650 static void ppce500_cpu_reset_sec(void *opaque)
651 {
652 PowerPCCPU *cpu = opaque;
653 CPUState *cs = CPU(cpu);
654
655 cpu_reset(cs);
656
657 /* Secondary CPU starts in halted state for now. Needs to change when
658 implementing non-kernel boot. */
659 cs->halted = 1;
660 cs->exception_index = EXCP_HLT;
661 }
662
663 static void ppce500_cpu_reset(void *opaque)
664 {
665 PowerPCCPU *cpu = opaque;
666 CPUState *cs = CPU(cpu);
667 CPUPPCState *env = &cpu->env;
668 struct boot_info *bi = env->load_info;
669
670 cpu_reset(cs);
671
672 /* Set initial guest state. */
673 cs->halted = 0;
674 env->gpr[1] = (16<<20) - 8;
675 env->gpr[3] = bi->dt_base;
676 env->gpr[4] = 0;
677 env->gpr[5] = 0;
678 env->gpr[6] = EPAPR_MAGIC;
679 env->gpr[7] = mmubooke_initial_mapsize(env);
680 env->gpr[8] = 0;
681 env->gpr[9] = 0;
682 env->nip = bi->entry;
683 mmubooke_create_initial_mapping(env);
684 }
685
686 static DeviceState *ppce500_init_mpic_qemu(PPCE500Params *params,
687 qemu_irq **irqs)
688 {
689 DeviceState *dev;
690 SysBusDevice *s;
691 int i, j, k;
692
693 dev = qdev_create(NULL, TYPE_OPENPIC);
694 qdev_prop_set_uint32(dev, "model", params->mpic_version);
695 qdev_prop_set_uint32(dev, "nb_cpus", smp_cpus);
696
697 qdev_init_nofail(dev);
698 s = SYS_BUS_DEVICE(dev);
699
700 k = 0;
701 for (i = 0; i < smp_cpus; i++) {
702 for (j = 0; j < OPENPIC_OUTPUT_NB; j++) {
703 sysbus_connect_irq(s, k++, irqs[i][j]);
704 }
705 }
706
707 return dev;
708 }
709
710 static DeviceState *ppce500_init_mpic_kvm(PPCE500Params *params,
711 qemu_irq **irqs)
712 {
713 DeviceState *dev;
714 CPUState *cs;
715 int r;
716
717 dev = qdev_create(NULL, TYPE_KVM_OPENPIC);
718 qdev_prop_set_uint32(dev, "model", params->mpic_version);
719
720 r = qdev_init(dev);
721 if (r) {
722 return NULL;
723 }
724
725 CPU_FOREACH(cs) {
726 if (kvm_openpic_connect_vcpu(dev, cs)) {
727 fprintf(stderr, "%s: failed to connect vcpu to irqchip\n",
728 __func__);
729 abort();
730 }
731 }
732
733 return dev;
734 }
735
736 static qemu_irq *ppce500_init_mpic(PPCE500Params *params, MemoryRegion *ccsr,
737 qemu_irq **irqs)
738 {
739 qemu_irq *mpic;
740 DeviceState *dev = NULL;
741 SysBusDevice *s;
742 int i;
743
744 mpic = g_new0(qemu_irq, 256);
745
746 if (kvm_enabled()) {
747 QemuOpts *machine_opts = qemu_get_machine_opts();
748 bool irqchip_allowed = qemu_opt_get_bool(machine_opts,
749 "kernel_irqchip", true);
750 bool irqchip_required = qemu_opt_get_bool(machine_opts,
751 "kernel_irqchip", false);
752
753 if (irqchip_allowed) {
754 dev = ppce500_init_mpic_kvm(params, irqs);
755 }
756
757 if (irqchip_required && !dev) {
758 fprintf(stderr, "%s: irqchip requested but unavailable\n",
759 __func__);
760 abort();
761 }
762 }
763
764 if (!dev) {
765 dev = ppce500_init_mpic_qemu(params, irqs);
766 }
767
768 for (i = 0; i < 256; i++) {
769 mpic[i] = qdev_get_gpio_in(dev, i);
770 }
771
772 s = SYS_BUS_DEVICE(dev);
773 memory_region_add_subregion(ccsr, MPC8544_MPIC_REGS_OFFSET,
774 s->mmio[0].memory);
775
776 return mpic;
777 }
778
779 static void ppce500_power_off(void *opaque, int line, int on)
780 {
781 if (on) {
782 qemu_system_shutdown_request();
783 }
784 }
785
786 void ppce500_init(MachineState *machine, PPCE500Params *params)
787 {
788 MemoryRegion *address_space_mem = get_system_memory();
789 MemoryRegion *ram = g_new(MemoryRegion, 1);
790 PCIBus *pci_bus;
791 CPUPPCState *env = NULL;
792 uint64_t loadaddr;
793 hwaddr kernel_base = -1LL;
794 int kernel_size = 0;
795 hwaddr dt_base = 0;
796 hwaddr initrd_base = 0;
797 int initrd_size = 0;
798 hwaddr cur_base = 0;
799 char *filename;
800 hwaddr bios_entry = 0;
801 target_long bios_size;
802 struct boot_info *boot_info;
803 int dt_size;
804 int i;
805 /* irq num for pin INTA, INTB, INTC and INTD is 1, 2, 3 and
806 * 4 respectively */
807 unsigned int pci_irq_nrs[PCI_NUM_PINS] = {1, 2, 3, 4};
808 qemu_irq **irqs, *mpic;
809 DeviceState *dev;
810 CPUPPCState *firstenv = NULL;
811 MemoryRegion *ccsr_addr_space;
812 SysBusDevice *s;
813 PPCE500CCSRState *ccsr;
814
815 /* Setup CPUs */
816 if (machine->cpu_model == NULL) {
817 machine->cpu_model = "e500v2_v30";
818 }
819
820 irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
821 irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
822 for (i = 0; i < smp_cpus; i++) {
823 PowerPCCPU *cpu;
824 CPUState *cs;
825 qemu_irq *input;
826
827 cpu = cpu_ppc_init(machine->cpu_model);
828 if (cpu == NULL) {
829 fprintf(stderr, "Unable to initialize CPU!\n");
830 exit(1);
831 }
832 env = &cpu->env;
833 cs = CPU(cpu);
834
835 if (!firstenv) {
836 firstenv = env;
837 }
838
839 irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
840 input = (qemu_irq *)env->irq_inputs;
841 irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
842 irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
843 env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i;
844 env->mpic_iack = MPC8544_CCSRBAR_BASE +
845 MPC8544_MPIC_REGS_OFFSET + 0xa0;
846
847 ppc_booke_timers_init(cpu, 400000000, PPC_TIMER_E500);
848
849 /* Register reset handler */
850 if (!i) {
851 /* Primary CPU */
852 struct boot_info *boot_info;
853 boot_info = g_malloc0(sizeof(struct boot_info));
854 qemu_register_reset(ppce500_cpu_reset, cpu);
855 env->load_info = boot_info;
856 } else {
857 /* Secondary CPUs */
858 qemu_register_reset(ppce500_cpu_reset_sec, cpu);
859 }
860 }
861
862 env = firstenv;
863
864 /* Fixup Memory size on a alignment boundary */
865 ram_size &= ~(RAM_SIZES_ALIGN - 1);
866 machine->ram_size = ram_size;
867
868 /* Register Memory */
869 memory_region_allocate_system_memory(ram, NULL, "mpc8544ds.ram", ram_size);
870 memory_region_add_subregion(address_space_mem, 0, ram);
871
872 dev = qdev_create(NULL, "e500-ccsr");
873 object_property_add_child(qdev_get_machine(), "e500-ccsr",
874 OBJECT(dev), NULL);
875 qdev_init_nofail(dev);
876 ccsr = CCSR(dev);
877 ccsr_addr_space = &ccsr->ccsr_space;
878 memory_region_add_subregion(address_space_mem, MPC8544_CCSRBAR_BASE,
879 ccsr_addr_space);
880
881 mpic = ppce500_init_mpic(params, ccsr_addr_space, irqs);
882
883 /* Serial */
884 if (serial_hds[0]) {
885 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL0_REGS_OFFSET,
886 0, mpic[42], 399193,
887 serial_hds[0], DEVICE_BIG_ENDIAN);
888 }
889
890 if (serial_hds[1]) {
891 serial_mm_init(ccsr_addr_space, MPC8544_SERIAL1_REGS_OFFSET,
892 0, mpic[42], 399193,
893 serial_hds[1], DEVICE_BIG_ENDIAN);
894 }
895
896 /* General Utility device */
897 dev = qdev_create(NULL, "mpc8544-guts");
898 qdev_init_nofail(dev);
899 s = SYS_BUS_DEVICE(dev);
900 memory_region_add_subregion(ccsr_addr_space, MPC8544_UTIL_OFFSET,
901 sysbus_mmio_get_region(s, 0));
902
903 /* PCI */
904 dev = qdev_create(NULL, "e500-pcihost");
905 qdev_prop_set_uint32(dev, "first_slot", params->pci_first_slot);
906 qdev_prop_set_uint32(dev, "first_pin_irq", pci_irq_nrs[0]);
907 qdev_init_nofail(dev);
908 s = SYS_BUS_DEVICE(dev);
909 for (i = 0; i < PCI_NUM_PINS; i++) {
910 sysbus_connect_irq(s, i, mpic[pci_irq_nrs[i]]);
911 }
912
913 memory_region_add_subregion(ccsr_addr_space, MPC8544_PCI_REGS_OFFSET,
914 sysbus_mmio_get_region(s, 0));
915
916 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
917 if (!pci_bus)
918 printf("couldn't create PCI controller!\n");
919
920 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, MPC8544_PCI_IO);
921
922 if (pci_bus) {
923 /* Register network interfaces. */
924 for (i = 0; i < nb_nics; i++) {
925 pci_nic_init_nofail(&nd_table[i], pci_bus, "virtio", NULL);
926 }
927 }
928
929 /* Register spinning region */
930 sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
931
932 if (cur_base < (32 * 1024 * 1024)) {
933 /* u-boot occupies memory up to 32MB, so load blobs above */
934 cur_base = (32 * 1024 * 1024);
935 }
936
937 if (params->has_mpc8xxx_gpio) {
938 qemu_irq poweroff_irq;
939
940 dev = qdev_create(NULL, "mpc8xxx_gpio");
941 s = SYS_BUS_DEVICE(dev);
942 qdev_init_nofail(dev);
943 sysbus_connect_irq(s, 0, mpic[MPC8XXX_GPIO_IRQ]);
944 memory_region_add_subregion(ccsr_addr_space, MPC8XXX_GPIO_OFFSET,
945 sysbus_mmio_get_region(s, 0));
946
947 /* Power Off GPIO at Pin 0 */
948 poweroff_irq = qemu_allocate_irq(ppce500_power_off, NULL, 0);
949 qdev_connect_gpio_out(dev, 0, poweroff_irq);
950 }
951
952 /* Platform Bus Device */
953 if (params->has_platform_bus) {
954 dev = qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE);
955 dev->id = TYPE_PLATFORM_BUS_DEVICE;
956 qdev_prop_set_uint32(dev, "num_irqs", params->platform_bus_num_irqs);
957 qdev_prop_set_uint32(dev, "mmio_size", params->platform_bus_size);
958 qdev_init_nofail(dev);
959 s = SYS_BUS_DEVICE(dev);
960
961 for (i = 0; i < params->platform_bus_num_irqs; i++) {
962 int irqn = params->platform_bus_first_irq + i;
963 sysbus_connect_irq(s, i, mpic[irqn]);
964 }
965
966 memory_region_add_subregion(address_space_mem,
967 params->platform_bus_base,
968 sysbus_mmio_get_region(s, 0));
969 }
970
971 /* Load kernel. */
972 if (machine->kernel_filename) {
973 kernel_base = cur_base;
974 kernel_size = load_image_targphys(machine->kernel_filename,
975 cur_base,
976 ram_size - cur_base);
977 if (kernel_size < 0) {
978 fprintf(stderr, "qemu: could not load kernel '%s'\n",
979 machine->kernel_filename);
980 exit(1);
981 }
982
983 cur_base += kernel_size;
984 }
985
986 /* Load initrd. */
987 if (machine->initrd_filename) {
988 initrd_base = (cur_base + INITRD_LOAD_PAD) & ~INITRD_PAD_MASK;
989 initrd_size = load_image_targphys(machine->initrd_filename, initrd_base,
990 ram_size - initrd_base);
991
992 if (initrd_size < 0) {
993 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
994 machine->initrd_filename);
995 exit(1);
996 }
997
998 cur_base = initrd_base + initrd_size;
999 }
1000
1001 /*
1002 * Smart firmware defaults ahead!
1003 *
1004 * We follow the following table to select which payload we execute.
1005 *
1006 * -kernel | -bios | payload
1007 * ---------+-------+---------
1008 * N | Y | u-boot
1009 * N | N | u-boot
1010 * Y | Y | u-boot
1011 * Y | N | kernel
1012 *
1013 * This ensures backwards compatibility with how we used to expose
1014 * -kernel to users but allows them to run through u-boot as well.
1015 */
1016 if (bios_name == NULL) {
1017 if (machine->kernel_filename) {
1018 bios_name = machine->kernel_filename;
1019 } else {
1020 bios_name = "u-boot.e500";
1021 }
1022 }
1023 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1024
1025 bios_size = load_elf(filename, NULL, NULL, &bios_entry, &loadaddr, NULL,
1026 1, ELF_MACHINE, 0);
1027 if (bios_size < 0) {
1028 /*
1029 * Hrm. No ELF image? Try a uImage, maybe someone is giving us an
1030 * ePAPR compliant kernel
1031 */
1032 kernel_size = load_uimage(filename, &bios_entry, &loadaddr, NULL,
1033 NULL, NULL);
1034 if (kernel_size < 0) {
1035 fprintf(stderr, "qemu: could not load firmware '%s'\n", filename);
1036 exit(1);
1037 }
1038 }
1039
1040 /* Reserve space for dtb */
1041 dt_base = (loadaddr + bios_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
1042
1043 dt_size = ppce500_prep_device_tree(machine, params, dt_base,
1044 initrd_base, initrd_size,
1045 kernel_base, kernel_size);
1046 if (dt_size < 0) {
1047 fprintf(stderr, "couldn't load device tree\n");
1048 exit(1);
1049 }
1050 assert(dt_size < DTB_MAX_SIZE);
1051
1052 boot_info = env->load_info;
1053 boot_info->entry = bios_entry;
1054 boot_info->dt_base = dt_base;
1055 boot_info->dt_size = dt_size;
1056
1057 if (kvm_enabled()) {
1058 kvmppc_init();
1059 }
1060 }
1061
1062 static int e500_ccsr_initfn(SysBusDevice *dev)
1063 {
1064 PPCE500CCSRState *ccsr;
1065
1066 ccsr = CCSR(dev);
1067 memory_region_init(&ccsr->ccsr_space, OBJECT(ccsr), "e500-ccsr",
1068 MPC8544_CCSRBAR_SIZE);
1069 return 0;
1070 }
1071
1072 static void e500_ccsr_class_init(ObjectClass *klass, void *data)
1073 {
1074 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
1075 k->init = e500_ccsr_initfn;
1076 }
1077
1078 static const TypeInfo e500_ccsr_info = {
1079 .name = TYPE_CCSR,
1080 .parent = TYPE_SYS_BUS_DEVICE,
1081 .instance_size = sizeof(PPCE500CCSRState),
1082 .class_init = e500_ccsr_class_init,
1083 };
1084
1085 static void e500_register_types(void)
1086 {
1087 type_register_static(&e500_ccsr_info);
1088 }
1089
1090 type_init(e500_register_types)
QEmu