hw/char/milkymist-uart.c

   1 /*
   2  *  QEMU model of the Milkymist UART block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.milkymist.org/socdoc/uart.pdf
  22  */
  23
  24 #include "hw/hw.h"
  25 #include "hw/sysbus.h"
  26 #include "trace.h"
  27 #include "sysemu/char.h"
  28 #include "qemu/error-report.h"
  29
  30 enum {
  31     R_RXTX = 0,
  32     R_DIV,
  33     R_STAT,
  34     R_CTRL,
  35     R_DBG,
  36     R_MAX
  37 };
  38
  39 enum {
  40     STAT_THRE   = (1<<0),
  41     STAT_RX_EVT = (1<<1),
  42     STAT_TX_EVT = (1<<2),
  43 };
  44
  45 enum {
  46     CTRL_RX_IRQ_EN = (1<<0),
  47     CTRL_TX_IRQ_EN = (1<<1),
  48     CTRL_THRU_EN   = (1<<2),
  49 };
  50
  51 enum {
  52     DBG_BREAK_EN = (1<<0),
  53 };
  54
  55 struct MilkymistUartState {
  56     SysBusDevice busdev;
  57     MemoryRegion regs_region;
  58     CharDriverState *chr;
  59     qemu_irq irq;
  60
  61     uint32_t regs[R_MAX];
  62 };
  63 typedef struct MilkymistUartState MilkymistUartState;
  64
  65 static void uart_update_irq(MilkymistUartState *s)
  66 {
  67     int rx_event = s->regs[R_STAT] & STAT_RX_EVT;
  68     int tx_event = s->regs[R_STAT] & STAT_TX_EVT;
  69     int rx_irq_en = s->regs[R_CTRL] & CTRL_RX_IRQ_EN;
  70     int tx_irq_en = s->regs[R_CTRL] & CTRL_TX_IRQ_EN;
  71
  72     if ((rx_irq_en && rx_event) || (tx_irq_en && tx_event)) {
  73         trace_milkymist_uart_raise_irq();
  74         qemu_irq_raise(s->irq);
  75     } else {
  76         trace_milkymist_uart_lower_irq();
  77         qemu_irq_lower(s->irq);
  78     }
  79 }
  80
  81 static uint64_t uart_read(void *opaque, hwaddr addr,
  82                           unsigned size)
  83 {
  84     MilkymistUartState *s = opaque;
  85     uint32_t r = 0;
  86
  87     addr >>= 2;
  88     switch (addr) {
  89     case R_RXTX:
  90         r = s->regs[addr];
  91         break;
  92     case R_DIV:
  93     case R_STAT:
  94     case R_CTRL:
  95     case R_DBG:
  96         r = s->regs[addr];
  97         break;
  98
  99     default:
 100         error_report("milkymist_uart: read access to unknown register 0x"
 101                 TARGET_FMT_plx, addr << 2);
 102         break;
 103     }
 104
 105     trace_milkymist_uart_memory_read(addr << 2, r);
 106
 107     return r;
 108 }
 109
 110 static void uart_write(void *opaque, hwaddr addr, uint64_t value,
 111                        unsigned size)
 112 {
 113     MilkymistUartState *s = opaque;
 114     unsigned char ch = value;
 115
 116     trace_milkymist_uart_memory_write(addr, value);
 117
 118     addr >>= 2;
 119     switch (addr) {
 120     case R_RXTX:
 121         if (s->chr) {
 122             qemu_chr_fe_write(s->chr, &ch, 1);
 123         }
 124         s->regs[R_STAT] |= STAT_TX_EVT;
 125         break;
 126     case R_DIV:
 127     case R_CTRL:
 128     case R_DBG:
 129         s->regs[addr] = value;
 130         break;
 131
 132     case R_STAT:
 133         /* write one to clear bits */
 134         s->regs[addr] &= ~(value & (STAT_RX_EVT | STAT_TX_EVT));
 135         qemu_chr_accept_input(s->chr);
 136         break;
 137
 138     default:
 139         error_report("milkymist_uart: write access to unknown register 0x"
 140                 TARGET_FMT_plx, addr << 2);
 141         break;
 142     }
 143
 144     uart_update_irq(s);
 145 }
 146
 147 static const MemoryRegionOps uart_mmio_ops = {
 148     .read = uart_read,
 149     .write = uart_write,
 150     .valid = {
 151         .min_access_size = 4,
 152         .max_access_size = 4,
 153     },
 154     .endianness = DEVICE_NATIVE_ENDIAN,
 155 };
 156
 157 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 158 {
 159     MilkymistUartState *s = opaque;
 160
 161     assert(!(s->regs[R_STAT] & STAT_RX_EVT));
 162
 163     s->regs[R_STAT] |= STAT_RX_EVT;
 164     s->regs[R_RXTX] = *buf;
 165
 166     uart_update_irq(s);
 167 }
 168
 169 static int uart_can_rx(void *opaque)
 170 {
 171     MilkymistUartState *s = opaque;
 172
 173     return !(s->regs[R_STAT] & STAT_RX_EVT);
 174 }
 175
 176 static void uart_event(void *opaque, int event)
 177 {
 178 }
 179
 180 static void milkymist_uart_reset(DeviceState *d)
 181 {
 182     MilkymistUartState *s = container_of(d, MilkymistUartState, busdev.qdev);
 183     int i;
 184
 185     for (i = 0; i < R_MAX; i++) {
 186         s->regs[i] = 0;
 187     }
 188
 189     /* THRE is always set */
 190     s->regs[R_STAT] = STAT_THRE;
 191 }
 192
 193 static int milkymist_uart_init(SysBusDevice *dev)
 194 {
 195     MilkymistUartState *s = FROM_SYSBUS(typeof(*s), dev);
 196
 197     sysbus_init_irq(dev, &s->irq);
 198
 199     memory_region_init_io(&s->regs_region, &uart_mmio_ops, s,
 200             "milkymist-uart", R_MAX * 4);
 201     sysbus_init_mmio(dev, &s->regs_region);
 202
 203     s->chr = qemu_char_get_next_serial();
 204     if (s->chr) {
 205         qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
 206     }
 207
 208     return 0;
 209 }
 210
 211 static const VMStateDescription vmstate_milkymist_uart = {
 212     .name = "milkymist-uart",
 213     .version_id = 1,
 214     .minimum_version_id = 1,
 215     .minimum_version_id_old = 1,
 216     .fields      = (VMStateField[]) {
 217         VMSTATE_UINT32_ARRAY(regs, MilkymistUartState, R_MAX),
 218         VMSTATE_END_OF_LIST()
 219     }
 220 };
 221
 222 static void milkymist_uart_class_init(ObjectClass *klass, void *data)
 223 {
 224     DeviceClass *dc = DEVICE_CLASS(klass);
 225     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 226
 227     k->init = milkymist_uart_init;
 228     dc->reset = milkymist_uart_reset;
 229     dc->vmsd = &vmstate_milkymist_uart;
 230 }
 231
 232 static const TypeInfo milkymist_uart_info = {
 233     .name          = "milkymist-uart",
 234     .parent        = TYPE_SYS_BUS_DEVICE,
 235     .instance_size = sizeof(MilkymistUartState),
 236     .class_init    = milkymist_uart_class_init,
 237 };
 238
 239 static void milkymist_uart_register_types(void)
 240 {
 241     type_register_static(&milkymist_uart_info);
 242 }
 243
 244 type_init(milkymist_uart_register_types)