hw/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc405.h"
  27 #include "nvram.h"
  28 #include "flash.h"
  29 #include "sysemu.h"
  30 #include "block.h"
  31 #include "boards.h"
  32 #include "qemu-log.h"
  33 #include "loader.h"
  34 #include "blockdev.h"
  35
  36 #define BIOS_FILENAME "ppc405_rom.bin"
  37 #define BIOS_SIZE (2048 * 1024)
  38
  39 #define KERNEL_LOAD_ADDR 0x00000000
  40 #define INITRD_LOAD_ADDR 0x01800000
  41
  42 #define USE_FLASH_BIOS
  43
  44 #define DEBUG_BOARD_INIT
  45
  46 /*****************************************************************************/
  47 /* PPC405EP reference board (IBM) */
  48 /* Standalone board with:
  49  * - PowerPC 405EP CPU
  50  * - SDRAM (0x00000000)
  51  * - Flash (0xFFF80000)
  52  * - SRAM  (0xFFF00000)
  53  * - NVRAM (0xF0000000)
  54  * - FPGA  (0xF0300000)
  55  */
  56 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  57 struct ref405ep_fpga_t {
  58     uint8_t reg0;
  59     uint8_t reg1;
  60 };
  61
  62 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
  63 {
  64     ref405ep_fpga_t *fpga;
  65     uint32_t ret;
  66
  67     fpga = opaque;
  68     switch (addr) {
  69     case 0x0:
  70         ret = fpga->reg0;
  71         break;
  72     case 0x1:
  73         ret = fpga->reg1;
  74         break;
  75     default:
  76         ret = 0;
  77         break;
  78     }
  79
  80     return ret;
  81 }
  82
  83 static void ref405ep_fpga_writeb (void *opaque,
  84                                   target_phys_addr_t addr, uint32_t value)
  85 {
  86     ref405ep_fpga_t *fpga;
  87
  88     fpga = opaque;
  89     switch (addr) {
  90     case 0x0:
  91         /* Read only */
  92         break;
  93     case 0x1:
  94         fpga->reg1 = value;
  95         break;
  96     default:
  97         break;
  98     }
  99 }
 100
 101 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
 102 {
 103     uint32_t ret;
 104
 105     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 106     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 107
 108     return ret;
 109 }
 110
 111 static void ref405ep_fpga_writew (void *opaque,
 112                                   target_phys_addr_t addr, uint32_t value)
 113 {
 114     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 115     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 116 }
 117
 118 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 119 {
 120     uint32_t ret;
 121
 122     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 123     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 124     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 125     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 126
 127     return ret;
 128 }
 129
 130 static void ref405ep_fpga_writel (void *opaque,
 131                                   target_phys_addr_t addr, uint32_t value)
 132 {
 133     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 134     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 135     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 136     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 137 }
 138
 139 static CPUReadMemoryFunc * const ref405ep_fpga_read[] = {
 140     &ref405ep_fpga_readb,
 141     &ref405ep_fpga_readw,
 142     &ref405ep_fpga_readl,
 143 };
 144
 145 static CPUWriteMemoryFunc * const ref405ep_fpga_write[] = {
 146     &ref405ep_fpga_writeb,
 147     &ref405ep_fpga_writew,
 148     &ref405ep_fpga_writel,
 149 };
 150
 151 static void ref405ep_fpga_reset (void *opaque)
 152 {
 153     ref405ep_fpga_t *fpga;
 154
 155     fpga = opaque;
 156     fpga->reg0 = 0x00;
 157     fpga->reg1 = 0x0F;
 158 }
 159
 160 static void ref405ep_fpga_init (uint32_t base)
 161 {
 162     ref405ep_fpga_t *fpga;
 163     int fpga_memory;
 164
 165     fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
 166     fpga_memory = cpu_register_io_memory(ref405ep_fpga_read,
 167                                          ref405ep_fpga_write, fpga);
 168     cpu_register_physical_memory(base, 0x00000100, fpga_memory);
 169     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 170 }
 171
 172 static void ref405ep_init (ram_addr_t ram_size,
 173                            const char *boot_device,
 174                            const char *kernel_filename,
 175                            const char *kernel_cmdline,
 176                            const char *initrd_filename,
 177                            const char *cpu_model)
 178 {
 179     char *filename;
 180     ppc4xx_bd_info_t bd;
 181     CPUPPCState *env;
 182     qemu_irq *pic;
 183     ram_addr_t sram_offset, bios_offset, bdloc;
 184     target_phys_addr_t ram_bases[2], ram_sizes[2];
 185     target_ulong sram_size, bios_size;
 186     //int phy_addr = 0;
 187     //static int phy_addr = 1;
 188     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 189     int linux_boot;
 190     int fl_idx, fl_sectors, len;
 191     DriveInfo *dinfo;
 192
 193     /* XXX: fix this */
 194     ram_bases[0] = qemu_ram_alloc(NULL, "ef405ep.ram", 0x08000000);
 195     ram_sizes[0] = 0x08000000;
 196     ram_bases[1] = 0x00000000;
 197     ram_sizes[1] = 0x00000000;
 198     ram_size = 128 * 1024 * 1024;
 199 #ifdef DEBUG_BOARD_INIT
 200     printf("%s: register cpu\n", __func__);
 201 #endif
 202     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 203                         kernel_filename == NULL ? 0 : 1);
 204     /* allocate SRAM */
 205     sram_size = 512 * 1024;
 206     sram_offset = qemu_ram_alloc(NULL, "ef405ep.sram", sram_size);
 207 #ifdef DEBUG_BOARD_INIT
 208     printf("%s: register SRAM at offset %08lx\n", __func__, sram_offset);
 209 #endif
 210     cpu_register_physical_memory(0xFFF00000, sram_size,
 211                                  sram_offset | IO_MEM_RAM);
 212     /* allocate and load BIOS */
 213 #ifdef DEBUG_BOARD_INIT
 214     printf("%s: register BIOS\n", __func__);
 215 #endif
 216     fl_idx = 0;
 217 #ifdef USE_FLASH_BIOS
 218     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 219     if (dinfo) {
 220         bios_size = bdrv_getlength(dinfo->bdrv);
 221         bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", bios_size);
 222         fl_sectors = (bios_size + 65535) >> 16;
 223 #ifdef DEBUG_BOARD_INIT
 224         printf("Register parallel flash %d size " TARGET_FMT_lx
 225                " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
 226                fl_idx, bios_size, bios_offset, -bios_size,
 227                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 228 #endif
 229         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 230                               dinfo->bdrv, 65536, fl_sectors, 1,
 231                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 232                               1);
 233         fl_idx++;
 234     } else
 235 #endif
 236     {
 237 #ifdef DEBUG_BOARD_INIT
 238         printf("Load BIOS from file\n");
 239 #endif
 240         bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", BIOS_SIZE);
 241         if (bios_name == NULL)
 242             bios_name = BIOS_FILENAME;
 243         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 244         if (filename) {
 245             bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
 246             qemu_free(filename);
 247         } else {
 248             bios_size = -1;
 249         }
 250         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 251             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 252                     bios_name);
 253             exit(1);
 254         }
 255         bios_size = (bios_size + 0xfff) & ~0xfff;
 256         cpu_register_physical_memory((uint32_t)(-bios_size),
 257                                      bios_size, bios_offset | IO_MEM_ROM);
 258     }
 259     /* Register FPGA */
 260 #ifdef DEBUG_BOARD_INIT
 261     printf("%s: register FPGA\n", __func__);
 262 #endif
 263     ref405ep_fpga_init(0xF0300000);
 264     /* Register NVRAM */
 265 #ifdef DEBUG_BOARD_INIT
 266     printf("%s: register NVRAM\n", __func__);
 267 #endif
 268     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 269     /* Load kernel */
 270     linux_boot = (kernel_filename != NULL);
 271     if (linux_boot) {
 272 #ifdef DEBUG_BOARD_INIT
 273         printf("%s: load kernel\n", __func__);
 274 #endif
 275         memset(&bd, 0, sizeof(bd));
 276         bd.bi_memstart = 0x00000000;
 277         bd.bi_memsize = ram_size;
 278         bd.bi_flashstart = -bios_size;
 279         bd.bi_flashsize = -bios_size;
 280         bd.bi_flashoffset = 0;
 281         bd.bi_sramstart = 0xFFF00000;
 282         bd.bi_sramsize = sram_size;
 283         bd.bi_bootflags = 0;
 284         bd.bi_intfreq = 133333333;
 285         bd.bi_busfreq = 33333333;
 286         bd.bi_baudrate = 115200;
 287         bd.bi_s_version[0] = 'Q';
 288         bd.bi_s_version[1] = 'M';
 289         bd.bi_s_version[2] = 'U';
 290         bd.bi_s_version[3] = '\0';
 291         bd.bi_r_version[0] = 'Q';
 292         bd.bi_r_version[1] = 'E';
 293         bd.bi_r_version[2] = 'M';
 294         bd.bi_r_version[3] = 'U';
 295         bd.bi_r_version[4] = '\0';
 296         bd.bi_procfreq = 133333333;
 297         bd.bi_plb_busfreq = 33333333;
 298         bd.bi_pci_busfreq = 33333333;
 299         bd.bi_opbfreq = 33333333;
 300         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 301         env->gpr[3] = bdloc;
 302         kernel_base = KERNEL_LOAD_ADDR;
 303         /* now we can load the kernel */
 304         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 305                                           ram_size - kernel_base);
 306         if (kernel_size < 0) {
 307             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 308                     kernel_filename);
 309             exit(1);
 310         }
 311         printf("Load kernel size " TARGET_FMT_ld " at " TARGET_FMT_lx,
 312                kernel_size, kernel_base);
 313         /* load initrd */
 314         if (initrd_filename) {
 315             initrd_base = INITRD_LOAD_ADDR;
 316             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 317                                               ram_size - initrd_base);
 318             if (initrd_size < 0) {
 319                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 320                         initrd_filename);
 321                 exit(1);
 322             }
 323         } else {
 324             initrd_base = 0;
 325             initrd_size = 0;
 326         }
 327         env->gpr[4] = initrd_base;
 328         env->gpr[5] = initrd_size;
 329         if (kernel_cmdline != NULL) {
 330             len = strlen(kernel_cmdline);
 331             bdloc -= ((len + 255) & ~255);
 332             cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
 333             env->gpr[6] = bdloc;
 334             env->gpr[7] = bdloc + len;
 335         } else {
 336             env->gpr[6] = 0;
 337             env->gpr[7] = 0;
 338         }
 339         env->nip = KERNEL_LOAD_ADDR;
 340     } else {
 341         kernel_base = 0;
 342         kernel_size = 0;
 343         initrd_base = 0;
 344         initrd_size = 0;
 345         bdloc = 0;
 346     }
 347 #ifdef DEBUG_BOARD_INIT
 348     printf("%s: Done\n", __func__);
 349 #endif
 350     printf("bdloc %016lx\n", (unsigned long)bdloc);
 351 }
 352
 353 static QEMUMachine ref405ep_machine = {
 354     .name = "ref405ep",
 355     .desc = "ref405ep",
 356     .init = ref405ep_init,
 357 };
 358
 359 /*****************************************************************************/
 360 /* AMCC Taihu evaluation board */
 361 /* - PowerPC 405EP processor
 362  * - SDRAM               128 MB at 0x00000000
 363  * - Boot flash          2 MB   at 0xFFE00000
 364  * - Application flash   32 MB  at 0xFC000000
 365  * - 2 serial ports
 366  * - 2 ethernet PHY
 367  * - 1 USB 1.1 device    0x50000000
 368  * - 1 LCD display       0x50100000
 369  * - 1 CPLD              0x50100000
 370  * - 1 I2C EEPROM
 371  * - 1 I2C thermal sensor
 372  * - a set of LEDs
 373  * - bit-bang SPI port using GPIOs
 374  * - 1 EBC interface connector 0 0x50200000
 375  * - 1 cardbus controller + expansion slot.
 376  * - 1 PCI expansion slot.
 377  */
 378 typedef struct taihu_cpld_t taihu_cpld_t;
 379 struct taihu_cpld_t {
 380     uint8_t reg0;
 381     uint8_t reg1;
 382 };
 383
 384 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
 385 {
 386     taihu_cpld_t *cpld;
 387     uint32_t ret;
 388
 389     cpld = opaque;
 390     switch (addr) {
 391     case 0x0:
 392         ret = cpld->reg0;
 393         break;
 394     case 0x1:
 395         ret = cpld->reg1;
 396         break;
 397     default:
 398         ret = 0;
 399         break;
 400     }
 401
 402     return ret;
 403 }
 404
 405 static void taihu_cpld_writeb (void *opaque,
 406                                target_phys_addr_t addr, uint32_t value)
 407 {
 408     taihu_cpld_t *cpld;
 409
 410     cpld = opaque;
 411     switch (addr) {
 412     case 0x0:
 413         /* Read only */
 414         break;
 415     case 0x1:
 416         cpld->reg1 = value;
 417         break;
 418     default:
 419         break;
 420     }
 421 }
 422
 423 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
 424 {
 425     uint32_t ret;
 426
 427     ret = taihu_cpld_readb(opaque, addr) << 8;
 428     ret |= taihu_cpld_readb(opaque, addr + 1);
 429
 430     return ret;
 431 }
 432
 433 static void taihu_cpld_writew (void *opaque,
 434                                target_phys_addr_t addr, uint32_t value)
 435 {
 436     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 437     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 438 }
 439
 440 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
 441 {
 442     uint32_t ret;
 443
 444     ret = taihu_cpld_readb(opaque, addr) << 24;
 445     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 446     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 447     ret |= taihu_cpld_readb(opaque, addr + 3);
 448
 449     return ret;
 450 }
 451
 452 static void taihu_cpld_writel (void *opaque,
 453                                target_phys_addr_t addr, uint32_t value)
 454 {
 455     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 456     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 457     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 458     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 459 }
 460
 461 static CPUReadMemoryFunc * const taihu_cpld_read[] = {
 462     &taihu_cpld_readb,
 463     &taihu_cpld_readw,
 464     &taihu_cpld_readl,
 465 };
 466
 467 static CPUWriteMemoryFunc * const taihu_cpld_write[] = {
 468     &taihu_cpld_writeb,
 469     &taihu_cpld_writew,
 470     &taihu_cpld_writel,
 471 };
 472
 473 static void taihu_cpld_reset (void *opaque)
 474 {
 475     taihu_cpld_t *cpld;
 476
 477     cpld = opaque;
 478     cpld->reg0 = 0x01;
 479     cpld->reg1 = 0x80;
 480 }
 481
 482 static void taihu_cpld_init (uint32_t base)
 483 {
 484     taihu_cpld_t *cpld;
 485     int cpld_memory;
 486
 487     cpld = qemu_mallocz(sizeof(taihu_cpld_t));
 488     cpld_memory = cpu_register_io_memory(taihu_cpld_read,
 489                                          taihu_cpld_write, cpld);
 490     cpu_register_physical_memory(base, 0x00000100, cpld_memory);
 491     qemu_register_reset(&taihu_cpld_reset, cpld);
 492 }
 493
 494 static void taihu_405ep_init(ram_addr_t ram_size,
 495                              const char *boot_device,
 496                              const char *kernel_filename,
 497                              const char *kernel_cmdline,
 498                              const char *initrd_filename,
 499                              const char *cpu_model)
 500 {
 501     char *filename;
 502     CPUPPCState *env;
 503     qemu_irq *pic;
 504     ram_addr_t bios_offset;
 505     target_phys_addr_t ram_bases[2], ram_sizes[2];
 506     target_ulong bios_size;
 507     target_ulong kernel_base, kernel_size, initrd_base, initrd_size;
 508     int linux_boot;
 509     int fl_idx, fl_sectors;
 510     DriveInfo *dinfo;
 511
 512     /* RAM is soldered to the board so the size cannot be changed */
 513     ram_bases[0] = qemu_ram_alloc(NULL, "taihu_405ep.ram-0", 0x04000000);
 514     ram_sizes[0] = 0x04000000;
 515     ram_bases[1] = qemu_ram_alloc(NULL, "taihu_405ep.ram-1", 0x04000000);
 516     ram_sizes[1] = 0x04000000;
 517     ram_size = 0x08000000;
 518 #ifdef DEBUG_BOARD_INIT
 519     printf("%s: register cpu\n", __func__);
 520 #endif
 521     env = ppc405ep_init(ram_bases, ram_sizes, 33333333, &pic,
 522                         kernel_filename == NULL ? 0 : 1);
 523     /* allocate and load BIOS */
 524 #ifdef DEBUG_BOARD_INIT
 525     printf("%s: register BIOS\n", __func__);
 526 #endif
 527     fl_idx = 0;
 528 #if defined(USE_FLASH_BIOS)
 529     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 530     if (dinfo) {
 531         bios_size = bdrv_getlength(dinfo->bdrv);
 532         /* XXX: should check that size is 2MB */
 533         //        bios_size = 2 * 1024 * 1024;
 534         fl_sectors = (bios_size + 65535) >> 16;
 535         bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", bios_size);
 536 #ifdef DEBUG_BOARD_INIT
 537         printf("Register parallel flash %d size " TARGET_FMT_lx
 538                " at offset %08lx addr " TARGET_FMT_lx " '%s' %d\n",
 539                fl_idx, bios_size, bios_offset, -bios_size,
 540                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 541 #endif
 542         pflash_cfi02_register((uint32_t)(-bios_size), bios_offset,
 543                               dinfo->bdrv, 65536, fl_sectors, 1,
 544                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 545                               1);
 546         fl_idx++;
 547     } else
 548 #endif
 549     {
 550 #ifdef DEBUG_BOARD_INIT
 551         printf("Load BIOS from file\n");
 552 #endif
 553         if (bios_name == NULL)
 554             bios_name = BIOS_FILENAME;
 555         bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", BIOS_SIZE);
 556         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 557         if (filename) {
 558             bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset));
 559         } else {
 560             bios_size = -1;
 561         }
 562         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 563             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 564                     bios_name);
 565             exit(1);
 566         }
 567         bios_size = (bios_size + 0xfff) & ~0xfff;
 568         cpu_register_physical_memory((uint32_t)(-bios_size),
 569                                      bios_size, bios_offset | IO_MEM_ROM);
 570     }
 571     /* Register Linux flash */
 572     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 573     if (dinfo) {
 574         bios_size = bdrv_getlength(dinfo->bdrv);
 575         /* XXX: should check that size is 32MB */
 576         bios_size = 32 * 1024 * 1024;
 577         fl_sectors = (bios_size + 65535) >> 16;
 578 #ifdef DEBUG_BOARD_INIT
 579         printf("Register parallel flash %d size " TARGET_FMT_lx
 580                " at offset %08lx  addr " TARGET_FMT_lx " '%s'\n",
 581                fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000,
 582                bdrv_get_device_name(dinfo->bdrv));
 583 #endif
 584         bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.flash", bios_size);
 585         pflash_cfi02_register(0xfc000000, bios_offset,
 586                               dinfo->bdrv, 65536, fl_sectors, 1,
 587                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 588                               1);
 589         fl_idx++;
 590     }
 591     /* Register CLPD & LCD display */
 592 #ifdef DEBUG_BOARD_INIT
 593     printf("%s: register CPLD\n", __func__);
 594 #endif
 595     taihu_cpld_init(0x50100000);
 596     /* Load kernel */
 597     linux_boot = (kernel_filename != NULL);
 598     if (linux_boot) {
 599 #ifdef DEBUG_BOARD_INIT
 600         printf("%s: load kernel\n", __func__);
 601 #endif
 602         kernel_base = KERNEL_LOAD_ADDR;
 603         /* now we can load the kernel */
 604         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 605                                           ram_size - kernel_base);
 606         if (kernel_size < 0) {
 607             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 608                     kernel_filename);
 609             exit(1);
 610         }
 611         /* load initrd */
 612         if (initrd_filename) {
 613             initrd_base = INITRD_LOAD_ADDR;
 614             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 615                                               ram_size - initrd_base);
 616             if (initrd_size < 0) {
 617                 fprintf(stderr,
 618                         "qemu: could not load initial ram disk '%s'\n",
 619                         initrd_filename);
 620                 exit(1);
 621             }
 622         } else {
 623             initrd_base = 0;
 624             initrd_size = 0;
 625         }
 626     } else {
 627         kernel_base = 0;
 628         kernel_size = 0;
 629         initrd_base = 0;
 630         initrd_size = 0;
 631     }
 632 #ifdef DEBUG_BOARD_INIT
 633     printf("%s: Done\n", __func__);
 634 #endif
 635 }
 636
 637 static QEMUMachine taihu_machine = {
 638     .name = "taihu",
 639     .desc = "taihu",
 640     .init = taihu_405ep_init,
 641 };
 642
 643 static void ppc405_machine_init(void)
 644 {
 645     qemu_register_machine(&ref405ep_machine);
 646     qemu_register_machine(&taihu_machine);
 647 }
 648
 649 machine_init(ppc405_machine_init);