?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
prepare pci nic init path for qdev property configuration.
[qemu.git] / hw / fdc.c
blobb584b9867c39833bd321dbeb3f843ad85dfc08ff
1 /*
2 * QEMU Floppy disk emulator (Intel 82078)
3 *
4 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 * Copyright (c) 2008 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 /*
26 * The controller is used in Sun4m systems in a slightly different
27 * way. There are changes in DOR register and DMA is not available.
28 */
29
30 #include "hw.h"
31 #include "fdc.h"
32 #include "block.h"
33 #include "qemu-timer.h"
34 #include "isa.h"
35 #include "sysbus.h"
36 #include "qdev-addr.h"
37
38 /********************************************************/
39 /* debug Floppy devices */
40 //#define DEBUG_FLOPPY
41
42 #ifdef DEBUG_FLOPPY
43 #define FLOPPY_DPRINTF(fmt, ...) \
44 do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
45 #else
46 #define FLOPPY_DPRINTF(fmt, ...)
47 #endif
48
49 #define FLOPPY_ERROR(fmt, ...) \
50 do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
51
52 /********************************************************/
53 /* Floppy drive emulation */
54
55 #define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
56 #define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
57
58 /* Will always be a fixed parameter for us */
59 #define FD_SECTOR_LEN 512
60 #define FD_SECTOR_SC 2 /* Sector size code */
61 #define FD_RESET_SENSEI_COUNT 4 /* Number of sense interrupts on RESET */
62
63 /* Floppy disk drive emulation */
64 typedef enum fdisk_type_t {
65 FDRIVE_DISK_288 = 0x01, /* 2.88 MB disk */
66 FDRIVE_DISK_144 = 0x02, /* 1.44 MB disk */
67 FDRIVE_DISK_720 = 0x03, /* 720 kB disk */
68 FDRIVE_DISK_USER = 0x04, /* User defined geometry */
69 FDRIVE_DISK_NONE = 0x05, /* No disk */
70 } fdisk_type_t;
71
72 typedef enum fdrive_type_t {
73 FDRIVE_DRV_144 = 0x00, /* 1.44 MB 3"5 drive */
74 FDRIVE_DRV_288 = 0x01, /* 2.88 MB 3"5 drive */
75 FDRIVE_DRV_120 = 0x02, /* 1.2 MB 5"25 drive */
76 FDRIVE_DRV_NONE = 0x03, /* No drive connected */
77 } fdrive_type_t;
78
79 typedef enum fdisk_flags_t {
80 FDISK_DBL_SIDES = 0x01,
81 } fdisk_flags_t;
82
83 typedef struct fdrive_t {
84 DriveInfo *dinfo;
85 BlockDriverState *bs;
86 /* Drive status */
87 fdrive_type_t drive;
88 uint8_t perpendicular; /* 2.88 MB access mode */
89 /* Position */
90 uint8_t head;
91 uint8_t track;
92 uint8_t sect;
93 /* Media */
94 fdisk_flags_t flags;
95 uint8_t last_sect; /* Nb sector per track */
96 uint8_t max_track; /* Nb of tracks */
97 uint16_t bps; /* Bytes per sector */
98 uint8_t ro; /* Is read-only */
99 } fdrive_t;
100
101 static void fd_init (fdrive_t *drv)
102 {
103 /* Drive */
104 drv->bs = drv->dinfo ? drv->dinfo->bdrv : NULL;
105 drv->drive = FDRIVE_DRV_NONE;
106 drv->perpendicular = 0;
107 /* Disk */
108 drv->last_sect = 0;
109 drv->max_track = 0;
110 }
111
112 static int _fd_sector (uint8_t head, uint8_t track,
113 uint8_t sect, uint8_t last_sect)
114 {
115 return (((track * 2) + head) * last_sect) + sect - 1;
116 }
117
118 /* Returns current position, in sectors, for given drive */
119 static int fd_sector (fdrive_t *drv)
120 {
121 return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
122 }
123
124 /* Seek to a new position:
125 * returns 0 if already on right track
126 * returns 1 if track changed
127 * returns 2 if track is invalid
128 * returns 3 if sector is invalid
129 * returns 4 if seek is disabled
130 */
131 static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
132 int enable_seek)
133 {
134 uint32_t sector;
135 int ret;
136
137 if (track > drv->max_track ||
138 (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
139 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
140 head, track, sect, 1,
141 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
142 drv->max_track, drv->last_sect);
143 return 2;
144 }
145 if (sect > drv->last_sect) {
146 FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
147 head, track, sect, 1,
148 (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
149 drv->max_track, drv->last_sect);
150 return 3;
151 }
152 sector = _fd_sector(head, track, sect, drv->last_sect);
153 ret = 0;
154 if (sector != fd_sector(drv)) {
155 #if 0
156 if (!enable_seek) {
157 FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
158 head, track, sect, 1, drv->max_track, drv->last_sect);
159 return 4;
160 }
161 #endif
162 drv->head = head;
163 if (drv->track != track)
164 ret = 1;
165 drv->track = track;
166 drv->sect = sect;
167 }
168
169 return ret;
170 }
171
172 /* Set drive back to track 0 */
173 static void fd_recalibrate (fdrive_t *drv)
174 {
175 FLOPPY_DPRINTF("recalibrate\n");
176 drv->head = 0;
177 drv->track = 0;
178 drv->sect = 1;
179 }
180
181 /* Recognize floppy formats */
182 typedef struct fd_format_t {
183 fdrive_type_t drive;
184 fdisk_type_t disk;
185 uint8_t last_sect;
186 uint8_t max_track;
187 uint8_t max_head;
188 const char *str;
189 } fd_format_t;
190
191 static const fd_format_t fd_formats[] = {
192 /* First entry is default format */
193 /* 1.44 MB 3"1/2 floppy disks */
194 { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
195 { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1, "1.6 MB 3\"1/2", },
196 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
197 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
198 { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
199 { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
200 { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
201 { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
202 /* 2.88 MB 3"1/2 floppy disks */
203 { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
204 { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
205 { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1, "3.2 MB 3\"1/2", },
206 { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
207 { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
208 /* 720 kB 3"1/2 floppy disks */
209 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 1, "720 kB 3\"1/2", },
210 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1, "800 kB 3\"1/2", },
211 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1, "820 kB 3\"1/2", },
212 { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1, "830 kB 3\"1/2", },
213 { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
214 { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
215 /* 1.2 MB 5"1/4 floppy disks */
216 { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1, "1.2 kB 5\"1/4", },
217 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
218 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
219 { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
220 { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1, "1.6 MB 5\"1/4", },
221 /* 720 kB 5"1/4 floppy disks */
222 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 80, 1, "720 kB 5\"1/4", },
223 { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1, "880 kB 5\"1/4", },
224 /* 360 kB 5"1/4 floppy disks */
225 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 1, "360 kB 5\"1/4", },
226 { FDRIVE_DRV_120, FDRIVE_DISK_288, 9, 40, 0, "180 kB 5\"1/4", },
227 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1, "410 kB 5\"1/4", },
228 { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1, "420 kB 5\"1/4", },
229 /* 320 kB 5"1/4 floppy disks */
230 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 1, "320 kB 5\"1/4", },
231 { FDRIVE_DRV_120, FDRIVE_DISK_288, 8, 40, 0, "160 kB 5\"1/4", },
232 /* 360 kB must match 5"1/4 better than 3"1/2... */
233 { FDRIVE_DRV_144, FDRIVE_DISK_720, 9, 80, 0, "360 kB 3\"1/2", },
234 /* end */
235 { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
236 };
237
238 /* Revalidate a disk drive after a disk change */
239 static void fd_revalidate (fdrive_t *drv)
240 {
241 const fd_format_t *parse;
242 uint64_t nb_sectors, size;
243 int i, first_match, match;
244 int nb_heads, max_track, last_sect, ro;
245
246 FLOPPY_DPRINTF("revalidate\n");
247 if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
248 ro = bdrv_is_read_only(drv->bs);
249 bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
250 if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
251 FLOPPY_DPRINTF("User defined disk (%d %d %d)",
252 nb_heads - 1, max_track, last_sect);
253 } else {
254 bdrv_get_geometry(drv->bs, &nb_sectors);
255 match = -1;
256 first_match = -1;
257 for (i = 0;; i++) {
258 parse = &fd_formats[i];
259 if (parse->drive == FDRIVE_DRV_NONE)
260 break;
261 if (drv->drive == parse->drive ||
262 drv->drive == FDRIVE_DRV_NONE) {
263 size = (parse->max_head + 1) * parse->max_track *
264 parse->last_sect;
265 if (nb_sectors == size) {
266 match = i;
267 break;
268 }
269 if (first_match == -1)
270 first_match = i;
271 }
272 }
273 if (match == -1) {
274 if (first_match == -1)
275 match = 1;
276 else
277 match = first_match;
278 parse = &fd_formats[match];
279 }
280 nb_heads = parse->max_head + 1;
281 max_track = parse->max_track;
282 last_sect = parse->last_sect;
283 drv->drive = parse->drive;
284 FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
285 nb_heads, max_track, last_sect, ro ? "ro" : "rw");
286 }
287 if (nb_heads == 1) {
288 drv->flags &= ~FDISK_DBL_SIDES;
289 } else {
290 drv->flags |= FDISK_DBL_SIDES;
291 }
292 drv->max_track = max_track;
293 drv->last_sect = last_sect;
294 drv->ro = ro;
295 } else {
296 FLOPPY_DPRINTF("No disk in drive\n");
297 drv->last_sect = 0;
298 drv->max_track = 0;
299 drv->flags &= ~FDISK_DBL_SIDES;
300 }
301 }
302
303 /********************************************************/
304 /* Intel 82078 floppy disk controller emulation */
305
306 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
307 static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
308 static int fdctrl_transfer_handler (void *opaque, int nchan,
309 int dma_pos, int dma_len);
310 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
311
312 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
313 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
314 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
315 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
316 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
317 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
318 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
319 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
320 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
321 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
322 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
323
324 enum {
325 FD_DIR_WRITE = 0,
326 FD_DIR_READ = 1,
327 FD_DIR_SCANE = 2,
328 FD_DIR_SCANL = 3,
329 FD_DIR_SCANH = 4,
330 };
331
332 enum {
333 FD_STATE_MULTI = 0x01, /* multi track flag */
334 FD_STATE_FORMAT = 0x02, /* format flag */
335 FD_STATE_SEEK = 0x04, /* seek flag */
336 };
337
338 enum {
339 FD_REG_SRA = 0x00,
340 FD_REG_SRB = 0x01,
341 FD_REG_DOR = 0x02,
342 FD_REG_TDR = 0x03,
343 FD_REG_MSR = 0x04,
344 FD_REG_DSR = 0x04,
345 FD_REG_FIFO = 0x05,
346 FD_REG_DIR = 0x07,
347 };
348
349 enum {
350 FD_CMD_READ_TRACK = 0x02,
351 FD_CMD_SPECIFY = 0x03,
352 FD_CMD_SENSE_DRIVE_STATUS = 0x04,
353 FD_CMD_WRITE = 0x05,
354 FD_CMD_READ = 0x06,
355 FD_CMD_RECALIBRATE = 0x07,
356 FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
357 FD_CMD_WRITE_DELETED = 0x09,
358 FD_CMD_READ_ID = 0x0a,
359 FD_CMD_READ_DELETED = 0x0c,
360 FD_CMD_FORMAT_TRACK = 0x0d,
361 FD_CMD_DUMPREG = 0x0e,
362 FD_CMD_SEEK = 0x0f,
363 FD_CMD_VERSION = 0x10,
364 FD_CMD_SCAN_EQUAL = 0x11,
365 FD_CMD_PERPENDICULAR_MODE = 0x12,
366 FD_CMD_CONFIGURE = 0x13,
367 FD_CMD_LOCK = 0x14,
368 FD_CMD_VERIFY = 0x16,
369 FD_CMD_POWERDOWN_MODE = 0x17,
370 FD_CMD_PART_ID = 0x18,
371 FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
372 FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
373 FD_CMD_SAVE = 0x2c,
374 FD_CMD_OPTION = 0x33,
375 FD_CMD_RESTORE = 0x4c,
376 FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
377 FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
378 FD_CMD_FORMAT_AND_WRITE = 0xcd,
379 FD_CMD_RELATIVE_SEEK_IN = 0xcf,
380 };
381
382 enum {
383 FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
384 FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
385 FD_CONFIG_POLL = 0x10, /* Poll enabled */
386 FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
387 FD_CONFIG_EIS = 0x40, /* No implied seeks */
388 };
389
390 enum {
391 FD_SR0_EQPMT = 0x10,
392 FD_SR0_SEEK = 0x20,
393 FD_SR0_ABNTERM = 0x40,
394 FD_SR0_INVCMD = 0x80,
395 FD_SR0_RDYCHG = 0xc0,
396 };
397
398 enum {
399 FD_SR1_EC = 0x80, /* End of cylinder */
400 };
401
402 enum {
403 FD_SR2_SNS = 0x04, /* Scan not satisfied */
404 FD_SR2_SEH = 0x08, /* Scan equal hit */
405 };
406
407 enum {
408 FD_SRA_DIR = 0x01,
409 FD_SRA_nWP = 0x02,
410 FD_SRA_nINDX = 0x04,
411 FD_SRA_HDSEL = 0x08,
412 FD_SRA_nTRK0 = 0x10,
413 FD_SRA_STEP = 0x20,
414 FD_SRA_nDRV2 = 0x40,
415 FD_SRA_INTPEND = 0x80,
416 };
417
418 enum {
419 FD_SRB_MTR0 = 0x01,
420 FD_SRB_MTR1 = 0x02,
421 FD_SRB_WGATE = 0x04,
422 FD_SRB_RDATA = 0x08,
423 FD_SRB_WDATA = 0x10,
424 FD_SRB_DR0 = 0x20,
425 };
426
427 enum {
428 #if MAX_FD == 4
429 FD_DOR_SELMASK = 0x03,
430 #else
431 FD_DOR_SELMASK = 0x01,
432 #endif
433 FD_DOR_nRESET = 0x04,
434 FD_DOR_DMAEN = 0x08,
435 FD_DOR_MOTEN0 = 0x10,
436 FD_DOR_MOTEN1 = 0x20,
437 FD_DOR_MOTEN2 = 0x40,
438 FD_DOR_MOTEN3 = 0x80,
439 };
440
441 enum {
442 #if MAX_FD == 4
443 FD_TDR_BOOTSEL = 0x0c,
444 #else
445 FD_TDR_BOOTSEL = 0x04,
446 #endif
447 };
448
449 enum {
450 FD_DSR_DRATEMASK= 0x03,
451 FD_DSR_PWRDOWN = 0x40,
452 FD_DSR_SWRESET = 0x80,
453 };
454
455 enum {
456 FD_MSR_DRV0BUSY = 0x01,
457 FD_MSR_DRV1BUSY = 0x02,
458 FD_MSR_DRV2BUSY = 0x04,
459 FD_MSR_DRV3BUSY = 0x08,
460 FD_MSR_CMDBUSY = 0x10,
461 FD_MSR_NONDMA = 0x20,
462 FD_MSR_DIO = 0x40,
463 FD_MSR_RQM = 0x80,
464 };
465
466 enum {
467 FD_DIR_DSKCHG = 0x80,
468 };
469
470 #define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
471 #define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
472 #define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
473
474 struct fdctrl_t {
475 /* Controller's identification */
476 uint8_t version;
477 /* HW */
478 qemu_irq irq;
479 int dma_chann;
480 /* Controller state */
481 QEMUTimer *result_timer;
482 uint8_t sra;
483 uint8_t srb;
484 uint8_t dor;
485 uint8_t dor_vmstate; /* only used as temp during vmstate */
486 uint8_t tdr;
487 uint8_t dsr;
488 uint8_t msr;
489 uint8_t cur_drv;
490 uint8_t status0;
491 uint8_t status1;
492 uint8_t status2;
493 /* Command FIFO */
494 uint8_t *fifo;
495 int32_t fifo_size;
496 uint32_t data_pos;
497 uint32_t data_len;
498 uint8_t data_state;
499 uint8_t data_dir;
500 uint8_t eot; /* last wanted sector */
501 /* States kept only to be returned back */
502 /* Timers state */
503 uint8_t timer0;
504 uint8_t timer1;
505 /* precompensation */
506 uint8_t precomp_trk;
507 uint8_t config;
508 uint8_t lock;
509 /* Power down config (also with status regB access mode */
510 uint8_t pwrd;
511 /* Sun4m quirks? */
512 int sun4m;
513 /* Floppy drives */
514 uint8_t num_floppies;
515 fdrive_t drives[MAX_FD];
516 int reset_sensei;
517 };
518
519 typedef struct fdctrl_sysbus_t {
520 SysBusDevice busdev;
521 struct fdctrl_t state;
522 } fdctrl_sysbus_t;
523
524 typedef struct fdctrl_isabus_t {
525 ISADevice busdev;
526 struct fdctrl_t state;
527 } fdctrl_isabus_t;
528
529 static uint32_t fdctrl_read (void *opaque, uint32_t reg)
530 {
531 fdctrl_t *fdctrl = opaque;
532 uint32_t retval;
533
534 switch (reg) {
535 case FD_REG_SRA:
536 retval = fdctrl_read_statusA(fdctrl);
537 break;
538 case FD_REG_SRB:
539 retval = fdctrl_read_statusB(fdctrl);
540 break;
541 case FD_REG_DOR:
542 retval = fdctrl_read_dor(fdctrl);
543 break;
544 case FD_REG_TDR:
545 retval = fdctrl_read_tape(fdctrl);
546 break;
547 case FD_REG_MSR:
548 retval = fdctrl_read_main_status(fdctrl);
549 break;
550 case FD_REG_FIFO:
551 retval = fdctrl_read_data(fdctrl);
552 break;
553 case FD_REG_DIR:
554 retval = fdctrl_read_dir(fdctrl);
555 break;
556 default:
557 retval = (uint32_t)(-1);
558 break;
559 }
560 FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
561
562 return retval;
563 }
564
565 static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
566 {
567 fdctrl_t *fdctrl = opaque;
568
569 FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
570
571 switch (reg) {
572 case FD_REG_DOR:
573 fdctrl_write_dor(fdctrl, value);
574 break;
575 case FD_REG_TDR:
576 fdctrl_write_tape(fdctrl, value);
577 break;
578 case FD_REG_DSR:
579 fdctrl_write_rate(fdctrl, value);
580 break;
581 case FD_REG_FIFO:
582 fdctrl_write_data(fdctrl, value);
583 break;
584 default:
585 break;
586 }
587 }
588
589 static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
590 {
591 return fdctrl_read(opaque, reg & 7);
592 }
593
594 static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
595 {
596 fdctrl_write(opaque, reg & 7, value);
597 }
598
599 static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
600 {
601 return fdctrl_read(opaque, (uint32_t)reg);
602 }
603
604 static void fdctrl_write_mem (void *opaque,
605 target_phys_addr_t reg, uint32_t value)
606 {
607 fdctrl_write(opaque, (uint32_t)reg, value);
608 }
609
610 static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
611 fdctrl_read_mem,
612 fdctrl_read_mem,
613 fdctrl_read_mem,
614 };
615
616 static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
617 fdctrl_write_mem,
618 fdctrl_write_mem,
619 fdctrl_write_mem,
620 };
621
622 static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
623 fdctrl_read_mem,
624 NULL,
625 NULL,
626 };
627
628 static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
629 fdctrl_write_mem,
630 NULL,
631 NULL,
632 };
633
634 static const VMStateDescription vmstate_fdrive = {
635 .name = "fdrive",
636 .version_id = 1,
637 .minimum_version_id = 1,
638 .minimum_version_id_old = 1,
639 .fields = (VMStateField []) {
640 VMSTATE_UINT8(head, fdrive_t),
641 VMSTATE_UINT8(track, fdrive_t),
642 VMSTATE_UINT8(sect, fdrive_t),
643 VMSTATE_END_OF_LIST()
644 }
645 };
646
647 static void fdc_pre_save(void *opaque)
648 {
649 fdctrl_t *s = opaque;
650
651 s->dor_vmstate = s->dor | GET_CUR_DRV(s);
652 }
653
654 static int fdc_post_load(void *opaque, int version_id)
655 {
656 fdctrl_t *s = opaque;
657
658 SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
659 s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
660 return 0;
661 }
662
663 static const VMStateDescription vmstate_fdc = {
664 .name = "fdc",
665 .version_id = 2,
666 .minimum_version_id = 2,
667 .minimum_version_id_old = 2,
668 .pre_save = fdc_pre_save,
669 .post_load = fdc_post_load,
670 .fields = (VMStateField []) {
671 /* Controller State */
672 VMSTATE_UINT8(sra, fdctrl_t),
673 VMSTATE_UINT8(srb, fdctrl_t),
674 VMSTATE_UINT8(dor_vmstate, fdctrl_t),
675 VMSTATE_UINT8(tdr, fdctrl_t),
676 VMSTATE_UINT8(dsr, fdctrl_t),
677 VMSTATE_UINT8(msr, fdctrl_t),
678 VMSTATE_UINT8(status0, fdctrl_t),
679 VMSTATE_UINT8(status1, fdctrl_t),
680 VMSTATE_UINT8(status2, fdctrl_t),
681 /* Command FIFO */
682 VMSTATE_VARRAY(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8),
683 VMSTATE_UINT32(data_pos, fdctrl_t),
684 VMSTATE_UINT32(data_len, fdctrl_t),
685 VMSTATE_UINT8(data_state, fdctrl_t),
686 VMSTATE_UINT8(data_dir, fdctrl_t),
687 VMSTATE_UINT8(eot, fdctrl_t),
688 /* States kept only to be returned back */
689 VMSTATE_UINT8(timer0, fdctrl_t),
690 VMSTATE_UINT8(timer1, fdctrl_t),
691 VMSTATE_UINT8(precomp_trk, fdctrl_t),
692 VMSTATE_UINT8(config, fdctrl_t),
693 VMSTATE_UINT8(lock, fdctrl_t),
694 VMSTATE_UINT8(pwrd, fdctrl_t),
695 VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t),
696 VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1,
697 vmstate_fdrive, fdrive_t),
698 VMSTATE_END_OF_LIST()
699 }
700 };
701
702 static void fdctrl_external_reset_sysbus(DeviceState *d)
703 {
704 fdctrl_sysbus_t *sys = container_of(d, fdctrl_sysbus_t, busdev.qdev);
705 fdctrl_t *s = &sys->state;
706
707 fdctrl_reset(s, 0);
708 }
709
710 static void fdctrl_external_reset_isa(DeviceState *d)
711 {
712 fdctrl_isabus_t *isa = container_of(d, fdctrl_isabus_t, busdev.qdev);
713 fdctrl_t *s = &isa->state;
714
715 fdctrl_reset(s, 0);
716 }
717
718 static void fdctrl_handle_tc(void *opaque, int irq, int level)
719 {
720 //fdctrl_t *s = opaque;
721
722 if (level) {
723 // XXX
724 FLOPPY_DPRINTF("TC pulsed\n");
725 }
726 }
727
728 /* XXX: may change if moved to bdrv */
729 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
730 {
731 return fdctrl->drives[drive_num].drive;
732 }
733
734 /* Change IRQ state */
735 static void fdctrl_reset_irq (fdctrl_t *fdctrl)
736 {
737 if (!(fdctrl->sra & FD_SRA_INTPEND))
738 return;
739 FLOPPY_DPRINTF("Reset interrupt\n");
740 qemu_set_irq(fdctrl->irq, 0);
741 fdctrl->sra &= ~FD_SRA_INTPEND;
742 }
743
744 static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
745 {
746 /* Sparc mutation */
747 if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
748 /* XXX: not sure */
749 fdctrl->msr &= ~FD_MSR_CMDBUSY;
750 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
751 fdctrl->status0 = status0;
752 return;
753 }
754 if (!(fdctrl->sra & FD_SRA_INTPEND)) {
755 qemu_set_irq(fdctrl->irq, 1);
756 fdctrl->sra |= FD_SRA_INTPEND;
757 }
758 fdctrl->reset_sensei = 0;
759 fdctrl->status0 = status0;
760 FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
761 }
762
763 /* Reset controller */
764 static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
765 {
766 int i;
767
768 FLOPPY_DPRINTF("reset controller\n");
769 fdctrl_reset_irq(fdctrl);
770 /* Initialise controller */
771 fdctrl->sra = 0;
772 fdctrl->srb = 0xc0;
773 if (!fdctrl->drives[1].bs)
774 fdctrl->sra |= FD_SRA_nDRV2;
775 fdctrl->cur_drv = 0;
776 fdctrl->dor = FD_DOR_nRESET;
777 fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
778 fdctrl->msr = FD_MSR_RQM;
779 /* FIFO state */
780 fdctrl->data_pos = 0;
781 fdctrl->data_len = 0;
782 fdctrl->data_state = 0;
783 fdctrl->data_dir = FD_DIR_WRITE;
784 for (i = 0; i < MAX_FD; i++)
785 fd_recalibrate(&fdctrl->drives[i]);
786 fdctrl_reset_fifo(fdctrl);
787 if (do_irq) {
788 fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
789 fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
790 }
791 }
792
793 static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
794 {
795 return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
796 }
797
798 static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
799 {
800 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
801 return &fdctrl->drives[1];
802 else
803 return &fdctrl->drives[0];
804 }
805
806 #if MAX_FD == 4
807 static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
808 {
809 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
810 return &fdctrl->drives[2];
811 else
812 return &fdctrl->drives[1];
813 }
814
815 static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
816 {
817 if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
818 return &fdctrl->drives[3];
819 else
820 return &fdctrl->drives[2];
821 }
822 #endif
823
824 static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
825 {
826 switch (fdctrl->cur_drv) {
827 case 0: return drv0(fdctrl);
828 case 1: return drv1(fdctrl);
829 #if MAX_FD == 4
830 case 2: return drv2(fdctrl);
831 case 3: return drv3(fdctrl);
832 #endif
833 default: return NULL;
834 }
835 }
836
837 /* Status A register : 0x00 (read-only) */
838 static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
839 {
840 uint32_t retval = fdctrl->sra;
841
842 FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
843
844 return retval;
845 }
846
847 /* Status B register : 0x01 (read-only) */
848 static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
849 {
850 uint32_t retval = fdctrl->srb;
851
852 FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
853
854 return retval;
855 }
856
857 /* Digital output register : 0x02 */
858 static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
859 {
860 uint32_t retval = fdctrl->dor;
861
862 /* Selected drive */
863 retval |= fdctrl->cur_drv;
864 FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
865
866 return retval;
867 }
868
869 static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
870 {
871 FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
872
873 /* Motors */
874 if (value & FD_DOR_MOTEN0)
875 fdctrl->srb |= FD_SRB_MTR0;
876 else
877 fdctrl->srb &= ~FD_SRB_MTR0;
878 if (value & FD_DOR_MOTEN1)
879 fdctrl->srb |= FD_SRB_MTR1;
880 else
881 fdctrl->srb &= ~FD_SRB_MTR1;
882
883 /* Drive */
884 if (value & 1)
885 fdctrl->srb |= FD_SRB_DR0;
886 else
887 fdctrl->srb &= ~FD_SRB_DR0;
888
889 /* Reset */
890 if (!(value & FD_DOR_nRESET)) {
891 if (fdctrl->dor & FD_DOR_nRESET) {
892 FLOPPY_DPRINTF("controller enter RESET state\n");
893 }
894 } else {
895 if (!(fdctrl->dor & FD_DOR_nRESET)) {
896 FLOPPY_DPRINTF("controller out of RESET state\n");
897 fdctrl_reset(fdctrl, 1);
898 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
899 }
900 }
901 /* Selected drive */
902 fdctrl->cur_drv = value & FD_DOR_SELMASK;
903
904 fdctrl->dor = value;
905 }
906
907 /* Tape drive register : 0x03 */
908 static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
909 {
910 uint32_t retval = fdctrl->tdr;
911
912 FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
913
914 return retval;
915 }
916
917 static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
918 {
919 /* Reset mode */
920 if (!(fdctrl->dor & FD_DOR_nRESET)) {
921 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
922 return;
923 }
924 FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
925 /* Disk boot selection indicator */
926 fdctrl->tdr = value & FD_TDR_BOOTSEL;
927 /* Tape indicators: never allow */
928 }
929
930 /* Main status register : 0x04 (read) */
931 static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
932 {
933 uint32_t retval = fdctrl->msr;
934
935 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
936 fdctrl->dor |= FD_DOR_nRESET;
937
938 FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
939
940 return retval;
941 }
942
943 /* Data select rate register : 0x04 (write) */
944 static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
945 {
946 /* Reset mode */
947 if (!(fdctrl->dor & FD_DOR_nRESET)) {
948 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
949 return;
950 }
951 FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
952 /* Reset: autoclear */
953 if (value & FD_DSR_SWRESET) {
954 fdctrl->dor &= ~FD_DOR_nRESET;
955 fdctrl_reset(fdctrl, 1);
956 fdctrl->dor |= FD_DOR_nRESET;
957 }
958 if (value & FD_DSR_PWRDOWN) {
959 fdctrl_reset(fdctrl, 1);
960 }
961 fdctrl->dsr = value;
962 }
963
964 static int fdctrl_media_changed(fdrive_t *drv)
965 {
966 int ret;
967
968 if (!drv->bs)
969 return 0;
970 ret = bdrv_media_changed(drv->bs);
971 if (ret) {
972 fd_revalidate(drv);
973 }
974 return ret;
975 }
976
977 /* Digital input register : 0x07 (read-only) */
978 static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
979 {
980 uint32_t retval = 0;
981
982 if (fdctrl_media_changed(drv0(fdctrl))
983 || fdctrl_media_changed(drv1(fdctrl))
984 #if MAX_FD == 4
985 || fdctrl_media_changed(drv2(fdctrl))
986 || fdctrl_media_changed(drv3(fdctrl))
987 #endif
988 )
989 retval |= FD_DIR_DSKCHG;
990 if (retval != 0)
991 FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
992
993 return retval;
994 }
995
996 /* FIFO state control */
997 static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
998 {
999 fdctrl->data_dir = FD_DIR_WRITE;
1000 fdctrl->data_pos = 0;
1001 fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
1002 }
1003
1004 /* Set FIFO status for the host to read */
1005 static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
1006 {
1007 fdctrl->data_dir = FD_DIR_READ;
1008 fdctrl->data_len = fifo_len;
1009 fdctrl->data_pos = 0;
1010 fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1011 if (do_irq)
1012 fdctrl_raise_irq(fdctrl, 0x00);
1013 }
1014
1015 /* Set an error: unimplemented/unknown command */
1016 static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1017 {
1018 FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1019 fdctrl->fifo[0] = FD_SR0_INVCMD;
1020 fdctrl_set_fifo(fdctrl, 1, 0);
1021 }
1022
1023 /* Seek to next sector */
1024 static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1025 {
1026 FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1027 cur_drv->head, cur_drv->track, cur_drv->sect,
1028 fd_sector(cur_drv));
1029 /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1030 error in fact */
1031 if (cur_drv->sect >= cur_drv->last_sect ||
1032 cur_drv->sect == fdctrl->eot) {
1033 cur_drv->sect = 1;
1034 if (FD_MULTI_TRACK(fdctrl->data_state)) {
1035 if (cur_drv->head == 0 &&
1036 (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1037 cur_drv->head = 1;
1038 } else {
1039 cur_drv->head = 0;
1040 cur_drv->track++;
1041 if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1042 return 0;
1043 }
1044 } else {
1045 cur_drv->track++;
1046 return 0;
1047 }
1048 FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1049 cur_drv->head, cur_drv->track,
1050 cur_drv->sect, fd_sector(cur_drv));
1051 } else {
1052 cur_drv->sect++;
1053 }
1054 return 1;
1055 }
1056
1057 /* Callback for transfer end (stop or abort) */
1058 static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1059 uint8_t status1, uint8_t status2)
1060 {
1061 fdrive_t *cur_drv;
1062
1063 cur_drv = get_cur_drv(fdctrl);
1064 FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1065 status0, status1, status2,
1066 status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1067 fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1068 fdctrl->fifo[1] = status1;
1069 fdctrl->fifo[2] = status2;
1070 fdctrl->fifo[3] = cur_drv->track;
1071 fdctrl->fifo[4] = cur_drv->head;
1072 fdctrl->fifo[5] = cur_drv->sect;
1073 fdctrl->fifo[6] = FD_SECTOR_SC;
1074 fdctrl->data_dir = FD_DIR_READ;
1075 if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1076 DMA_release_DREQ(fdctrl->dma_chann);
1077 }
1078 fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1079 fdctrl->msr &= ~FD_MSR_NONDMA;
1080 fdctrl_set_fifo(fdctrl, 7, 1);
1081 }
1082
1083 /* Prepare a data transfer (either DMA or FIFO) */
1084 static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1085 {
1086 fdrive_t *cur_drv;
1087 uint8_t kh, kt, ks;
1088 int did_seek = 0;
1089
1090 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1091 cur_drv = get_cur_drv(fdctrl);
1092 kt = fdctrl->fifo[2];
1093 kh = fdctrl->fifo[3];
1094 ks = fdctrl->fifo[4];
1095 FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1096 GET_CUR_DRV(fdctrl), kh, kt, ks,
1097 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1098 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1099 case 2:
1100 /* sect too big */
1101 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1102 fdctrl->fifo[3] = kt;
1103 fdctrl->fifo[4] = kh;
1104 fdctrl->fifo[5] = ks;
1105 return;
1106 case 3:
1107 /* track too big */
1108 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1109 fdctrl->fifo[3] = kt;
1110 fdctrl->fifo[4] = kh;
1111 fdctrl->fifo[5] = ks;
1112 return;
1113 case 4:
1114 /* No seek enabled */
1115 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1116 fdctrl->fifo[3] = kt;
1117 fdctrl->fifo[4] = kh;
1118 fdctrl->fifo[5] = ks;
1119 return;
1120 case 1:
1121 did_seek = 1;
1122 break;
1123 default:
1124 break;
1125 }
1126
1127 /* Set the FIFO state */
1128 fdctrl->data_dir = direction;
1129 fdctrl->data_pos = 0;
1130 fdctrl->msr |= FD_MSR_CMDBUSY;
1131 if (fdctrl->fifo[0] & 0x80)
1132 fdctrl->data_state |= FD_STATE_MULTI;
1133 else
1134 fdctrl->data_state &= ~FD_STATE_MULTI;
1135 if (did_seek)
1136 fdctrl->data_state |= FD_STATE_SEEK;
1137 else
1138 fdctrl->data_state &= ~FD_STATE_SEEK;
1139 if (fdctrl->fifo[5] == 00) {
1140 fdctrl->data_len = fdctrl->fifo[8];
1141 } else {
1142 int tmp;
1143 fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1144 tmp = (fdctrl->fifo[6] - ks + 1);
1145 if (fdctrl->fifo[0] & 0x80)
1146 tmp += fdctrl->fifo[6];
1147 fdctrl->data_len *= tmp;
1148 }
1149 fdctrl->eot = fdctrl->fifo[6];
1150 if (fdctrl->dor & FD_DOR_DMAEN) {
1151 int dma_mode;
1152 /* DMA transfer are enabled. Check if DMA channel is well programmed */
1153 dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1154 dma_mode = (dma_mode >> 2) & 3;
1155 FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1156 dma_mode, direction,
1157 (128 << fdctrl->fifo[5]) *
1158 (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1159 if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1160 direction == FD_DIR_SCANH) && dma_mode == 0) ||
1161 (direction == FD_DIR_WRITE && dma_mode == 2) ||
1162 (direction == FD_DIR_READ && dma_mode == 1)) {
1163 /* No access is allowed until DMA transfer has completed */
1164 fdctrl->msr &= ~FD_MSR_RQM;
1165 /* Now, we just have to wait for the DMA controller to
1166 * recall us...
1167 */
1168 DMA_hold_DREQ(fdctrl->dma_chann);
1169 DMA_schedule(fdctrl->dma_chann);
1170 return;
1171 } else {
1172 FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1173 }
1174 }
1175 FLOPPY_DPRINTF("start non-DMA transfer\n");
1176 fdctrl->msr |= FD_MSR_NONDMA;
1177 if (direction != FD_DIR_WRITE)
1178 fdctrl->msr |= FD_MSR_DIO;
1179 /* IO based transfer: calculate len */
1180 fdctrl_raise_irq(fdctrl, 0x00);
1181
1182 return;
1183 }
1184
1185 /* Prepare a transfer of deleted data */
1186 static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1187 {
1188 FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1189
1190 /* We don't handle deleted data,
1191 * so we don't return *ANYTHING*
1192 */
1193 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1194 }
1195
1196 /* handlers for DMA transfers */
1197 static int fdctrl_transfer_handler (void *opaque, int nchan,
1198 int dma_pos, int dma_len)
1199 {
1200 fdctrl_t *fdctrl;
1201 fdrive_t *cur_drv;
1202 int len, start_pos, rel_pos;
1203 uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1204
1205 fdctrl = opaque;
1206 if (fdctrl->msr & FD_MSR_RQM) {
1207 FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1208 return 0;
1209 }
1210 cur_drv = get_cur_drv(fdctrl);
1211 if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1212 fdctrl->data_dir == FD_DIR_SCANH)
1213 status2 = FD_SR2_SNS;
1214 if (dma_len > fdctrl->data_len)
1215 dma_len = fdctrl->data_len;
1216 if (cur_drv->bs == NULL) {
1217 if (fdctrl->data_dir == FD_DIR_WRITE)
1218 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1219 else
1220 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1221 len = 0;
1222 goto transfer_error;
1223 }
1224 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1225 for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1226 len = dma_len - fdctrl->data_pos;
1227 if (len + rel_pos > FD_SECTOR_LEN)
1228 len = FD_SECTOR_LEN - rel_pos;
1229 FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1230 "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1231 fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1232 cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1233 fd_sector(cur_drv) * FD_SECTOR_LEN);
1234 if (fdctrl->data_dir != FD_DIR_WRITE ||
1235 len < FD_SECTOR_LEN || rel_pos != 0) {
1236 /* READ & SCAN commands and realign to a sector for WRITE */
1237 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1238 fdctrl->fifo, 1) < 0) {
1239 FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1240 fd_sector(cur_drv));
1241 /* Sure, image size is too small... */
1242 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1243 }
1244 }
1245 switch (fdctrl->data_dir) {
1246 case FD_DIR_READ:
1247 /* READ commands */
1248 DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1249 fdctrl->data_pos, len);
1250 break;
1251 case FD_DIR_WRITE:
1252 /* WRITE commands */
1253 DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1254 fdctrl->data_pos, len);
1255 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1256 fdctrl->fifo, 1) < 0) {
1257 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1258 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1259 goto transfer_error;
1260 }
1261 break;
1262 default:
1263 /* SCAN commands */
1264 {
1265 uint8_t tmpbuf[FD_SECTOR_LEN];
1266 int ret;
1267 DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1268 ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1269 if (ret == 0) {
1270 status2 = FD_SR2_SEH;
1271 goto end_transfer;
1272 }
1273 if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1274 (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1275 status2 = 0x00;
1276 goto end_transfer;
1277 }
1278 }
1279 break;
1280 }
1281 fdctrl->data_pos += len;
1282 rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1283 if (rel_pos == 0) {
1284 /* Seek to next sector */
1285 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1286 break;
1287 }
1288 }
1289 end_transfer:
1290 len = fdctrl->data_pos - start_pos;
1291 FLOPPY_DPRINTF("end transfer %d %d %d\n",
1292 fdctrl->data_pos, len, fdctrl->data_len);
1293 if (fdctrl->data_dir == FD_DIR_SCANE ||
1294 fdctrl->data_dir == FD_DIR_SCANL ||
1295 fdctrl->data_dir == FD_DIR_SCANH)
1296 status2 = FD_SR2_SEH;
1297 if (FD_DID_SEEK(fdctrl->data_state))
1298 status0 |= FD_SR0_SEEK;
1299 fdctrl->data_len -= len;
1300 fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1301 transfer_error:
1302
1303 return len;
1304 }
1305
1306 /* Data register : 0x05 */
1307 static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1308 {
1309 fdrive_t *cur_drv;
1310 uint32_t retval = 0;
1311 int pos;
1312
1313 cur_drv = get_cur_drv(fdctrl);
1314 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1315 if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1316 FLOPPY_ERROR("controller not ready for reading\n");
1317 return 0;
1318 }
1319 pos = fdctrl->data_pos;
1320 if (fdctrl->msr & FD_MSR_NONDMA) {
1321 pos %= FD_SECTOR_LEN;
1322 if (pos == 0) {
1323 if (fdctrl->data_pos != 0)
1324 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1325 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1326 fd_sector(cur_drv));
1327 return 0;
1328 }
1329 if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1330 FLOPPY_DPRINTF("error getting sector %d\n",
1331 fd_sector(cur_drv));
1332 /* Sure, image size is too small... */
1333 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1334 }
1335 }
1336 }
1337 retval = fdctrl->fifo[pos];
1338 if (++fdctrl->data_pos == fdctrl->data_len) {
1339 fdctrl->data_pos = 0;
1340 /* Switch from transfer mode to status mode
1341 * then from status mode to command mode
1342 */
1343 if (fdctrl->msr & FD_MSR_NONDMA) {
1344 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1345 } else {
1346 fdctrl_reset_fifo(fdctrl);
1347 fdctrl_reset_irq(fdctrl);
1348 }
1349 }
1350 FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1351
1352 return retval;
1353 }
1354
1355 static void fdctrl_format_sector (fdctrl_t *fdctrl)
1356 {
1357 fdrive_t *cur_drv;
1358 uint8_t kh, kt, ks;
1359
1360 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1361 cur_drv = get_cur_drv(fdctrl);
1362 kt = fdctrl->fifo[6];
1363 kh = fdctrl->fifo[7];
1364 ks = fdctrl->fifo[8];
1365 FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1366 GET_CUR_DRV(fdctrl), kh, kt, ks,
1367 _fd_sector(kh, kt, ks, cur_drv->last_sect));
1368 switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1369 case 2:
1370 /* sect too big */
1371 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1372 fdctrl->fifo[3] = kt;
1373 fdctrl->fifo[4] = kh;
1374 fdctrl->fifo[5] = ks;
1375 return;
1376 case 3:
1377 /* track too big */
1378 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1379 fdctrl->fifo[3] = kt;
1380 fdctrl->fifo[4] = kh;
1381 fdctrl->fifo[5] = ks;
1382 return;
1383 case 4:
1384 /* No seek enabled */
1385 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1386 fdctrl->fifo[3] = kt;
1387 fdctrl->fifo[4] = kh;
1388 fdctrl->fifo[5] = ks;
1389 return;
1390 case 1:
1391 fdctrl->data_state |= FD_STATE_SEEK;
1392 break;
1393 default:
1394 break;
1395 }
1396 memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1397 if (cur_drv->bs == NULL ||
1398 bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1399 FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1400 fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1401 } else {
1402 if (cur_drv->sect == cur_drv->last_sect) {
1403 fdctrl->data_state &= ~FD_STATE_FORMAT;
1404 /* Last sector done */
1405 if (FD_DID_SEEK(fdctrl->data_state))
1406 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1407 else
1408 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1409 } else {
1410 /* More to do */
1411 fdctrl->data_pos = 0;
1412 fdctrl->data_len = 4;
1413 }
1414 }
1415 }
1416
1417 static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1418 {
1419 fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1420 fdctrl->fifo[0] = fdctrl->lock << 4;
1421 fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1422 }
1423
1424 static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1425 {
1426 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1427
1428 /* Drives position */
1429 fdctrl->fifo[0] = drv0(fdctrl)->track;
1430 fdctrl->fifo[1] = drv1(fdctrl)->track;
1431 #if MAX_FD == 4
1432 fdctrl->fifo[2] = drv2(fdctrl)->track;
1433 fdctrl->fifo[3] = drv3(fdctrl)->track;
1434 #else
1435 fdctrl->fifo[2] = 0;
1436 fdctrl->fifo[3] = 0;
1437 #endif
1438 /* timers */
1439 fdctrl->fifo[4] = fdctrl->timer0;
1440 fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1441 fdctrl->fifo[6] = cur_drv->last_sect;
1442 fdctrl->fifo[7] = (fdctrl->lock << 7) |
1443 (cur_drv->perpendicular << 2);
1444 fdctrl->fifo[8] = fdctrl->config;
1445 fdctrl->fifo[9] = fdctrl->precomp_trk;
1446 fdctrl_set_fifo(fdctrl, 10, 0);
1447 }
1448
1449 static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1450 {
1451 /* Controller's version */
1452 fdctrl->fifo[0] = fdctrl->version;
1453 fdctrl_set_fifo(fdctrl, 1, 1);
1454 }
1455
1456 static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1457 {
1458 fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1459 fdctrl_set_fifo(fdctrl, 1, 0);
1460 }
1461
1462 static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1463 {
1464 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1465
1466 /* Drives position */
1467 drv0(fdctrl)->track = fdctrl->fifo[3];
1468 drv1(fdctrl)->track = fdctrl->fifo[4];
1469 #if MAX_FD == 4
1470 drv2(fdctrl)->track = fdctrl->fifo[5];
1471 drv3(fdctrl)->track = fdctrl->fifo[6];
1472 #endif
1473 /* timers */
1474 fdctrl->timer0 = fdctrl->fifo[7];
1475 fdctrl->timer1 = fdctrl->fifo[8];
1476 cur_drv->last_sect = fdctrl->fifo[9];
1477 fdctrl->lock = fdctrl->fifo[10] >> 7;
1478 cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1479 fdctrl->config = fdctrl->fifo[11];
1480 fdctrl->precomp_trk = fdctrl->fifo[12];
1481 fdctrl->pwrd = fdctrl->fifo[13];
1482 fdctrl_reset_fifo(fdctrl);
1483 }
1484
1485 static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1486 {
1487 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1488
1489 fdctrl->fifo[0] = 0;
1490 fdctrl->fifo[1] = 0;
1491 /* Drives position */
1492 fdctrl->fifo[2] = drv0(fdctrl)->track;
1493 fdctrl->fifo[3] = drv1(fdctrl)->track;
1494 #if MAX_FD == 4
1495 fdctrl->fifo[4] = drv2(fdctrl)->track;
1496 fdctrl->fifo[5] = drv3(fdctrl)->track;
1497 #else
1498 fdctrl->fifo[4] = 0;
1499 fdctrl->fifo[5] = 0;
1500 #endif
1501 /* timers */
1502 fdctrl->fifo[6] = fdctrl->timer0;
1503 fdctrl->fifo[7] = fdctrl->timer1;
1504 fdctrl->fifo[8] = cur_drv->last_sect;
1505 fdctrl->fifo[9] = (fdctrl->lock << 7) |
1506 (cur_drv->perpendicular << 2);
1507 fdctrl->fifo[10] = fdctrl->config;
1508 fdctrl->fifo[11] = fdctrl->precomp_trk;
1509 fdctrl->fifo[12] = fdctrl->pwrd;
1510 fdctrl->fifo[13] = 0;
1511 fdctrl->fifo[14] = 0;
1512 fdctrl_set_fifo(fdctrl, 15, 1);
1513 }
1514
1515 static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1516 {
1517 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1518
1519 /* XXX: should set main status register to busy */
1520 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1521 qemu_mod_timer(fdctrl->result_timer,
1522 qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
1523 }
1524
1525 static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1526 {
1527 fdrive_t *cur_drv;
1528
1529 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1530 cur_drv = get_cur_drv(fdctrl);
1531 fdctrl->data_state |= FD_STATE_FORMAT;
1532 if (fdctrl->fifo[0] & 0x80)
1533 fdctrl->data_state |= FD_STATE_MULTI;
1534 else
1535 fdctrl->data_state &= ~FD_STATE_MULTI;
1536 fdctrl->data_state &= ~FD_STATE_SEEK;
1537 cur_drv->bps =
1538 fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1539 #if 0
1540 cur_drv->last_sect =
1541 cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1542 fdctrl->fifo[3] / 2;
1543 #else
1544 cur_drv->last_sect = fdctrl->fifo[3];
1545 #endif
1546 /* TODO: implement format using DMA expected by the Bochs BIOS
1547 * and Linux fdformat (read 3 bytes per sector via DMA and fill
1548 * the sector with the specified fill byte
1549 */
1550 fdctrl->data_state &= ~FD_STATE_FORMAT;
1551 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1552 }
1553
1554 static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1555 {
1556 fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1557 fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1558 if (fdctrl->fifo[2] & 1)
1559 fdctrl->dor &= ~FD_DOR_DMAEN;
1560 else
1561 fdctrl->dor |= FD_DOR_DMAEN;
1562 /* No result back */
1563 fdctrl_reset_fifo(fdctrl);
1564 }
1565
1566 static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1567 {
1568 fdrive_t *cur_drv;
1569
1570 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1571 cur_drv = get_cur_drv(fdctrl);
1572 cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1573 /* 1 Byte status back */
1574 fdctrl->fifo[0] = (cur_drv->ro << 6) |
1575 (cur_drv->track == 0 ? 0x10 : 0x00) |
1576 (cur_drv->head << 2) |
1577 GET_CUR_DRV(fdctrl) |
1578 0x28;
1579 fdctrl_set_fifo(fdctrl, 1, 0);
1580 }
1581
1582 static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1583 {
1584 fdrive_t *cur_drv;
1585
1586 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1587 cur_drv = get_cur_drv(fdctrl);
1588 fd_recalibrate(cur_drv);
1589 fdctrl_reset_fifo(fdctrl);
1590 /* Raise Interrupt */
1591 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1592 }
1593
1594 static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1595 {
1596 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1597
1598 if(fdctrl->reset_sensei > 0) {
1599 fdctrl->fifo[0] =
1600 FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1601 fdctrl->reset_sensei--;
1602 } else {
1603 /* XXX: status0 handling is broken for read/write
1604 commands, so we do this hack. It should be suppressed
1605 ASAP */
1606 fdctrl->fifo[0] =
1607 FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1608 }
1609
1610 fdctrl->fifo[1] = cur_drv->track;
1611 fdctrl_set_fifo(fdctrl, 2, 0);
1612 fdctrl_reset_irq(fdctrl);
1613 fdctrl->status0 = FD_SR0_RDYCHG;
1614 }
1615
1616 static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1617 {
1618 fdrive_t *cur_drv;
1619
1620 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1621 cur_drv = get_cur_drv(fdctrl);
1622 fdctrl_reset_fifo(fdctrl);
1623 if (fdctrl->fifo[2] > cur_drv->max_track) {
1624 fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1625 } else {
1626 cur_drv->track = fdctrl->fifo[2];
1627 /* Raise Interrupt */
1628 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1629 }
1630 }
1631
1632 static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1633 {
1634 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1635
1636 if (fdctrl->fifo[1] & 0x80)
1637 cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1638 /* No result back */
1639 fdctrl_reset_fifo(fdctrl);
1640 }
1641
1642 static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1643 {
1644 fdctrl->config = fdctrl->fifo[2];
1645 fdctrl->precomp_trk = fdctrl->fifo[3];
1646 /* No result back */
1647 fdctrl_reset_fifo(fdctrl);
1648 }
1649
1650 static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1651 {
1652 fdctrl->pwrd = fdctrl->fifo[1];
1653 fdctrl->fifo[0] = fdctrl->fifo[1];
1654 fdctrl_set_fifo(fdctrl, 1, 1);
1655 }
1656
1657 static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1658 {
1659 /* No result back */
1660 fdctrl_reset_fifo(fdctrl);
1661 }
1662
1663 static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1664 {
1665 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1666
1667 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1668 /* Command parameters done */
1669 if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1670 fdctrl->fifo[0] = fdctrl->fifo[1];
1671 fdctrl->fifo[2] = 0;
1672 fdctrl->fifo[3] = 0;
1673 fdctrl_set_fifo(fdctrl, 4, 1);
1674 } else {
1675 fdctrl_reset_fifo(fdctrl);
1676 }
1677 } else if (fdctrl->data_len > 7) {
1678 /* ERROR */
1679 fdctrl->fifo[0] = 0x80 |
1680 (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1681 fdctrl_set_fifo(fdctrl, 1, 1);
1682 }
1683 }
1684
1685 static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1686 {
1687 fdrive_t *cur_drv;
1688
1689 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1690 cur_drv = get_cur_drv(fdctrl);
1691 if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1692 cur_drv->track = cur_drv->max_track - 1;
1693 } else {
1694 cur_drv->track += fdctrl->fifo[2];
1695 }
1696 fdctrl_reset_fifo(fdctrl);
1697 /* Raise Interrupt */
1698 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1699 }
1700
1701 static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1702 {
1703 fdrive_t *cur_drv;
1704
1705 SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1706 cur_drv = get_cur_drv(fdctrl);
1707 if (fdctrl->fifo[2] > cur_drv->track) {
1708 cur_drv->track = 0;
1709 } else {
1710 cur_drv->track -= fdctrl->fifo[2];
1711 }
1712 fdctrl_reset_fifo(fdctrl);
1713 /* Raise Interrupt */
1714 fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1715 }
1716
1717 static const struct {
1718 uint8_t value;
1719 uint8_t mask;
1720 const char* name;
1721 int parameters;
1722 void (*handler)(fdctrl_t *fdctrl, int direction);
1723 int direction;
1724 } handlers[] = {
1725 { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1726 { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1727 { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1728 { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1729 { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1730 { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1731 { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1732 { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1733 { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1734 { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1735 { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1736 { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1737 { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1738 { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1739 { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1740 { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1741 { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1742 { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1743 { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1744 { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1745 { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1746 { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1747 { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1748 { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1749 { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1750 { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1751 { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1752 { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1753 { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1754 { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1755 { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1756 { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1757 };
1758 /* Associate command to an index in the 'handlers' array */
1759 static uint8_t command_to_handler[256];
1760
1761 static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1762 {
1763 fdrive_t *cur_drv;
1764 int pos;
1765
1766 /* Reset mode */
1767 if (!(fdctrl->dor & FD_DOR_nRESET)) {
1768 FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1769 return;
1770 }
1771 if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1772 FLOPPY_ERROR("controller not ready for writing\n");
1773 return;
1774 }
1775 fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1776 /* Is it write command time ? */
1777 if (fdctrl->msr & FD_MSR_NONDMA) {
1778 /* FIFO data write */
1779 pos = fdctrl->data_pos++;
1780 pos %= FD_SECTOR_LEN;
1781 fdctrl->fifo[pos] = value;
1782 if (pos == FD_SECTOR_LEN - 1 ||
1783 fdctrl->data_pos == fdctrl->data_len) {
1784 cur_drv = get_cur_drv(fdctrl);
1785 if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1786 FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1787 return;
1788 }
1789 if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1790 FLOPPY_DPRINTF("error seeking to next sector %d\n",
1791 fd_sector(cur_drv));
1792 return;
1793 }
1794 }
1795 /* Switch from transfer mode to status mode
1796 * then from status mode to command mode
1797 */
1798 if (fdctrl->data_pos == fdctrl->data_len)
1799 fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1800 return;
1801 }
1802 if (fdctrl->data_pos == 0) {
1803 /* Command */
1804 pos = command_to_handler[value & 0xff];
1805 FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1806 fdctrl->data_len = handlers[pos].parameters + 1;
1807 }
1808
1809 FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1810 fdctrl->fifo[fdctrl->data_pos++] = value;
1811 if (fdctrl->data_pos == fdctrl->data_len) {
1812 /* We now have all parameters
1813 * and will be able to treat the command
1814 */
1815 if (fdctrl->data_state & FD_STATE_FORMAT) {
1816 fdctrl_format_sector(fdctrl);
1817 return;
1818 }
1819
1820 pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1821 FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1822 (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1823 }
1824 }
1825
1826 static void fdctrl_result_timer(void *opaque)
1827 {
1828 fdctrl_t *fdctrl = opaque;
1829 fdrive_t *cur_drv = get_cur_drv(fdctrl);
1830
1831 /* Pretend we are spinning.
1832 * This is needed for Coherent, which uses READ ID to check for
1833 * sector interleaving.
1834 */
1835 if (cur_drv->last_sect != 0) {
1836 cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1837 }
1838 fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1839 }
1840
1841 /* Init functions */
1842 static void fdctrl_connect_drives(fdctrl_t *fdctrl)
1843 {
1844 unsigned int i;
1845
1846 for (i = 0; i < MAX_FD; i++) {
1847 fd_init(&fdctrl->drives[i]);
1848 fd_revalidate(&fdctrl->drives[i]);
1849 }
1850 }
1851
1852 fdctrl_t *fdctrl_init_isa(DriveInfo **fds)
1853 {
1854 ISADevice *dev;
1855
1856 dev = isa_create("isa-fdc");
1857 qdev_prop_set_drive(&dev->qdev, "driveA", fds[0]);
1858 qdev_prop_set_drive(&dev->qdev, "driveB", fds[1]);
1859 if (qdev_init(&dev->qdev) < 0)
1860 return NULL;
1861 return &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state);
1862 }
1863
1864 fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1865 target_phys_addr_t mmio_base,
1866 DriveInfo **fds)
1867 {
1868 fdctrl_t *fdctrl;
1869 DeviceState *dev;
1870 fdctrl_sysbus_t *sys;
1871
1872 dev = qdev_create(NULL, "sysbus-fdc");
1873 sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1874 fdctrl = &sys->state;
1875 fdctrl->dma_chann = dma_chann; /* FIXME */
1876 qdev_prop_set_drive(dev, "driveA", fds[0]);
1877 qdev_prop_set_drive(dev, "driveB", fds[1]);
1878 qdev_init_nofail(dev);
1879 sysbus_connect_irq(&sys->busdev, 0, irq);
1880 sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1881
1882 return fdctrl;
1883 }
1884
1885 fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1886 DriveInfo **fds, qemu_irq *fdc_tc)
1887 {
1888 DeviceState *dev;
1889 fdctrl_sysbus_t *sys;
1890 fdctrl_t *fdctrl;
1891
1892 dev = qdev_create(NULL, "SUNW,fdtwo");
1893 qdev_prop_set_drive(dev, "drive", fds[0]);
1894 qdev_init_nofail(dev);
1895 sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1896 fdctrl = &sys->state;
1897 sysbus_connect_irq(&sys->busdev, 0, irq);
1898 sysbus_mmio_map(&sys->busdev, 0, io_base);
1899 *fdc_tc = qdev_get_gpio_in(dev, 0);
1900
1901 return fdctrl;
1902 }
1903
1904 static int fdctrl_init_common(fdctrl_t *fdctrl)
1905 {
1906 int i, j;
1907 static int command_tables_inited = 0;
1908
1909 /* Fill 'command_to_handler' lookup table */
1910 if (!command_tables_inited) {
1911 command_tables_inited = 1;
1912 for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1913 for (j = 0; j < sizeof(command_to_handler); j++) {
1914 if ((j & handlers[i].mask) == handlers[i].value) {
1915 command_to_handler[j] = i;
1916 }
1917 }
1918 }
1919 }
1920
1921 FLOPPY_DPRINTF("init controller\n");
1922 fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1923 fdctrl->fifo_size = 512;
1924 fdctrl->result_timer = qemu_new_timer(vm_clock,
1925 fdctrl_result_timer, fdctrl);
1926
1927 fdctrl->version = 0x90; /* Intel 82078 controller */
1928 fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1929 fdctrl->num_floppies = MAX_FD;
1930
1931 if (fdctrl->dma_chann != -1)
1932 DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl);
1933 fdctrl_connect_drives(fdctrl);
1934
1935 return 0;
1936 }
1937
1938 static int isabus_fdc_init1(ISADevice *dev)
1939 {
1940 fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev);
1941 fdctrl_t *fdctrl = &isa->state;
1942 int iobase = 0x3f0;
1943 int isairq = 6;
1944 int dma_chann = 2;
1945 int ret;
1946
1947 register_ioport_read(iobase + 0x01, 5, 1,
1948 &fdctrl_read_port, fdctrl);
1949 register_ioport_read(iobase + 0x07, 1, 1,
1950 &fdctrl_read_port, fdctrl);
1951 register_ioport_write(iobase + 0x01, 5, 1,
1952 &fdctrl_write_port, fdctrl);
1953 register_ioport_write(iobase + 0x07, 1, 1,
1954 &fdctrl_write_port, fdctrl);
1955 isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1956 fdctrl->dma_chann = dma_chann;
1957
1958 ret = fdctrl_init_common(fdctrl);
1959 fdctrl_external_reset_isa(&isa->busdev.qdev);
1960
1961 return ret;
1962 }
1963
1964 static int sysbus_fdc_init1(SysBusDevice *dev)
1965 {
1966 fdctrl_sysbus_t *sys = DO_UPCAST(fdctrl_sysbus_t, busdev, dev);
1967 fdctrl_t *fdctrl = &sys->state;
1968 int io;
1969 int ret;
1970
1971 io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
1972 sysbus_init_mmio(dev, 0x08, io);
1973 sysbus_init_irq(dev, &fdctrl->irq);
1974 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1975 fdctrl->dma_chann = -1;
1976
1977 ret = fdctrl_init_common(fdctrl);
1978 fdctrl_external_reset_sysbus(&sys->busdev.qdev);
1979
1980 return ret;
1981 }
1982
1983 static int sun4m_fdc_init1(SysBusDevice *dev)
1984 {
1985 fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
1986 int io;
1987
1988 io = cpu_register_io_memory(fdctrl_mem_read_strict,
1989 fdctrl_mem_write_strict, fdctrl);
1990 sysbus_init_mmio(dev, 0x08, io);
1991 sysbus_init_irq(dev, &fdctrl->irq);
1992 qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1993
1994 fdctrl->sun4m = 1;
1995 return fdctrl_init_common(fdctrl);
1996 }
1997
1998 static ISADeviceInfo isa_fdc_info = {
1999 .init = isabus_fdc_init1,
2000 .qdev.name = "isa-fdc",
2001 .qdev.size = sizeof(fdctrl_isabus_t),
2002 .qdev.vmsd = &vmstate_fdc,
2003 .qdev.reset = fdctrl_external_reset_isa,
2004 .qdev.props = (Property[]) {
2005 DEFINE_PROP_DRIVE("driveA", fdctrl_isabus_t, state.drives[0].dinfo),
2006 DEFINE_PROP_DRIVE("driveB", fdctrl_isabus_t, state.drives[1].dinfo),
2007 DEFINE_PROP_END_OF_LIST(),
2008 },
2009 };
2010
2011 static SysBusDeviceInfo sysbus_fdc_info = {
2012 .init = sysbus_fdc_init1,
2013 .qdev.name = "sysbus-fdc",
2014 .qdev.size = sizeof(fdctrl_sysbus_t),
2015 .qdev.vmsd = &vmstate_fdc,
2016 .qdev.reset = fdctrl_external_reset_sysbus,
2017 .qdev.props = (Property[]) {
2018 DEFINE_PROP_DRIVE("driveA", fdctrl_sysbus_t, state.drives[0].dinfo),
2019 DEFINE_PROP_DRIVE("driveB", fdctrl_sysbus_t, state.drives[1].dinfo),
2020 DEFINE_PROP_END_OF_LIST(),
2021 },
2022 };
2023
2024 static SysBusDeviceInfo sun4m_fdc_info = {
2025 .init = sun4m_fdc_init1,
2026 .qdev.name = "SUNW,fdtwo",
2027 .qdev.size = sizeof(fdctrl_sysbus_t),
2028 .qdev.vmsd = &vmstate_fdc,
2029 .qdev.reset = fdctrl_external_reset_sysbus,
2030 .qdev.props = (Property[]) {
2031 DEFINE_PROP_DRIVE("drive", fdctrl_sysbus_t, state.drives[0].dinfo),
2032 DEFINE_PROP_END_OF_LIST(),
2033 },
2034 };
2035
2036 static void fdc_register_devices(void)
2037 {
2038 isa_qdev_register(&isa_fdc_info);
2039 sysbus_register_withprop(&sysbus_fdc_info);
2040 sysbus_register_withprop(&sun4m_fdc_info);
2041 }
2042
2043 device_init(fdc_register_devices)
QEmu