2 * Q35 chipset based pc system emulator
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 * Copyright (c) 2009, 2010
6 * Isaku Yamahata <yamahata at valinux co jp>
7 * VA Linux Systems Japan K.K.
8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
10 * This is based on pc.c, but heavily modified.
12 * Permission is hereby granted, free of charge, to any person obtaining a copy
13 * of this software and associated documentation files (the "Software"), to deal
14 * in the Software without restriction, including without limitation the rights
15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16 * copies of the Software, and to permit persons to whom the Software is
17 * furnished to do so, subject to the following conditions:
19 * The above copyright notice and this permission notice shall be included in
20 * all copies or substantial portions of the Software.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "sysemu/arch_init.h"
32 #include "hw/i2c/smbus.h"
33 #include "hw/boards.h"
34 #include "hw/timer/mc146818rtc.h"
35 #include "hw/xen/xen.h"
36 #include "sysemu/kvm.h"
37 #include "hw/kvm/clock.h"
38 #include "hw/pci-host/q35.h"
39 #include "exec/address-spaces.h"
40 #include "hw/i386/ich9.h"
41 #include "hw/ide/pci.h"
42 #include "hw/ide/ahci.h"
44 #include "hw/cpu/icc_bus.h"
46 /* ICH9 AHCI has 6 ports */
47 #define MAX_SATA_PORTS 6
49 static bool has_pvpanic
= true;
50 static bool has_pci_info
= true;
52 /* PC hardware initialisation */
53 static void pc_q35_init(QEMUMachineInitArgs
*args
)
55 ram_addr_t ram_size
= args
->ram_size
;
56 const char *cpu_model
= args
->cpu_model
;
57 const char *kernel_filename
= args
->kernel_filename
;
58 const char *kernel_cmdline
= args
->kernel_cmdline
;
59 const char *initrd_filename
= args
->initrd_filename
;
60 const char *boot_device
= args
->boot_device
;
61 ram_addr_t below_4g_mem_size
, above_4g_mem_size
;
65 BusState
*idebus
[MAX_SATA_PORTS
];
68 MemoryRegion
*pci_memory
;
69 MemoryRegion
*rom_memory
;
70 MemoryRegion
*ram_memory
;
78 ICH9LPCState
*ich9_lpc
;
80 DeviceState
*icc_bridge
;
81 PcGuestInfo
*guest_info
;
83 icc_bridge
= qdev_create(NULL
, TYPE_ICC_BRIDGE
);
84 object_property_add_child(qdev_get_machine(), "icc-bridge",
85 OBJECT(icc_bridge
), NULL
);
87 pc_cpus_init(cpu_model
, icc_bridge
);
88 pc_acpi_init("q35-acpi-dsdt.aml");
92 if (ram_size
>= 0xb0000000) {
93 above_4g_mem_size
= ram_size
- 0xb0000000;
94 below_4g_mem_size
= 0xb0000000;
96 above_4g_mem_size
= 0;
97 below_4g_mem_size
= ram_size
;
102 pci_memory
= g_new(MemoryRegion
, 1);
103 memory_region_init(pci_memory
, NULL
, "pci", INT64_MAX
);
104 rom_memory
= pci_memory
;
107 rom_memory
= get_system_memory();
110 guest_info
= pc_guest_info_init(below_4g_mem_size
, above_4g_mem_size
);
111 guest_info
->has_pci_info
= has_pci_info
;
113 /* allocate ram and load rom/bios */
114 if (!xen_enabled()) {
115 pc_memory_init(get_system_memory(), kernel_filename
, kernel_cmdline
,
116 initrd_filename
, below_4g_mem_size
, above_4g_mem_size
,
117 rom_memory
, &ram_memory
, guest_info
);
121 gsi_state
= g_malloc0(sizeof(*gsi_state
));
122 if (kvm_irqchip_in_kernel()) {
123 kvm_pc_setup_irq_routing(pci_enabled
);
124 gsi
= qemu_allocate_irqs(kvm_pc_gsi_handler
, gsi_state
,
127 gsi
= qemu_allocate_irqs(gsi_handler
, gsi_state
, GSI_NUM_PINS
);
130 /* create pci host bus */
131 q35_host
= Q35_HOST_DEVICE(qdev_create(NULL
, TYPE_Q35_HOST_DEVICE
));
133 q35_host
->mch
.ram_memory
= ram_memory
;
134 q35_host
->mch
.pci_address_space
= pci_memory
;
135 q35_host
->mch
.system_memory
= get_system_memory();
136 q35_host
->mch
.address_space_io
= get_system_io();
137 q35_host
->mch
.below_4g_mem_size
= below_4g_mem_size
;
138 q35_host
->mch
.above_4g_mem_size
= above_4g_mem_size
;
139 q35_host
->mch
.guest_info
= guest_info
;
141 qdev_init_nofail(DEVICE(q35_host
));
142 host_bus
= q35_host
->host
.pci
.bus
;
144 lpc
= pci_create_simple_multifunction(host_bus
, PCI_DEVFN(ICH9_LPC_DEV
,
145 ICH9_LPC_FUNC
), true,
146 TYPE_ICH9_LPC_DEVICE
);
147 ich9_lpc
= ICH9_LPC_DEVICE(lpc
);
149 ich9_lpc
->ioapic
= gsi_state
->ioapic_irq
;
150 pci_bus_irqs(host_bus
, ich9_lpc_set_irq
, ich9_lpc_map_irq
, ich9_lpc
,
152 pci_bus_set_route_irq_fn(host_bus
, ich9_route_intx_pin_to_irq
);
153 isa_bus
= ich9_lpc
->isa_bus
;
156 isa_bus_irqs(isa_bus
, gsi
);
158 if (kvm_irqchip_in_kernel()) {
159 i8259
= kvm_i8259_init(isa_bus
);
160 } else if (xen_enabled()) {
161 i8259
= xen_interrupt_controller_init();
163 cpu_irq
= pc_allocate_cpu_irq();
164 i8259
= i8259_init(isa_bus
, cpu_irq
[0]);
167 for (i
= 0; i
< ISA_NUM_IRQS
; i
++) {
168 gsi_state
->i8259_irq
[i
] = i8259
[i
];
171 ioapic_init_gsi(gsi_state
, NULL
);
173 qdev_init_nofail(icc_bridge
);
175 pc_register_ferr_irq(gsi
[13]);
177 /* init basic PC hardware */
178 pc_basic_device_init(isa_bus
, gsi
, &rtc_state
, &floppy
, false);
180 /* connect pm stuff to lpc */
181 ich9_lpc_pm_init(lpc
);
183 /* ahci and SATA device, for q35 1 ahci controller is built-in */
184 ahci
= pci_create_simple_multifunction(host_bus
,
185 PCI_DEVFN(ICH9_SATA1_DEV
,
188 idebus
[0] = qdev_get_child_bus(&ahci
->qdev
, "ide.0");
189 idebus
[1] = qdev_get_child_bus(&ahci
->qdev
, "ide.1");
191 if (usb_enabled(false)) {
192 /* Should we create 6 UHCI according to ich9 spec? */
193 ehci_create_ich9_with_companions(host_bus
, 0x1d);
196 /* TODO: Populate SPD eeprom data. */
197 smbus_eeprom_init(ich9_smb_init(host_bus
,
198 PCI_DEVFN(ICH9_SMB_DEV
, ICH9_SMB_FUNC
),
202 pc_cmos_init(below_4g_mem_size
, above_4g_mem_size
, boot_device
,
203 floppy
, idebus
[0], idebus
[1], rtc_state
);
205 /* the rest devices to which pci devfn is automatically assigned */
206 pc_vga_init(isa_bus
, host_bus
);
207 pc_nic_init(isa_bus
, host_bus
);
209 pc_pci_device_init(host_bus
);
213 pvpanic_init(isa_bus
);
217 static void pc_q35_init_1_5(QEMUMachineInitArgs
*args
)
219 has_pci_info
= false;
223 static void pc_q35_init_1_4(QEMUMachineInitArgs
*args
)
226 x86_cpu_compat_set_features("n270", FEAT_1_ECX
, 0, CPUID_EXT_MOVBE
);
227 pc_q35_init_1_5(args
);
230 static QEMUMachine pc_q35_machine_v1_6
= {
231 .name
= "pc-q35-1.6",
233 .desc
= "Standard PC (Q35 + ICH9, 2009)",
235 .hot_add_cpu
= pc_hot_add_cpu
,
237 DEFAULT_MACHINE_OPTIONS
,
240 static QEMUMachine pc_q35_machine_v1_5
= {
241 .name
= "pc-q35-1.5",
242 .desc
= "Standard PC (Q35 + ICH9, 2009)",
243 .init
= pc_q35_init_1_5
,
244 .hot_add_cpu
= pc_hot_add_cpu
,
246 .compat_props
= (GlobalProperty
[]) {
248 { /* end of list */ }
250 DEFAULT_MACHINE_OPTIONS
,
253 static QEMUMachine pc_q35_machine_v1_4
= {
254 .name
= "pc-q35-1.4",
255 .desc
= "Standard PC (Q35 + ICH9, 2009)",
256 .init
= pc_q35_init_1_4
,
258 .compat_props
= (GlobalProperty
[]) {
260 { /* end of list */ }
262 DEFAULT_MACHINE_OPTIONS
,
265 static void pc_q35_machine_init(void)
267 qemu_register_machine(&pc_q35_machine_v1_6
);
268 qemu_register_machine(&pc_q35_machine_v1_5
);
269 qemu_register_machine(&pc_q35_machine_v1_4
);
272 machine_init(pc_q35_machine_init
);