2 * StrongARM SA-1100/SA-1110 emulation
4 * Copyright (C) 2011 Dmitry Eremin-Solenikov
6 * Largely based on StrongARM emulation:
7 * Copyright (c) 2006 Openedhand Ltd.
8 * Written by Andrzej Zaborowski <balrog@zabor.org>
10 * UART code based on QEMU 16550A UART emulation
11 * Copyright (c) 2003-2004 Fabrice Bellard
12 * Copyright (c) 2008 Citrix Systems, Inc.
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
23 * You should have received a copy of the GNU General Public License along
24 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Contributions after 2012-01-13 are licensed under the terms of the
27 * GNU GPL, version 2 or (at your option) any later version.
30 #include "strongarm.h"
31 #include "qemu-error.h"
40 - Implement cp15, c14 ?
41 - Implement cp15, c15 !!! (idle used in L)
42 - Implement idle mode handling/DIM
43 - Implement sleep mode/Wake sources
44 - Implement reset control
45 - Implement memory control regs
47 - Maybe support MBGNT/MBREQ
52 - Enhance UART with modem signals
56 # define DPRINTF(format, ...) printf(format , ## __VA_ARGS__)
58 # define DPRINTF(format, ...) do { } while (0)
62 target_phys_addr_t io_base
;
65 { 0x80010000, SA_PIC_UART1
},
66 { 0x80030000, SA_PIC_UART2
},
67 { 0x80050000, SA_PIC_UART3
},
71 /* Interrupt Controller */
91 #define SA_PIC_SRCS 32
94 static void strongarm_pic_update(void *opaque
)
96 StrongARMPICState
*s
= opaque
;
98 /* FIXME: reflect DIM */
99 qemu_set_irq(s
->fiq
, s
->pending
& s
->enabled
& s
->is_fiq
);
100 qemu_set_irq(s
->irq
, s
->pending
& s
->enabled
& ~s
->is_fiq
);
103 static void strongarm_pic_set_irq(void *opaque
, int irq
, int level
)
105 StrongARMPICState
*s
= opaque
;
108 s
->pending
|= 1 << irq
;
110 s
->pending
&= ~(1 << irq
);
113 strongarm_pic_update(s
);
116 static uint64_t strongarm_pic_mem_read(void *opaque
, target_phys_addr_t offset
,
119 StrongARMPICState
*s
= opaque
;
123 return s
->pending
& ~s
->is_fiq
& s
->enabled
;
129 return s
->int_idle
== 0;
131 return s
->pending
& s
->is_fiq
& s
->enabled
;
135 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
141 static void strongarm_pic_mem_write(void *opaque
, target_phys_addr_t offset
,
142 uint64_t value
, unsigned size
)
144 StrongARMPICState
*s
= opaque
;
154 s
->int_idle
= (value
& 1) ? 0 : ~0;
157 printf("%s: Bad register offset 0x" TARGET_FMT_plx
"\n",
161 strongarm_pic_update(s
);
164 static const MemoryRegionOps strongarm_pic_ops
= {
165 .read
= strongarm_pic_mem_read
,
166 .write
= strongarm_pic_mem_write
,
167 .endianness
= DEVICE_NATIVE_ENDIAN
,
170 static int strongarm_pic_initfn(SysBusDevice
*dev
)
172 StrongARMPICState
*s
= FROM_SYSBUS(StrongARMPICState
, dev
);
174 qdev_init_gpio_in(&dev
->qdev
, strongarm_pic_set_irq
, SA_PIC_SRCS
);
175 memory_region_init_io(&s
->iomem
, &strongarm_pic_ops
, s
, "pic", 0x1000);
176 sysbus_init_mmio(dev
, &s
->iomem
);
177 sysbus_init_irq(dev
, &s
->irq
);
178 sysbus_init_irq(dev
, &s
->fiq
);
183 static int strongarm_pic_post_load(void *opaque
, int version_id
)
185 strongarm_pic_update(opaque
);
189 static VMStateDescription vmstate_strongarm_pic_regs
= {
190 .name
= "strongarm_pic",
192 .minimum_version_id
= 0,
193 .minimum_version_id_old
= 0,
194 .post_load
= strongarm_pic_post_load
,
195 .fields
= (VMStateField
[]) {
196 VMSTATE_UINT32(pending
, StrongARMPICState
),
197 VMSTATE_UINT32(enabled
, StrongARMPICState
),
198 VMSTATE_UINT32(is_fiq
, StrongARMPICState
),
199 VMSTATE_UINT32(int_idle
, StrongARMPICState
),
200 VMSTATE_END_OF_LIST(),
204 static SysBusDeviceInfo strongarm_pic_info
= {
205 .init
= strongarm_pic_initfn
,
206 .qdev
.name
= "strongarm_pic",
207 .qdev
.desc
= "StrongARM PIC",
208 .qdev
.size
= sizeof(StrongARMPICState
),
209 .qdev
.vmsd
= &vmstate_strongarm_pic_regs
,
212 /* Real-Time Clock */
213 #define RTAR 0x00 /* RTC Alarm register */
214 #define RCNR 0x04 /* RTC Counter register */
215 #define RTTR 0x08 /* RTC Timer Trim register */
216 #define RTSR 0x10 /* RTC Status register */
218 #define RTSR_AL (1 << 0) /* RTC Alarm detected */
219 #define RTSR_HZ (1 << 1) /* RTC 1Hz detected */
220 #define RTSR_ALE (1 << 2) /* RTC Alarm enable */
221 #define RTSR_HZE (1 << 3) /* RTC 1Hz enable */
223 /* 16 LSB of RTTR are clockdiv for internal trim logic,
224 * trim delete isn't emulated, so
225 * f = 32 768 / (RTTR_trim + 1) */
235 QEMUTimer
*rtc_alarm
;
241 static inline void strongarm_rtc_int_update(StrongARMRTCState
*s
)
243 qemu_set_irq(s
->rtc_irq
, s
->rtsr
& RTSR_AL
);
244 qemu_set_irq(s
->rtc_hz_irq
, s
->rtsr
& RTSR_HZ
);
247 static void strongarm_rtc_hzupdate(StrongARMRTCState
*s
)
249 int64_t rt
= qemu_get_clock_ms(rt_clock
);
250 s
->last_rcnr
+= ((rt
- s
->last_hz
) << 15) /
251 (1000 * ((s
->rttr
& 0xffff) + 1));
255 static inline void strongarm_rtc_timer_update(StrongARMRTCState
*s
)
257 if ((s
->rtsr
& RTSR_HZE
) && !(s
->rtsr
& RTSR_HZ
)) {
258 qemu_mod_timer(s
->rtc_hz
, s
->last_hz
+ 1000);
260 qemu_del_timer(s
->rtc_hz
);
263 if ((s
->rtsr
& RTSR_ALE
) && !(s
->rtsr
& RTSR_AL
)) {
264 qemu_mod_timer(s
->rtc_alarm
, s
->last_hz
+
265 (((s
->rtar
- s
->last_rcnr
) * 1000 *
266 ((s
->rttr
& 0xffff) + 1)) >> 15));
268 qemu_del_timer(s
->rtc_alarm
);
272 static inline void strongarm_rtc_alarm_tick(void *opaque
)
274 StrongARMRTCState
*s
= opaque
;
276 strongarm_rtc_timer_update(s
);
277 strongarm_rtc_int_update(s
);
280 static inline void strongarm_rtc_hz_tick(void *opaque
)
282 StrongARMRTCState
*s
= opaque
;
284 strongarm_rtc_timer_update(s
);
285 strongarm_rtc_int_update(s
);
288 static uint64_t strongarm_rtc_read(void *opaque
, target_phys_addr_t addr
,
291 StrongARMRTCState
*s
= opaque
;
301 return s
->last_rcnr
+
302 ((qemu_get_clock_ms(rt_clock
) - s
->last_hz
) << 15) /
303 (1000 * ((s
->rttr
& 0xffff) + 1));
305 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
310 static void strongarm_rtc_write(void *opaque
, target_phys_addr_t addr
,
311 uint64_t value
, unsigned size
)
313 StrongARMRTCState
*s
= opaque
;
318 strongarm_rtc_hzupdate(s
);
320 strongarm_rtc_timer_update(s
);
325 s
->rtsr
= (value
& (RTSR_ALE
| RTSR_HZE
)) |
326 (s
->rtsr
& ~(value
& (RTSR_AL
| RTSR_HZ
)));
328 if (s
->rtsr
!= old_rtsr
) {
329 strongarm_rtc_timer_update(s
);
332 strongarm_rtc_int_update(s
);
337 strongarm_rtc_timer_update(s
);
341 strongarm_rtc_hzupdate(s
);
342 s
->last_rcnr
= value
;
343 strongarm_rtc_timer_update(s
);
347 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
351 static const MemoryRegionOps strongarm_rtc_ops
= {
352 .read
= strongarm_rtc_read
,
353 .write
= strongarm_rtc_write
,
354 .endianness
= DEVICE_NATIVE_ENDIAN
,
357 static int strongarm_rtc_init(SysBusDevice
*dev
)
359 StrongARMRTCState
*s
= FROM_SYSBUS(StrongARMRTCState
, dev
);
365 qemu_get_timedate(&tm
, 0);
367 s
->last_rcnr
= (uint32_t) mktimegm(&tm
);
368 s
->last_hz
= qemu_get_clock_ms(rt_clock
);
370 s
->rtc_alarm
= qemu_new_timer_ms(rt_clock
, strongarm_rtc_alarm_tick
, s
);
371 s
->rtc_hz
= qemu_new_timer_ms(rt_clock
, strongarm_rtc_hz_tick
, s
);
373 sysbus_init_irq(dev
, &s
->rtc_irq
);
374 sysbus_init_irq(dev
, &s
->rtc_hz_irq
);
376 memory_region_init_io(&s
->iomem
, &strongarm_rtc_ops
, s
, "rtc", 0x10000);
377 sysbus_init_mmio(dev
, &s
->iomem
);
382 static void strongarm_rtc_pre_save(void *opaque
)
384 StrongARMRTCState
*s
= opaque
;
386 strongarm_rtc_hzupdate(s
);
389 static int strongarm_rtc_post_load(void *opaque
, int version_id
)
391 StrongARMRTCState
*s
= opaque
;
393 strongarm_rtc_timer_update(s
);
394 strongarm_rtc_int_update(s
);
399 static const VMStateDescription vmstate_strongarm_rtc_regs
= {
400 .name
= "strongarm-rtc",
402 .minimum_version_id
= 0,
403 .minimum_version_id_old
= 0,
404 .pre_save
= strongarm_rtc_pre_save
,
405 .post_load
= strongarm_rtc_post_load
,
406 .fields
= (VMStateField
[]) {
407 VMSTATE_UINT32(rttr
, StrongARMRTCState
),
408 VMSTATE_UINT32(rtsr
, StrongARMRTCState
),
409 VMSTATE_UINT32(rtar
, StrongARMRTCState
),
410 VMSTATE_UINT32(last_rcnr
, StrongARMRTCState
),
411 VMSTATE_INT64(last_hz
, StrongARMRTCState
),
412 VMSTATE_END_OF_LIST(),
416 static SysBusDeviceInfo strongarm_rtc_sysbus_info
= {
417 .init
= strongarm_rtc_init
,
418 .qdev
.name
= "strongarm-rtc",
419 .qdev
.desc
= "StrongARM RTC Controller",
420 .qdev
.size
= sizeof(StrongARMRTCState
),
421 .qdev
.vmsd
= &vmstate_strongarm_rtc_regs
,
434 typedef struct StrongARMGPIOInfo StrongARMGPIOInfo
;
435 struct StrongARMGPIOInfo
{
438 qemu_irq handler
[28];
455 static void strongarm_gpio_irq_update(StrongARMGPIOInfo
*s
)
458 for (i
= 0; i
< 11; i
++) {
459 qemu_set_irq(s
->irqs
[i
], s
->status
& (1 << i
));
462 qemu_set_irq(s
->irqX
, (s
->status
& ~0x7ff));
465 static void strongarm_gpio_set(void *opaque
, int line
, int level
)
467 StrongARMGPIOInfo
*s
= opaque
;
473 s
->status
|= s
->rising
& mask
&
474 ~s
->ilevel
& ~s
->dir
;
477 s
->status
|= s
->falling
& mask
&
482 if (s
->status
& mask
) {
483 strongarm_gpio_irq_update(s
);
487 static void strongarm_gpio_handler_update(StrongARMGPIOInfo
*s
)
489 uint32_t level
, diff
;
492 level
= s
->olevel
& s
->dir
;
494 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
496 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
499 s
->prev_level
= level
;
502 static uint64_t strongarm_gpio_read(void *opaque
, target_phys_addr_t offset
,
505 StrongARMGPIOInfo
*s
= opaque
;
508 case GPDR
: /* GPIO Pin-Direction registers */
511 case GPSR
: /* GPIO Pin-Output Set registers */
512 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx
"\n",
514 return s
->gpsr
; /* Return last written value. */
516 case GPCR
: /* GPIO Pin-Output Clear registers */
517 DPRINTF("%s: Read from a write-only register 0x" TARGET_FMT_plx
"\n",
519 return 31337; /* Specified as unpredictable in the docs. */
521 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
524 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
527 case GAFR
: /* GPIO Alternate Function registers */
530 case GPLR
: /* GPIO Pin-Level registers */
531 return (s
->olevel
& s
->dir
) |
532 (s
->ilevel
& ~s
->dir
);
534 case GEDR
: /* GPIO Edge Detect Status registers */
538 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
544 static void strongarm_gpio_write(void *opaque
, target_phys_addr_t offset
,
545 uint64_t value
, unsigned size
)
547 StrongARMGPIOInfo
*s
= opaque
;
550 case GPDR
: /* GPIO Pin-Direction registers */
552 strongarm_gpio_handler_update(s
);
555 case GPSR
: /* GPIO Pin-Output Set registers */
557 strongarm_gpio_handler_update(s
);
561 case GPCR
: /* GPIO Pin-Output Clear registers */
563 strongarm_gpio_handler_update(s
);
566 case GRER
: /* GPIO Rising-Edge Detect Enable registers */
570 case GFER
: /* GPIO Falling-Edge Detect Enable registers */
574 case GAFR
: /* GPIO Alternate Function registers */
578 case GEDR
: /* GPIO Edge Detect Status registers */
580 strongarm_gpio_irq_update(s
);
584 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
588 static const MemoryRegionOps strongarm_gpio_ops
= {
589 .read
= strongarm_gpio_read
,
590 .write
= strongarm_gpio_write
,
591 .endianness
= DEVICE_NATIVE_ENDIAN
,
594 static DeviceState
*strongarm_gpio_init(target_phys_addr_t base
,
600 dev
= qdev_create(NULL
, "strongarm-gpio");
601 qdev_init_nofail(dev
);
603 sysbus_mmio_map(sysbus_from_qdev(dev
), 0, base
);
604 for (i
= 0; i
< 12; i
++)
605 sysbus_connect_irq(sysbus_from_qdev(dev
), i
,
606 qdev_get_gpio_in(pic
, SA_PIC_GPIO0_EDGE
+ i
));
611 static int strongarm_gpio_initfn(SysBusDevice
*dev
)
613 StrongARMGPIOInfo
*s
;
616 s
= FROM_SYSBUS(StrongARMGPIOInfo
, dev
);
618 qdev_init_gpio_in(&dev
->qdev
, strongarm_gpio_set
, 28);
619 qdev_init_gpio_out(&dev
->qdev
, s
->handler
, 28);
621 memory_region_init_io(&s
->iomem
, &strongarm_gpio_ops
, s
, "gpio", 0x1000);
623 sysbus_init_mmio(dev
, &s
->iomem
);
624 for (i
= 0; i
< 11; i
++) {
625 sysbus_init_irq(dev
, &s
->irqs
[i
]);
627 sysbus_init_irq(dev
, &s
->irqX
);
632 static const VMStateDescription vmstate_strongarm_gpio_regs
= {
633 .name
= "strongarm-gpio",
635 .minimum_version_id
= 0,
636 .minimum_version_id_old
= 0,
637 .fields
= (VMStateField
[]) {
638 VMSTATE_UINT32(ilevel
, StrongARMGPIOInfo
),
639 VMSTATE_UINT32(olevel
, StrongARMGPIOInfo
),
640 VMSTATE_UINT32(dir
, StrongARMGPIOInfo
),
641 VMSTATE_UINT32(rising
, StrongARMGPIOInfo
),
642 VMSTATE_UINT32(falling
, StrongARMGPIOInfo
),
643 VMSTATE_UINT32(status
, StrongARMGPIOInfo
),
644 VMSTATE_UINT32(gafr
, StrongARMGPIOInfo
),
645 VMSTATE_END_OF_LIST(),
649 static SysBusDeviceInfo strongarm_gpio_info
= {
650 .init
= strongarm_gpio_initfn
,
651 .qdev
.name
= "strongarm-gpio",
652 .qdev
.desc
= "StrongARM GPIO controller",
653 .qdev
.size
= sizeof(StrongARMGPIOInfo
),
656 /* Peripheral Pin Controller */
663 typedef struct StrongARMPPCInfo StrongARMPPCInfo
;
664 struct StrongARMPPCInfo
{
667 qemu_irq handler
[28];
679 static void strongarm_ppc_set(void *opaque
, int line
, int level
)
681 StrongARMPPCInfo
*s
= opaque
;
684 s
->ilevel
|= 1 << line
;
686 s
->ilevel
&= ~(1 << line
);
690 static void strongarm_ppc_handler_update(StrongARMPPCInfo
*s
)
692 uint32_t level
, diff
;
695 level
= s
->olevel
& s
->dir
;
697 for (diff
= s
->prev_level
^ level
; diff
; diff
^= 1 << bit
) {
699 qemu_set_irq(s
->handler
[bit
], (level
>> bit
) & 1);
702 s
->prev_level
= level
;
705 static uint64_t strongarm_ppc_read(void *opaque
, target_phys_addr_t offset
,
708 StrongARMPPCInfo
*s
= opaque
;
711 case PPDR
: /* PPC Pin Direction registers */
712 return s
->dir
| ~0x3fffff;
714 case PPSR
: /* PPC Pin State registers */
715 return (s
->olevel
& s
->dir
) |
716 (s
->ilevel
& ~s
->dir
) |
720 return s
->ppar
| ~0x41000;
726 return s
->ppfr
| ~0x7f001;
729 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
735 static void strongarm_ppc_write(void *opaque
, target_phys_addr_t offset
,
736 uint64_t value
, unsigned size
)
738 StrongARMPPCInfo
*s
= opaque
;
741 case PPDR
: /* PPC Pin Direction registers */
742 s
->dir
= value
& 0x3fffff;
743 strongarm_ppc_handler_update(s
);
746 case PPSR
: /* PPC Pin State registers */
747 s
->olevel
= value
& s
->dir
& 0x3fffff;
748 strongarm_ppc_handler_update(s
);
752 s
->ppar
= value
& 0x41000;
756 s
->psdr
= value
& 0x3fffff;
760 s
->ppfr
= value
& 0x7f001;
764 printf("%s: Bad offset 0x" TARGET_FMT_plx
"\n", __func__
, offset
);
768 static const MemoryRegionOps strongarm_ppc_ops
= {
769 .read
= strongarm_ppc_read
,
770 .write
= strongarm_ppc_write
,
771 .endianness
= DEVICE_NATIVE_ENDIAN
,
774 static int strongarm_ppc_init(SysBusDevice
*dev
)
778 s
= FROM_SYSBUS(StrongARMPPCInfo
, dev
);
780 qdev_init_gpio_in(&dev
->qdev
, strongarm_ppc_set
, 22);
781 qdev_init_gpio_out(&dev
->qdev
, s
->handler
, 22);
783 memory_region_init_io(&s
->iomem
, &strongarm_ppc_ops
, s
, "ppc", 0x1000);
785 sysbus_init_mmio(dev
, &s
->iomem
);
790 static const VMStateDescription vmstate_strongarm_ppc_regs
= {
791 .name
= "strongarm-ppc",
793 .minimum_version_id
= 0,
794 .minimum_version_id_old
= 0,
795 .fields
= (VMStateField
[]) {
796 VMSTATE_UINT32(ilevel
, StrongARMPPCInfo
),
797 VMSTATE_UINT32(olevel
, StrongARMPPCInfo
),
798 VMSTATE_UINT32(dir
, StrongARMPPCInfo
),
799 VMSTATE_UINT32(ppar
, StrongARMPPCInfo
),
800 VMSTATE_UINT32(psdr
, StrongARMPPCInfo
),
801 VMSTATE_UINT32(ppfr
, StrongARMPPCInfo
),
802 VMSTATE_END_OF_LIST(),
806 static SysBusDeviceInfo strongarm_ppc_info
= {
807 .init
= strongarm_ppc_init
,
808 .qdev
.name
= "strongarm-ppc",
809 .qdev
.desc
= "StrongARM PPC controller",
810 .qdev
.size
= sizeof(StrongARMPPCInfo
),
822 #define UTCR0_PE (1 << 0) /* Parity enable */
823 #define UTCR0_OES (1 << 1) /* Even parity */
824 #define UTCR0_SBS (1 << 2) /* 2 stop bits */
825 #define UTCR0_DSS (1 << 3) /* 8-bit data */
827 #define UTCR3_RXE (1 << 0) /* Rx enable */
828 #define UTCR3_TXE (1 << 1) /* Tx enable */
829 #define UTCR3_BRK (1 << 2) /* Force Break */
830 #define UTCR3_RIE (1 << 3) /* Rx int enable */
831 #define UTCR3_TIE (1 << 4) /* Tx int enable */
832 #define UTCR3_LBM (1 << 5) /* Loopback */
834 #define UTSR0_TFS (1 << 0) /* Tx FIFO nearly empty */
835 #define UTSR0_RFS (1 << 1) /* Rx FIFO nearly full */
836 #define UTSR0_RID (1 << 2) /* Receiver Idle */
837 #define UTSR0_RBB (1 << 3) /* Receiver begin break */
838 #define UTSR0_REB (1 << 4) /* Receiver end break */
839 #define UTSR0_EIF (1 << 5) /* Error in FIFO */
841 #define UTSR1_RNE (1 << 1) /* Receive FIFO not empty */
842 #define UTSR1_TNF (1 << 2) /* Transmit FIFO not full */
843 #define UTSR1_PRE (1 << 3) /* Parity error */
844 #define UTSR1_FRE (1 << 4) /* Frame error */
845 #define UTSR1_ROR (1 << 5) /* Receive Over Run */
847 #define RX_FIFO_PRE (1 << 8)
848 #define RX_FIFO_FRE (1 << 9)
849 #define RX_FIFO_ROR (1 << 10)
854 CharDriverState
*chr
;
866 uint16_t rx_fifo
[12]; /* value + error flags in high bits */
870 uint64_t char_transmit_time
; /* time to transmit a char in ticks*/
872 QEMUTimer
*rx_timeout_timer
;
874 } StrongARMUARTState
;
876 static void strongarm_uart_update_status(StrongARMUARTState
*s
)
880 if (s
->tx_len
!= 8) {
884 if (s
->rx_len
!= 0) {
885 uint16_t ent
= s
->rx_fifo
[s
->rx_start
];
888 if (ent
& RX_FIFO_PRE
) {
889 s
->utsr1
|= UTSR1_PRE
;
891 if (ent
& RX_FIFO_FRE
) {
892 s
->utsr1
|= UTSR1_FRE
;
894 if (ent
& RX_FIFO_ROR
) {
895 s
->utsr1
|= UTSR1_ROR
;
902 static void strongarm_uart_update_int_status(StrongARMUARTState
*s
)
904 uint16_t utsr0
= s
->utsr0
&
905 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
);
908 if ((s
->utcr3
& UTCR3_TXE
) &&
909 (s
->utcr3
& UTCR3_TIE
) &&
914 if ((s
->utcr3
& UTCR3_RXE
) &&
915 (s
->utcr3
& UTCR3_RIE
) &&
920 for (i
= 0; i
< s
->rx_len
&& i
< 4; i
++)
921 if (s
->rx_fifo
[(s
->rx_start
+ i
) % 12] & ~0xff) {
927 qemu_set_irq(s
->irq
, utsr0
);
930 static void strongarm_uart_update_parameters(StrongARMUARTState
*s
)
932 int speed
, parity
, data_bits
, stop_bits
, frame_size
;
933 QEMUSerialSetParams ssp
;
937 if (s
->utcr0
& UTCR0_PE
) {
940 if (s
->utcr0
& UTCR0_OES
) {
948 if (s
->utcr0
& UTCR0_SBS
) {
954 data_bits
= (s
->utcr0
& UTCR0_DSS
) ? 8 : 7;
955 frame_size
+= data_bits
+ stop_bits
;
956 speed
= 3686400 / 16 / (s
->brd
+ 1);
959 ssp
.data_bits
= data_bits
;
960 ssp
.stop_bits
= stop_bits
;
961 s
->char_transmit_time
= (get_ticks_per_sec() / speed
) * frame_size
;
963 qemu_chr_fe_ioctl(s
->chr
, CHR_IOCTL_SERIAL_SET_PARAMS
, &ssp
);
966 DPRINTF(stderr
, "%s speed=%d parity=%c data=%d stop=%d\n", s
->chr
->label
,
967 speed
, parity
, data_bits
, stop_bits
);
970 static void strongarm_uart_rx_to(void *opaque
)
972 StrongARMUARTState
*s
= opaque
;
975 s
->utsr0
|= UTSR0_RID
;
976 strongarm_uart_update_int_status(s
);
980 static void strongarm_uart_rx_push(StrongARMUARTState
*s
, uint16_t c
)
982 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
987 if (s
->wait_break_end
) {
988 s
->utsr0
|= UTSR0_REB
;
989 s
->wait_break_end
= false;
992 if (s
->rx_len
< 12) {
993 s
->rx_fifo
[(s
->rx_start
+ s
->rx_len
) % 12] = c
;
996 s
->rx_fifo
[(s
->rx_start
+ 11) % 12] |= RX_FIFO_ROR
;
999 static int strongarm_uart_can_receive(void *opaque
)
1001 StrongARMUARTState
*s
= opaque
;
1003 if (s
->rx_len
== 12) {
1006 /* It's best not to get more than 2/3 of RX FIFO, so advertise that much */
1007 if (s
->rx_len
< 8) {
1008 return 8 - s
->rx_len
;
1013 static void strongarm_uart_receive(void *opaque
, const uint8_t *buf
, int size
)
1015 StrongARMUARTState
*s
= opaque
;
1018 for (i
= 0; i
< size
; i
++) {
1019 strongarm_uart_rx_push(s
, buf
[i
]);
1022 /* call the timeout receive callback in 3 char transmit time */
1023 qemu_mod_timer(s
->rx_timeout_timer
,
1024 qemu_get_clock_ns(vm_clock
) + s
->char_transmit_time
* 3);
1026 strongarm_uart_update_status(s
);
1027 strongarm_uart_update_int_status(s
);
1030 static void strongarm_uart_event(void *opaque
, int event
)
1032 StrongARMUARTState
*s
= opaque
;
1033 if (event
== CHR_EVENT_BREAK
) {
1034 s
->utsr0
|= UTSR0_RBB
;
1035 strongarm_uart_rx_push(s
, RX_FIFO_FRE
);
1036 s
->wait_break_end
= true;
1037 strongarm_uart_update_status(s
);
1038 strongarm_uart_update_int_status(s
);
1042 static void strongarm_uart_tx(void *opaque
)
1044 StrongARMUARTState
*s
= opaque
;
1045 uint64_t new_xmit_ts
= qemu_get_clock_ns(vm_clock
);
1047 if (s
->utcr3
& UTCR3_LBM
) /* loopback */ {
1048 strongarm_uart_receive(s
, &s
->tx_fifo
[s
->tx_start
], 1);
1049 } else if (s
->chr
) {
1050 qemu_chr_fe_write(s
->chr
, &s
->tx_fifo
[s
->tx_start
], 1);
1053 s
->tx_start
= (s
->tx_start
+ 1) % 8;
1056 qemu_mod_timer(s
->tx_timer
, new_xmit_ts
+ s
->char_transmit_time
);
1058 strongarm_uart_update_status(s
);
1059 strongarm_uart_update_int_status(s
);
1062 static uint64_t strongarm_uart_read(void *opaque
, target_phys_addr_t addr
,
1065 StrongARMUARTState
*s
= opaque
;
1076 return s
->brd
& 0xff;
1082 if (s
->rx_len
!= 0) {
1083 ret
= s
->rx_fifo
[s
->rx_start
];
1084 s
->rx_start
= (s
->rx_start
+ 1) % 12;
1086 strongarm_uart_update_status(s
);
1087 strongarm_uart_update_int_status(s
);
1099 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1104 static void strongarm_uart_write(void *opaque
, target_phys_addr_t addr
,
1105 uint64_t value
, unsigned size
)
1107 StrongARMUARTState
*s
= opaque
;
1111 s
->utcr0
= value
& 0x7f;
1112 strongarm_uart_update_parameters(s
);
1116 s
->brd
= (s
->brd
& 0xff) | ((value
& 0xf) << 8);
1117 strongarm_uart_update_parameters(s
);
1121 s
->brd
= (s
->brd
& 0xf00) | (value
& 0xff);
1122 strongarm_uart_update_parameters(s
);
1126 s
->utcr3
= value
& 0x3f;
1127 if ((s
->utcr3
& UTCR3_RXE
) == 0) {
1130 if ((s
->utcr3
& UTCR3_TXE
) == 0) {
1133 strongarm_uart_update_status(s
);
1134 strongarm_uart_update_int_status(s
);
1138 if ((s
->utcr3
& UTCR3_TXE
) && s
->tx_len
!= 8) {
1139 s
->tx_fifo
[(s
->tx_start
+ s
->tx_len
) % 8] = value
;
1141 strongarm_uart_update_status(s
);
1142 strongarm_uart_update_int_status(s
);
1143 if (s
->tx_len
== 1) {
1144 strongarm_uart_tx(s
);
1150 s
->utsr0
= s
->utsr0
& ~(value
&
1151 (UTSR0_REB
| UTSR0_RBB
| UTSR0_RID
));
1152 strongarm_uart_update_int_status(s
);
1156 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1160 static const MemoryRegionOps strongarm_uart_ops
= {
1161 .read
= strongarm_uart_read
,
1162 .write
= strongarm_uart_write
,
1163 .endianness
= DEVICE_NATIVE_ENDIAN
,
1166 static int strongarm_uart_init(SysBusDevice
*dev
)
1168 StrongARMUARTState
*s
= FROM_SYSBUS(StrongARMUARTState
, dev
);
1170 memory_region_init_io(&s
->iomem
, &strongarm_uart_ops
, s
, "uart", 0x10000);
1171 sysbus_init_mmio(dev
, &s
->iomem
);
1172 sysbus_init_irq(dev
, &s
->irq
);
1174 s
->rx_timeout_timer
= qemu_new_timer_ns(vm_clock
, strongarm_uart_rx_to
, s
);
1175 s
->tx_timer
= qemu_new_timer_ns(vm_clock
, strongarm_uart_tx
, s
);
1178 qemu_chr_add_handlers(s
->chr
,
1179 strongarm_uart_can_receive
,
1180 strongarm_uart_receive
,
1181 strongarm_uart_event
,
1188 static void strongarm_uart_reset(DeviceState
*dev
)
1190 StrongARMUARTState
*s
= DO_UPCAST(StrongARMUARTState
, busdev
.qdev
, dev
);
1192 s
->utcr0
= UTCR0_DSS
; /* 8 data, no parity */
1193 s
->brd
= 23; /* 9600 */
1194 /* enable send & recv - this actually violates spec */
1195 s
->utcr3
= UTCR3_TXE
| UTCR3_RXE
;
1197 s
->rx_len
= s
->tx_len
= 0;
1199 strongarm_uart_update_parameters(s
);
1200 strongarm_uart_update_status(s
);
1201 strongarm_uart_update_int_status(s
);
1204 static int strongarm_uart_post_load(void *opaque
, int version_id
)
1206 StrongARMUARTState
*s
= opaque
;
1208 strongarm_uart_update_parameters(s
);
1209 strongarm_uart_update_status(s
);
1210 strongarm_uart_update_int_status(s
);
1212 /* tx and restart timer */
1214 strongarm_uart_tx(s
);
1217 /* restart rx timeout timer */
1219 qemu_mod_timer(s
->rx_timeout_timer
,
1220 qemu_get_clock_ns(vm_clock
) + s
->char_transmit_time
* 3);
1226 static const VMStateDescription vmstate_strongarm_uart_regs
= {
1227 .name
= "strongarm-uart",
1229 .minimum_version_id
= 0,
1230 .minimum_version_id_old
= 0,
1231 .post_load
= strongarm_uart_post_load
,
1232 .fields
= (VMStateField
[]) {
1233 VMSTATE_UINT8(utcr0
, StrongARMUARTState
),
1234 VMSTATE_UINT16(brd
, StrongARMUARTState
),
1235 VMSTATE_UINT8(utcr3
, StrongARMUARTState
),
1236 VMSTATE_UINT8(utsr0
, StrongARMUARTState
),
1237 VMSTATE_UINT8_ARRAY(tx_fifo
, StrongARMUARTState
, 8),
1238 VMSTATE_UINT8(tx_start
, StrongARMUARTState
),
1239 VMSTATE_UINT8(tx_len
, StrongARMUARTState
),
1240 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMUARTState
, 12),
1241 VMSTATE_UINT8(rx_start
, StrongARMUARTState
),
1242 VMSTATE_UINT8(rx_len
, StrongARMUARTState
),
1243 VMSTATE_BOOL(wait_break_end
, StrongARMUARTState
),
1244 VMSTATE_END_OF_LIST(),
1248 static SysBusDeviceInfo strongarm_uart_info
= {
1249 .init
= strongarm_uart_init
,
1250 .qdev
.name
= "strongarm-uart",
1251 .qdev
.desc
= "StrongARM UART controller",
1252 .qdev
.size
= sizeof(StrongARMUARTState
),
1253 .qdev
.reset
= strongarm_uart_reset
,
1254 .qdev
.vmsd
= &vmstate_strongarm_uart_regs
,
1255 .qdev
.props
= (Property
[]) {
1256 DEFINE_PROP_CHR("chardev", StrongARMUARTState
, chr
),
1257 DEFINE_PROP_END_OF_LIST(),
1261 /* Synchronous Serial Ports */
1263 SysBusDevice busdev
;
1271 uint16_t rx_fifo
[8];
1274 } StrongARMSSPState
;
1276 #define SSCR0 0x60 /* SSP Control register 0 */
1277 #define SSCR1 0x64 /* SSP Control register 1 */
1278 #define SSDR 0x6c /* SSP Data register */
1279 #define SSSR 0x74 /* SSP Status register */
1281 /* Bitfields for above registers */
1282 #define SSCR0_SPI(x) (((x) & 0x30) == 0x00)
1283 #define SSCR0_SSP(x) (((x) & 0x30) == 0x10)
1284 #define SSCR0_UWIRE(x) (((x) & 0x30) == 0x20)
1285 #define SSCR0_PSP(x) (((x) & 0x30) == 0x30)
1286 #define SSCR0_SSE (1 << 7)
1287 #define SSCR0_DSS(x) (((x) & 0xf) + 1)
1288 #define SSCR1_RIE (1 << 0)
1289 #define SSCR1_TIE (1 << 1)
1290 #define SSCR1_LBM (1 << 2)
1291 #define SSSR_TNF (1 << 2)
1292 #define SSSR_RNE (1 << 3)
1293 #define SSSR_TFS (1 << 5)
1294 #define SSSR_RFS (1 << 6)
1295 #define SSSR_ROR (1 << 7)
1296 #define SSSR_RW 0x0080
1298 static void strongarm_ssp_int_update(StrongARMSSPState
*s
)
1302 level
|= (s
->sssr
& SSSR_ROR
);
1303 level
|= (s
->sssr
& SSSR_RFS
) && (s
->sscr
[1] & SSCR1_RIE
);
1304 level
|= (s
->sssr
& SSSR_TFS
) && (s
->sscr
[1] & SSCR1_TIE
);
1305 qemu_set_irq(s
->irq
, level
);
1308 static void strongarm_ssp_fifo_update(StrongARMSSPState
*s
)
1310 s
->sssr
&= ~SSSR_TFS
;
1311 s
->sssr
&= ~SSSR_TNF
;
1312 if (s
->sscr
[0] & SSCR0_SSE
) {
1313 if (s
->rx_level
>= 4) {
1314 s
->sssr
|= SSSR_RFS
;
1316 s
->sssr
&= ~SSSR_RFS
;
1319 s
->sssr
|= SSSR_RNE
;
1321 s
->sssr
&= ~SSSR_RNE
;
1323 /* TX FIFO is never filled, so it is always in underrun
1324 condition if SSP is enabled */
1325 s
->sssr
|= SSSR_TFS
;
1326 s
->sssr
|= SSSR_TNF
;
1329 strongarm_ssp_int_update(s
);
1332 static uint64_t strongarm_ssp_read(void *opaque
, target_phys_addr_t addr
,
1335 StrongARMSSPState
*s
= opaque
;
1346 if (~s
->sscr
[0] & SSCR0_SSE
) {
1349 if (s
->rx_level
< 1) {
1350 printf("%s: SSP Rx Underrun\n", __func__
);
1354 retval
= s
->rx_fifo
[s
->rx_start
++];
1356 strongarm_ssp_fifo_update(s
);
1359 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1365 static void strongarm_ssp_write(void *opaque
, target_phys_addr_t addr
,
1366 uint64_t value
, unsigned size
)
1368 StrongARMSSPState
*s
= opaque
;
1372 s
->sscr
[0] = value
& 0xffbf;
1373 if ((s
->sscr
[0] & SSCR0_SSE
) && SSCR0_DSS(value
) < 4) {
1374 printf("%s: Wrong data size: %i bits\n", __func__
,
1375 (int)SSCR0_DSS(value
));
1377 if (!(value
& SSCR0_SSE
)) {
1381 strongarm_ssp_fifo_update(s
);
1385 s
->sscr
[1] = value
& 0x2f;
1386 if (value
& SSCR1_LBM
) {
1387 printf("%s: Attempt to use SSP LBM mode\n", __func__
);
1389 strongarm_ssp_fifo_update(s
);
1393 s
->sssr
&= ~(value
& SSSR_RW
);
1394 strongarm_ssp_int_update(s
);
1398 if (SSCR0_UWIRE(s
->sscr
[0])) {
1401 /* Note how 32bits overflow does no harm here */
1402 value
&= (1 << SSCR0_DSS(s
->sscr
[0])) - 1;
1404 /* Data goes from here to the Tx FIFO and is shifted out from
1405 * there directly to the slave, no need to buffer it.
1407 if (s
->sscr
[0] & SSCR0_SSE
) {
1409 if (s
->sscr
[1] & SSCR1_LBM
) {
1412 readval
= ssi_transfer(s
->bus
, value
);
1415 if (s
->rx_level
< 0x08) {
1416 s
->rx_fifo
[(s
->rx_start
+ s
->rx_level
++) & 0x7] = readval
;
1418 s
->sssr
|= SSSR_ROR
;
1421 strongarm_ssp_fifo_update(s
);
1425 printf("%s: Bad register 0x" TARGET_FMT_plx
"\n", __func__
, addr
);
1430 static const MemoryRegionOps strongarm_ssp_ops
= {
1431 .read
= strongarm_ssp_read
,
1432 .write
= strongarm_ssp_write
,
1433 .endianness
= DEVICE_NATIVE_ENDIAN
,
1436 static int strongarm_ssp_post_load(void *opaque
, int version_id
)
1438 StrongARMSSPState
*s
= opaque
;
1440 strongarm_ssp_fifo_update(s
);
1445 static int strongarm_ssp_init(SysBusDevice
*dev
)
1447 StrongARMSSPState
*s
= FROM_SYSBUS(StrongARMSSPState
, dev
);
1449 sysbus_init_irq(dev
, &s
->irq
);
1451 memory_region_init_io(&s
->iomem
, &strongarm_ssp_ops
, s
, "ssp", 0x1000);
1452 sysbus_init_mmio(dev
, &s
->iomem
);
1454 s
->bus
= ssi_create_bus(&dev
->qdev
, "ssi");
1458 static void strongarm_ssp_reset(DeviceState
*dev
)
1460 StrongARMSSPState
*s
= DO_UPCAST(StrongARMSSPState
, busdev
.qdev
, dev
);
1461 s
->sssr
= 0x03; /* 3 bit data, SPI, disabled */
1466 static const VMStateDescription vmstate_strongarm_ssp_regs
= {
1467 .name
= "strongarm-ssp",
1469 .minimum_version_id
= 0,
1470 .minimum_version_id_old
= 0,
1471 .post_load
= strongarm_ssp_post_load
,
1472 .fields
= (VMStateField
[]) {
1473 VMSTATE_UINT16_ARRAY(sscr
, StrongARMSSPState
, 2),
1474 VMSTATE_UINT16(sssr
, StrongARMSSPState
),
1475 VMSTATE_UINT16_ARRAY(rx_fifo
, StrongARMSSPState
, 8),
1476 VMSTATE_UINT8(rx_start
, StrongARMSSPState
),
1477 VMSTATE_UINT8(rx_level
, StrongARMSSPState
),
1478 VMSTATE_END_OF_LIST(),
1482 static SysBusDeviceInfo strongarm_ssp_info
= {
1483 .init
= strongarm_ssp_init
,
1484 .qdev
.name
= "strongarm-ssp",
1485 .qdev
.desc
= "StrongARM SSP controller",
1486 .qdev
.size
= sizeof(StrongARMSSPState
),
1487 .qdev
.reset
= strongarm_ssp_reset
,
1488 .qdev
.vmsd
= &vmstate_strongarm_ssp_regs
,
1491 /* Main CPU functions */
1492 StrongARMState
*sa1110_init(MemoryRegion
*sysmem
,
1493 unsigned int sdram_size
, const char *rev
)
1499 s
= g_malloc0(sizeof(StrongARMState
));
1505 if (strncmp(rev
, "sa1110", 6)) {
1506 error_report("Machine requires a SA1110 processor.");
1510 s
->env
= cpu_init(rev
);
1513 error_report("Unable to find CPU definition");
1517 memory_region_init_ram(&s
->sdram
, "strongarm.sdram", sdram_size
);
1518 vmstate_register_ram_global(&s
->sdram
);
1519 memory_region_add_subregion(sysmem
, SA_SDCS0
, &s
->sdram
);
1521 pic
= arm_pic_init_cpu(s
->env
);
1522 s
->pic
= sysbus_create_varargs("strongarm_pic", 0x90050000,
1523 pic
[ARM_PIC_CPU_IRQ
], pic
[ARM_PIC_CPU_FIQ
], NULL
);
1525 sysbus_create_varargs("pxa25x-timer", 0x90000000,
1526 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC0
),
1527 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC1
),
1528 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC2
),
1529 qdev_get_gpio_in(s
->pic
, SA_PIC_OSTC3
),
1532 sysbus_create_simple("strongarm-rtc", 0x90010000,
1533 qdev_get_gpio_in(s
->pic
, SA_PIC_RTC_ALARM
));
1535 s
->gpio
= strongarm_gpio_init(0x90040000, s
->pic
);
1537 s
->ppc
= sysbus_create_varargs("strongarm-ppc", 0x90060000, NULL
);
1539 for (i
= 0; sa_serial
[i
].io_base
; i
++) {
1540 DeviceState
*dev
= qdev_create(NULL
, "strongarm-uart");
1541 qdev_prop_set_chr(dev
, "chardev", serial_hds
[i
]);
1542 qdev_init_nofail(dev
);
1543 sysbus_mmio_map(sysbus_from_qdev(dev
), 0,
1544 sa_serial
[i
].io_base
);
1545 sysbus_connect_irq(sysbus_from_qdev(dev
), 0,
1546 qdev_get_gpio_in(s
->pic
, sa_serial
[i
].irq
));
1549 s
->ssp
= sysbus_create_varargs("strongarm-ssp", 0x80070000,
1550 qdev_get_gpio_in(s
->pic
, SA_PIC_SSP
), NULL
);
1551 s
->ssp_bus
= (SSIBus
*)qdev_get_child_bus(s
->ssp
, "ssi");
1556 static void strongarm_register_devices(void)
1558 sysbus_register_withprop(&strongarm_pic_info
);
1559 sysbus_register_withprop(&strongarm_rtc_sysbus_info
);
1560 sysbus_register_withprop(&strongarm_gpio_info
);
1561 sysbus_register_withprop(&strongarm_ppc_info
);
1562 sysbus_register_withprop(&strongarm_uart_info
);
1563 sysbus_register_withprop(&strongarm_ssp_info
);
1565 device_init(strongarm_register_devices
)