target-mips/helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdarg.h>
  20 #include <stdlib.h>
  21 #include <stdio.h>
  22 #include <string.h>
  23 #include <inttypes.h>
  24 #include <signal.h>
  25
  26 #include "cpu.h"
  27 #include "exec-all.h"
  28
  29 enum {
  30     TLBRET_DIRTY = -4,
  31     TLBRET_INVALID = -3,
  32     TLBRET_NOMATCH = -2,
  33     TLBRET_BADADDR = -1,
  34     TLBRET_MATCH = 0
  35 };
  36
  37 #if !defined(CONFIG_USER_ONLY)
  38
  39 /* no MMU emulation */
  40 int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
  41                         target_ulong address, int rw, int access_type)
  42 {
  43     *physical = address;
  44     *prot = PAGE_READ | PAGE_WRITE;
  45     return TLBRET_MATCH;
  46 }
  47
  48 /* fixed mapping MMU emulation */
  49 int fixed_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
  50                            target_ulong address, int rw, int access_type)
  51 {
  52     if (address <= (int32_t)0x7FFFFFFFUL) {
  53         if (!(env->CP0_Status & (1 << CP0St_ERL)))
  54             *physical = address + 0x40000000UL;
  55         else
  56             *physical = address;
  57     } else if (address <= (int32_t)0xBFFFFFFFUL)
  58         *physical = address & 0x1FFFFFFF;
  59     else
  60         *physical = address;
  61
  62     *prot = PAGE_READ | PAGE_WRITE;
  63     return TLBRET_MATCH;
  64 }
  65
  66 /* MIPS32/MIPS64 R4000-style MMU emulation */
  67 int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
  68                      target_ulong address, int rw, int access_type)
  69 {
  70     uint8_t ASID = env->CP0_EntryHi & 0xFF;
  71     int i;
  72
  73     for (i = 0; i < env->tlb->tlb_in_use; i++) {
  74         r4k_tlb_t *tlb = &env->tlb->mmu.r4k.tlb[i];
  75         /* 1k pages are not supported. */
  76         target_ulong mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
  77         target_ulong tag = address & ~mask;
  78         target_ulong VPN = tlb->VPN & ~mask;
  79 #if defined(TARGET_MIPS64)
  80         tag &= env->SEGMask;
  81 #endif
  82
  83         /* Check ASID, virtual page number & size */
  84         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
  85             /* TLB match */
  86             int n = !!(address & mask & ~(mask >> 1));
  87             /* Check access rights */
  88             if (!(n ? tlb->V1 : tlb->V0))
  89                 return TLBRET_INVALID;
  90             if (rw == 0 || (n ? tlb->D1 : tlb->D0)) {
  91                 *physical = tlb->PFN[n] | (address & (mask >> 1));
  92                 *prot = PAGE_READ;
  93                 if (n ? tlb->D1 : tlb->D0)
  94                     *prot |= PAGE_WRITE;
  95                 return TLBRET_MATCH;
  96             }
  97             return TLBRET_DIRTY;
  98         }
  99     }
 100     return TLBRET_NOMATCH;
 101 }
 102
 103 static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
 104                                 int *prot, target_ulong address,
 105                                 int rw, int access_type)
 106 {
 107     /* User mode can only access useg/xuseg */
 108     int user_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM;
 109     int supervisor_mode = (env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_SM;
 110     int kernel_mode = !user_mode && !supervisor_mode;
 111 #if defined(TARGET_MIPS64)
 112     int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 113     int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 114     int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 115 #endif
 116     int ret = TLBRET_MATCH;
 117
 118 #if 0
 119     qemu_log("user mode %d h %08x\n", user_mode, env->hflags);
 120 #endif
 121
 122     if (address <= (int32_t)0x7FFFFFFFUL) {
 123         /* useg */
 124         if (env->CP0_Status & (1 << CP0St_ERL)) {
 125             *physical = address & 0xFFFFFFFF;
 126             *prot = PAGE_READ | PAGE_WRITE;
 127         } else {
 128             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 129         }
 130 #if defined(TARGET_MIPS64)
 131     } else if (address < 0x4000000000000000ULL) {
 132         /* xuseg */
 133         if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 134             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 135         } else {
 136             ret = TLBRET_BADADDR;
 137         }
 138     } else if (address < 0x8000000000000000ULL) {
 139         /* xsseg */
 140         if ((supervisor_mode || kernel_mode) &&
 141             SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
 142             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 143         } else {
 144             ret = TLBRET_BADADDR;
 145         }
 146     } else if (address < 0xC000000000000000ULL) {
 147         /* xkphys */
 148         if (kernel_mode && KX &&
 149             (address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) {
 150             *physical = address & env->PAMask;
 151             *prot = PAGE_READ | PAGE_WRITE;
 152         } else {
 153             ret = TLBRET_BADADDR;
 154         }
 155     } else if (address < 0xFFFFFFFF80000000ULL) {
 156         /* xkseg */
 157         if (kernel_mode && KX &&
 158             address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
 159             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 160         } else {
 161             ret = TLBRET_BADADDR;
 162         }
 163 #endif
 164     } else if (address < (int32_t)0xA0000000UL) {
 165         /* kseg0 */
 166         if (kernel_mode) {
 167             *physical = address - (int32_t)0x80000000UL;
 168             *prot = PAGE_READ | PAGE_WRITE;
 169         } else {
 170             ret = TLBRET_BADADDR;
 171         }
 172     } else if (address < (int32_t)0xC0000000UL) {
 173         /* kseg1 */
 174         if (kernel_mode) {
 175             *physical = address - (int32_t)0xA0000000UL;
 176             *prot = PAGE_READ | PAGE_WRITE;
 177         } else {
 178             ret = TLBRET_BADADDR;
 179         }
 180     } else if (address < (int32_t)0xE0000000UL) {
 181         /* sseg (kseg2) */
 182         if (supervisor_mode || kernel_mode) {
 183             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 184         } else {
 185             ret = TLBRET_BADADDR;
 186         }
 187     } else {
 188         /* kseg3 */
 189         /* XXX: debug segment is not emulated */
 190         if (kernel_mode) {
 191             ret = env->tlb->map_address(env, physical, prot, address, rw, access_type);
 192         } else {
 193             ret = TLBRET_BADADDR;
 194         }
 195     }
 196 #if 0
 197     qemu_log(TARGET_FMT_lx " %d %d => " TARGET_FMT_lx " %d (%d)\n",
 198             address, rw, access_type, *physical, *prot, ret);
 199 #endif
 200
 201     return ret;
 202 }
 203 #endif
 204
 205 static void raise_mmu_exception(CPUState *env, target_ulong address,
 206                                 int rw, int tlb_error)
 207 {
 208     int exception = 0, error_code = 0;
 209
 210     switch (tlb_error) {
 211     default:
 212     case TLBRET_BADADDR:
 213         /* Reference to kernel address from user mode or supervisor mode */
 214         /* Reference to supervisor address from user mode */
 215         if (rw)
 216             exception = EXCP_AdES;
 217         else
 218             exception = EXCP_AdEL;
 219         break;
 220     case TLBRET_NOMATCH:
 221         /* No TLB match for a mapped address */
 222         if (rw)
 223             exception = EXCP_TLBS;
 224         else
 225             exception = EXCP_TLBL;
 226         error_code = 1;
 227         break;
 228     case TLBRET_INVALID:
 229         /* TLB match with no valid bit */
 230         if (rw)
 231             exception = EXCP_TLBS;
 232         else
 233             exception = EXCP_TLBL;
 234         break;
 235     case TLBRET_DIRTY:
 236         /* TLB match but 'D' bit is cleared */
 237         exception = EXCP_LTLBL;
 238         break;
 239
 240     }
 241     /* Raise exception */
 242     env->CP0_BadVAddr = address;
 243     env->CP0_Context = (env->CP0_Context & ~0x007fffff) |
 244                        ((address >> 9) & 0x007ffff0);
 245     env->CP0_EntryHi =
 246         (env->CP0_EntryHi & 0xFF) | (address & (TARGET_PAGE_MASK << 1));
 247 #if defined(TARGET_MIPS64)
 248     env->CP0_EntryHi &= env->SEGMask;
 249     env->CP0_XContext = (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
 250                         ((address & 0xC00000000000ULL) >> (55 - env->SEGBITS)) |
 251                         ((address & ((1ULL << env->SEGBITS) - 1) & 0xFFFFFFFFFFFFE000ULL) >> 9);
 252 #endif
 253     env->exception_index = exception;
 254     env->error_code = error_code;
 255 }
 256
 257 #if !defined(CONFIG_USER_ONLY)
 258 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 259 {
 260     target_phys_addr_t phys_addr;
 261     int prot;
 262
 263     if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
 264         return -1;
 265     return phys_addr;
 266 }
 267 #endif
 268
 269 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
 270                                int mmu_idx, int is_softmmu)
 271 {
 272 #if !defined(CONFIG_USER_ONLY)
 273     target_phys_addr_t physical;
 274     int prot;
 275 #endif
 276     int access_type;
 277     int ret = 0;
 278
 279 #if 0
 280     log_cpu_state(env, 0);
 281 #endif
 282     qemu_log("%s pc " TARGET_FMT_lx " ad " TARGET_FMT_lx " rw %d mmu_idx %d smmu %d\n",
 283               __func__, env->active_tc.PC, address, rw, mmu_idx, is_softmmu);
 284
 285     rw &= 1;
 286
 287     /* data access */
 288     /* XXX: put correct access by using cpu_restore_state()
 289        correctly */
 290     access_type = ACCESS_INT;
 291 #if defined(CONFIG_USER_ONLY)
 292     ret = TLBRET_NOMATCH;
 293 #else
 294     ret = get_physical_address(env, &physical, &prot,
 295                                address, rw, access_type);
 296     qemu_log("%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx " prot %d\n",
 297               __func__, address, ret, physical, prot);
 298     if (ret == TLBRET_MATCH) {
 299        tlb_set_page(env, address & TARGET_PAGE_MASK,
 300                     physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
 301                     mmu_idx, TARGET_PAGE_SIZE);
 302        ret = 0;
 303     } else if (ret < 0)
 304 #endif
 305     {
 306         raise_mmu_exception(env, address, rw, ret);
 307         ret = 1;
 308     }
 309
 310     return ret;
 311 }
 312
 313 #if !defined(CONFIG_USER_ONLY)
 314 target_phys_addr_t cpu_mips_translate_address(CPUState *env, target_ulong address, int rw)
 315 {
 316     target_phys_addr_t physical;
 317     int prot;
 318     int access_type;
 319     int ret = 0;
 320
 321     rw &= 1;
 322
 323     /* data access */
 324     access_type = ACCESS_INT;
 325     ret = get_physical_address(env, &physical, &prot,
 326                                address, rw, access_type);
 327     if (ret != TLBRET_MATCH) {
 328         raise_mmu_exception(env, address, rw, ret);
 329         return -1LL;
 330     } else {
 331         return physical;
 332     }
 333 }
 334 #endif
 335
 336 static const char * const excp_names[EXCP_LAST + 1] = {
 337     [EXCP_RESET] = "reset",
 338     [EXCP_SRESET] = "soft reset",
 339     [EXCP_DSS] = "debug single step",
 340     [EXCP_DINT] = "debug interrupt",
 341     [EXCP_NMI] = "non-maskable interrupt",
 342     [EXCP_MCHECK] = "machine check",
 343     [EXCP_EXT_INTERRUPT] = "interrupt",
 344     [EXCP_DFWATCH] = "deferred watchpoint",
 345     [EXCP_DIB] = "debug instruction breakpoint",
 346     [EXCP_IWATCH] = "instruction fetch watchpoint",
 347     [EXCP_AdEL] = "address error load",
 348     [EXCP_AdES] = "address error store",
 349     [EXCP_TLBF] = "TLB refill",
 350     [EXCP_IBE] = "instruction bus error",
 351     [EXCP_DBp] = "debug breakpoint",
 352     [EXCP_SYSCALL] = "syscall",
 353     [EXCP_BREAK] = "break",
 354     [EXCP_CpU] = "coprocessor unusable",
 355     [EXCP_RI] = "reserved instruction",
 356     [EXCP_OVERFLOW] = "arithmetic overflow",
 357     [EXCP_TRAP] = "trap",
 358     [EXCP_FPE] = "floating point",
 359     [EXCP_DDBS] = "debug data break store",
 360     [EXCP_DWATCH] = "data watchpoint",
 361     [EXCP_LTLBL] = "TLB modify",
 362     [EXCP_TLBL] = "TLB load",
 363     [EXCP_TLBS] = "TLB store",
 364     [EXCP_DBE] = "data bus error",
 365     [EXCP_DDBL] = "debug data break load",
 366     [EXCP_THREAD] = "thread",
 367     [EXCP_MDMX] = "MDMX",
 368     [EXCP_C2E] = "precise coprocessor 2",
 369     [EXCP_CACHE] = "cache error",
 370 };
 371
 372 #if !defined(CONFIG_USER_ONLY)
 373 static target_ulong exception_resume_pc (CPUState *env)
 374 {
 375     target_ulong bad_pc;
 376     target_ulong isa_mode;
 377
 378     isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
 379     bad_pc = env->active_tc.PC | isa_mode;
 380     if (env->hflags & MIPS_HFLAG_BMASK) {
 381         /* If the exception was raised from a delay slot, come back to
 382            the jump.  */
 383         bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
 384     }
 385
 386     return bad_pc;
 387 }
 388
 389 static void set_hflags_for_handler (CPUState *env)
 390 {
 391     /* Exception handlers are entered in 32-bit mode.  */
 392     env->hflags &= ~(MIPS_HFLAG_M16);
 393     /* ...except that microMIPS lets you choose.  */
 394     if (env->insn_flags & ASE_MICROMIPS) {
 395         env->hflags |= (!!(env->CP0_Config3
 396                            & (1 << CP0C3_ISA_ON_EXC))
 397                         << MIPS_HFLAG_M16_SHIFT);
 398     }
 399 }
 400 #endif
 401
 402 void do_interrupt (CPUState *env)
 403 {
 404 #if !defined(CONFIG_USER_ONLY)
 405     target_ulong offset;
 406     int cause = -1;
 407     const char *name;
 408
 409     if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
 410         if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
 411             name = "unknown";
 412         else
 413             name = excp_names[env->exception_index];
 414
 415         qemu_log("%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
 416                  __func__, env->active_tc.PC, env->CP0_EPC, name);
 417     }
 418     if (env->exception_index == EXCP_EXT_INTERRUPT &&
 419         (env->hflags & MIPS_HFLAG_DM))
 420         env->exception_index = EXCP_DINT;
 421     offset = 0x180;
 422     switch (env->exception_index) {
 423     case EXCP_DSS:
 424         env->CP0_Debug |= 1 << CP0DB_DSS;
 425         /* Debug single step cannot be raised inside a delay slot and
 426            resume will always occur on the next instruction
 427            (but we assume the pc has always been updated during
 428            code translation). */
 429         env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
 430         goto enter_debug_mode;
 431     case EXCP_DINT:
 432         env->CP0_Debug |= 1 << CP0DB_DINT;
 433         goto set_DEPC;
 434     case EXCP_DIB:
 435         env->CP0_Debug |= 1 << CP0DB_DIB;
 436         goto set_DEPC;
 437     case EXCP_DBp:
 438         env->CP0_Debug |= 1 << CP0DB_DBp;
 439         goto set_DEPC;
 440     case EXCP_DDBS:
 441         env->CP0_Debug |= 1 << CP0DB_DDBS;
 442         goto set_DEPC;
 443     case EXCP_DDBL:
 444         env->CP0_Debug |= 1 << CP0DB_DDBL;
 445     set_DEPC:
 446         env->CP0_DEPC = exception_resume_pc(env);
 447         env->hflags &= ~MIPS_HFLAG_BMASK;
 448  enter_debug_mode:
 449         env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 450         env->hflags &= ~(MIPS_HFLAG_KSU);
 451         /* EJTAG probe trap enable is not implemented... */
 452         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 453             env->CP0_Cause &= ~(1 << CP0Ca_BD);
 454         env->active_tc.PC = (int32_t)0xBFC00480;
 455         set_hflags_for_handler(env);
 456         break;
 457     case EXCP_RESET:
 458         cpu_reset(env);
 459         break;
 460     case EXCP_SRESET:
 461         env->CP0_Status |= (1 << CP0St_SR);
 462         memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
 463         goto set_error_EPC;
 464     case EXCP_NMI:
 465         env->CP0_Status |= (1 << CP0St_NMI);
 466  set_error_EPC:
 467         env->CP0_ErrorEPC = exception_resume_pc(env);
 468         env->hflags &= ~MIPS_HFLAG_BMASK;
 469         env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
 470         env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 471         env->hflags &= ~(MIPS_HFLAG_KSU);
 472         if (!(env->CP0_Status & (1 << CP0St_EXL)))
 473             env->CP0_Cause &= ~(1 << CP0Ca_BD);
 474         env->active_tc.PC = (int32_t)0xBFC00000;
 475         set_hflags_for_handler(env);
 476         break;
 477     case EXCP_EXT_INTERRUPT:
 478         cause = 0;
 479         if (env->CP0_Cause & (1 << CP0Ca_IV))
 480             offset = 0x200;
 481
 482         if (env->CP0_Config3 & ((1 << CP0C3_VInt) | (1 << CP0C3_VEIC))) {
 483             /* Vectored Interrupts.  */
 484             unsigned int spacing;
 485             unsigned int vector;
 486             unsigned int pending = (env->CP0_Cause & CP0Ca_IP_mask) >> 8;
 487
 488             /* Compute the Vector Spacing.  */
 489             spacing = (env->CP0_IntCtl >> CP0IntCtl_VS) & ((1 << 6) - 1);
 490             spacing <<= 5;
 491
 492             if (env->CP0_Config3 & (1 << CP0C3_VInt)) {
 493                 /* For VInt mode, the MIPS computes the vector internally.  */
 494                 for (vector = 0; vector < 8; vector++) {
 495                     if (pending & 1) {
 496                         /* Found it.  */
 497                         break;
 498                     }
 499                     pending >>= 1;
 500                 }
 501             } else {
 502                 /* For VEIC mode, the external interrupt controller feeds the
 503                    vector throught the CP0Cause IP lines.  */
 504                 vector = pending;
 505             }
 506             offset = 0x200 + vector * spacing;
 507         }
 508         goto set_EPC;
 509     case EXCP_LTLBL:
 510         cause = 1;
 511         goto set_EPC;
 512     case EXCP_TLBL:
 513         cause = 2;
 514         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 515 #if defined(TARGET_MIPS64)
 516             int R = env->CP0_BadVAddr >> 62;
 517             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 518             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 519             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 520
 521             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 522                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 523                 offset = 0x080;
 524             else
 525 #endif
 526                 offset = 0x000;
 527         }
 528         goto set_EPC;
 529     case EXCP_TLBS:
 530         cause = 3;
 531         if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
 532 #if defined(TARGET_MIPS64)
 533             int R = env->CP0_BadVAddr >> 62;
 534             int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
 535             int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
 536             int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
 537
 538             if (((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX)) &&
 539                 (!(env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F))))
 540                 offset = 0x080;
 541             else
 542 #endif
 543                 offset = 0x000;
 544         }
 545         goto set_EPC;
 546     case EXCP_AdEL:
 547         cause = 4;
 548         goto set_EPC;
 549     case EXCP_AdES:
 550         cause = 5;
 551         goto set_EPC;
 552     case EXCP_IBE:
 553         cause = 6;
 554         goto set_EPC;
 555     case EXCP_DBE:
 556         cause = 7;
 557         goto set_EPC;
 558     case EXCP_SYSCALL:
 559         cause = 8;
 560         goto set_EPC;
 561     case EXCP_BREAK:
 562         cause = 9;
 563         goto set_EPC;
 564     case EXCP_RI:
 565         cause = 10;
 566         goto set_EPC;
 567     case EXCP_CpU:
 568         cause = 11;
 569         env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
 570                          (env->error_code << CP0Ca_CE);
 571         goto set_EPC;
 572     case EXCP_OVERFLOW:
 573         cause = 12;
 574         goto set_EPC;
 575     case EXCP_TRAP:
 576         cause = 13;
 577         goto set_EPC;
 578     case EXCP_FPE:
 579         cause = 15;
 580         goto set_EPC;
 581     case EXCP_C2E:
 582         cause = 18;
 583         goto set_EPC;
 584     case EXCP_MDMX:
 585         cause = 22;
 586         goto set_EPC;
 587     case EXCP_DWATCH:
 588         cause = 23;
 589         /* XXX: TODO: manage defered watch exceptions */
 590         goto set_EPC;
 591     case EXCP_MCHECK:
 592         cause = 24;
 593         goto set_EPC;
 594     case EXCP_THREAD:
 595         cause = 25;
 596         goto set_EPC;
 597     case EXCP_CACHE:
 598         cause = 30;
 599         if (env->CP0_Status & (1 << CP0St_BEV)) {
 600             offset = 0x100;
 601         } else {
 602             offset = 0x20000100;
 603         }
 604  set_EPC:
 605         if (!(env->CP0_Status & (1 << CP0St_EXL))) {
 606             env->CP0_EPC = exception_resume_pc(env);
 607             if (env->hflags & MIPS_HFLAG_BMASK) {
 608                 env->CP0_Cause |= (1 << CP0Ca_BD);
 609             } else {
 610                 env->CP0_Cause &= ~(1 << CP0Ca_BD);
 611             }
 612             env->CP0_Status |= (1 << CP0St_EXL);
 613             env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
 614             env->hflags &= ~(MIPS_HFLAG_KSU);
 615         }
 616         env->hflags &= ~MIPS_HFLAG_BMASK;
 617         if (env->CP0_Status & (1 << CP0St_BEV)) {
 618             env->active_tc.PC = (int32_t)0xBFC00200;
 619         } else {
 620             env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
 621         }
 622         env->active_tc.PC += offset;
 623         set_hflags_for_handler(env);
 624         env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
 625         break;
 626     default:
 627         qemu_log("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 628         printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
 629         exit(1);
 630     }
 631     if (qemu_log_enabled() && env->exception_index != EXCP_EXT_INTERRUPT) {
 632         qemu_log("%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
 633                 "    S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
 634                 __func__, env->active_tc.PC, env->CP0_EPC, cause,
 635                 env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
 636                 env->CP0_DEPC);
 637     }
 638 #endif
 639     env->exception_index = EXCP_NONE;
 640 }
 641
 642 #if !defined(CONFIG_USER_ONLY)
 643 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
 644 {
 645     r4k_tlb_t *tlb;
 646     target_ulong addr;
 647     target_ulong end;
 648     uint8_t ASID = env->CP0_EntryHi & 0xFF;
 649     target_ulong mask;
 650
 651     tlb = &env->tlb->mmu.r4k.tlb[idx];
 652     /* The qemu TLB is flushed when the ASID changes, so no need to
 653        flush these entries again.  */
 654     if (tlb->G == 0 && tlb->ASID != ASID) {
 655         return;
 656     }
 657
 658     if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
 659         /* For tlbwr, we can shadow the discarded entry into
 660            a new (fake) TLB entry, as long as the guest can not
 661            tell that it's there.  */
 662         env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
 663         env->tlb->tlb_in_use++;
 664         return;
 665     }
 666
 667     /* 1k pages are not supported. */
 668     mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
 669     if (tlb->V0) {
 670         addr = tlb->VPN & ~mask;
 671 #if defined(TARGET_MIPS64)
 672         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 673             addr |= 0x3FFFFF0000000000ULL;
 674         }
 675 #endif
 676         end = addr | (mask >> 1);
 677         while (addr < end) {
 678             tlb_flush_page (env, addr);
 679             addr += TARGET_PAGE_SIZE;
 680         }
 681     }
 682     if (tlb->V1) {
 683         addr = (tlb->VPN & ~mask) | ((mask >> 1) + 1);
 684 #if defined(TARGET_MIPS64)
 685         if (addr >= (0xFFFFFFFF80000000ULL & env->SEGMask)) {
 686             addr |= 0x3FFFFF0000000000ULL;
 687         }
 688 #endif
 689         end = addr | mask;
 690         while (addr - 1 < end) {
 691             tlb_flush_page (env, addr);
 692             addr += TARGET_PAGE_SIZE;
 693         }
 694     }
 695 }
 696 #endif