s390: Channel I/O basic definitions.
[qemu.git] / hw / qxl.h
blobf867a1d0ac699e3ff179111fbf6dfac90ffb6a78
1 #ifndef HW_QXL_H
2 #define HW_QXL_H 1
4 #include "qemu-common.h"
6 #include "ui/console.h"
7 #include "hw.h"
8 #include "pci/pci.h"
9 #include "vga_int.h"
10 #include "qemu/thread.h"
12 #include "ui/qemu-spice.h"
13 #include "ui/spice-display.h"
15 enum qxl_mode {
16 QXL_MODE_UNDEFINED,
17 QXL_MODE_VGA,
18 QXL_MODE_COMPAT, /* spice 0.4.x */
19 QXL_MODE_NATIVE,
22 #ifndef QXL_VRAM64_RANGE_INDEX
23 #define QXL_VRAM64_RANGE_INDEX 4
24 #endif
26 #define QXL_UNDEFINED_IO UINT32_MAX
28 #define QXL_NUM_DIRTY_RECTS 64
30 typedef struct PCIQXLDevice {
31 PCIDevice pci;
32 SimpleSpiceDisplay ssd;
33 int id;
34 uint32_t debug;
35 uint32_t guestdebug;
36 uint32_t cmdlog;
38 uint32_t guest_bug;
40 enum qxl_mode mode;
41 uint32_t cmdflags;
42 int generation;
43 uint32_t revision;
45 int32_t num_memslots;
47 uint32_t current_async;
48 QemuMutex async_lock;
50 struct guest_slots {
51 QXLMemSlot slot;
52 void *ptr;
53 uint64_t size;
54 uint64_t delta;
55 uint32_t active;
56 } guest_slots[NUM_MEMSLOTS];
58 struct guest_primary {
59 QXLSurfaceCreate surface;
60 uint32_t commands;
61 uint32_t resized;
62 int32_t qxl_stride;
63 uint32_t abs_stride;
64 uint32_t bits_pp;
65 uint32_t bytes_pp;
66 uint8_t *data;
67 } guest_primary;
69 struct surfaces {
70 QXLPHYSICAL *cmds;
71 uint32_t count;
72 uint32_t max;
73 } guest_surfaces;
74 QXLPHYSICAL guest_cursor;
76 QXLPHYSICAL guest_monitors_config;
78 QemuMutex track_lock;
80 /* thread signaling */
81 QemuThread main;
82 int pipe[2];
84 /* ram pci bar */
85 QXLRam *ram;
86 VGACommonState vga;
87 uint32_t num_free_res;
88 QXLReleaseInfo *last_release;
89 uint32_t last_release_offset;
90 uint32_t oom_running;
91 uint32_t vgamem_size;
93 /* rom pci bar */
94 QXLRom shadow_rom;
95 QXLRom *rom;
96 QXLModes *modes;
97 uint32_t rom_size;
98 MemoryRegion rom_bar;
100 /* vram pci bar */
101 uint32_t vram_size;
102 MemoryRegion vram_bar;
103 uint32_t vram32_size;
104 MemoryRegion vram32_bar;
106 /* io bar */
107 MemoryRegion io_bar;
109 /* user-friendly properties (in megabytes) */
110 uint32_t ram_size_mb;
111 uint32_t vram_size_mb;
112 uint32_t vram32_size_mb;
113 uint32_t vgamem_size_mb;
115 /* qxl_render_update state */
116 int render_update_cookie_num;
117 int num_dirty_rects;
118 QXLRect dirty[QXL_NUM_DIRTY_RECTS];
119 QEMUBH *update_area_bh;
120 } PCIQXLDevice;
122 #define PANIC_ON(x) if ((x)) { \
123 printf("%s: PANIC %s failed\n", __FUNCTION__, #x); \
124 abort(); \
127 #define dprint(_qxl, _level, _fmt, ...) \
128 do { \
129 if (_qxl->debug >= _level) { \
130 fprintf(stderr, "qxl-%d: ", _qxl->id); \
131 fprintf(stderr, _fmt, ## __VA_ARGS__); \
133 } while (0)
135 #define QXL_DEFAULT_REVISION QXL_REVISION_STABLE_V12
137 /* qxl.c */
138 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL phys, int group_id);
139 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
140 GCC_FMT_ATTR(2, 3);
142 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
143 struct QXLRect *area, struct QXLRect *dirty_rects,
144 uint32_t num_dirty_rects,
145 uint32_t clear_dirty_region,
146 qxl_async_io async, QXLCookie *cookie);
147 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
148 uint32_t count);
149 void qxl_spice_oom(PCIQXLDevice *qxl);
150 void qxl_spice_reset_memslots(PCIQXLDevice *qxl);
151 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl);
152 void qxl_spice_reset_cursor(PCIQXLDevice *qxl);
154 /* qxl-logger.c */
155 int qxl_log_cmd_cursor(PCIQXLDevice *qxl, QXLCursorCmd *cmd, int group_id);
156 int qxl_log_command(PCIQXLDevice *qxl, const char *ring, QXLCommandExt *ext);
158 /* qxl-render.c */
159 void qxl_render_resize(PCIQXLDevice *qxl);
160 void qxl_render_update(PCIQXLDevice *qxl);
161 int qxl_render_cursor(PCIQXLDevice *qxl, QXLCommandExt *ext);
162 void qxl_render_update_area_done(PCIQXLDevice *qxl, QXLCookie *cookie);
163 void qxl_render_update_area_bh(void *opaque);
165 #endif