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ppc/pnv: Complete user created PHB3 devices
[qemu.git] / hw / ppc / pnv.c
blob8dc63823573ed42b21aefa41cf3e1cc52542d95a
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu-common.h"
22 #include "qemu/datadir.h"
23 #include "qemu/units.h"
24 #include "qemu/cutils.h"
25 #include "qapi/error.h"
26 #include "sysemu/qtest.h"
27 #include "sysemu/sysemu.h"
28 #include "sysemu/numa.h"
29 #include "sysemu/reset.h"
30 #include "sysemu/runstate.h"
31 #include "sysemu/cpus.h"
32 #include "sysemu/device_tree.h"
33 #include "sysemu/hw_accel.h"
34 #include "target/ppc/cpu.h"
35 #include "hw/ppc/fdt.h"
36 #include "hw/ppc/ppc.h"
37 #include "hw/ppc/pnv.h"
38 #include "hw/ppc/pnv_core.h"
39 #include "hw/loader.h"
40 #include "hw/nmi.h"
41 #include "qapi/visitor.h"
42 #include "monitor/monitor.h"
43 #include "hw/intc/intc.h"
44 #include "hw/ipmi/ipmi.h"
45 #include "target/ppc/mmu-hash64.h"
46 #include "hw/pci/msi.h"
47
48 #include "hw/ppc/xics.h"
49 #include "hw/qdev-properties.h"
50 #include "hw/ppc/pnv_xscom.h"
51 #include "hw/ppc/pnv_pnor.h"
52
53 #include "hw/isa/isa.h"
54 #include "hw/char/serial.h"
55 #include "hw/rtc/mc146818rtc.h"
56
57 #include <libfdt.h>
58
59 #define FDT_MAX_SIZE (1 * MiB)
60
61 #define FW_FILE_NAME "skiboot.lid"
62 #define FW_LOAD_ADDR 0x0
63 #define FW_MAX_SIZE (16 * MiB)
64
65 #define KERNEL_LOAD_ADDR 0x20000000
66 #define KERNEL_MAX_SIZE (128 * MiB)
67 #define INITRD_LOAD_ADDR 0x28000000
68 #define INITRD_MAX_SIZE (128 * MiB)
69
70 static const char *pnv_chip_core_typename(const PnvChip *o)
71 {
72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
75 const char *core_type = object_class_get_name(object_class_by_name(s));
76 g_free(s);
77 return core_type;
78 }
79
80 /*
81 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
82 * 4 * 4 sockets * 12 cores * 8 threads = 1536
83 * Let's make it 2^11
84 */
85 #define MAX_CPUS 2048
86
87 /*
88 * Memory nodes are created by hostboot, one for each range of memory
89 * that has a different "affinity". In practice, it means one range
90 * per chip.
91 */
92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
93 {
94 char *mem_name;
95 uint64_t mem_reg_property[2];
96 int off;
97
98 mem_reg_property[0] = cpu_to_be64(start);
99 mem_reg_property[1] = cpu_to_be64(size);
100
101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
102 off = fdt_add_subnode(fdt, 0, mem_name);
103 g_free(mem_name);
104
105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
107 sizeof(mem_reg_property))));
108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
109 }
110
111 static int get_cpus_node(void *fdt)
112 {
113 int cpus_offset = fdt_path_offset(fdt, "/cpus");
114
115 if (cpus_offset < 0) {
116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
117 if (cpus_offset) {
118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
120 }
121 }
122 _FDT(cpus_offset);
123 return cpus_offset;
124 }
125
126 /*
127 * The PowerNV cores (and threads) need to use real HW ids and not an
128 * incremental index like it has been done on other platforms. This HW
129 * id is stored in the CPU PIR, it is used to create cpu nodes in the
130 * device tree, used in XSCOM to address cores and in interrupt
131 * servers.
132 */
133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
134 {
135 PowerPCCPU *cpu = pc->threads[0];
136 CPUState *cs = CPU(cpu);
137 DeviceClass *dc = DEVICE_GET_CLASS(cs);
138 int smt_threads = CPU_CORE(pc)->nr_threads;
139 CPUPPCState *env = &cpu->env;
140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
141 uint32_t servers_prop[smt_threads];
142 int i;
143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
144 0xffffffff, 0xffffffff};
145 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
146 uint32_t cpufreq = 1000000000;
147 uint32_t page_sizes_prop[64];
148 size_t page_sizes_prop_size;
149 const uint8_t pa_features[] = { 24, 0,
150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
154 int offset;
155 char *nodename;
156 int cpus_offset = get_cpus_node(fdt);
157
158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
159 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
160 _FDT(offset);
161 g_free(nodename);
162
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
164
165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
168
169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
171 env->dcache_line_size)));
172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
173 env->dcache_line_size)));
174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
175 env->icache_line_size)));
176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
177 env->icache_line_size)));
178
179 if (pcc->l1_dcache_size) {
180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
181 pcc->l1_dcache_size)));
182 } else {
183 warn_report("Unknown L1 dcache size for cpu");
184 }
185 if (pcc->l1_icache_size) {
186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
187 pcc->l1_icache_size)));
188 } else {
189 warn_report("Unknown L1 icache size for cpu");
190 }
191
192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
195 cpu->hash64_opts->slb_size)));
196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
198
199 if (ppc_has_spr(cpu, SPR_PURR)) {
200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
201 }
202
203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
205 segs, sizeof(segs))));
206 }
207
208 /*
209 * Advertise VMX/VSX (vector extensions) if available
210 * 0 / no property == no vector extensions
211 * 1 == VMX / Altivec available
212 * 2 == VSX available
213 */
214 if (env->insns_flags & PPC_ALTIVEC) {
215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
216
217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
218 }
219
220 /*
221 * Advertise DFP (Decimal Floating Point) if available
222 * 0 / no property == no DFP
223 * 1 == DFP available
224 */
225 if (env->insns_flags2 & PPC2_DFP) {
226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
227 }
228
229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
230 sizeof(page_sizes_prop));
231 if (page_sizes_prop_size) {
232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
233 page_sizes_prop, page_sizes_prop_size)));
234 }
235
236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
237 pa_features, sizeof(pa_features))));
238
239 /* Build interrupt servers properties */
240 for (i = 0; i < smt_threads; i++) {
241 servers_prop[i] = cpu_to_be32(pc->pir + i);
242 }
243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
244 servers_prop, sizeof(servers_prop))));
245 }
246
247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
248 uint32_t nr_threads)
249 {
250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
251 char *name;
252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
253 uint32_t irange[2], i, rsize;
254 uint64_t *reg;
255 int offset;
256
257 irange[0] = cpu_to_be32(pir);
258 irange[1] = cpu_to_be32(nr_threads);
259
260 rsize = sizeof(uint64_t) * 2 * nr_threads;
261 reg = g_malloc(rsize);
262 for (i = 0; i < nr_threads; i++) {
263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
264 reg[i * 2 + 1] = cpu_to_be64(0x1000);
265 }
266
267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
268 offset = fdt_add_subnode(fdt, 0, name);
269 _FDT(offset);
270 g_free(name);
271
272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
274 _FDT((fdt_setprop_string(fdt, offset, "device_type",
275 "PowerPC-External-Interrupt-Presentation")));
276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
278 irange, sizeof(irange))));
279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
281 g_free(reg);
282 }
283
284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
285 {
286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
287 int i;
288
289 pnv_dt_xscom(chip, fdt, 0,
290 cpu_to_be64(PNV_XSCOM_BASE(chip)),
291 cpu_to_be64(PNV_XSCOM_SIZE),
292 compat, sizeof(compat));
293
294 for (i = 0; i < chip->nr_cores; i++) {
295 PnvCore *pnv_core = chip->cores[i];
296
297 pnv_dt_core(chip, pnv_core, fdt);
298
299 /* Interrupt Control Presenters (ICP). One per core. */
300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
301 }
302
303 if (chip->ram_size) {
304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
305 }
306 }
307
308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
309 {
310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
311 int i;
312
313 pnv_dt_xscom(chip, fdt, 0,
314 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
315 cpu_to_be64(PNV9_XSCOM_SIZE),
316 compat, sizeof(compat));
317
318 for (i = 0; i < chip->nr_cores; i++) {
319 PnvCore *pnv_core = chip->cores[i];
320
321 pnv_dt_core(chip, pnv_core, fdt);
322 }
323
324 if (chip->ram_size) {
325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
326 }
327
328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
329 }
330
331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
332 {
333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
334 int i;
335
336 pnv_dt_xscom(chip, fdt, 0,
337 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
338 cpu_to_be64(PNV10_XSCOM_SIZE),
339 compat, sizeof(compat));
340
341 for (i = 0; i < chip->nr_cores; i++) {
342 PnvCore *pnv_core = chip->cores[i];
343
344 pnv_dt_core(chip, pnv_core, fdt);
345 }
346
347 if (chip->ram_size) {
348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
349 }
350
351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
352 }
353
354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
355 {
356 uint32_t io_base = d->ioport_id;
357 uint32_t io_regs[] = {
358 cpu_to_be32(1),
359 cpu_to_be32(io_base),
360 cpu_to_be32(2)
361 };
362 char *name;
363 int node;
364
365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
366 node = fdt_add_subnode(fdt, lpc_off, name);
367 _FDT(node);
368 g_free(name);
369
370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
372 }
373
374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
375 {
376 const char compatible[] = "ns16550\0pnpPNP,501";
377 uint32_t io_base = d->ioport_id;
378 uint32_t io_regs[] = {
379 cpu_to_be32(1),
380 cpu_to_be32(io_base),
381 cpu_to_be32(8)
382 };
383 char *name;
384 int node;
385
386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
387 node = fdt_add_subnode(fdt, lpc_off, name);
388 _FDT(node);
389 g_free(name);
390
391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
392 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
393 sizeof(compatible))));
394
395 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
396 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0])));
398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
399 fdt_get_phandle(fdt, lpc_off))));
400
401 /* This is needed by Linux */
402 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
403 }
404
405 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
406 {
407 const char compatible[] = "bt\0ipmi-bt";
408 uint32_t io_base;
409 uint32_t io_regs[] = {
410 cpu_to_be32(1),
411 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
412 cpu_to_be32(3)
413 };
414 uint32_t irq;
415 char *name;
416 int node;
417
418 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
419 io_regs[1] = cpu_to_be32(io_base);
420
421 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
422
423 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
424 node = fdt_add_subnode(fdt, lpc_off, name);
425 _FDT(node);
426 g_free(name);
427
428 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
429 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
430 sizeof(compatible))));
431
432 /* Mark it as reserved to avoid Linux trying to claim it */
433 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
434 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
435 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
436 fdt_get_phandle(fdt, lpc_off))));
437 }
438
439 typedef struct ForeachPopulateArgs {
440 void *fdt;
441 int offset;
442 } ForeachPopulateArgs;
443
444 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
445 {
446 ForeachPopulateArgs *args = opaque;
447 ISADevice *d = ISA_DEVICE(dev);
448
449 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
450 pnv_dt_rtc(d, args->fdt, args->offset);
451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
452 pnv_dt_serial(d, args->fdt, args->offset);
453 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
454 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
455 } else {
456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
457 d->ioport_id);
458 }
459
460 return 0;
461 }
462
463 /*
464 * The default LPC bus of a multichip system is on chip 0. It's
465 * recognized by the firmware (skiboot) using a "primary" property.
466 */
467 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
468 {
469 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
470 ForeachPopulateArgs args = {
471 .fdt = fdt,
472 .offset = isa_offset,
473 };
474 uint32_t phandle;
475
476 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
477
478 phandle = qemu_fdt_alloc_phandle(fdt);
479 assert(phandle > 0);
480 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
481
482 /*
483 * ISA devices are not necessarily parented to the ISA bus so we
484 * can not use object_child_foreach()
485 */
486 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
487 &args);
488 }
489
490 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
491 {
492 int off;
493
494 off = fdt_add_subnode(fdt, 0, "ibm,opal");
495 off = fdt_add_subnode(fdt, off, "power-mgt");
496
497 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
498 }
499
500 static void *pnv_dt_create(MachineState *machine)
501 {
502 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
503 PnvMachineState *pnv = PNV_MACHINE(machine);
504 void *fdt;
505 char *buf;
506 int off;
507 int i;
508
509 fdt = g_malloc0(FDT_MAX_SIZE);
510 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
511
512 /* /qemu node */
513 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
514
515 /* Root node */
516 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
517 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
518 _FDT((fdt_setprop_string(fdt, 0, "model",
519 "IBM PowerNV (emulated by qemu)")));
520 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
521
522 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
523 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
524 if (qemu_uuid_set) {
525 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
526 }
527 g_free(buf);
528
529 off = fdt_add_subnode(fdt, 0, "chosen");
530 if (machine->kernel_cmdline) {
531 _FDT((fdt_setprop_string(fdt, off, "bootargs",
532 machine->kernel_cmdline)));
533 }
534
535 if (pnv->initrd_size) {
536 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
537 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
538
539 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
540 &start_prop, sizeof(start_prop))));
541 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
542 &end_prop, sizeof(end_prop))));
543 }
544
545 /* Populate device tree for each chip */
546 for (i = 0; i < pnv->num_chips; i++) {
547 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
548 }
549
550 /* Populate ISA devices on chip 0 */
551 pnv_dt_isa(pnv, fdt);
552
553 if (pnv->bmc) {
554 pnv_dt_bmc_sensors(pnv->bmc, fdt);
555 }
556
557 /* Create an extra node for power management on machines that support it */
558 if (pmc->dt_power_mgt) {
559 pmc->dt_power_mgt(pnv, fdt);
560 }
561
562 return fdt;
563 }
564
565 static void pnv_powerdown_notify(Notifier *n, void *opaque)
566 {
567 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
568
569 if (pnv->bmc) {
570 pnv_bmc_powerdown(pnv->bmc);
571 }
572 }
573
574 static void pnv_reset(MachineState *machine)
575 {
576 PnvMachineState *pnv = PNV_MACHINE(machine);
577 IPMIBmc *bmc;
578 void *fdt;
579
580 qemu_devices_reset();
581
582 /*
583 * The machine should provide by default an internal BMC simulator.
584 * If not, try to use the BMC device that was provided on the command
585 * line.
586 */
587 bmc = pnv_bmc_find(&error_fatal);
588 if (!pnv->bmc) {
589 if (!bmc) {
590 if (!qtest_enabled()) {
591 warn_report("machine has no BMC device. Use '-device "
592 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
593 "to define one");
594 }
595 } else {
596 pnv_bmc_set_pnor(bmc, pnv->pnor);
597 pnv->bmc = bmc;
598 }
599 }
600
601 fdt = pnv_dt_create(machine);
602
603 /* Pack resulting tree */
604 _FDT((fdt_pack(fdt)));
605
606 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
607 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
608
609 g_free(fdt);
610 }
611
612 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
613 {
614 Pnv8Chip *chip8 = PNV8_CHIP(chip);
615 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
616 }
617
618 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
619 {
620 Pnv8Chip *chip8 = PNV8_CHIP(chip);
621 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
622 }
623
624 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
625 {
626 Pnv9Chip *chip9 = PNV9_CHIP(chip);
627 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
628 }
629
630 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
631 {
632 Pnv10Chip *chip10 = PNV10_CHIP(chip);
633 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
634 }
635
636 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
637 {
638 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
639 }
640
641 static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque)
642 {
643 Monitor *mon = opaque;
644 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
645
646 if (phb3) {
647 pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
648 ics_pic_print_info(&phb3->lsis, mon);
649 }
650 return 0;
651 }
652
653 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
654 {
655 Pnv8Chip *chip8 = PNV8_CHIP(chip);
656
657 ics_pic_print_info(&chip8->psi.ics, mon);
658 object_child_foreach(OBJECT(chip),
659 pnv_chip_power8_pic_print_info_child, mon);
660 }
661
662 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
663 {
664 Monitor *mon = opaque;
665 PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4);
666
667 if (phb4) {
668 pnv_phb4_pic_print_info(phb4, mon);
669 }
670 return 0;
671 }
672
673 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
674 {
675 Pnv9Chip *chip9 = PNV9_CHIP(chip);
676
677 pnv_xive_pic_print_info(&chip9->xive, mon);
678 pnv_psi_pic_print_info(&chip9->psi, mon);
679
680 object_child_foreach_recursive(OBJECT(chip),
681 pnv_chip_power9_pic_print_info_child, mon);
682 }
683
684 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
685 uint32_t core_id)
686 {
687 return PNV_XSCOM_EX_BASE(core_id);
688 }
689
690 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
691 uint32_t core_id)
692 {
693 return PNV9_XSCOM_EC_BASE(core_id);
694 }
695
696 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
697 uint32_t core_id)
698 {
699 return PNV10_XSCOM_EC_BASE(core_id);
700 }
701
702 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
703 {
704 PowerPCCPUClass *ppc_default =
705 POWERPC_CPU_CLASS(object_class_by_name(default_type));
706 PowerPCCPUClass *ppc =
707 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
708
709 return ppc_default->pvr_match(ppc_default, ppc->pvr);
710 }
711
712 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
713 {
714 ISADevice *dev = isa_new("isa-ipmi-bt");
715
716 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
717 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
718 isa_realize_and_unref(dev, bus, &error_fatal);
719 }
720
721 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
722 {
723 Pnv10Chip *chip10 = PNV10_CHIP(chip);
724
725 pnv_psi_pic_print_info(&chip10->psi, mon);
726 }
727
728 /* Always give the first 1GB to chip 0 else we won't boot */
729 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
730 {
731 MachineState *machine = MACHINE(pnv);
732 uint64_t ram_per_chip;
733
734 assert(machine->ram_size >= 1 * GiB);
735
736 ram_per_chip = machine->ram_size / pnv->num_chips;
737 if (ram_per_chip >= 1 * GiB) {
738 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
739 }
740
741 assert(pnv->num_chips > 1);
742
743 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
744 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
745 }
746
747 static void pnv_init(MachineState *machine)
748 {
749 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
750 PnvMachineState *pnv = PNV_MACHINE(machine);
751 MachineClass *mc = MACHINE_GET_CLASS(machine);
752 char *fw_filename;
753 long fw_size;
754 uint64_t chip_ram_start = 0;
755 int i;
756 char *chip_typename;
757 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
758 DeviceState *dev;
759
760 if (kvm_enabled()) {
761 error_report("The powernv machine does not work with KVM acceleration");
762 exit(EXIT_FAILURE);
763 }
764
765 /* allocate RAM */
766 if (machine->ram_size < mc->default_ram_size) {
767 char *sz = size_to_str(mc->default_ram_size);
768 error_report("Invalid RAM size, should be bigger than %s", sz);
769 g_free(sz);
770 exit(EXIT_FAILURE);
771 }
772 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
773
774 /*
775 * Create our simple PNOR device
776 */
777 dev = qdev_new(TYPE_PNV_PNOR);
778 if (pnor) {
779 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
780 }
781 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
782 pnv->pnor = PNV_PNOR(dev);
783
784 /* load skiboot firmware */
785 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
786 if (!fw_filename) {
787 error_report("Could not find OPAL firmware '%s'", bios_name);
788 exit(1);
789 }
790
791 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
792 if (fw_size < 0) {
793 error_report("Could not load OPAL firmware '%s'", fw_filename);
794 exit(1);
795 }
796 g_free(fw_filename);
797
798 /* load kernel */
799 if (machine->kernel_filename) {
800 long kernel_size;
801
802 kernel_size = load_image_targphys(machine->kernel_filename,
803 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
804 if (kernel_size < 0) {
805 error_report("Could not load kernel '%s'",
806 machine->kernel_filename);
807 exit(1);
808 }
809 }
810
811 /* load initrd */
812 if (machine->initrd_filename) {
813 pnv->initrd_base = INITRD_LOAD_ADDR;
814 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
815 pnv->initrd_base, INITRD_MAX_SIZE);
816 if (pnv->initrd_size < 0) {
817 error_report("Could not load initial ram disk '%s'",
818 machine->initrd_filename);
819 exit(1);
820 }
821 }
822
823 /* MSIs are supported on this platform */
824 msi_nonbroken = true;
825
826 /*
827 * Check compatibility of the specified CPU with the machine
828 * default.
829 */
830 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
831 error_report("invalid CPU model '%s' for %s machine",
832 machine->cpu_type, mc->name);
833 exit(1);
834 }
835
836 /* Create the processor chips */
837 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
838 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
839 i, machine->cpu_type);
840 if (!object_class_by_name(chip_typename)) {
841 error_report("invalid chip model '%.*s' for %s machine",
842 i, machine->cpu_type, mc->name);
843 exit(1);
844 }
845
846 pnv->num_chips =
847 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
848 /*
849 * TODO: should we decide on how many chips we can create based
850 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
851 */
852 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
853 error_report("invalid number of chips: '%d'", pnv->num_chips);
854 error_printf(
855 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
856 exit(1);
857 }
858
859 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
860 for (i = 0; i < pnv->num_chips; i++) {
861 char chip_name[32];
862 Object *chip = OBJECT(qdev_new(chip_typename));
863 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i);
864
865 pnv->chips[i] = PNV_CHIP(chip);
866
867 /* Distribute RAM among the chips */
868 object_property_set_int(chip, "ram-start", chip_ram_start,
869 &error_fatal);
870 object_property_set_int(chip, "ram-size", chip_ram_size,
871 &error_fatal);
872 chip_ram_start += chip_ram_size;
873
874 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
875 object_property_add_child(OBJECT(pnv), chip_name, chip);
876 object_property_set_int(chip, "chip-id", i, &error_fatal);
877 object_property_set_int(chip, "nr-cores", machine->smp.cores,
878 &error_fatal);
879 object_property_set_int(chip, "nr-threads", machine->smp.threads,
880 &error_fatal);
881 /*
882 * The POWER8 machine use the XICS interrupt interface.
883 * Propagate the XICS fabric to the chip and its controllers.
884 */
885 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
886 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
887 }
888 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
889 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
890 &error_abort);
891 }
892 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
893 }
894 g_free(chip_typename);
895
896 /* Instantiate ISA bus on chip 0 */
897 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
898
899 /* Create serial port */
900 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
901
902 /* Create an RTC ISA device too */
903 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
904
905 /*
906 * Create the machine BMC simulator and the IPMI BT device for
907 * communication with the BMC
908 */
909 if (defaults_enabled()) {
910 pnv->bmc = pnv_bmc_create(pnv->pnor);
911 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
912 }
913
914 /*
915 * The PNOR is mapped on the LPC FW address space by the BMC.
916 * Since we can not reach the remote BMC machine with LPC memops,
917 * map it always for now.
918 */
919 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
920 &pnv->pnor->mmio);
921
922 /*
923 * OpenPOWER systems use a IPMI SEL Event message to notify the
924 * host to powerdown
925 */
926 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
927 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
928 }
929
930 /*
931 * 0:21 Reserved - Read as zeros
932 * 22:24 Chip ID
933 * 25:28 Core number
934 * 29:31 Thread ID
935 */
936 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
937 {
938 return (chip->chip_id << 7) | (core_id << 3);
939 }
940
941 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
942 Error **errp)
943 {
944 Pnv8Chip *chip8 = PNV8_CHIP(chip);
945 Error *local_err = NULL;
946 Object *obj;
947 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
948
949 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
950 if (local_err) {
951 error_propagate(errp, local_err);
952 return;
953 }
954
955 pnv_cpu->intc = obj;
956 }
957
958
959 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
960 {
961 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
962
963 icp_reset(ICP(pnv_cpu->intc));
964 }
965
966 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
967 {
968 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
969
970 icp_destroy(ICP(pnv_cpu->intc));
971 pnv_cpu->intc = NULL;
972 }
973
974 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
975 Monitor *mon)
976 {
977 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
978 }
979
980 /*
981 * 0:48 Reserved - Read as zeroes
982 * 49:52 Node ID
983 * 53:55 Chip ID
984 * 56 Reserved - Read as zero
985 * 57:61 Core number
986 * 62:63 Thread ID
987 *
988 * We only care about the lower bits. uint32_t is fine for the moment.
989 */
990 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
991 {
992 return (chip->chip_id << 8) | (core_id << 2);
993 }
994
995 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
996 {
997 return (chip->chip_id << 8) | (core_id << 2);
998 }
999
1000 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1001 Error **errp)
1002 {
1003 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1004 Error *local_err = NULL;
1005 Object *obj;
1006 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1007
1008 /*
1009 * The core creates its interrupt presenter but the XIVE interrupt
1010 * controller object is initialized afterwards. Hopefully, it's
1011 * only used at runtime.
1012 */
1013 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
1014 &local_err);
1015 if (local_err) {
1016 error_propagate(errp, local_err);
1017 return;
1018 }
1019
1020 pnv_cpu->intc = obj;
1021 }
1022
1023 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1024 {
1025 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1026
1027 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1028 }
1029
1030 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1031 {
1032 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1033
1034 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1035 pnv_cpu->intc = NULL;
1036 }
1037
1038 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1039 Monitor *mon)
1040 {
1041 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1042 }
1043
1044 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1045 Error **errp)
1046 {
1047 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1048
1049 /* Will be defined when the interrupt controller is */
1050 pnv_cpu->intc = NULL;
1051 }
1052
1053 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1054 {
1055 ;
1056 }
1057
1058 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1059 {
1060 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1061
1062 pnv_cpu->intc = NULL;
1063 }
1064
1065 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1066 Monitor *mon)
1067 {
1068 }
1069
1070 /*
1071 * Allowed core identifiers on a POWER8 Processor Chip :
1072 *
1073 * <EX0 reserved>
1074 * EX1 - Venice only
1075 * EX2 - Venice only
1076 * EX3 - Venice only
1077 * EX4
1078 * EX5
1079 * EX6
1080 * <EX7,8 reserved> <reserved>
1081 * EX9 - Venice only
1082 * EX10 - Venice only
1083 * EX11 - Venice only
1084 * EX12
1085 * EX13
1086 * EX14
1087 * <EX15 reserved>
1088 */
1089 #define POWER8E_CORE_MASK (0x7070ull)
1090 #define POWER8_CORE_MASK (0x7e7eull)
1091
1092 /*
1093 * POWER9 has 24 cores, ids starting at 0x0
1094 */
1095 #define POWER9_CORE_MASK (0xffffffffffffffull)
1096
1097
1098 #define POWER10_CORE_MASK (0xffffffffffffffull)
1099
1100 static void pnv_chip_power8_instance_init(Object *obj)
1101 {
1102 PnvChip *chip = PNV_CHIP(obj);
1103 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1104 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1105 int i;
1106
1107 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1108 (Object **)&chip8->xics,
1109 object_property_allow_set_link,
1110 OBJ_PROP_LINK_STRONG);
1111
1112 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1113
1114 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1115
1116 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1117
1118 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1119
1120 if (defaults_enabled()) {
1121 chip->num_phbs = pcc->num_phbs;
1122 }
1123
1124 for (i = 0; i < chip->num_phbs; i++) {
1125 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3);
1126 }
1127
1128 }
1129
1130 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1131 {
1132 PnvChip *chip = PNV_CHIP(chip8);
1133 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1134 int i, j;
1135 char *name;
1136
1137 name = g_strdup_printf("icp-%x", chip->chip_id);
1138 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1139 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1140 g_free(name);
1141
1142 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1143
1144 /* Map the ICP registers for each thread */
1145 for (i = 0; i < chip->nr_cores; i++) {
1146 PnvCore *pnv_core = chip->cores[i];
1147 int core_hwid = CPU_CORE(pnv_core)->core_id;
1148
1149 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1150 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1151 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1152
1153 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1154 &icp->mmio);
1155 }
1156 }
1157 }
1158
1159 /* Attach a root port device */
1160 void pnv_phb_attach_root_port(PCIHostState *pci, const char *name)
1161 {
1162 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name);
1163
1164 pci_realize_and_unref(root, pci->bus, &error_fatal);
1165 }
1166
1167 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1168 {
1169 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1170 PnvChip *chip = PNV_CHIP(dev);
1171 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1172 Pnv8Psi *psi8 = &chip8->psi;
1173 Error *local_err = NULL;
1174 int i;
1175
1176 assert(chip8->xics);
1177
1178 /* XSCOM bridge is first */
1179 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1180 if (local_err) {
1181 error_propagate(errp, local_err);
1182 return;
1183 }
1184 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1185
1186 pcc->parent_realize(dev, &local_err);
1187 if (local_err) {
1188 error_propagate(errp, local_err);
1189 return;
1190 }
1191
1192 /* Processor Service Interface (PSI) Host Bridge */
1193 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip),
1194 &error_fatal);
1195 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS,
1196 OBJECT(chip8->xics), &error_abort);
1197 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) {
1198 return;
1199 }
1200 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1201 &PNV_PSI(psi8)->xscom_regs);
1202
1203 /* Create LPC controller */
1204 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi),
1205 &error_abort);
1206 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1207 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1208
1209 chip->fw_mr = &chip8->lpc.isa_fw;
1210 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1211 (uint64_t) PNV_XSCOM_BASE(chip),
1212 PNV_XSCOM_LPC_BASE);
1213
1214 /*
1215 * Interrupt Management Area. This is the memory region holding
1216 * all the Interrupt Control Presenter (ICP) registers
1217 */
1218 pnv_chip_icp_realize(chip8, &local_err);
1219 if (local_err) {
1220 error_propagate(errp, local_err);
1221 return;
1222 }
1223
1224 /* Create the simplified OCC model */
1225 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi),
1226 &error_abort);
1227 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1228 return;
1229 }
1230 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1231
1232 /* OCC SRAM model */
1233 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1234 &chip8->occ.sram_regs);
1235
1236 /* HOMER */
1237 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1238 &error_abort);
1239 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1240 return;
1241 }
1242 /* Homer Xscom region */
1243 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1244
1245 /* Homer mmio region */
1246 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1247 &chip8->homer.regs);
1248
1249 /* PHB3 controllers */
1250 for (i = 0; i < chip->num_phbs; i++) {
1251 PnvPHB3 *phb = &chip8->phbs[i];
1252
1253 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1254 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1255 &error_fatal);
1256 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
1257 &error_fatal);
1258 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1259 return;
1260 }
1261 }
1262 }
1263
1264 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1265 {
1266 addr &= (PNV_XSCOM_SIZE - 1);
1267 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1268 }
1269
1270 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1271 {
1272 DeviceClass *dc = DEVICE_CLASS(klass);
1273 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1274
1275 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1276 k->cores_mask = POWER8E_CORE_MASK;
1277 k->num_phbs = 3;
1278 k->core_pir = pnv_chip_core_pir_p8;
1279 k->intc_create = pnv_chip_power8_intc_create;
1280 k->intc_reset = pnv_chip_power8_intc_reset;
1281 k->intc_destroy = pnv_chip_power8_intc_destroy;
1282 k->intc_print_info = pnv_chip_power8_intc_print_info;
1283 k->isa_create = pnv_chip_power8_isa_create;
1284 k->dt_populate = pnv_chip_power8_dt_populate;
1285 k->pic_print_info = pnv_chip_power8_pic_print_info;
1286 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1287 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1288 dc->desc = "PowerNV Chip POWER8E";
1289
1290 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1291 &k->parent_realize);
1292 }
1293
1294 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1295 {
1296 DeviceClass *dc = DEVICE_CLASS(klass);
1297 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1298
1299 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1300 k->cores_mask = POWER8_CORE_MASK;
1301 k->num_phbs = 3;
1302 k->core_pir = pnv_chip_core_pir_p8;
1303 k->intc_create = pnv_chip_power8_intc_create;
1304 k->intc_reset = pnv_chip_power8_intc_reset;
1305 k->intc_destroy = pnv_chip_power8_intc_destroy;
1306 k->intc_print_info = pnv_chip_power8_intc_print_info;
1307 k->isa_create = pnv_chip_power8_isa_create;
1308 k->dt_populate = pnv_chip_power8_dt_populate;
1309 k->pic_print_info = pnv_chip_power8_pic_print_info;
1310 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1311 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1312 dc->desc = "PowerNV Chip POWER8";
1313
1314 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1315 &k->parent_realize);
1316 }
1317
1318 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1319 {
1320 DeviceClass *dc = DEVICE_CLASS(klass);
1321 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1322
1323 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1324 k->cores_mask = POWER8_CORE_MASK;
1325 k->num_phbs = 4;
1326 k->core_pir = pnv_chip_core_pir_p8;
1327 k->intc_create = pnv_chip_power8_intc_create;
1328 k->intc_reset = pnv_chip_power8_intc_reset;
1329 k->intc_destroy = pnv_chip_power8_intc_destroy;
1330 k->intc_print_info = pnv_chip_power8_intc_print_info;
1331 k->isa_create = pnv_chip_power8nvl_isa_create;
1332 k->dt_populate = pnv_chip_power8_dt_populate;
1333 k->pic_print_info = pnv_chip_power8_pic_print_info;
1334 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1335 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1336 dc->desc = "PowerNV Chip POWER8NVL";
1337
1338 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1339 &k->parent_realize);
1340 }
1341
1342 static void pnv_chip_power9_instance_init(Object *obj)
1343 {
1344 PnvChip *chip = PNV_CHIP(obj);
1345 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1346 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1347 int i;
1348
1349 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1350 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1351 "xive-fabric");
1352
1353 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1354
1355 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1356
1357 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1358
1359 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1360
1361 /* Number of PECs is the chip default */
1362 chip->num_pecs = pcc->num_pecs;
1363
1364 for (i = 0; i < chip->num_pecs; i++) {
1365 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1366 TYPE_PNV_PHB4_PEC);
1367 }
1368 }
1369
1370 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1371 {
1372 PnvChip *chip = PNV_CHIP(chip9);
1373 int i;
1374
1375 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1376 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1377
1378 for (i = 0; i < chip9->nr_quads; i++) {
1379 char eq_name[32];
1380 PnvQuad *eq = &chip9->quads[i];
1381 PnvCore *pnv_core = chip->cores[i * 4];
1382 int core_id = CPU_CORE(pnv_core)->core_id;
1383
1384 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1385 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1386 sizeof(*eq), TYPE_PNV_QUAD,
1387 &error_fatal, NULL);
1388
1389 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
1390 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1391
1392 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
1393 &eq->xscom_regs);
1394 }
1395 }
1396
1397 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
1398 {
1399 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1400 int i;
1401
1402 for (i = 0; i < chip->num_pecs; i++) {
1403 PnvPhb4PecState *pec = &chip9->pecs[i];
1404 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1405 uint32_t pec_nest_base;
1406 uint32_t pec_pci_base;
1407
1408 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1409 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1410 &error_fatal);
1411 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1412 &error_fatal);
1413 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1414 return;
1415 }
1416
1417 pec_nest_base = pecc->xscom_nest_base(pec);
1418 pec_pci_base = pecc->xscom_pci_base(pec);
1419
1420 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1421 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1422 }
1423 }
1424
1425 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1426 {
1427 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1428 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1429 PnvChip *chip = PNV_CHIP(dev);
1430 Pnv9Psi *psi9 = &chip9->psi;
1431 Error *local_err = NULL;
1432
1433 /* XSCOM bridge is first */
1434 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1435 if (local_err) {
1436 error_propagate(errp, local_err);
1437 return;
1438 }
1439 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1440
1441 pcc->parent_realize(dev, &local_err);
1442 if (local_err) {
1443 error_propagate(errp, local_err);
1444 return;
1445 }
1446
1447 pnv_chip_quad_realize(chip9, &local_err);
1448 if (local_err) {
1449 error_propagate(errp, local_err);
1450 return;
1451 }
1452
1453 /* XIVE interrupt controller (POWER9) */
1454 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1455 PNV9_XIVE_IC_BASE(chip), &error_fatal);
1456 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1457 PNV9_XIVE_VC_BASE(chip), &error_fatal);
1458 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1459 PNV9_XIVE_PC_BASE(chip), &error_fatal);
1460 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1461 PNV9_XIVE_TM_BASE(chip), &error_fatal);
1462 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1463 &error_abort);
1464 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1465 return;
1466 }
1467 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1468 &chip9->xive.xscom_regs);
1469
1470 /* Processor Service Interface (PSI) Host Bridge */
1471 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
1472 &error_fatal);
1473 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
1474 return;
1475 }
1476 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1477 &PNV_PSI(psi9)->xscom_regs);
1478
1479 /* LPC */
1480 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi),
1481 &error_abort);
1482 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1483 return;
1484 }
1485 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1486 &chip9->lpc.xscom_regs);
1487
1488 chip->fw_mr = &chip9->lpc.isa_fw;
1489 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1490 (uint64_t) PNV9_LPCM_BASE(chip));
1491
1492 /* Create the simplified OCC model */
1493 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi),
1494 &error_abort);
1495 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1496 return;
1497 }
1498 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1499
1500 /* OCC SRAM model */
1501 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1502 &chip9->occ.sram_regs);
1503
1504 /* HOMER */
1505 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1506 &error_abort);
1507 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1508 return;
1509 }
1510 /* Homer Xscom region */
1511 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1512
1513 /* Homer mmio region */
1514 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1515 &chip9->homer.regs);
1516
1517 /* PEC PHBs */
1518 pnv_chip_power9_pec_realize(chip, &local_err);
1519 if (local_err) {
1520 error_propagate(errp, local_err);
1521 return;
1522 }
1523 }
1524
1525 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1526 {
1527 addr &= (PNV9_XSCOM_SIZE - 1);
1528 return addr >> 3;
1529 }
1530
1531 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1532 {
1533 DeviceClass *dc = DEVICE_CLASS(klass);
1534 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1535
1536 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1537 k->cores_mask = POWER9_CORE_MASK;
1538 k->core_pir = pnv_chip_core_pir_p9;
1539 k->intc_create = pnv_chip_power9_intc_create;
1540 k->intc_reset = pnv_chip_power9_intc_reset;
1541 k->intc_destroy = pnv_chip_power9_intc_destroy;
1542 k->intc_print_info = pnv_chip_power9_intc_print_info;
1543 k->isa_create = pnv_chip_power9_isa_create;
1544 k->dt_populate = pnv_chip_power9_dt_populate;
1545 k->pic_print_info = pnv_chip_power9_pic_print_info;
1546 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1547 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1548 dc->desc = "PowerNV Chip POWER9";
1549 k->num_pecs = PNV9_CHIP_MAX_PEC;
1550
1551 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1552 &k->parent_realize);
1553 }
1554
1555 static void pnv_chip_power10_instance_init(Object *obj)
1556 {
1557 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1558
1559 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1560 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1561 }
1562
1563 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1564 {
1565 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1566 PnvChip *chip = PNV_CHIP(dev);
1567 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1568 Error *local_err = NULL;
1569
1570 /* XSCOM bridge is first */
1571 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1572 if (local_err) {
1573 error_propagate(errp, local_err);
1574 return;
1575 }
1576 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1577
1578 pcc->parent_realize(dev, &local_err);
1579 if (local_err) {
1580 error_propagate(errp, local_err);
1581 return;
1582 }
1583
1584 /* Processor Service Interface (PSI) Host Bridge */
1585 object_property_set_int(OBJECT(&chip10->psi), "bar",
1586 PNV10_PSIHB_BASE(chip), &error_fatal);
1587 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
1588 return;
1589 }
1590 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1591 &PNV_PSI(&chip10->psi)->xscom_regs);
1592
1593 /* LPC */
1594 object_property_set_link(OBJECT(&chip10->lpc), "psi",
1595 OBJECT(&chip10->psi), &error_abort);
1596 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
1597 return;
1598 }
1599 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1600 &chip10->lpc.xscom_regs);
1601
1602 chip->fw_mr = &chip10->lpc.isa_fw;
1603 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1604 (uint64_t) PNV10_LPCM_BASE(chip));
1605 }
1606
1607 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1608 {
1609 addr &= (PNV10_XSCOM_SIZE - 1);
1610 return addr >> 3;
1611 }
1612
1613 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1614 {
1615 DeviceClass *dc = DEVICE_CLASS(klass);
1616 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1617
1618 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1619 k->cores_mask = POWER10_CORE_MASK;
1620 k->core_pir = pnv_chip_core_pir_p10;
1621 k->intc_create = pnv_chip_power10_intc_create;
1622 k->intc_reset = pnv_chip_power10_intc_reset;
1623 k->intc_destroy = pnv_chip_power10_intc_destroy;
1624 k->intc_print_info = pnv_chip_power10_intc_print_info;
1625 k->isa_create = pnv_chip_power10_isa_create;
1626 k->dt_populate = pnv_chip_power10_dt_populate;
1627 k->pic_print_info = pnv_chip_power10_pic_print_info;
1628 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1629 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1630 dc->desc = "PowerNV Chip POWER10";
1631
1632 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1633 &k->parent_realize);
1634 }
1635
1636 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1637 {
1638 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1639 int cores_max;
1640
1641 /*
1642 * No custom mask for this chip, let's use the default one from *
1643 * the chip class
1644 */
1645 if (!chip->cores_mask) {
1646 chip->cores_mask = pcc->cores_mask;
1647 }
1648
1649 /* filter alien core ids ! some are reserved */
1650 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1651 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1652 chip->cores_mask);
1653 return;
1654 }
1655 chip->cores_mask &= pcc->cores_mask;
1656
1657 /* now that we have a sane layout, let check the number of cores */
1658 cores_max = ctpop64(chip->cores_mask);
1659 if (chip->nr_cores > cores_max) {
1660 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1661 cores_max);
1662 return;
1663 }
1664 }
1665
1666 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1667 {
1668 Error *error = NULL;
1669 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1670 const char *typename = pnv_chip_core_typename(chip);
1671 int i, core_hwid;
1672 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1673
1674 if (!object_class_by_name(typename)) {
1675 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1676 return;
1677 }
1678
1679 /* Cores */
1680 pnv_chip_core_sanitize(chip, &error);
1681 if (error) {
1682 error_propagate(errp, error);
1683 return;
1684 }
1685
1686 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1687
1688 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1689 && (i < chip->nr_cores); core_hwid++) {
1690 char core_name[32];
1691 PnvCore *pnv_core;
1692 uint64_t xscom_core_base;
1693
1694 if (!(chip->cores_mask & (1ull << core_hwid))) {
1695 continue;
1696 }
1697
1698 pnv_core = PNV_CORE(object_new(typename));
1699
1700 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1701 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
1702 chip->cores[i] = pnv_core;
1703 object_property_set_int(OBJECT(pnv_core), "nr-threads",
1704 chip->nr_threads, &error_fatal);
1705 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
1706 core_hwid, &error_fatal);
1707 object_property_set_int(OBJECT(pnv_core), "pir",
1708 pcc->core_pir(chip, core_hwid), &error_fatal);
1709 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
1710 &error_fatal);
1711 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
1712 &error_abort);
1713 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
1714
1715 /* Each core has an XSCOM MMIO region */
1716 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1717
1718 pnv_xscom_add_subregion(chip, xscom_core_base,
1719 &pnv_core->xscom_regs);
1720 i++;
1721 }
1722 }
1723
1724 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1725 {
1726 PnvChip *chip = PNV_CHIP(dev);
1727 Error *error = NULL;
1728
1729 /* Cores */
1730 pnv_chip_core_realize(chip, &error);
1731 if (error) {
1732 error_propagate(errp, error);
1733 return;
1734 }
1735 }
1736
1737 static Property pnv_chip_properties[] = {
1738 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1739 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1740 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1741 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1742 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1743 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
1744 DEFINE_PROP_END_OF_LIST(),
1745 };
1746
1747 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1748 {
1749 DeviceClass *dc = DEVICE_CLASS(klass);
1750
1751 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1752 dc->realize = pnv_chip_realize;
1753 device_class_set_props(dc, pnv_chip_properties);
1754 dc->desc = "PowerNV Chip";
1755 }
1756
1757 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
1758 {
1759 int i, j;
1760
1761 for (i = 0; i < chip->nr_cores; i++) {
1762 PnvCore *pc = chip->cores[i];
1763 CPUCore *cc = CPU_CORE(pc);
1764
1765 for (j = 0; j < cc->nr_threads; j++) {
1766 if (ppc_cpu_pir(pc->threads[j]) == pir) {
1767 return pc->threads[j];
1768 }
1769 }
1770 }
1771 return NULL;
1772 }
1773
1774 typedef struct ForeachPhb3Args {
1775 int irq;
1776 ICSState *ics;
1777 } ForeachPhb3Args;
1778
1779 static int pnv_ics_get_child(Object *child, void *opaque)
1780 {
1781 ForeachPhb3Args *args = opaque;
1782 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
1783
1784 if (phb3) {
1785 if (ics_valid_irq(&phb3->lsis, args->irq)) {
1786 args->ics = &phb3->lsis;
1787 }
1788 if (ics_valid_irq(ICS(&phb3->msis), args->irq)) {
1789 args->ics = ICS(&phb3->msis);
1790 }
1791 }
1792 return args->ics ? 1 : 0;
1793 }
1794
1795 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
1796 {
1797 PnvMachineState *pnv = PNV_MACHINE(xi);
1798 ForeachPhb3Args args = { irq, NULL };
1799 int i;
1800
1801 for (i = 0; i < pnv->num_chips; i++) {
1802 PnvChip *chip = pnv->chips[i];
1803 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1804
1805 if (ics_valid_irq(&chip8->psi.ics, irq)) {
1806 return &chip8->psi.ics;
1807 }
1808
1809 object_child_foreach(OBJECT(chip), pnv_ics_get_child, &args);
1810 if (args.ics) {
1811 return args.ics;
1812 }
1813 }
1814 return NULL;
1815 }
1816
1817 void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index)
1818 {
1819 Object *parent = OBJECT(chip);
1820 g_autofree char *default_id =
1821 g_strdup_printf("%s[%d]", object_get_typename(obj), index);
1822
1823 if (obj->parent == parent) {
1824 return;
1825 }
1826
1827 object_ref(obj);
1828 object_unparent(obj);
1829 object_property_add_child(
1830 parent, DEVICE(obj)->id ? DEVICE(obj)->id : default_id, obj);
1831 object_unref(obj);
1832 }
1833
1834 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
1835 {
1836 int i;
1837
1838 for (i = 0; i < pnv->num_chips; i++) {
1839 PnvChip *chip = pnv->chips[i];
1840 if (chip->chip_id == chip_id) {
1841 return chip;
1842 }
1843 }
1844 return NULL;
1845 }
1846
1847 static int pnv_ics_resend_child(Object *child, void *opaque)
1848 {
1849 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3);
1850
1851 if (phb3) {
1852 ics_resend(&phb3->lsis);
1853 ics_resend(ICS(&phb3->msis));
1854 }
1855 return 0;
1856 }
1857
1858 static void pnv_ics_resend(XICSFabric *xi)
1859 {
1860 PnvMachineState *pnv = PNV_MACHINE(xi);
1861 int i;
1862
1863 for (i = 0; i < pnv->num_chips; i++) {
1864 PnvChip *chip = pnv->chips[i];
1865 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
1866
1867 ics_resend(&chip8->psi.ics);
1868 object_child_foreach(OBJECT(chip), pnv_ics_resend_child, NULL);
1869 }
1870 }
1871
1872 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
1873 {
1874 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
1875
1876 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
1877 }
1878
1879 static void pnv_pic_print_info(InterruptStatsProvider *obj,
1880 Monitor *mon)
1881 {
1882 PnvMachineState *pnv = PNV_MACHINE(obj);
1883 int i;
1884 CPUState *cs;
1885
1886 CPU_FOREACH(cs) {
1887 PowerPCCPU *cpu = POWERPC_CPU(cs);
1888
1889 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
1890 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
1891 mon);
1892 }
1893
1894 for (i = 0; i < pnv->num_chips; i++) {
1895 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
1896 }
1897 }
1898
1899 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
1900 uint8_t nvt_blk, uint32_t nvt_idx,
1901 bool cam_ignore, uint8_t priority,
1902 uint32_t logic_serv,
1903 XiveTCTXMatch *match)
1904 {
1905 PnvMachineState *pnv = PNV_MACHINE(xfb);
1906 int total_count = 0;
1907 int i;
1908
1909 for (i = 0; i < pnv->num_chips; i++) {
1910 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
1911 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
1912 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
1913 int count;
1914
1915 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
1916 priority, logic_serv, match);
1917
1918 if (count < 0) {
1919 return count;
1920 }
1921
1922 total_count += count;
1923 }
1924
1925 return total_count;
1926 }
1927
1928 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
1929 {
1930 MachineClass *mc = MACHINE_CLASS(oc);
1931 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
1932 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1933 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
1934
1935 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
1936 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
1937
1938 xic->icp_get = pnv_icp_get;
1939 xic->ics_get = pnv_ics_get;
1940 xic->ics_resend = pnv_ics_resend;
1941
1942 pmc->compat = compat;
1943 pmc->compat_size = sizeof(compat);
1944
1945 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB3);
1946 }
1947
1948 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
1949 {
1950 MachineClass *mc = MACHINE_CLASS(oc);
1951 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
1952 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1953 static const char compat[] = "qemu,powernv9\0ibm,powernv";
1954
1955 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
1956 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
1957 xfc->match_nvt = pnv_match_nvt;
1958
1959 mc->alias = "powernv";
1960
1961 pmc->compat = compat;
1962 pmc->compat_size = sizeof(compat);
1963 pmc->dt_power_mgt = pnv_dt_power_mgt;
1964 }
1965
1966 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
1967 {
1968 MachineClass *mc = MACHINE_CLASS(oc);
1969 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
1970 static const char compat[] = "qemu,powernv10\0ibm,powernv";
1971
1972 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
1973 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
1974
1975 pmc->compat = compat;
1976 pmc->compat_size = sizeof(compat);
1977 pmc->dt_power_mgt = pnv_dt_power_mgt;
1978 }
1979
1980 static bool pnv_machine_get_hb(Object *obj, Error **errp)
1981 {
1982 PnvMachineState *pnv = PNV_MACHINE(obj);
1983
1984 return !!pnv->fw_load_addr;
1985 }
1986
1987 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
1988 {
1989 PnvMachineState *pnv = PNV_MACHINE(obj);
1990
1991 if (value) {
1992 pnv->fw_load_addr = 0x8000000;
1993 }
1994 }
1995
1996 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
1997 {
1998 PowerPCCPU *cpu = POWERPC_CPU(cs);
1999 CPUPPCState *env = &cpu->env;
2000
2001 cpu_synchronize_state(cs);
2002 ppc_cpu_do_system_reset(cs);
2003 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
2004 /*
2005 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2006 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2007 * (PPC_BIT(43)).
2008 */
2009 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
2010 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2011 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
2012 }
2013 } else {
2014 /*
2015 * For non-powersave system resets, SRR1[42:45] are defined to be
2016 * implementation-dependent. The POWER9 User Manual specifies that
2017 * an external (SCOM driven, which may come from a BMC nmi command or
2018 * another CPU requesting a NMI IPI) system reset exception should be
2019 * 0b0010 (PPC_BIT(44)).
2020 */
2021 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
2022 }
2023 }
2024
2025 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
2026 {
2027 CPUState *cs;
2028
2029 CPU_FOREACH(cs) {
2030 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2031 }
2032 }
2033
2034 static void pnv_machine_class_init(ObjectClass *oc, void *data)
2035 {
2036 MachineClass *mc = MACHINE_CLASS(oc);
2037 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
2038 NMIClass *nc = NMI_CLASS(oc);
2039
2040 mc->desc = "IBM PowerNV (Non-Virtualized)";
2041 mc->init = pnv_init;
2042 mc->reset = pnv_reset;
2043 mc->max_cpus = MAX_CPUS;
2044 /* Pnv provides a AHCI device for storage */
2045 mc->block_default_type = IF_IDE;
2046 mc->no_parallel = 1;
2047 mc->default_boot_order = NULL;
2048 /*
2049 * RAM defaults to less than 2048 for 32-bit hosts, and large
2050 * enough to fit the maximum initrd size at it's load address
2051 */
2052 mc->default_ram_size = 1 * GiB;
2053 mc->default_ram_id = "pnv.ram";
2054 ispc->print_info = pnv_pic_print_info;
2055 nc->nmi_monitor_handler = pnv_nmi;
2056
2057 object_class_property_add_bool(oc, "hb-mode",
2058 pnv_machine_get_hb, pnv_machine_set_hb);
2059 object_class_property_set_description(oc, "hb-mode",
2060 "Use a hostboot like boot loader");
2061 }
2062
2063 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2064 { \
2065 .name = type, \
2066 .class_init = class_initfn, \
2067 .parent = TYPE_PNV8_CHIP, \
2068 }
2069
2070 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2071 { \
2072 .name = type, \
2073 .class_init = class_initfn, \
2074 .parent = TYPE_PNV9_CHIP, \
2075 }
2076
2077 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2078 { \
2079 .name = type, \
2080 .class_init = class_initfn, \
2081 .parent = TYPE_PNV10_CHIP, \
2082 }
2083
2084 static const TypeInfo types[] = {
2085 {
2086 .name = MACHINE_TYPE_NAME("powernv10"),
2087 .parent = TYPE_PNV_MACHINE,
2088 .class_init = pnv_machine_power10_class_init,
2089 },
2090 {
2091 .name = MACHINE_TYPE_NAME("powernv9"),
2092 .parent = TYPE_PNV_MACHINE,
2093 .class_init = pnv_machine_power9_class_init,
2094 .interfaces = (InterfaceInfo[]) {
2095 { TYPE_XIVE_FABRIC },
2096 { },
2097 },
2098 },
2099 {
2100 .name = MACHINE_TYPE_NAME("powernv8"),
2101 .parent = TYPE_PNV_MACHINE,
2102 .class_init = pnv_machine_power8_class_init,
2103 .interfaces = (InterfaceInfo[]) {
2104 { TYPE_XICS_FABRIC },
2105 { },
2106 },
2107 },
2108 {
2109 .name = TYPE_PNV_MACHINE,
2110 .parent = TYPE_MACHINE,
2111 .abstract = true,
2112 .instance_size = sizeof(PnvMachineState),
2113 .class_init = pnv_machine_class_init,
2114 .class_size = sizeof(PnvMachineClass),
2115 .interfaces = (InterfaceInfo[]) {
2116 { TYPE_INTERRUPT_STATS_PROVIDER },
2117 { TYPE_NMI },
2118 { },
2119 },
2120 },
2121 {
2122 .name = TYPE_PNV_CHIP,
2123 .parent = TYPE_SYS_BUS_DEVICE,
2124 .class_init = pnv_chip_class_init,
2125 .instance_size = sizeof(PnvChip),
2126 .class_size = sizeof(PnvChipClass),
2127 .abstract = true,
2128 },
2129
2130 /*
2131 * P10 chip and variants
2132 */
2133 {
2134 .name = TYPE_PNV10_CHIP,
2135 .parent = TYPE_PNV_CHIP,
2136 .instance_init = pnv_chip_power10_instance_init,
2137 .instance_size = sizeof(Pnv10Chip),
2138 },
2139 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2140
2141 /*
2142 * P9 chip and variants
2143 */
2144 {
2145 .name = TYPE_PNV9_CHIP,
2146 .parent = TYPE_PNV_CHIP,
2147 .instance_init = pnv_chip_power9_instance_init,
2148 .instance_size = sizeof(Pnv9Chip),
2149 },
2150 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2151
2152 /*
2153 * P8 chip and variants
2154 */
2155 {
2156 .name = TYPE_PNV8_CHIP,
2157 .parent = TYPE_PNV_CHIP,
2158 .instance_init = pnv_chip_power8_instance_init,
2159 .instance_size = sizeof(Pnv8Chip),
2160 },
2161 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2162 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2163 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2164 pnv_chip_power8nvl_class_init),
2165 };
2166
2167 DEFINE_TYPES(types)
QEmu