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ppc/pnv: Complete user created PHB3 devices
[qemu.git] / hw / pci-host / bonito.c
bloba57e81e3a97a933b3b1e03290da6f2b185c90d89
1 /*
2 * bonito north bridge support
3 *
4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org)
5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
6 *
7 * This code is licensed under the GNU GPL v2.
8 *
9 * Contributions after 2012-01-13 are licensed under the terms of the
10 * GNU GPL, version 2 or (at your option) any later version.
11 */
12
13 /*
14 * fuloong 2e mini pc has a bonito north bridge.
15 */
16
17 /*
18 * what is the meaning of devfn in qemu and IDSEL in bonito northbridge?
19 *
20 * devfn pci_slot<<3 + funno
21 * one pci bus can have 32 devices and each device can have 8 functions.
22 *
23 * In bonito north bridge, pci slot = IDSEL bit - 12.
24 * For example, PCI_IDSEL_VIA686B = 17,
25 * pci slot = 17-12=5
26 *
27 * so
28 * VT686B_FUN0's devfn = (5<<3)+0
29 * VT686B_FUN1's devfn = (5<<3)+1
30 *
31 * qemu also uses pci address for north bridge to access pci config register.
32 * bus_no [23:16]
33 * dev_no [15:11]
34 * fun_no [10:8]
35 * reg_no [7:2]
36 *
37 * so function bonito_sbridge_pciaddr for the translation from
38 * north bridge address to pci address.
39 */
40
41 #include "qemu/osdep.h"
42 #include "qemu/units.h"
43 #include "qapi/error.h"
44 #include "qemu/error-report.h"
45 #include "hw/pci/pci.h"
46 #include "hw/irq.h"
47 #include "hw/mips/mips.h"
48 #include "hw/pci/pci_host.h"
49 #include "migration/vmstate.h"
50 #include "sysemu/reset.h"
51 #include "sysemu/runstate.h"
52 #include "hw/misc/unimp.h"
53 #include "hw/registerfields.h"
54 #include "qom/object.h"
55 #include "trace.h"
56
57 /* #define DEBUG_BONITO */
58
59 #ifdef DEBUG_BONITO
60 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__)
61 #else
62 #define DPRINTF(fmt, ...)
63 #endif
64
65 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/
66 #define BONITO_BOOT_BASE 0x1fc00000
67 #define BONITO_BOOT_SIZE 0x00100000
68 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1)
69 #define BONITO_FLASH_BASE 0x1c000000
70 #define BONITO_FLASH_SIZE 0x03000000
71 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1)
72 #define BONITO_SOCKET_BASE 0x1f800000
73 #define BONITO_SOCKET_SIZE 0x00400000
74 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1)
75 #define BONITO_REG_BASE 0x1fe00000
76 #define BONITO_REG_SIZE 0x00040000
77 #define BONITO_REG_TOP (BONITO_REG_BASE + BONITO_REG_SIZE - 1)
78 #define BONITO_DEV_BASE 0x1ff00000
79 #define BONITO_DEV_SIZE 0x00100000
80 #define BONITO_DEV_TOP (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1)
81 #define BONITO_PCILO_BASE 0x10000000
82 #define BONITO_PCILO_BASE_VA 0xb0000000
83 #define BONITO_PCILO_SIZE 0x0c000000
84 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1)
85 #define BONITO_PCILO0_BASE 0x10000000
86 #define BONITO_PCILO1_BASE 0x14000000
87 #define BONITO_PCILO2_BASE 0x18000000
88 #define BONITO_PCIHI_BASE 0x20000000
89 #define BONITO_PCIHI_SIZE 0x60000000
90 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1)
91 #define BONITO_PCIIO_BASE 0x1fd00000
92 #define BONITO_PCIIO_BASE_VA 0xbfd00000
93 #define BONITO_PCIIO_SIZE 0x00010000
94 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1)
95 #define BONITO_PCICFG_BASE 0x1fe80000
96 #define BONITO_PCICFG_SIZE 0x00080000
97 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1)
98
99
100 #define BONITO_PCICONFIGBASE 0x00
101 #define BONITO_REGBASE 0x100
102
103 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE + BONITO_REG_BASE)
104 #define BONITO_PCICONFIG_SIZE (0x100)
105
106 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE + BONITO_REG_BASE)
107 #define BONITO_INTERNAL_REG_SIZE (0x70)
108
109 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE)
110 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE)
111
112
113
114 /* 1. Bonito h/w Configuration */
115 /* Power on register */
116
117 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */
118
119 /* PCI configuration register */
120 #define BONITO_BONGENCFG_OFFSET 0x4
121 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */
122 REG32(BONGENCFG, 0x104)
123 FIELD(BONGENCFG, DEBUGMODE, 0, 1)
124 FIELD(BONGENCFG, SNOOP, 1, 1)
125 FIELD(BONGENCFG, CPUSELFRESET, 2, 1)
126 FIELD(BONGENCFG, BYTESWAP, 6, 1)
127 FIELD(BONGENCFG, UNCACHED, 7, 1)
128 FIELD(BONGENCFG, PREFETCH, 8, 1)
129 FIELD(BONGENCFG, WRITEBEHIND, 9, 1)
130 FIELD(BONGENCFG, PCIQUEUE, 12, 1)
131
132 /* 2. IO & IDE configuration */
133 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */
134
135 /* 3. IO & IDE configuration */
136 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */
137
138 /* 4. PCI address map control */
139 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */
140 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */
141 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */
142
143 /* 5. ICU & GPIO regs */
144 /* GPIO Regs - r/w */
145 #define BONITO_GPIODATA_OFFSET 0x1c
146 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */
147 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */
148
149 /* ICU Configuration Regs - r/w */
150 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */
151 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */
152 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */
153
154 /* ICU Enable Regs - IntEn & IntISR are r/o. */
155 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */
156 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */
157 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */
158 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */
159
160 /* PCI mail boxes */
161 #define BONITO_PCIMAIL0_OFFSET 0x40
162 #define BONITO_PCIMAIL1_OFFSET 0x44
163 #define BONITO_PCIMAIL2_OFFSET 0x48
164 #define BONITO_PCIMAIL3_OFFSET 0x4c
165 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */
166 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */
167 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */
168 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */
169
170 /* 6. PCI cache */
171 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */
172 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */
173 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */
174 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */
175
176 /* 7. other*/
177 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */
178 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */
179 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */
180 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */
181
182 #define BONITO_REGS (0x70 >> 2)
183
184 /* PCI config for south bridge. type 0 */
185 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */
186 #define BONITO_PCICONF_IDSEL_OFFSET 11
187 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */
188 #define BONITO_PCICONF_FUN_OFFSET 8
189 #define BONITO_PCICONF_REG_MASK_DS (~3) /* Per datasheet */
190 #define BONITO_PCICONF_REG_MASK_HW 0xff /* As seen running PMON */
191 #define BONITO_PCICONF_REG_OFFSET 0
192
193
194 /* idsel BIT = pci slot number +12 */
195 #define PCI_SLOT_BASE 12
196 #define PCI_IDSEL_VIA686B_BIT (17)
197 #define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT)
198
199 #define PCI_ADDR(busno , devno , funno , regno) \
200 ((PCI_BUILD_BDF(busno, PCI_DEVFN(devno , funno)) << 8) + (regno))
201
202 typedef struct BonitoState BonitoState;
203
204 struct PCIBonitoState {
205 PCIDevice dev;
206
207 BonitoState *pcihost;
208 uint32_t regs[BONITO_REGS];
209
210 struct bonldma {
211 uint32_t ldmactrl;
212 uint32_t ldmastat;
213 uint32_t ldmaaddr;
214 uint32_t ldmago;
215 } bonldma;
216
217 /* Based at 1fe00300, bonito Copier */
218 struct boncop {
219 uint32_t copctrl;
220 uint32_t copstat;
221 uint32_t coppaddr;
222 uint32_t copgo;
223 } boncop;
224
225 /* Bonito registers */
226 MemoryRegion iomem;
227 MemoryRegion iomem_ldma;
228 MemoryRegion iomem_cop;
229 MemoryRegion bonito_pciio;
230 MemoryRegion bonito_localio;
231
232 };
233 typedef struct PCIBonitoState PCIBonitoState;
234
235 struct BonitoState {
236 PCIHostState parent_obj;
237 qemu_irq *pic;
238 PCIBonitoState *pci_dev;
239 MemoryRegion pci_mem;
240 };
241
242 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost"
243 OBJECT_DECLARE_SIMPLE_TYPE(BonitoState, BONITO_PCI_HOST_BRIDGE)
244
245 #define TYPE_PCI_BONITO "Bonito"
246 OBJECT_DECLARE_SIMPLE_TYPE(PCIBonitoState, PCI_BONITO)
247
248 static void bonito_writel(void *opaque, hwaddr addr,
249 uint64_t val, unsigned size)
250 {
251 PCIBonitoState *s = opaque;
252 uint32_t saddr;
253 int reset = 0;
254
255 saddr = addr >> 2;
256
257 DPRINTF("bonito_writel "TARGET_FMT_plx" val %lx saddr %x\n",
258 addr, val, saddr);
259 switch (saddr) {
260 case BONITO_BONPONCFG:
261 case BONITO_IODEVCFG:
262 case BONITO_SDCFG:
263 case BONITO_PCIMAP:
264 case BONITO_PCIMEMBASECFG:
265 case BONITO_PCIMAP_CFG:
266 case BONITO_GPIODATA:
267 case BONITO_GPIOIE:
268 case BONITO_INTEDGE:
269 case BONITO_INTSTEER:
270 case BONITO_INTPOL:
271 case BONITO_PCIMAIL0:
272 case BONITO_PCIMAIL1:
273 case BONITO_PCIMAIL2:
274 case BONITO_PCIMAIL3:
275 case BONITO_PCICACHECTRL:
276 case BONITO_PCICACHETAG:
277 case BONITO_PCIBADADDR:
278 case BONITO_PCIMSTAT:
279 case BONITO_TIMECFG:
280 case BONITO_CPUCFG:
281 case BONITO_DQCFG:
282 case BONITO_MEMSIZE:
283 s->regs[saddr] = val;
284 break;
285 case BONITO_BONGENCFG:
286 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) {
287 reset = 1; /* bit 2 jump from 0 to 1 cause reset */
288 }
289 s->regs[saddr] = val;
290 if (reset) {
291 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
292 }
293 break;
294 case BONITO_INTENSET:
295 s->regs[BONITO_INTENSET] = val;
296 s->regs[BONITO_INTEN] |= val;
297 break;
298 case BONITO_INTENCLR:
299 s->regs[BONITO_INTENCLR] = val;
300 s->regs[BONITO_INTEN] &= ~val;
301 break;
302 case BONITO_INTEN:
303 case BONITO_INTISR:
304 DPRINTF("write to readonly bonito register %x\n", saddr);
305 break;
306 default:
307 DPRINTF("write to unknown bonito register %x\n", saddr);
308 break;
309 }
310 }
311
312 static uint64_t bonito_readl(void *opaque, hwaddr addr,
313 unsigned size)
314 {
315 PCIBonitoState *s = opaque;
316 uint32_t saddr;
317
318 saddr = addr >> 2;
319
320 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr);
321 switch (saddr) {
322 case BONITO_INTISR:
323 return s->regs[saddr];
324 default:
325 return s->regs[saddr];
326 }
327 }
328
329 static const MemoryRegionOps bonito_ops = {
330 .read = bonito_readl,
331 .write = bonito_writel,
332 .endianness = DEVICE_NATIVE_ENDIAN,
333 .valid = {
334 .min_access_size = 4,
335 .max_access_size = 4,
336 },
337 };
338
339 static void bonito_pciconf_writel(void *opaque, hwaddr addr,
340 uint64_t val, unsigned size)
341 {
342 PCIBonitoState *s = opaque;
343 PCIDevice *d = PCI_DEVICE(s);
344
345 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %lx\n", addr, val);
346 d->config_write(d, addr, val, 4);
347 }
348
349 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr,
350 unsigned size)
351 {
352
353 PCIBonitoState *s = opaque;
354 PCIDevice *d = PCI_DEVICE(s);
355
356 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr);
357 return d->config_read(d, addr, 4);
358 }
359
360 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */
361
362 static const MemoryRegionOps bonito_pciconf_ops = {
363 .read = bonito_pciconf_readl,
364 .write = bonito_pciconf_writel,
365 .endianness = DEVICE_NATIVE_ENDIAN,
366 .valid = {
367 .min_access_size = 4,
368 .max_access_size = 4,
369 },
370 };
371
372 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr,
373 unsigned size)
374 {
375 uint32_t val;
376 PCIBonitoState *s = opaque;
377
378 if (addr >= sizeof(s->bonldma)) {
379 return 0;
380 }
381
382 val = ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)];
383
384 return val;
385 }
386
387 static void bonito_ldma_writel(void *opaque, hwaddr addr,
388 uint64_t val, unsigned size)
389 {
390 PCIBonitoState *s = opaque;
391
392 if (addr >= sizeof(s->bonldma)) {
393 return;
394 }
395
396 ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff;
397 }
398
399 static const MemoryRegionOps bonito_ldma_ops = {
400 .read = bonito_ldma_readl,
401 .write = bonito_ldma_writel,
402 .endianness = DEVICE_NATIVE_ENDIAN,
403 .valid = {
404 .min_access_size = 4,
405 .max_access_size = 4,
406 },
407 };
408
409 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr,
410 unsigned size)
411 {
412 uint32_t val;
413 PCIBonitoState *s = opaque;
414
415 if (addr >= sizeof(s->boncop)) {
416 return 0;
417 }
418
419 val = ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)];
420
421 return val;
422 }
423
424 static void bonito_cop_writel(void *opaque, hwaddr addr,
425 uint64_t val, unsigned size)
426 {
427 PCIBonitoState *s = opaque;
428
429 if (addr >= sizeof(s->boncop)) {
430 return;
431 }
432
433 ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff;
434 }
435
436 static const MemoryRegionOps bonito_cop_ops = {
437 .read = bonito_cop_readl,
438 .write = bonito_cop_writel,
439 .endianness = DEVICE_NATIVE_ENDIAN,
440 .valid = {
441 .min_access_size = 4,
442 .max_access_size = 4,
443 },
444 };
445
446 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr)
447 {
448 PCIBonitoState *s = opaque;
449 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
450 uint32_t cfgaddr;
451 uint32_t idsel;
452 uint32_t devno;
453 uint32_t funno;
454 uint32_t regno;
455 uint32_t pciaddr;
456
457 /* support type0 pci config */
458 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) {
459 return 0xffffffff;
460 }
461
462 cfgaddr = addr & 0xffff;
463 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16;
464
465 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >>
466 BONITO_PCICONF_IDSEL_OFFSET;
467 devno = ctz32(idsel);
468 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET;
469 regno = (cfgaddr & BONITO_PCICONF_REG_MASK_HW) >> BONITO_PCICONF_REG_OFFSET;
470
471 if (idsel == 0) {
472 error_report("error in bonito pci config address 0x" TARGET_FMT_plx
473 ",pcimap_cfg=0x%x", addr, s->regs[BONITO_PCIMAP_CFG]);
474 exit(1);
475 }
476 pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno);
477 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n",
478 cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno);
479
480 return pciaddr;
481 }
482
483 static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val,
484 unsigned size)
485 {
486 PCIBonitoState *s = opaque;
487 PCIDevice *d = PCI_DEVICE(s);
488 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
489 uint32_t pciaddr;
490 uint16_t status;
491
492 DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %lx\n",
493 addr, size, val);
494
495 pciaddr = bonito_sbridge_pciaddr(s, addr);
496
497 if (pciaddr == 0xffffffff) {
498 return;
499 }
500 if (addr & ~BONITO_PCICONF_REG_MASK_DS) {
501 trace_bonito_spciconf_small_access(addr, size);
502 }
503
504 /* set the pci address in s->config_reg */
505 phb->config_reg = (pciaddr) | (1u << 31);
506 pci_data_write(phb->bus, phb->config_reg, val, size);
507
508 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
509 status = pci_get_word(d->config + PCI_STATUS);
510 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
511 pci_set_word(d->config + PCI_STATUS, status);
512 }
513
514 static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size)
515 {
516 PCIBonitoState *s = opaque;
517 PCIDevice *d = PCI_DEVICE(s);
518 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
519 uint32_t pciaddr;
520 uint16_t status;
521
522 DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size);
523
524 pciaddr = bonito_sbridge_pciaddr(s, addr);
525
526 if (pciaddr == 0xffffffff) {
527 return MAKE_64BIT_MASK(0, size * 8);
528 }
529 if (addr & ~BONITO_PCICONF_REG_MASK_DS) {
530 trace_bonito_spciconf_small_access(addr, size);
531 }
532
533 /* set the pci address in s->config_reg */
534 phb->config_reg = (pciaddr) | (1u << 31);
535
536 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */
537 status = pci_get_word(d->config + PCI_STATUS);
538 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT);
539 pci_set_word(d->config + PCI_STATUS, status);
540
541 return pci_data_read(phb->bus, phb->config_reg, size);
542 }
543
544 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */
545 static const MemoryRegionOps bonito_spciconf_ops = {
546 .read = bonito_spciconf_read,
547 .write = bonito_spciconf_write,
548 .valid.min_access_size = 1,
549 .valid.max_access_size = 4,
550 .impl.min_access_size = 1,
551 .impl.max_access_size = 4,
552 .endianness = DEVICE_NATIVE_ENDIAN,
553 };
554
555 #define BONITO_IRQ_BASE 32
556
557 static void pci_bonito_set_irq(void *opaque, int irq_num, int level)
558 {
559 BonitoState *s = opaque;
560 qemu_irq *pic = s->pic;
561 PCIBonitoState *bonito_state = s->pci_dev;
562 int internal_irq = irq_num - BONITO_IRQ_BASE;
563
564 if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) {
565 qemu_irq_pulse(*pic);
566 } else { /* level triggered */
567 if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) {
568 qemu_irq_raise(*pic);
569 } else {
570 qemu_irq_lower(*pic);
571 }
572 }
573 }
574
575 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */
576 static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
577 {
578 int slot;
579
580 slot = PCI_SLOT(pci_dev->devfn);
581
582 switch (slot) {
583 case 5: /* FULOONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
584 return irq_num % 4 + BONITO_IRQ_BASE;
585 case 6: /* FULOONG2E_ATI_SLOT, VGA */
586 return 4 + BONITO_IRQ_BASE;
587 case 7: /* FULOONG2E_RTL_SLOT, RTL8139 */
588 return 5 + BONITO_IRQ_BASE;
589 case 8 ... 12: /* PCI slot 1 to 4 */
590 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
591 default: /* Unknown device, don't do any translation */
592 return irq_num;
593 }
594 }
595
596 static void bonito_reset(void *opaque)
597 {
598 PCIBonitoState *s = opaque;
599 uint32_t val = 0;
600
601 /* set the default value of north bridge registers */
602
603 s->regs[BONITO_BONPONCFG] = 0xc40;
604 val = FIELD_DP32(val, BONGENCFG, PCIQUEUE, 1);
605 val = FIELD_DP32(val, BONGENCFG, WRITEBEHIND, 1);
606 val = FIELD_DP32(val, BONGENCFG, PREFETCH, 1);
607 val = FIELD_DP32(val, BONGENCFG, UNCACHED, 1);
608 val = FIELD_DP32(val, BONGENCFG, CPUSELFRESET, 1);
609 s->regs[BONITO_BONGENCFG] = val;
610
611 s->regs[BONITO_IODEVCFG] = 0x2bff8010;
612 s->regs[BONITO_SDCFG] = 0x255e0091;
613
614 s->regs[BONITO_GPIODATA] = 0x1ff;
615 s->regs[BONITO_GPIOIE] = 0x1ff;
616 s->regs[BONITO_DQCFG] = 0x8;
617 s->regs[BONITO_MEMSIZE] = 0x10000000;
618 s->regs[BONITO_PCIMAP] = 0x6140;
619 }
620
621 static const VMStateDescription vmstate_bonito = {
622 .name = "Bonito",
623 .version_id = 1,
624 .minimum_version_id = 1,
625 .fields = (VMStateField[]) {
626 VMSTATE_PCI_DEVICE(dev, PCIBonitoState),
627 VMSTATE_END_OF_LIST()
628 }
629 };
630
631 static void bonito_pcihost_realize(DeviceState *dev, Error **errp)
632 {
633 PCIHostState *phb = PCI_HOST_BRIDGE(dev);
634 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
635 MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3);
636
637 memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE);
638 phb->bus = pci_register_root_bus(dev, "pci",
639 pci_bonito_set_irq, pci_bonito_map_irq,
640 dev, &bs->pci_mem, get_system_io(),
641 PCI_DEVFN(5, 0), 32, TYPE_PCI_BUS);
642
643 for (size_t i = 0; i < 3; i++) {
644 char *name = g_strdup_printf("pci.lomem%zu", i);
645
646 memory_region_init_alias(&pcimem_lo_alias[i], NULL, name,
647 &bs->pci_mem, i * 64 * MiB, 64 * MiB);
648 memory_region_add_subregion(get_system_memory(),
649 BONITO_PCILO_BASE + i * 64 * MiB,
650 &pcimem_lo_alias[i]);
651 g_free(name);
652 }
653
654 create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB);
655 }
656
657 static void bonito_realize(PCIDevice *dev, Error **errp)
658 {
659 PCIBonitoState *s = PCI_BONITO(dev);
660 SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
661 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
662 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(s->pcihost);
663 MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1);
664
665 /*
666 * Bonito North Bridge, built on FPGA,
667 * VENDOR_ID/DEVICE_ID are "undefined"
668 */
669 pci_config_set_prog_interface(dev->config, 0x00);
670
671 /* set the north bridge register mapping */
672 memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s,
673 "north-bridge-register", BONITO_INTERNAL_REG_SIZE);
674 sysbus_init_mmio(sysbus, &s->iomem);
675 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE);
676
677 /* set the north bridge pci configure mapping */
678 memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s,
679 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE);
680 sysbus_init_mmio(sysbus, &phb->conf_mem);
681 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE);
682
683 /* set the south bridge pci configure mapping */
684 memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s,
685 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE);
686 sysbus_init_mmio(sysbus, &phb->data_mem);
687 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
688
689 create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE);
690
691 memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s,
692 "ldma", 0x100);
693 sysbus_init_mmio(sysbus, &s->iomem_ldma);
694 sysbus_mmio_map(sysbus, 3, 0x1fe00200);
695
696 /* PCI copier */
697 memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s,
698 "cop", 0x100);
699 sysbus_init_mmio(sysbus, &s->iomem_cop);
700 sysbus_mmio_map(sysbus, 4, 0x1fe00300);
701
702 create_unimplemented_device("ROMCS", BONITO_FLASH_BASE, 60 * MiB);
703
704 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
705 memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio",
706 get_system_io(), 0, BONITO_PCIIO_SIZE);
707 sysbus_init_mmio(sysbus, &s->bonito_pciio);
708 sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE);
709
710 /* add pci local io mapping */
711
712 memory_region_init_alias(&s->bonito_localio, OBJECT(s), "IOCS[0]",
713 get_system_io(), 0, 256 * KiB);
714 sysbus_init_mmio(sysbus, &s->bonito_localio);
715 sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE);
716 create_unimplemented_device("IOCS[1]", BONITO_DEV_BASE + 1 * 256 * KiB,
717 256 * KiB);
718 create_unimplemented_device("IOCS[2]", BONITO_DEV_BASE + 2 * 256 * KiB,
719 256 * KiB);
720 create_unimplemented_device("IOCS[3]", BONITO_DEV_BASE + 3 * 256 * KiB,
721 256 * KiB);
722
723 memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias",
724 &bs->pci_mem, 0, BONITO_PCIHI_SIZE);
725 memory_region_add_subregion(get_system_memory(),
726 BONITO_PCIHI_BASE, pcimem_alias);
727 create_unimplemented_device("PCI_2",
728 (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE,
729 2 * GiB);
730
731 /* set the default value of north bridge pci config */
732 pci_set_word(dev->config + PCI_COMMAND, 0x0000);
733 pci_set_word(dev->config + PCI_STATUS, 0x0000);
734 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000);
735 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000);
736
737 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00);
738 pci_config_set_interrupt_pin(dev->config, 0x01); /* interrupt pin A */
739
740 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c);
741 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00);
742
743 qemu_register_reset(bonito_reset, s);
744 }
745
746 PCIBus *bonito_init(qemu_irq *pic)
747 {
748 DeviceState *dev;
749 BonitoState *pcihost;
750 PCIHostState *phb;
751 PCIBonitoState *s;
752 PCIDevice *d;
753
754 dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE);
755 phb = PCI_HOST_BRIDGE(dev);
756 pcihost = BONITO_PCI_HOST_BRIDGE(dev);
757 pcihost->pic = pic;
758 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
759
760 d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO);
761 s = PCI_BONITO(d);
762 s->pcihost = pcihost;
763 pcihost->pci_dev = s;
764 pci_realize_and_unref(d, phb->bus, &error_fatal);
765
766 return phb->bus;
767 }
768
769 static void bonito_class_init(ObjectClass *klass, void *data)
770 {
771 DeviceClass *dc = DEVICE_CLASS(klass);
772 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
773
774 k->realize = bonito_realize;
775 k->vendor_id = 0xdf53;
776 k->device_id = 0x00d5;
777 k->revision = 0x01;
778 k->class_id = PCI_CLASS_BRIDGE_HOST;
779 dc->desc = "Host bridge";
780 dc->vmsd = &vmstate_bonito;
781 /*
782 * PCI-facing part of the host bridge, not usable without the
783 * host-facing part, which can't be device_add'ed, yet.
784 */
785 dc->user_creatable = false;
786 }
787
788 static const TypeInfo bonito_info = {
789 .name = TYPE_PCI_BONITO,
790 .parent = TYPE_PCI_DEVICE,
791 .instance_size = sizeof(PCIBonitoState),
792 .class_init = bonito_class_init,
793 .interfaces = (InterfaceInfo[]) {
794 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
795 { },
796 },
797 };
798
799 static void bonito_pcihost_class_init(ObjectClass *klass, void *data)
800 {
801 DeviceClass *dc = DEVICE_CLASS(klass);
802
803 dc->realize = bonito_pcihost_realize;
804 }
805
806 static const TypeInfo bonito_pcihost_info = {
807 .name = TYPE_BONITO_PCI_HOST_BRIDGE,
808 .parent = TYPE_PCI_HOST_BRIDGE,
809 .instance_size = sizeof(BonitoState),
810 .class_init = bonito_pcihost_class_init,
811 };
812
813 static void bonito_register_types(void)
814 {
815 type_register_static(&bonito_pcihost_info);
816 type_register_static(&bonito_info);
817 }
818
819 type_init(bonito_register_types)
QEmu