hw/versatilepb.c

   1 /*
   2  * ARM Versatile Platform/Application Baseboard System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL.
   8  */
   9
  10 #include "sysbus.h"
  11 #include "arm-misc.h"
  12 #include "primecell.h"
  13 #include "devices.h"
  14 #include "net.h"
  15 #include "sysemu.h"
  16 #include "pci.h"
  17 #include "usb-ohci.h"
  18 #include "boards.h"
  19 #include "blockdev.h"
  20
  21 /* Primary interrupt controller.  */
  22
  23 typedef struct vpb_sic_state
  24 {
  25   SysBusDevice busdev;
  26   uint32_t level;
  27   uint32_t mask;
  28   uint32_t pic_enable;
  29   qemu_irq parent[32];
  30   int irq;
  31 } vpb_sic_state;
  32
  33 static void vpb_sic_update(vpb_sic_state *s)
  34 {
  35     uint32_t flags;
  36
  37     flags = s->level & s->mask;
  38     qemu_set_irq(s->parent[s->irq], flags != 0);
  39 }
  40
  41 static void vpb_sic_update_pic(vpb_sic_state *s)
  42 {
  43     int i;
  44     uint32_t mask;
  45
  46     for (i = 21; i <= 30; i++) {
  47         mask = 1u << i;
  48         if (!(s->pic_enable & mask))
  49             continue;
  50         qemu_set_irq(s->parent[i], (s->level & mask) != 0);
  51     }
  52 }
  53
  54 static void vpb_sic_set_irq(void *opaque, int irq, int level)
  55 {
  56     vpb_sic_state *s = (vpb_sic_state *)opaque;
  57     if (level)
  58         s->level |= 1u << irq;
  59     else
  60         s->level &= ~(1u << irq);
  61     if (s->pic_enable & (1u << irq))
  62         qemu_set_irq(s->parent[irq], level);
  63     vpb_sic_update(s);
  64 }
  65
  66 static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
  67 {
  68     vpb_sic_state *s = (vpb_sic_state *)opaque;
  69
  70     switch (offset >> 2) {
  71     case 0: /* STATUS */
  72         return s->level & s->mask;
  73     case 1: /* RAWSTAT */
  74         return s->level;
  75     case 2: /* ENABLE */
  76         return s->mask;
  77     case 4: /* SOFTINT */
  78         return s->level & 1;
  79     case 8: /* PICENABLE */
  80         return s->pic_enable;
  81     default:
  82         printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
  83         return 0;
  84     }
  85 }
  86
  87 static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
  88                           uint32_t value)
  89 {
  90     vpb_sic_state *s = (vpb_sic_state *)opaque;
  91
  92     switch (offset >> 2) {
  93     case 2: /* ENSET */
  94         s->mask |= value;
  95         break;
  96     case 3: /* ENCLR */
  97         s->mask &= ~value;
  98         break;
  99     case 4: /* SOFTINTSET */
 100         if (value)
 101             s->mask |= 1;
 102         break;
 103     case 5: /* SOFTINTCLR */
 104         if (value)
 105             s->mask &= ~1u;
 106         break;
 107     case 8: /* PICENSET */
 108         s->pic_enable |= (value & 0x7fe00000);
 109         vpb_sic_update_pic(s);
 110         break;
 111     case 9: /* PICENCLR */
 112         s->pic_enable &= ~value;
 113         vpb_sic_update_pic(s);
 114         break;
 115     default:
 116         printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
 117         return;
 118     }
 119     vpb_sic_update(s);
 120 }
 121
 122 static CPUReadMemoryFunc * const vpb_sic_readfn[] = {
 123    vpb_sic_read,
 124    vpb_sic_read,
 125    vpb_sic_read
 126 };
 127
 128 static CPUWriteMemoryFunc * const vpb_sic_writefn[] = {
 129    vpb_sic_write,
 130    vpb_sic_write,
 131    vpb_sic_write
 132 };
 133
 134 static int vpb_sic_init(SysBusDevice *dev)
 135 {
 136     vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
 137     int iomemtype;
 138     int i;
 139
 140     qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
 141     for (i = 0; i < 32; i++) {
 142         sysbus_init_irq(dev, &s->parent[i]);
 143     }
 144     s->irq = 31;
 145     iomemtype = cpu_register_io_memory(vpb_sic_readfn,
 146                                        vpb_sic_writefn, s,
 147                                        DEVICE_NATIVE_ENDIAN);
 148     sysbus_init_mmio(dev, 0x1000, iomemtype);
 149     /* ??? Save/restore.  */
 150     return 0;
 151 }
 152
 153 /* Board init.  */
 154
 155 /* The AB and PB boards both use the same core, just with different
 156    peripherans and expansion busses.  For now we emulate a subset of the
 157    PB peripherals and just change the board ID.  */
 158
 159 static struct arm_boot_info versatile_binfo;
 160
 161 static void versatile_init(ram_addr_t ram_size,
 162                      const char *boot_device,
 163                      const char *kernel_filename, const char *kernel_cmdline,
 164                      const char *initrd_filename, const char *cpu_model,
 165                      int board_id)
 166 {
 167     CPUState *env;
 168     ram_addr_t ram_offset;
 169     qemu_irq *cpu_pic;
 170     qemu_irq pic[32];
 171     qemu_irq sic[32];
 172     DeviceState *dev;
 173     PCIBus *pci_bus;
 174     NICInfo *nd;
 175     int n;
 176     int done_smc = 0;
 177
 178     if (!cpu_model)
 179         cpu_model = "arm926";
 180     env = cpu_init(cpu_model);
 181     if (!env) {
 182         fprintf(stderr, "Unable to find CPU definition\n");
 183         exit(1);
 184     }
 185     ram_offset = qemu_ram_alloc(NULL, "versatile.ram", ram_size);
 186     /* ??? RAM should repeat to fill physical memory space.  */
 187     /* SDRAM at address zero.  */
 188     cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
 189
 190     arm_sysctl_init(0x10000000, 0x41007004, 0x02000000);
 191     cpu_pic = arm_pic_init_cpu(env);
 192     dev = sysbus_create_varargs("pl190", 0x10140000,
 193                                 cpu_pic[0], cpu_pic[1], NULL);
 194     for (n = 0; n < 32; n++) {
 195         pic[n] = qdev_get_gpio_in(dev, n);
 196     }
 197     dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
 198     for (n = 0; n < 32; n++) {
 199         sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
 200         sic[n] = qdev_get_gpio_in(dev, n);
 201     }
 202
 203     sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
 204     sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
 205
 206     dev = sysbus_create_varargs("versatile_pci", 0x40000000,
 207                                 sic[27], sic[28], sic[29], sic[30], NULL);
 208     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
 209
 210     /* The Versatile PCI bridge does not provide access to PCI IO space,
 211        so many of the qemu PCI devices are not useable.  */
 212     for(n = 0; n < nb_nics; n++) {
 213         nd = &nd_table[n];
 214
 215         if ((!nd->model && !done_smc) || strcmp(nd->model, "smc91c111") == 0) {
 216             smc91c111_init(nd, 0x10010000, sic[25]);
 217             done_smc = 1;
 218         } else {
 219             pci_nic_init_nofail(nd, "rtl8139", NULL);
 220         }
 221     }
 222     if (usb_enabled) {
 223         usb_ohci_init_pci(pci_bus, -1);
 224     }
 225     n = drive_get_max_bus(IF_SCSI);
 226     while (n >= 0) {
 227         pci_create_simple(pci_bus, -1, "lsi53c895a");
 228         n--;
 229     }
 230
 231     sysbus_create_simple("pl011", 0x101f1000, pic[12]);
 232     sysbus_create_simple("pl011", 0x101f2000, pic[13]);
 233     sysbus_create_simple("pl011", 0x101f3000, pic[14]);
 234     sysbus_create_simple("pl011", 0x10009000, sic[6]);
 235
 236     sysbus_create_simple("pl080", 0x10130000, pic[17]);
 237     sysbus_create_simple("sp804", 0x101e2000, pic[4]);
 238     sysbus_create_simple("sp804", 0x101e3000, pic[5]);
 239
 240     /* The versatile/PB actually has a modified Color LCD controller
 241        that includes hardware cursor support from the PL111.  */
 242     sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
 243
 244     sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
 245     sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
 246
 247     /* Add PL031 Real Time Clock. */
 248     sysbus_create_simple("pl031", 0x101e8000, pic[10]);
 249
 250     /* Memory map for Versatile/PB:  */
 251     /* 0x10000000 System registers.  */
 252     /* 0x10001000 PCI controller config registers.  */
 253     /* 0x10002000 Serial bus interface.  */
 254     /*  0x10003000 Secondary interrupt controller.  */
 255     /* 0x10004000 AACI (audio).  */
 256     /*  0x10005000 MMCI0.  */
 257     /*  0x10006000 KMI0 (keyboard).  */
 258     /*  0x10007000 KMI1 (mouse).  */
 259     /* 0x10008000 Character LCD Interface.  */
 260     /*  0x10009000 UART3.  */
 261     /* 0x1000a000 Smart card 1.  */
 262     /*  0x1000b000 MMCI1.  */
 263     /*  0x10010000 Ethernet.  */
 264     /* 0x10020000 USB.  */
 265     /* 0x10100000 SSMC.  */
 266     /* 0x10110000 MPMC.  */
 267     /*  0x10120000 CLCD Controller.  */
 268     /*  0x10130000 DMA Controller.  */
 269     /*  0x10140000 Vectored interrupt controller.  */
 270     /* 0x101d0000 AHB Monitor Interface.  */
 271     /* 0x101e0000 System Controller.  */
 272     /* 0x101e1000 Watchdog Interface.  */
 273     /* 0x101e2000 Timer 0/1.  */
 274     /* 0x101e3000 Timer 2/3.  */
 275     /* 0x101e4000 GPIO port 0.  */
 276     /* 0x101e5000 GPIO port 1.  */
 277     /* 0x101e6000 GPIO port 2.  */
 278     /* 0x101e7000 GPIO port 3.  */
 279     /* 0x101e8000 RTC.  */
 280     /* 0x101f0000 Smart card 0.  */
 281     /*  0x101f1000 UART0.  */
 282     /*  0x101f2000 UART1.  */
 283     /*  0x101f3000 UART2.  */
 284     /* 0x101f4000 SSPI.  */
 285
 286     versatile_binfo.ram_size = ram_size;
 287     versatile_binfo.kernel_filename = kernel_filename;
 288     versatile_binfo.kernel_cmdline = kernel_cmdline;
 289     versatile_binfo.initrd_filename = initrd_filename;
 290     versatile_binfo.board_id = board_id;
 291     arm_load_kernel(env, &versatile_binfo);
 292 }
 293
 294 static void vpb_init(ram_addr_t ram_size,
 295                      const char *boot_device,
 296                      const char *kernel_filename, const char *kernel_cmdline,
 297                      const char *initrd_filename, const char *cpu_model)
 298 {
 299     versatile_init(ram_size,
 300                    boot_device,
 301                    kernel_filename, kernel_cmdline,
 302                    initrd_filename, cpu_model, 0x183);
 303 }
 304
 305 static void vab_init(ram_addr_t ram_size,
 306                      const char *boot_device,
 307                      const char *kernel_filename, const char *kernel_cmdline,
 308                      const char *initrd_filename, const char *cpu_model)
 309 {
 310     versatile_init(ram_size,
 311                    boot_device,
 312                    kernel_filename, kernel_cmdline,
 313                    initrd_filename, cpu_model, 0x25e);
 314 }
 315
 316 static QEMUMachine versatilepb_machine = {
 317     .name = "versatilepb",
 318     .desc = "ARM Versatile/PB (ARM926EJ-S)",
 319     .init = vpb_init,
 320     .use_scsi = 1,
 321 };
 322
 323 static QEMUMachine versatileab_machine = {
 324     .name = "versatileab",
 325     .desc = "ARM Versatile/AB (ARM926EJ-S)",
 326     .init = vab_init,
 327     .use_scsi = 1,
 328 };
 329
 330 static void versatile_machine_init(void)
 331 {
 332     qemu_register_machine(&versatilepb_machine);
 333     qemu_register_machine(&versatileab_machine);
 334 }
 335
 336 machine_init(versatile_machine_init);
 337
 338 static void versatilepb_register_devices(void)
 339 {
 340     sysbus_register_dev("versatilepb_sic", sizeof(vpb_sic_state),
 341                         vpb_sic_init);
 342 }
 343
 344 device_init(versatilepb_register_devices)