hw/lan9118.c

   1 /*
   2  * SMSC LAN9118 Ethernet interface emulation
   3  *
   4  * Copyright (c) 2009 CodeSourcery, LLC.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GNU GPL v2
   8  */
   9
  10 #include "sysbus.h"
  11 #include "net.h"
  12 #include "devices.h"
  13 /* For crc32 */
  14 #include <zlib.h>
  15
  16 //#define DEBUG_LAN9118
  17
  18 #ifdef DEBUG_LAN9118
  19 #define DPRINTF(fmt, ...) \
  20 do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
  21 #define BADF(fmt, ...) \
  22 do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
  23 #else
  24 #define DPRINTF(fmt, ...) do {} while(0)
  25 #define BADF(fmt, ...) \
  26 do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
  27 #endif
  28
  29 #define CSR_ID_REV      0x50
  30 #define CSR_IRQ_CFG     0x54
  31 #define CSR_INT_STS     0x58
  32 #define CSR_INT_EN      0x5c
  33 #define CSR_BYTE_TEST   0x64
  34 #define CSR_FIFO_INT    0x68
  35 #define CSR_RX_CFG      0x6c
  36 #define CSR_TX_CFG      0x70
  37 #define CSR_HW_CFG      0x74
  38 #define CSR_RX_DP_CTRL  0x78
  39 #define CSR_RX_FIFO_INF 0x7c
  40 #define CSR_TX_FIFO_INF 0x80
  41 #define CSR_PMT_CTRL    0x84
  42 #define CSR_GPIO_CFG    0x88
  43 #define CSR_GPT_CFG     0x8c
  44 #define CSR_GPT_CNT     0x90
  45 #define CSR_WORD_SWAP   0x98
  46 #define CSR_FREE_RUN    0x9c
  47 #define CSR_RX_DROP     0xa0
  48 #define CSR_MAC_CSR_CMD 0xa4
  49 #define CSR_MAC_CSR_DATA 0xa8
  50 #define CSR_AFC_CFG     0xac
  51 #define CSR_E2P_CMD     0xb0
  52 #define CSR_E2P_DATA    0xb4
  53
  54 /* IRQ_CFG */
  55 #define IRQ_INT         0x00001000
  56 #define IRQ_EN          0x00000100
  57 #define IRQ_POL         0x00000010
  58 #define IRQ_TYPE        0x00000001
  59
  60 /* INT_STS/INT_EN */
  61 #define SW_INT          0x80000000
  62 #define TXSTOP_INT      0x02000000
  63 #define RXSTOP_INT      0x01000000
  64 #define RXDFH_INT       0x00800000
  65 #define TX_IOC_INT      0x00200000
  66 #define RXD_INT         0x00100000
  67 #define GPT_INT         0x00080000
  68 #define PHY_INT         0x00040000
  69 #define PME_INT         0x00020000
  70 #define TXSO_INT        0x00010000
  71 #define RWT_INT         0x00008000
  72 #define RXE_INT         0x00004000
  73 #define TXE_INT         0x00002000
  74 #define TDFU_INT        0x00000800
  75 #define TDFO_INT        0x00000400
  76 #define TDFA_INT        0x00000200
  77 #define TSFF_INT        0x00000100
  78 #define TSFL_INT        0x00000080
  79 #define RXDF_INT        0x00000040
  80 #define RDFL_INT        0x00000020
  81 #define RSFF_INT        0x00000010
  82 #define RSFL_INT        0x00000008
  83 #define GPIO2_INT       0x00000004
  84 #define GPIO1_INT       0x00000002
  85 #define GPIO0_INT       0x00000001
  86 #define RESERVED_INT    0x7c001000
  87
  88 #define MAC_CR          1
  89 #define MAC_ADDRH       2
  90 #define MAC_ADDRL       3
  91 #define MAC_HASHH       4
  92 #define MAC_HASHL       5
  93 #define MAC_MII_ACC     6
  94 #define MAC_MII_DATA    7
  95 #define MAC_FLOW        8
  96 #define MAC_VLAN1       9 /* TODO */
  97 #define MAC_VLAN2       10 /* TODO */
  98 #define MAC_WUFF        11 /* TODO */
  99 #define MAC_WUCSR       12 /* TODO */
 100
 101 #define MAC_CR_RXALL    0x80000000
 102 #define MAC_CR_RCVOWN   0x00800000
 103 #define MAC_CR_LOOPBK   0x00200000
 104 #define MAC_CR_FDPX     0x00100000
 105 #define MAC_CR_MCPAS    0x00080000
 106 #define MAC_CR_PRMS     0x00040000
 107 #define MAC_CR_INVFILT  0x00020000
 108 #define MAC_CR_PASSBAD  0x00010000
 109 #define MAC_CR_HO       0x00008000
 110 #define MAC_CR_HPFILT   0x00002000
 111 #define MAC_CR_LCOLL    0x00001000
 112 #define MAC_CR_BCAST    0x00000800
 113 #define MAC_CR_DISRTY   0x00000400
 114 #define MAC_CR_PADSTR   0x00000100
 115 #define MAC_CR_BOLMT    0x000000c0
 116 #define MAC_CR_DFCHK    0x00000020
 117 #define MAC_CR_TXEN     0x00000008
 118 #define MAC_CR_RXEN     0x00000004
 119 #define MAC_CR_RESERVED 0x7f404213
 120
 121 #define PHY_INT_ENERGYON            0x80
 122 #define PHY_INT_AUTONEG_COMPLETE    0x40
 123 #define PHY_INT_FAULT               0x20
 124 #define PHY_INT_DOWN                0x10
 125 #define PHY_INT_AUTONEG_LP          0x08
 126 #define PHY_INT_PARFAULT            0x04
 127 #define PHY_INT_AUTONEG_PAGE        0x02
 128
 129 #define GPT_TIMER_EN    0x20000000
 130
 131 enum tx_state {
 132     TX_IDLE,
 133     TX_B,
 134     TX_DATA
 135 };
 136
 137 typedef struct {
 138     enum tx_state state;
 139     uint32_t cmd_a;
 140     uint32_t cmd_b;
 141     int buffer_size;
 142     int offset;
 143     int pad;
 144     int fifo_used;
 145     int len;
 146     uint8_t data[2048];
 147 } LAN9118Packet;
 148
 149 typedef struct {
 150     SysBusDevice busdev;
 151     NICState *nic;
 152     NICConf conf;
 153     qemu_irq irq;
 154     int mmio_index;
 155     ptimer_state *timer;
 156
 157     uint32_t irq_cfg;
 158     uint32_t int_sts;
 159     uint32_t int_en;
 160     uint32_t fifo_int;
 161     uint32_t rx_cfg;
 162     uint32_t tx_cfg;
 163     uint32_t hw_cfg;
 164     uint32_t pmt_ctrl;
 165     uint32_t gpio_cfg;
 166     uint32_t gpt_cfg;
 167     uint32_t word_swap;
 168     uint32_t free_timer_start;
 169     uint32_t mac_cmd;
 170     uint32_t mac_data;
 171     uint32_t afc_cfg;
 172     uint32_t e2p_cmd;
 173     uint32_t e2p_data;
 174
 175     uint32_t mac_cr;
 176     uint32_t mac_hashh;
 177     uint32_t mac_hashl;
 178     uint32_t mac_mii_acc;
 179     uint32_t mac_mii_data;
 180     uint32_t mac_flow;
 181
 182     uint32_t phy_status;
 183     uint32_t phy_control;
 184     uint32_t phy_advertise;
 185     uint32_t phy_int;
 186     uint32_t phy_int_mask;
 187
 188     int eeprom_writable;
 189     uint8_t eeprom[8];
 190
 191     int tx_fifo_size;
 192     LAN9118Packet *txp;
 193     LAN9118Packet tx_packet;
 194
 195     int tx_status_fifo_used;
 196     int tx_status_fifo_head;
 197     uint32_t tx_status_fifo[512];
 198
 199     int rx_status_fifo_size;
 200     int rx_status_fifo_used;
 201     int rx_status_fifo_head;
 202     uint32_t rx_status_fifo[896];
 203     int rx_fifo_size;
 204     int rx_fifo_used;
 205     int rx_fifo_head;
 206     uint32_t rx_fifo[3360];
 207     int rx_packet_size_head;
 208     int rx_packet_size_tail;
 209     int rx_packet_size[1024];
 210
 211     int rxp_offset;
 212     int rxp_size;
 213     int rxp_pad;
 214 } lan9118_state;
 215
 216 static void lan9118_update(lan9118_state *s)
 217 {
 218     int level;
 219
 220     /* TODO: Implement FIFO level IRQs.  */
 221     level = (s->int_sts & s->int_en) != 0;
 222     if (level) {
 223         s->irq_cfg |= IRQ_INT;
 224     } else {
 225         s->irq_cfg &= ~IRQ_INT;
 226     }
 227     if ((s->irq_cfg & IRQ_EN) == 0) {
 228         level = 0;
 229     }
 230     qemu_set_irq(s->irq, level);
 231 }
 232
 233 static void lan9118_mac_changed(lan9118_state *s)
 234 {
 235     qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
 236 }
 237
 238 static void lan9118_reload_eeprom(lan9118_state *s)
 239 {
 240     int i;
 241     if (s->eeprom[0] != 0xa5) {
 242         s->e2p_cmd &= ~0x10;
 243         DPRINTF("MACADDR load failed\n");
 244         return;
 245     }
 246     for (i = 0; i < 6; i++) {
 247         s->conf.macaddr.a[i] = s->eeprom[i + 1];
 248     }
 249     s->e2p_cmd |= 0x10;
 250     DPRINTF("MACADDR loaded from eeprom\n");
 251     lan9118_mac_changed(s);
 252 }
 253
 254 static void phy_update_irq(lan9118_state *s)
 255 {
 256     if (s->phy_int & s->phy_int_mask) {
 257         s->int_sts |= PHY_INT;
 258     } else {
 259         s->int_sts &= ~PHY_INT;
 260     }
 261     lan9118_update(s);
 262 }
 263
 264 static void phy_update_link(lan9118_state *s)
 265 {
 266     /* Autonegotiation status mirrors link status.  */
 267     if (s->nic->nc.link_down) {
 268         s->phy_status &= ~0x0024;
 269         s->phy_int |= PHY_INT_DOWN;
 270     } else {
 271         s->phy_status |= 0x0024;
 272         s->phy_int |= PHY_INT_ENERGYON;
 273         s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
 274     }
 275     phy_update_irq(s);
 276 }
 277
 278 static void lan9118_set_link(VLANClientState *nc)
 279 {
 280     phy_update_link(DO_UPCAST(NICState, nc, nc)->opaque);
 281 }
 282
 283 static void phy_reset(lan9118_state *s)
 284 {
 285     s->phy_status = 0x7809;
 286     s->phy_control = 0x3000;
 287     s->phy_advertise = 0x01e1;
 288     s->phy_int_mask = 0;
 289     s->phy_int = 0;
 290     phy_update_link(s);
 291 }
 292
 293 static void lan9118_reset(DeviceState *d)
 294 {
 295     lan9118_state *s = FROM_SYSBUS(lan9118_state, sysbus_from_qdev(d));
 296
 297     s->irq_cfg &= ~(IRQ_TYPE | IRQ_POL);
 298     s->int_sts = 0;
 299     s->int_en = 0;
 300     s->fifo_int = 0x48000000;
 301     s->rx_cfg = 0;
 302     s->tx_cfg = 0;
 303     s->hw_cfg = 0x00050000;
 304     s->pmt_ctrl &= 0x45;
 305     s->gpio_cfg = 0;
 306     s->txp->fifo_used = 0;
 307     s->txp->state = TX_IDLE;
 308     s->txp->cmd_a = 0xffffffffu;
 309     s->txp->cmd_b = 0xffffffffu;
 310     s->txp->len = 0;
 311     s->txp->fifo_used = 0;
 312     s->tx_fifo_size = 4608;
 313     s->tx_status_fifo_used = 0;
 314     s->rx_status_fifo_size = 704;
 315     s->rx_fifo_size = 2640;
 316     s->rx_fifo_used = 0;
 317     s->rx_status_fifo_size = 176;
 318     s->rx_status_fifo_used = 0;
 319     s->rxp_offset = 0;
 320     s->rxp_size = 0;
 321     s->rxp_pad = 0;
 322     s->rx_packet_size_tail = s->rx_packet_size_head;
 323     s->rx_packet_size[s->rx_packet_size_head] = 0;
 324     s->mac_cmd = 0;
 325     s->mac_data = 0;
 326     s->afc_cfg = 0;
 327     s->e2p_cmd = 0;
 328     s->e2p_data = 0;
 329     s->free_timer_start = qemu_get_clock(vm_clock) / 40;
 330
 331     ptimer_stop(s->timer);
 332     ptimer_set_count(s->timer, 0xffff);
 333     s->gpt_cfg = 0xffff;
 334
 335     s->mac_cr = MAC_CR_PRMS;
 336     s->mac_hashh = 0;
 337     s->mac_hashl = 0;
 338     s->mac_mii_acc = 0;
 339     s->mac_mii_data = 0;
 340     s->mac_flow = 0;
 341
 342     phy_reset(s);
 343
 344     s->eeprom_writable = 0;
 345     lan9118_reload_eeprom(s);
 346 }
 347
 348 static int lan9118_can_receive(VLANClientState *nc)
 349 {
 350     return 1;
 351 }
 352
 353 static void rx_fifo_push(lan9118_state *s, uint32_t val)
 354 {
 355     int fifo_pos;
 356     fifo_pos = s->rx_fifo_head + s->rx_fifo_used;
 357     if (fifo_pos >= s->rx_fifo_size)
 358       fifo_pos -= s->rx_fifo_size;
 359     s->rx_fifo[fifo_pos] = val;
 360     s->rx_fifo_used++;
 361 }
 362
 363 /* Return nonzero if the packet is accepted by the filter.  */
 364 static int lan9118_filter(lan9118_state *s, const uint8_t *addr)
 365 {
 366     int multicast;
 367     uint32_t hash;
 368
 369     if (s->mac_cr & MAC_CR_PRMS) {
 370         return 1;
 371     }
 372     if (addr[0] == 0xff && addr[1] == 0xff && addr[2] == 0xff &&
 373         addr[3] == 0xff && addr[4] == 0xff && addr[5] == 0xff) {
 374         return (s->mac_cr & MAC_CR_BCAST) == 0;
 375     }
 376
 377     multicast = addr[0] & 1;
 378     if (multicast &&s->mac_cr & MAC_CR_MCPAS) {
 379         return 1;
 380     }
 381     if (multicast ? (s->mac_cr & MAC_CR_HPFILT) == 0
 382                   : (s->mac_cr & MAC_CR_HO) == 0) {
 383         /* Exact matching.  */
 384         hash = memcmp(addr, s->conf.macaddr.a, 6);
 385         if (s->mac_cr & MAC_CR_INVFILT) {
 386             return hash != 0;
 387         } else {
 388             return hash == 0;
 389         }
 390     } else {
 391         /* Hash matching  */
 392         hash = (crc32(~0, addr, 6) >> 26);
 393         if (hash & 0x20) {
 394             return (s->mac_hashh >> (hash & 0x1f)) & 1;
 395         } else {
 396             return (s->mac_hashl >> (hash & 0x1f)) & 1;
 397         }
 398     }
 399 }
 400
 401 static ssize_t lan9118_receive(VLANClientState *nc, const uint8_t *buf,
 402                                size_t size)
 403 {
 404     lan9118_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
 405     int fifo_len;
 406     int offset;
 407     int src_pos;
 408     int n;
 409     int filter;
 410     uint32_t val;
 411     uint32_t crc;
 412     uint32_t status;
 413
 414     if ((s->mac_cr & MAC_CR_RXEN) == 0) {
 415         return -1;
 416     }
 417
 418     if (size >= 2048 || size < 14) {
 419         return -1;
 420     }
 421
 422     /* TODO: Implement FIFO overflow notification.  */
 423     if (s->rx_status_fifo_used == s->rx_status_fifo_size) {
 424         return -1;
 425     }
 426
 427     filter = lan9118_filter(s, buf);
 428     if (!filter && (s->mac_cr & MAC_CR_RXALL) == 0) {
 429         return size;
 430     }
 431
 432     offset = (s->rx_cfg >> 8) & 0x1f;
 433     n = offset & 3;
 434     fifo_len = (size + n + 3) >> 2;
 435     /* Add a word for the CRC.  */
 436     fifo_len++;
 437     if (s->rx_fifo_size - s->rx_fifo_used < fifo_len) {
 438         return -1;
 439     }
 440
 441     DPRINTF("Got packet len:%d fifo:%d filter:%s\n",
 442             (int)size, fifo_len, filter ? "pass" : "fail");
 443     val = 0;
 444     crc = bswap32(crc32(~0, buf, size));
 445     for (src_pos = 0; src_pos < size; src_pos++) {
 446         val = (val >> 8) | ((uint32_t)buf[src_pos] << 24);
 447         n++;
 448         if (n == 4) {
 449             n = 0;
 450             rx_fifo_push(s, val);
 451             val = 0;
 452         }
 453     }
 454     if (n) {
 455         val >>= ((4 - n) * 8);
 456         val |= crc << (n * 8);
 457         rx_fifo_push(s, val);
 458         val = crc >> ((4 - n) * 8);
 459         rx_fifo_push(s, val);
 460     } else {
 461         rx_fifo_push(s, crc);
 462     }
 463     n = s->rx_status_fifo_head + s->rx_status_fifo_used;
 464     if (n >= s->rx_status_fifo_size) {
 465         n -= s->rx_status_fifo_size;
 466     }
 467     s->rx_packet_size[s->rx_packet_size_tail] = fifo_len;
 468     s->rx_packet_size_tail = (s->rx_packet_size_tail + 1023) & 1023;
 469     s->rx_status_fifo_used++;
 470
 471     status = (size + 4) << 16;
 472     if (buf[0] == 0xff && buf[1] == 0xff && buf[2] == 0xff &&
 473         buf[3] == 0xff && buf[4] == 0xff && buf[5] == 0xff) {
 474         status |= 0x00002000;
 475     } else if (buf[0] & 1) {
 476         status |= 0x00000400;
 477     }
 478     if (!filter) {
 479         status |= 0x40000000;
 480     }
 481     s->rx_status_fifo[n] = status;
 482
 483     if (s->rx_status_fifo_used > (s->fifo_int & 0xff)) {
 484         s->int_sts |= RSFL_INT;
 485     }
 486     lan9118_update(s);
 487
 488     return size;
 489 }
 490
 491 static uint32_t rx_fifo_pop(lan9118_state *s)
 492 {
 493     int n;
 494     uint32_t val;
 495
 496     if (s->rxp_size == 0 && s->rxp_pad == 0) {
 497         s->rxp_size = s->rx_packet_size[s->rx_packet_size_head];
 498         s->rx_packet_size[s->rx_packet_size_head] = 0;
 499         if (s->rxp_size != 0) {
 500             s->rx_packet_size_head = (s->rx_packet_size_head + 1023) & 1023;
 501             s->rxp_offset = (s->rx_cfg >> 10) & 7;
 502             n = s->rxp_offset + s->rxp_size;
 503             switch (s->rx_cfg >> 30) {
 504             case 1:
 505                 n = (-n) & 3;
 506                 break;
 507             case 2:
 508                 n = (-n) & 7;
 509                 break;
 510             default:
 511                 n = 0;
 512                 break;
 513             }
 514             s->rxp_pad = n;
 515             DPRINTF("Pop packet size:%d offset:%d pad: %d\n",
 516                     s->rxp_size, s->rxp_offset, s->rxp_pad);
 517         }
 518     }
 519     if (s->rxp_offset > 0) {
 520         s->rxp_offset--;
 521         val = 0;
 522     } else if (s->rxp_size > 0) {
 523         s->rxp_size--;
 524         val = s->rx_fifo[s->rx_fifo_head++];
 525         if (s->rx_fifo_head >= s->rx_fifo_size) {
 526             s->rx_fifo_head -= s->rx_fifo_size;
 527         }
 528         s->rx_fifo_used--;
 529     } else if (s->rxp_pad > 0) {
 530         s->rxp_pad--;
 531         val =  0;
 532     } else {
 533         DPRINTF("RX underflow\n");
 534         s->int_sts |= RXE_INT;
 535         val =  0;
 536     }
 537     lan9118_update(s);
 538     return val;
 539 }
 540
 541 static void do_tx_packet(lan9118_state *s)
 542 {
 543     int n;
 544     uint32_t status;
 545
 546     /* FIXME: Honor TX disable, and allow queueing of packets.  */
 547     if (s->phy_control & 0x4000)  {
 548         /* This assumes the receive routine doesn't touch the VLANClient.  */
 549         lan9118_receive(&s->nic->nc, s->txp->data, s->txp->len);
 550     } else {
 551         qemu_send_packet(&s->nic->nc, s->txp->data, s->txp->len);
 552     }
 553     s->txp->fifo_used = 0;
 554
 555     if (s->tx_status_fifo_used == 512) {
 556         /* Status FIFO full */
 557         return;
 558     }
 559     /* Add entry to status FIFO.  */
 560     status = s->txp->cmd_b & 0xffff0000u;
 561     DPRINTF("Sent packet tag:%04x len %d\n", status >> 16, s->txp->len);
 562     n = (s->tx_status_fifo_head + s->tx_status_fifo_used) & 511;
 563     s->tx_status_fifo[n] = status;
 564     s->tx_status_fifo_used++;
 565     if (s->tx_status_fifo_used == 512) {
 566         s->int_sts |= TSFF_INT;
 567         /* TODO: Stop transmission.  */
 568     }
 569 }
 570
 571 static uint32_t rx_status_fifo_pop(lan9118_state *s)
 572 {
 573     uint32_t val;
 574
 575     val = s->rx_status_fifo[s->rx_status_fifo_head];
 576     if (s->rx_status_fifo_used != 0) {
 577         s->rx_status_fifo_used--;
 578         s->rx_status_fifo_head++;
 579         if (s->rx_status_fifo_head >= s->rx_status_fifo_size) {
 580             s->rx_status_fifo_head -= s->rx_status_fifo_size;
 581         }
 582         /* ??? What value should be returned when the FIFO is empty?  */
 583         DPRINTF("RX status pop 0x%08x\n", val);
 584     }
 585     return val;
 586 }
 587
 588 static uint32_t tx_status_fifo_pop(lan9118_state *s)
 589 {
 590     uint32_t val;
 591
 592     val = s->tx_status_fifo[s->tx_status_fifo_head];
 593     if (s->tx_status_fifo_used != 0) {
 594         s->tx_status_fifo_used--;
 595         s->tx_status_fifo_head = (s->tx_status_fifo_head + 1) & 511;
 596         /* ??? What value should be returned when the FIFO is empty?  */
 597     }
 598     return val;
 599 }
 600
 601 static void tx_fifo_push(lan9118_state *s, uint32_t val)
 602 {
 603     int n;
 604
 605     if (s->txp->fifo_used == s->tx_fifo_size) {
 606         s->int_sts |= TDFO_INT;
 607         return;
 608     }
 609     switch (s->txp->state) {
 610     case TX_IDLE:
 611         s->txp->cmd_a = val & 0x831f37ff;
 612         s->txp->fifo_used++;
 613         s->txp->state = TX_B;
 614         break;
 615     case TX_B:
 616         if (s->txp->cmd_a & 0x2000) {
 617             /* First segment */
 618             s->txp->cmd_b = val;
 619             s->txp->fifo_used++;
 620             s->txp->buffer_size = s->txp->cmd_a & 0x7ff;
 621             s->txp->offset = (s->txp->cmd_a >> 16) & 0x1f;
 622             /* End alignment does not include command words.  */
 623             n = (s->txp->buffer_size + s->txp->offset + 3) >> 2;
 624             switch ((n >> 24) & 3) {
 625             case 1:
 626                 n = (-n) & 3;
 627                 break;
 628             case 2:
 629                 n = (-n) & 7;
 630                 break;
 631             default:
 632                 n = 0;
 633             }
 634             s->txp->pad = n;
 635             s->txp->len = 0;
 636         }
 637         DPRINTF("Block len:%d offset:%d pad:%d cmd %08x\n",
 638                 s->txp->buffer_size, s->txp->offset, s->txp->pad,
 639                 s->txp->cmd_a);
 640         s->txp->state = TX_DATA;
 641         break;
 642     case TX_DATA:
 643         if (s->txp->offset >= 4) {
 644             s->txp->offset -= 4;
 645             break;
 646         }
 647         if (s->txp->buffer_size <= 0 && s->txp->pad != 0) {
 648             s->txp->pad--;
 649         } else {
 650             n = 4;
 651             while (s->txp->offset) {
 652                 val >>= 8;
 653                 n--;
 654                 s->txp->offset--;
 655             }
 656             /* Documentation is somewhat unclear on the ordering of bytes
 657                in FIFO words.  Empirical results show it to be little-endian.
 658                */
 659             /* TODO: FIFO overflow checking.  */
 660             while (n--) {
 661                 s->txp->data[s->txp->len] = val & 0xff;
 662                 s->txp->len++;
 663                 val >>= 8;
 664                 s->txp->buffer_size--;
 665             }
 666             s->txp->fifo_used++;
 667         }
 668         if (s->txp->buffer_size <= 0 && s->txp->pad == 0) {
 669             if (s->txp->cmd_a & 0x1000) {
 670                 do_tx_packet(s);
 671             }
 672             if (s->txp->cmd_a & 0x80000000) {
 673                 s->int_sts |= TX_IOC_INT;
 674             }
 675             s->txp->state = TX_IDLE;
 676         }
 677         break;
 678     }
 679 }
 680
 681 static uint32_t do_phy_read(lan9118_state *s, int reg)
 682 {
 683     uint32_t val;
 684
 685     switch (reg) {
 686     case 0: /* Basic Control */
 687         return s->phy_control;
 688     case 1: /* Basic Status */
 689         return s->phy_status;
 690     case 2: /* ID1 */
 691         return 0x0007;
 692     case 3: /* ID2 */
 693         return 0xc0d1;
 694     case 4: /* Auto-neg advertisment */
 695         return s->phy_advertise;
 696     case 5: /* Auto-neg Link Partner Ability */
 697         return 0x0f71;
 698     case 6: /* Auto-neg Expansion */
 699         return 1;
 700         /* TODO 17, 18, 27, 29, 30, 31 */
 701     case 29: /* Interrupt source.  */
 702         val = s->phy_int;
 703         s->phy_int = 0;
 704         phy_update_irq(s);
 705         return val;
 706     case 30: /* Interrupt mask */
 707         return s->phy_int_mask;
 708     default:
 709         BADF("PHY read reg %d\n", reg);
 710         return 0;
 711     }
 712 }
 713
 714 static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
 715 {
 716     switch (reg) {
 717     case 0: /* Basic Control */
 718         if (val & 0x8000) {
 719             phy_reset(s);
 720             break;
 721         }
 722         s->phy_control = val & 0x7980;
 723         /* Complete autonegotiation imediately.  */
 724         if (val & 0x1000) {
 725             s->phy_status |= 0x0020;
 726         }
 727         break;
 728     case 4: /* Auto-neg advertisment */
 729         s->phy_advertise = (val & 0x2d7f) | 0x80;
 730         break;
 731         /* TODO 17, 18, 27, 31 */
 732     case 30: /* Interrupt mask */
 733         s->phy_int_mask = val & 0xff;
 734         phy_update_irq(s);
 735         break;
 736     default:
 737         BADF("PHY write reg %d = 0x%04x\n", reg, val);
 738     }
 739 }
 740
 741 static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
 742 {
 743     switch (reg) {
 744     case MAC_CR:
 745         if ((s->mac_cr & MAC_CR_RXEN) != 0 && (val & MAC_CR_RXEN) == 0) {
 746             s->int_sts |= RXSTOP_INT;
 747         }
 748         s->mac_cr = val & ~MAC_CR_RESERVED;
 749         DPRINTF("MAC_CR: %08x\n", val);
 750         break;
 751     case MAC_ADDRH:
 752         s->conf.macaddr.a[4] = val & 0xff;
 753         s->conf.macaddr.a[5] = (val >> 8) & 0xff;
 754         lan9118_mac_changed(s);
 755         break;
 756     case MAC_ADDRL:
 757         s->conf.macaddr.a[0] = val & 0xff;
 758         s->conf.macaddr.a[1] = (val >> 8) & 0xff;
 759         s->conf.macaddr.a[2] = (val >> 16) & 0xff;
 760         s->conf.macaddr.a[3] = (val >> 24) & 0xff;
 761         lan9118_mac_changed(s);
 762         break;
 763     case MAC_HASHH:
 764         s->mac_hashh = val;
 765         break;
 766     case MAC_HASHL:
 767         s->mac_hashl = val;
 768         break;
 769     case MAC_MII_ACC:
 770         s->mac_mii_acc = val & 0xffc2;
 771         if (val & 2) {
 772             DPRINTF("PHY write %d = 0x%04x\n",
 773                     (val >> 6) & 0x1f, s->mac_mii_data);
 774             do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
 775         } else {
 776             s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
 777             DPRINTF("PHY read %d = 0x%04x\n",
 778                     (val >> 6) & 0x1f, s->mac_mii_data);
 779         }
 780         break;
 781     case MAC_MII_DATA:
 782         s->mac_mii_data = val & 0xffff;
 783         break;
 784     case MAC_FLOW:
 785         s->mac_flow = val & 0xffff0000;
 786         break;
 787     default:
 788         hw_error("lan9118: Unimplemented MAC register write: %d = 0x%x\n",
 789                  s->mac_cmd & 0xf, val);
 790     }
 791 }
 792
 793 static uint32_t do_mac_read(lan9118_state *s, int reg)
 794 {
 795     switch (reg) {
 796     case MAC_CR:
 797         return s->mac_cr;
 798     case MAC_ADDRH:
 799         return s->conf.macaddr.a[4] | (s->conf.macaddr.a[5] << 8);
 800     case MAC_ADDRL:
 801         return s->conf.macaddr.a[0] | (s->conf.macaddr.a[1] << 8)
 802                | (s->conf.macaddr.a[2] << 16) | (s->conf.macaddr.a[3] << 24);
 803     case MAC_HASHH:
 804         return s->mac_hashh;
 805         break;
 806     case MAC_HASHL:
 807         return s->mac_hashl;
 808         break;
 809     case MAC_MII_ACC:
 810         return s->mac_mii_acc;
 811     case MAC_MII_DATA:
 812         return s->mac_mii_data;
 813     case MAC_FLOW:
 814         return s->mac_flow;
 815     default:
 816         hw_error("lan9118: Unimplemented MAC register read: %d\n",
 817                  s->mac_cmd & 0xf);
 818     }
 819 }
 820
 821 static void lan9118_eeprom_cmd(lan9118_state *s, int cmd, int addr)
 822 {
 823     s->e2p_cmd = (s->e2p_cmd & 0x10) | (cmd << 28) | addr;
 824     switch (cmd) {
 825     case 0:
 826         s->e2p_data = s->eeprom[addr];
 827         DPRINTF("EEPROM Read %d = 0x%02x\n", addr, s->e2p_data);
 828         break;
 829     case 1:
 830         s->eeprom_writable = 0;
 831         DPRINTF("EEPROM Write Disable\n");
 832         break;
 833     case 2: /* EWEN */
 834         s->eeprom_writable = 1;
 835         DPRINTF("EEPROM Write Enable\n");
 836         break;
 837     case 3: /* WRITE */
 838         if (s->eeprom_writable) {
 839             s->eeprom[addr] &= s->e2p_data;
 840             DPRINTF("EEPROM Write %d = 0x%02x\n", addr, s->e2p_data);
 841         } else {
 842             DPRINTF("EEPROM Write %d (ignored)\n", addr);
 843         }
 844         break;
 845     case 4: /* WRAL */
 846         if (s->eeprom_writable) {
 847             for (addr = 0; addr < 128; addr++) {
 848                 s->eeprom[addr] &= s->e2p_data;
 849             }
 850             DPRINTF("EEPROM Write All 0x%02x\n", s->e2p_data);
 851         } else {
 852             DPRINTF("EEPROM Write All (ignored)\n");
 853         }
 854     case 5: /* ERASE */
 855         if (s->eeprom_writable) {
 856             s->eeprom[addr] = 0xff;
 857             DPRINTF("EEPROM Erase %d\n", addr);
 858         } else {
 859             DPRINTF("EEPROM Erase %d (ignored)\n", addr);
 860         }
 861         break;
 862     case 6: /* ERAL */
 863         if (s->eeprom_writable) {
 864             memset(s->eeprom, 0xff, 128);
 865             DPRINTF("EEPROM Erase All\n");
 866         } else {
 867             DPRINTF("EEPROM Erase All (ignored)\n");
 868         }
 869         break;
 870     case 7: /* RELOAD */
 871         lan9118_reload_eeprom(s);
 872         break;
 873     }
 874 }
 875
 876 static void lan9118_tick(void *opaque)
 877 {
 878     lan9118_state *s = (lan9118_state *)opaque;
 879     if (s->int_en & GPT_INT) {
 880         s->int_sts |= GPT_INT;
 881     }
 882     lan9118_update(s);
 883 }
 884
 885 static void lan9118_writel(void *opaque, target_phys_addr_t offset,
 886                            uint32_t val)
 887 {
 888     lan9118_state *s = (lan9118_state *)opaque;
 889     offset &= 0xff;
 890
 891     //DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
 892     if (offset >= 0x20 && offset < 0x40) {
 893         /* TX FIFO */
 894         tx_fifo_push(s, val);
 895         return;
 896     }
 897     switch (offset) {
 898     case CSR_IRQ_CFG:
 899         /* TODO: Implement interrupt deassertion intervals.  */
 900         s->irq_cfg = (s->irq_cfg & IRQ_INT) | (val & IRQ_EN);
 901         break;
 902     case CSR_INT_STS:
 903         s->int_sts &= ~val;
 904         break;
 905     case CSR_INT_EN:
 906         s->int_en = val & ~RESERVED_INT;
 907         s->int_sts |= val & SW_INT;
 908         break;
 909     case CSR_FIFO_INT:
 910         DPRINTF("FIFO INT levels %08x\n", val);
 911         s->fifo_int = val;
 912         break;
 913     case CSR_RX_CFG:
 914         if (val & 0x8000) {
 915             /* RX_DUMP */
 916             s->rx_fifo_used = 0;
 917             s->rx_status_fifo_used = 0;
 918             s->rx_packet_size_tail = s->rx_packet_size_head;
 919             s->rx_packet_size[s->rx_packet_size_head] = 0;
 920         }
 921         s->rx_cfg = val & 0xcfff1ff0;
 922         break;
 923     case CSR_TX_CFG:
 924         if (val & 0x8000) {
 925             s->tx_status_fifo_used = 0;
 926         }
 927         if (val & 0x4000) {
 928             s->txp->state = TX_IDLE;
 929             s->txp->fifo_used = 0;
 930             s->txp->cmd_a = 0xffffffff;
 931         }
 932         s->tx_cfg = val & 6;
 933         break;
 934     case CSR_HW_CFG:
 935         if (val & 1) {
 936             /* SRST */
 937             lan9118_reset(&s->busdev.qdev);
 938         } else {
 939             s->hw_cfg = val & 0x003f300;
 940         }
 941         break;
 942     case CSR_RX_DP_CTRL:
 943         if (val & 0x80000000) {
 944             /* Skip forward to next packet.  */
 945             s->rxp_pad = 0;
 946             s->rxp_offset = 0;
 947             if (s->rxp_size == 0) {
 948                 /* Pop a word to start the next packet.  */
 949                 rx_fifo_pop(s);
 950                 s->rxp_pad = 0;
 951                 s->rxp_offset = 0;
 952             }
 953             s->rx_fifo_head += s->rxp_size;
 954             if (s->rx_fifo_head >= s->rx_fifo_size) {
 955                 s->rx_fifo_head -= s->rx_fifo_size;
 956             }
 957         }
 958         break;
 959     case CSR_PMT_CTRL:
 960         if (val & 0x400) {
 961             phy_reset(s);
 962         }
 963         s->pmt_ctrl &= ~0x34e;
 964         s->pmt_ctrl |= (val & 0x34e);
 965         break;
 966     case CSR_GPIO_CFG:
 967         /* Probably just enabling LEDs.  */
 968         s->gpio_cfg = val & 0x7777071f;
 969         break;
 970     case CSR_GPT_CFG:
 971         if ((s->gpt_cfg ^ val) & GPT_TIMER_EN) {
 972             if (val & GPT_TIMER_EN) {
 973                 ptimer_set_count(s->timer, val & 0xffff);
 974                 ptimer_run(s->timer, 0);
 975             } else {
 976                 ptimer_stop(s->timer);
 977                 ptimer_set_count(s->timer, 0xffff);
 978             }
 979         }
 980         s->gpt_cfg = val & (GPT_TIMER_EN | 0xffff);
 981         break;
 982     case CSR_WORD_SWAP:
 983         /* Ignored because we're in 32-bit mode.  */
 984         s->word_swap = val;
 985         break;
 986     case CSR_MAC_CSR_CMD:
 987         s->mac_cmd = val & 0x4000000f;
 988         if (val & 0x80000000) {
 989             if (val & 0x40000000) {
 990                 s->mac_data = do_mac_read(s, val & 0xf);
 991                 DPRINTF("MAC read %d = 0x%08x\n", val & 0xf, s->mac_data);
 992             } else {
 993                 DPRINTF("MAC write %d = 0x%08x\n", val & 0xf, s->mac_data);
 994                 do_mac_write(s, val & 0xf, s->mac_data);
 995             }
 996         }
 997         break;
 998     case CSR_MAC_CSR_DATA:
 999         s->mac_data = val;
1000         break;
1001     case CSR_AFC_CFG:
1002         s->afc_cfg = val & 0x00ffffff;
1003         break;
1004     case CSR_E2P_CMD:
1005         lan9118_eeprom_cmd(s, (val >> 28) & 7, val & 0xff);
1006         break;
1007     case CSR_E2P_DATA:
1008         s->e2p_data = val & 0xff;
1009         break;
1010
1011     default:
1012         hw_error("lan9118_write: Bad reg 0x%x = %x\n", (int)offset, val);
1013         break;
1014     }
1015     lan9118_update(s);
1016 }
1017
1018 static uint32_t lan9118_readl(void *opaque, target_phys_addr_t offset)
1019 {
1020     lan9118_state *s = (lan9118_state *)opaque;
1021
1022     //DPRINTF("Read reg 0x%02x\n", (int)offset);
1023     if (offset < 0x20) {
1024         /* RX FIFO */
1025         return rx_fifo_pop(s);
1026     }
1027     switch (offset) {
1028     case 0x40:
1029         return rx_status_fifo_pop(s);
1030     case 0x44:
1031         return s->rx_status_fifo[s->tx_status_fifo_head];
1032     case 0x48:
1033         return tx_status_fifo_pop(s);
1034     case 0x4c:
1035         return s->tx_status_fifo[s->tx_status_fifo_head];
1036     case CSR_ID_REV:
1037         return 0x01180001;
1038     case CSR_IRQ_CFG:
1039         return s->irq_cfg;
1040     case CSR_INT_STS:
1041         return s->int_sts;
1042     case CSR_INT_EN:
1043         return s->int_en;
1044     case CSR_BYTE_TEST:
1045         return 0x87654321;
1046     case CSR_FIFO_INT:
1047         return s->fifo_int;
1048     case CSR_RX_CFG:
1049         return s->rx_cfg;
1050     case CSR_TX_CFG:
1051         return s->tx_cfg;
1052     case CSR_HW_CFG:
1053         return s->hw_cfg | 0x4;
1054     case CSR_RX_DP_CTRL:
1055         return 0;
1056     case CSR_RX_FIFO_INF:
1057         return (s->rx_status_fifo_used << 16) | (s->rx_fifo_used << 2);
1058     case CSR_TX_FIFO_INF:
1059         return (s->tx_status_fifo_used << 16)
1060                | (s->tx_fifo_size - s->txp->fifo_used);
1061     case CSR_PMT_CTRL:
1062         return s->pmt_ctrl;
1063     case CSR_GPIO_CFG:
1064         return s->gpio_cfg;
1065     case CSR_GPT_CFG:
1066         return s->gpt_cfg;
1067     case CSR_GPT_CNT:
1068         return ptimer_get_count(s->timer);
1069     case CSR_WORD_SWAP:
1070         return s->word_swap;
1071     case CSR_FREE_RUN:
1072         return (qemu_get_clock(vm_clock) / 40) - s->free_timer_start;
1073     case CSR_RX_DROP:
1074         /* TODO: Implement dropped frames counter.  */
1075         return 0;
1076     case CSR_MAC_CSR_CMD:
1077         return s->mac_cmd;
1078     case CSR_MAC_CSR_DATA:
1079         return s->mac_data;
1080     case CSR_AFC_CFG:
1081         return s->afc_cfg;
1082     case CSR_E2P_CMD:
1083         return s->e2p_cmd;
1084     case CSR_E2P_DATA:
1085         return s->e2p_data;
1086     }
1087     hw_error("lan9118_read: Bad reg 0x%x\n", (int)offset);
1088     return 0;
1089 }
1090
1091 static CPUReadMemoryFunc * const lan9118_readfn[] = {
1092     lan9118_readl,
1093     lan9118_readl,
1094     lan9118_readl
1095 };
1096
1097 static CPUWriteMemoryFunc * const lan9118_writefn[] = {
1098     lan9118_writel,
1099     lan9118_writel,
1100     lan9118_writel
1101 };
1102
1103 static void lan9118_cleanup(VLANClientState *nc)
1104 {
1105     lan9118_state *s = DO_UPCAST(NICState, nc, nc)->opaque;
1106
1107     s->nic = NULL;
1108 }
1109
1110 static NetClientInfo net_lan9118_info = {
1111     .type = NET_CLIENT_TYPE_NIC,
1112     .size = sizeof(NICState),
1113     .can_receive = lan9118_can_receive,
1114     .receive = lan9118_receive,
1115     .cleanup = lan9118_cleanup,
1116     .link_status_changed = lan9118_set_link,
1117 };
1118
1119 static int lan9118_init1(SysBusDevice *dev)
1120 {
1121     lan9118_state *s = FROM_SYSBUS(lan9118_state, dev);
1122     QEMUBH *bh;
1123     int i;
1124
1125     s->mmio_index = cpu_register_io_memory(lan9118_readfn,
1126                                            lan9118_writefn, s);
1127     sysbus_init_mmio(dev, 0x100, s->mmio_index);
1128     sysbus_init_irq(dev, &s->irq);
1129     qemu_macaddr_default_if_unset(&s->conf.macaddr);
1130
1131     s->nic = qemu_new_nic(&net_lan9118_info, &s->conf,
1132                           dev->qdev.info->name, dev->qdev.id, s);
1133     qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
1134     s->eeprom[0] = 0xa5;
1135     for (i = 0; i < 6; i++) {
1136         s->eeprom[i + 1] = s->conf.macaddr.a[i];
1137     }
1138     s->pmt_ctrl = 1;
1139     s->txp = &s->tx_packet;
1140
1141     bh = qemu_bh_new(lan9118_tick, s);
1142     s->timer = ptimer_init(bh);
1143     ptimer_set_freq(s->timer, 10000);
1144     ptimer_set_limit(s->timer, 0xffff, 1);
1145
1146     /* ??? Save/restore.  */
1147     return 0;
1148 }
1149
1150 static SysBusDeviceInfo lan9118_info = {
1151     .init = lan9118_init1,
1152     .qdev.name  = "lan9118",
1153     .qdev.size  = sizeof(lan9118_state),
1154     .qdev.reset = lan9118_reset,
1155     .qdev.props = (Property[]) {
1156         DEFINE_NIC_PROPERTIES(lan9118_state, conf),
1157         DEFINE_PROP_END_OF_LIST(),
1158     }
1159 };
1160
1161 static void lan9118_register_devices(void)
1162 {
1163     sysbus_register_withprop(&lan9118_info);
1164 }
1165
1166 /* Legacy helper function.  Should go away when machine config files are
1167    implemented.  */
1168 void lan9118_init(NICInfo *nd, uint32_t base, qemu_irq irq)
1169 {
1170     DeviceState *dev;
1171     SysBusDevice *s;
1172
1173     qemu_check_nic_model(nd, "lan9118");
1174     dev = qdev_create(NULL, "lan9118");
1175     qdev_set_nic_properties(dev, nd);
1176     qdev_init_nofail(dev);
1177     s = sysbus_from_qdev(dev);
1178     sysbus_mmio_map(s, 0, base);
1179     sysbus_connect_irq(s, 0, irq);
1180 }
1181
1182 device_init(lan9118_register_devices)