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ide/qdev: add ide bus.
[qemu.git] / hw / ide / pci.c
blob607472bb55bba2776f687c5f387fbacd4ec89614
1 /*
2 * QEMU IDE Emulation: PCI Bus support.
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include <hw/hw.h>
26 #include <hw/pc.h>
27 #include <hw/pci.h>
28 #include "block.h"
29 #include "block_int.h"
30 #include "sysemu.h"
31 #include "dma.h"
32
33 #include <hw/ide/internal.h>
34
35 /***********************************************************/
36 /* PCI IDE definitions */
37
38 /* CMD646 specific */
39 #define MRDMODE 0x71
40 #define MRDMODE_INTR_CH0 0x04
41 #define MRDMODE_INTR_CH1 0x08
42 #define MRDMODE_BLK_CH0 0x10
43 #define MRDMODE_BLK_CH1 0x20
44 #define UDIDETCR0 0x73
45 #define UDIDETCR1 0x7B
46
47 #define IDE_TYPE_PIIX3 0
48 #define IDE_TYPE_CMD646 1
49 #define IDE_TYPE_PIIX4 2
50
51 typedef struct PCIIDEState {
52 PCIDevice dev;
53 IDEBus bus[2];
54 BMDMAState bmdma[2];
55 int type; /* see IDE_TYPE_xxx */
56 } PCIIDEState;
57
58 static void cmd646_update_irq(PCIIDEState *d);
59
60 static void ide_map(PCIDevice *pci_dev, int region_num,
61 uint32_t addr, uint32_t size, int type)
62 {
63 PCIIDEState *d = (PCIIDEState *)pci_dev;
64 IDEBus *bus;
65
66 if (region_num <= 3) {
67 bus = &d->bus[(region_num >> 1)];
68 if (region_num & 1) {
69 register_ioport_read(addr + 2, 1, 1, ide_status_read, bus);
70 register_ioport_write(addr + 2, 1, 1, ide_cmd_write, bus);
71 } else {
72 register_ioport_write(addr, 8, 1, ide_ioport_write, bus);
73 register_ioport_read(addr, 8, 1, ide_ioport_read, bus);
74
75 /* data ports */
76 register_ioport_write(addr, 2, 2, ide_data_writew, bus);
77 register_ioport_read(addr, 2, 2, ide_data_readw, bus);
78 register_ioport_write(addr, 4, 4, ide_data_writel, bus);
79 register_ioport_read(addr, 4, 4, ide_data_readl, bus);
80 }
81 }
82 }
83
84 static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
85 {
86 BMDMAState *bm = opaque;
87 #ifdef DEBUG_IDE
88 printf("%s: 0x%08x\n", __func__, val);
89 #endif
90 if (!(val & BM_CMD_START)) {
91 /* XXX: do it better */
92 ide_dma_cancel(bm);
93 bm->cmd = val & 0x09;
94 } else {
95 if (!(bm->status & BM_STATUS_DMAING)) {
96 bm->status |= BM_STATUS_DMAING;
97 /* start dma transfer if possible */
98 if (bm->dma_cb)
99 bm->dma_cb(bm, 0);
100 }
101 bm->cmd = val & 0x09;
102 }
103 }
104
105 static uint32_t bmdma_readb(void *opaque, uint32_t addr)
106 {
107 BMDMAState *bm = opaque;
108 PCIIDEState *pci_dev;
109 uint32_t val;
110
111 switch(addr & 3) {
112 case 0:
113 val = bm->cmd;
114 break;
115 case 1:
116 pci_dev = bm->pci_dev;
117 if (pci_dev->type == IDE_TYPE_CMD646) {
118 val = pci_dev->dev.config[MRDMODE];
119 } else {
120 val = 0xff;
121 }
122 break;
123 case 2:
124 val = bm->status;
125 break;
126 case 3:
127 pci_dev = bm->pci_dev;
128 if (pci_dev->type == IDE_TYPE_CMD646) {
129 if (bm == &pci_dev->bmdma[0])
130 val = pci_dev->dev.config[UDIDETCR0];
131 else
132 val = pci_dev->dev.config[UDIDETCR1];
133 } else {
134 val = 0xff;
135 }
136 break;
137 default:
138 val = 0xff;
139 break;
140 }
141 #ifdef DEBUG_IDE
142 printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
143 #endif
144 return val;
145 }
146
147 static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
148 {
149 BMDMAState *bm = opaque;
150 PCIIDEState *pci_dev;
151 #ifdef DEBUG_IDE
152 printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
153 #endif
154 switch(addr & 3) {
155 case 1:
156 pci_dev = bm->pci_dev;
157 if (pci_dev->type == IDE_TYPE_CMD646) {
158 pci_dev->dev.config[MRDMODE] =
159 (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
160 cmd646_update_irq(pci_dev);
161 }
162 break;
163 case 2:
164 bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
165 break;
166 case 3:
167 pci_dev = bm->pci_dev;
168 if (pci_dev->type == IDE_TYPE_CMD646) {
169 if (bm == &pci_dev->bmdma[0])
170 pci_dev->dev.config[UDIDETCR0] = val;
171 else
172 pci_dev->dev.config[UDIDETCR1] = val;
173 }
174 break;
175 }
176 }
177
178 static uint32_t bmdma_addr_readb(void *opaque, uint32_t addr)
179 {
180 BMDMAState *bm = opaque;
181 uint32_t val;
182 val = (bm->addr >> ((addr & 3) * 8)) & 0xff;
183 #ifdef DEBUG_IDE
184 printf("%s: 0x%08x\n", __func__, val);
185 #endif
186 return val;
187 }
188
189 static void bmdma_addr_writeb(void *opaque, uint32_t addr, uint32_t val)
190 {
191 BMDMAState *bm = opaque;
192 int shift = (addr & 3) * 8;
193 #ifdef DEBUG_IDE
194 printf("%s: 0x%08x\n", __func__, val);
195 #endif
196 bm->addr &= ~(0xFF << shift);
197 bm->addr |= ((val & 0xFF) << shift) & ~3;
198 bm->cur_addr = bm->addr;
199 }
200
201 static uint32_t bmdma_addr_readw(void *opaque, uint32_t addr)
202 {
203 BMDMAState *bm = opaque;
204 uint32_t val;
205 val = (bm->addr >> ((addr & 3) * 8)) & 0xffff;
206 #ifdef DEBUG_IDE
207 printf("%s: 0x%08x\n", __func__, val);
208 #endif
209 return val;
210 }
211
212 static void bmdma_addr_writew(void *opaque, uint32_t addr, uint32_t val)
213 {
214 BMDMAState *bm = opaque;
215 int shift = (addr & 3) * 8;
216 #ifdef DEBUG_IDE
217 printf("%s: 0x%08x\n", __func__, val);
218 #endif
219 bm->addr &= ~(0xFFFF << shift);
220 bm->addr |= ((val & 0xFFFF) << shift) & ~3;
221 bm->cur_addr = bm->addr;
222 }
223
224 static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
225 {
226 BMDMAState *bm = opaque;
227 uint32_t val;
228 val = bm->addr;
229 #ifdef DEBUG_IDE
230 printf("%s: 0x%08x\n", __func__, val);
231 #endif
232 return val;
233 }
234
235 static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
236 {
237 BMDMAState *bm = opaque;
238 #ifdef DEBUG_IDE
239 printf("%s: 0x%08x\n", __func__, val);
240 #endif
241 bm->addr = val & ~3;
242 bm->cur_addr = bm->addr;
243 }
244
245 static void bmdma_map(PCIDevice *pci_dev, int region_num,
246 uint32_t addr, uint32_t size, int type)
247 {
248 PCIIDEState *d = (PCIIDEState *)pci_dev;
249 int i;
250
251 for(i = 0;i < 2; i++) {
252 BMDMAState *bm = &d->bmdma[i];
253 d->bus[i].bmdma = bm;
254 bm->pci_dev = DO_UPCAST(PCIIDEState, dev, pci_dev);
255 bm->bus = d->bus+i;
256 qemu_add_vm_change_state_handler(ide_dma_restart_cb, bm);
257
258 register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
259
260 register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
261 register_ioport_read(addr, 4, 1, bmdma_readb, bm);
262
263 register_ioport_write(addr + 4, 4, 1, bmdma_addr_writeb, bm);
264 register_ioport_read(addr + 4, 4, 1, bmdma_addr_readb, bm);
265 register_ioport_write(addr + 4, 4, 2, bmdma_addr_writew, bm);
266 register_ioport_read(addr + 4, 4, 2, bmdma_addr_readw, bm);
267 register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
268 register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
269 addr += 8;
270 }
271 }
272
273 static void pci_ide_save(QEMUFile* f, void *opaque)
274 {
275 PCIIDEState *d = opaque;
276 int i;
277
278 pci_device_save(&d->dev, f);
279
280 for(i = 0; i < 2; i++) {
281 BMDMAState *bm = &d->bmdma[i];
282 uint8_t ifidx;
283 qemu_put_8s(f, &bm->cmd);
284 qemu_put_8s(f, &bm->status);
285 qemu_put_be32s(f, &bm->addr);
286 qemu_put_sbe64s(f, &bm->sector_num);
287 qemu_put_be32s(f, &bm->nsector);
288 ifidx = bm->unit + 2*i;
289 qemu_put_8s(f, &ifidx);
290 /* XXX: if a transfer is pending, we do not save it yet */
291 }
292
293 /* per IDE interface data */
294 for(i = 0; i < 2; i++) {
295 idebus_save(f, &d->bus[i]);
296 }
297
298 /* per IDE drive data */
299 for(i = 0; i < 2; i++) {
300 ide_save(f, &d->bus[i].ifs[0]);
301 ide_save(f, &d->bus[i].ifs[1]);
302 }
303 }
304
305 static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
306 {
307 PCIIDEState *d = opaque;
308 int ret, i;
309
310 if (version_id != 2 && version_id != 3)
311 return -EINVAL;
312 ret = pci_device_load(&d->dev, f);
313 if (ret < 0)
314 return ret;
315
316 for(i = 0; i < 2; i++) {
317 BMDMAState *bm = &d->bmdma[i];
318 uint8_t ifidx;
319 qemu_get_8s(f, &bm->cmd);
320 qemu_get_8s(f, &bm->status);
321 qemu_get_be32s(f, &bm->addr);
322 qemu_get_sbe64s(f, &bm->sector_num);
323 qemu_get_be32s(f, &bm->nsector);
324 qemu_get_8s(f, &ifidx);
325 bm->unit = ifidx & 1;
326 /* XXX: if a transfer is pending, we do not save it yet */
327 }
328
329 /* per IDE interface data */
330 for(i = 0; i < 2; i++) {
331 idebus_load(f, &d->bus[i], version_id);
332 }
333
334 /* per IDE drive data */
335 for(i = 0; i < 2; i++) {
336 ide_load(f, &d->bus[i].ifs[0], version_id);
337 ide_load(f, &d->bus[i].ifs[1], version_id);
338 }
339 return 0;
340 }
341
342 /* XXX: call it also when the MRDMODE is changed from the PCI config
343 registers */
344 static void cmd646_update_irq(PCIIDEState *d)
345 {
346 int pci_level;
347 pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
348 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
349 ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
350 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
351 qemu_set_irq(d->dev.irq[0], pci_level);
352 }
353
354 /* the PCI irq level is the logical OR of the two channels */
355 static void cmd646_set_irq(void *opaque, int channel, int level)
356 {
357 PCIIDEState *d = opaque;
358 int irq_mask;
359
360 irq_mask = MRDMODE_INTR_CH0 << channel;
361 if (level)
362 d->dev.config[MRDMODE] |= irq_mask;
363 else
364 d->dev.config[MRDMODE] &= ~irq_mask;
365 cmd646_update_irq(d);
366 }
367
368 static void cmd646_reset(void *opaque)
369 {
370 PCIIDEState *d = opaque;
371 unsigned int i;
372
373 for (i = 0; i < 2; i++)
374 ide_dma_cancel(&d->bmdma[i]);
375 }
376
377 /* CMD646 PCI IDE controller */
378 void pci_cmd646_ide_init(PCIBus *bus, DriveInfo **hd_table,
379 int secondary_ide_enabled)
380 {
381 PCIIDEState *d;
382 uint8_t *pci_conf;
383 qemu_irq *irq;
384
385 d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
386 sizeof(PCIIDEState),
387 -1,
388 NULL, NULL);
389 d->type = IDE_TYPE_CMD646;
390 pci_conf = d->dev.config;
391 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_CMD);
392 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_CMD_646);
393
394 pci_conf[0x08] = 0x07; // IDE controller revision
395 pci_conf[0x09] = 0x8f;
396
397 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
398 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
399
400 pci_conf[0x51] = 0x04; // enable IDE0
401 if (secondary_ide_enabled) {
402 /* XXX: if not enabled, really disable the seconday IDE controller */
403 pci_conf[0x51] |= 0x08; /* enable IDE1 */
404 }
405
406 pci_register_bar((PCIDevice *)d, 0, 0x8,
407 PCI_ADDRESS_SPACE_IO, ide_map);
408 pci_register_bar((PCIDevice *)d, 1, 0x4,
409 PCI_ADDRESS_SPACE_IO, ide_map);
410 pci_register_bar((PCIDevice *)d, 2, 0x8,
411 PCI_ADDRESS_SPACE_IO, ide_map);
412 pci_register_bar((PCIDevice *)d, 3, 0x4,
413 PCI_ADDRESS_SPACE_IO, ide_map);
414 pci_register_bar((PCIDevice *)d, 4, 0x10,
415 PCI_ADDRESS_SPACE_IO, bmdma_map);
416
417 pci_conf[0x3d] = 0x01; // interrupt on pin 1
418
419 irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
420 ide_init2(&d->bus[0], hd_table[0], hd_table[1], irq[0]);
421 ide_init2(&d->bus[1], hd_table[2], hd_table[3], irq[1]);
422
423 register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
424 qemu_register_reset(cmd646_reset, d);
425 cmd646_reset(d);
426 }
427
428 static void piix3_reset(void *opaque)
429 {
430 PCIIDEState *d = opaque;
431 uint8_t *pci_conf = d->dev.config;
432 int i;
433
434 for (i = 0; i < 2; i++)
435 ide_dma_cancel(&d->bmdma[i]);
436
437 pci_conf[0x04] = 0x00;
438 pci_conf[0x05] = 0x00;
439 pci_conf[0x06] = 0x80; /* FBC */
440 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
441 pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
442 }
443
444 /* hd_table must contain 4 block drivers */
445 /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
446 void pci_piix3_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
447 {
448 PCIIDEState *d;
449 uint8_t *pci_conf;
450
451 /* register a function 1 of PIIX3 */
452 d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
453 sizeof(PCIIDEState),
454 devfn,
455 NULL, NULL);
456 d->type = IDE_TYPE_PIIX3;
457
458 pci_conf = d->dev.config;
459 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
460 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_1);
461 pci_conf[0x09] = 0x80; // legacy ATA mode
462 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
463 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
464
465 qemu_register_reset(piix3_reset, d);
466 piix3_reset(d);
467
468 pci_register_bar((PCIDevice *)d, 4, 0x10,
469 PCI_ADDRESS_SPACE_IO, bmdma_map);
470
471 ide_init2(&d->bus[0], hd_table[0], hd_table[1], isa_reserve_irq(14));
472 ide_init2(&d->bus[1], hd_table[2], hd_table[3], isa_reserve_irq(15));
473 ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
474 ide_init_ioport(&d->bus[1], 0x170, 0x376);
475
476 register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
477 }
478
479 /* hd_table must contain 4 block drivers */
480 /* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
481 void pci_piix4_ide_init(PCIBus *bus, DriveInfo **hd_table, int devfn)
482 {
483 PCIIDEState *d;
484 uint8_t *pci_conf;
485
486 /* register a function 1 of PIIX4 */
487 d = (PCIIDEState *)pci_register_device(bus, "PIIX4 IDE",
488 sizeof(PCIIDEState),
489 devfn,
490 NULL, NULL);
491 d->type = IDE_TYPE_PIIX4;
492
493 pci_conf = d->dev.config;
494 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
495 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB);
496 pci_conf[0x09] = 0x80; // legacy ATA mode
497 pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_IDE);
498 pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
499
500 qemu_register_reset(piix3_reset, d);
501 piix3_reset(d);
502
503 pci_register_bar((PCIDevice *)d, 4, 0x10,
504 PCI_ADDRESS_SPACE_IO, bmdma_map);
505
506 ide_init2(&d->bus[0], hd_table[0], hd_table[1], isa_reserve_irq(14));
507 ide_init2(&d->bus[1], hd_table[2], hd_table[3], isa_reserve_irq(15));
508 ide_init_ioport(&d->bus[0], 0x1f0, 0x3f6);
509 ide_init_ioport(&d->bus[1], 0x170, 0x376);
510
511 register_savevm("ide", 0, 3, pci_ide_save, pci_ide_load, d);
512 }
513
QEmu