hw/timer/xilinx_timer.c

   1 /*
   2  * QEMU model of the Xilinx timer block.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "hw/ptimer.h"
  27 #include "qemu/log.h"
  28 #include "qemu/main-loop.h"
  29
  30 #define D(x)
  31
  32 #define R_TCSR     0
  33 #define R_TLR      1
  34 #define R_TCR      2
  35 #define R_MAX      4
  36
  37 #define TCSR_MDT        (1<<0)
  38 #define TCSR_UDT        (1<<1)
  39 #define TCSR_GENT       (1<<2)
  40 #define TCSR_CAPT       (1<<3)
  41 #define TCSR_ARHT       (1<<4)
  42 #define TCSR_LOAD       (1<<5)
  43 #define TCSR_ENIT       (1<<6)
  44 #define TCSR_ENT        (1<<7)
  45 #define TCSR_TINT       (1<<8)
  46 #define TCSR_PWMA       (1<<9)
  47 #define TCSR_ENALL      (1<<10)
  48
  49 struct xlx_timer
  50 {
  51     QEMUBH *bh;
  52     ptimer_state *ptimer;
  53     void *parent;
  54     int nr; /* for debug.  */
  55
  56     unsigned long timer_div;
  57
  58     uint32_t regs[R_MAX];
  59 };
  60
  61 #define TYPE_XILINX_TIMER "xlnx.xps-timer"
  62 #define XILINX_TIMER(obj) \
  63     OBJECT_CHECK(struct timerblock, (obj), TYPE_XILINX_TIMER)
  64
  65 struct timerblock
  66 {
  67     SysBusDevice parent_obj;
  68
  69     MemoryRegion mmio;
  70     qemu_irq irq;
  71     uint8_t one_timer_only;
  72     uint32_t freq_hz;
  73     struct xlx_timer *timers;
  74 };
  75
  76 static inline unsigned int num_timers(struct timerblock *t)
  77 {
  78     return 2 - t->one_timer_only;
  79 }
  80
  81 static inline unsigned int timer_from_addr(hwaddr addr)
  82 {
  83     /* Timers get a 4x32bit control reg area each.  */
  84     return addr >> 2;
  85 }
  86
  87 static void timer_update_irq(struct timerblock *t)
  88 {
  89     unsigned int i, irq = 0;
  90     uint32_t csr;
  91
  92     for (i = 0; i < num_timers(t); i++) {
  93         csr = t->timers[i].regs[R_TCSR];
  94         irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
  95     }
  96
  97     /* All timers within the same slave share a single IRQ line.  */
  98     qemu_set_irq(t->irq, !!irq);
  99 }
 100
 101 static uint64_t
 102 timer_read(void *opaque, hwaddr addr, unsigned int size)
 103 {
 104     struct timerblock *t = opaque;
 105     struct xlx_timer *xt;
 106     uint32_t r = 0;
 107     unsigned int timer;
 108
 109     addr >>= 2;
 110     timer = timer_from_addr(addr);
 111     xt = &t->timers[timer];
 112     /* Further decoding to address a specific timers reg.  */
 113     addr &= 0x3;
 114     switch (addr)
 115     {
 116         case R_TCR:
 117                 r = ptimer_get_count(xt->ptimer);
 118                 if (!(xt->regs[R_TCSR] & TCSR_UDT))
 119                     r = ~r;
 120                 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
 121                          timer, r, xt->regs[R_TCSR] & TCSR_UDT));
 122             break;
 123         default:
 124             if (addr < ARRAY_SIZE(xt->regs))
 125                 r = xt->regs[addr];
 126             break;
 127
 128     }
 129     D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
 130     return r;
 131 }
 132
 133 static void timer_enable(struct xlx_timer *xt)
 134 {
 135     uint64_t count;
 136
 137     D(fprintf(stderr, "%s timer=%d down=%d\n", __func__,
 138               xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
 139
 140     ptimer_stop(xt->ptimer);
 141
 142     if (xt->regs[R_TCSR] & TCSR_UDT)
 143         count = xt->regs[R_TLR];
 144     else
 145         count = ~0 - xt->regs[R_TLR];
 146     ptimer_set_limit(xt->ptimer, count, 1);
 147     ptimer_run(xt->ptimer, 1);
 148 }
 149
 150 static void
 151 timer_write(void *opaque, hwaddr addr,
 152             uint64_t val64, unsigned int size)
 153 {
 154     struct timerblock *t = opaque;
 155     struct xlx_timer *xt;
 156     unsigned int timer;
 157     uint32_t value = val64;
 158
 159     addr >>= 2;
 160     timer = timer_from_addr(addr);
 161     xt = &t->timers[timer];
 162     D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n",
 163              __func__, addr * 4, value, timer, addr & 3));
 164     /* Further decoding to address a specific timers reg.  */
 165     addr &= 3;
 166     switch (addr)
 167     {
 168         case R_TCSR:
 169             if (value & TCSR_TINT)
 170                 value &= ~TCSR_TINT;
 171
 172             xt->regs[addr] = value;
 173             if (value & TCSR_ENT)
 174                 timer_enable(xt);
 175             break;
 176
 177         default:
 178             if (addr < ARRAY_SIZE(xt->regs))
 179                 xt->regs[addr] = value;
 180             break;
 181     }
 182     timer_update_irq(t);
 183 }
 184
 185 static const MemoryRegionOps timer_ops = {
 186     .read = timer_read,
 187     .write = timer_write,
 188     .endianness = DEVICE_NATIVE_ENDIAN,
 189     .valid = {
 190         .min_access_size = 4,
 191         .max_access_size = 4
 192     }
 193 };
 194
 195 static void timer_hit(void *opaque)
 196 {
 197     struct xlx_timer *xt = opaque;
 198     struct timerblock *t = xt->parent;
 199     D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
 200     xt->regs[R_TCSR] |= TCSR_TINT;
 201
 202     if (xt->regs[R_TCSR] & TCSR_ARHT)
 203         timer_enable(xt);
 204     timer_update_irq(t);
 205 }
 206
 207 static int xilinx_timer_init(SysBusDevice *dev)
 208 {
 209     struct timerblock *t = XILINX_TIMER(dev);
 210     unsigned int i;
 211
 212     /* All timers share a single irq line.  */
 213     sysbus_init_irq(dev, &t->irq);
 214
 215     /* Init all the ptimers.  */
 216     t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
 217     for (i = 0; i < num_timers(t); i++) {
 218         struct xlx_timer *xt = &t->timers[i];
 219
 220         xt->parent = t;
 221         xt->nr = i;
 222         xt->bh = qemu_bh_new(timer_hit, xt);
 223         xt->ptimer = ptimer_init(xt->bh);
 224         ptimer_set_freq(xt->ptimer, t->freq_hz);
 225     }
 226
 227     memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
 228                           R_MAX * 4 * num_timers(t));
 229     sysbus_init_mmio(dev, &t->mmio);
 230     return 0;
 231 }
 232
 233 static Property xilinx_timer_properties[] = {
 234     DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
 235                                                                 62 * 1000000),
 236     DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
 237     DEFINE_PROP_END_OF_LIST(),
 238 };
 239
 240 static void xilinx_timer_class_init(ObjectClass *klass, void *data)
 241 {
 242     DeviceClass *dc = DEVICE_CLASS(klass);
 243     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 244
 245     k->init = xilinx_timer_init;
 246     dc->props = xilinx_timer_properties;
 247 }
 248
 249 static const TypeInfo xilinx_timer_info = {
 250     .name          = TYPE_XILINX_TIMER,
 251     .parent        = TYPE_SYS_BUS_DEVICE,
 252     .instance_size = sizeof(struct timerblock),
 253     .class_init    = xilinx_timer_class_init,
 254 };
 255
 256 static void xilinx_timer_register_types(void)
 257 {
 258     type_register_static(&xilinx_timer_info);
 259 }
 260
 261 type_init(xilinx_timer_register_types)