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ui/vnc-enc-tight: remove switch and have single return
[qemu.git] / target-i386 / cpu.c
blobdb12728abf88a7fbb08c127b7ffb5d69b29c7c63
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "qemu/cutils.h"
21
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/cpus.h"
26 #include "kvm_i386.h"
27
28 #include "qemu/error-report.h"
29 #include "qemu/option.h"
30 #include "qemu/config-file.h"
31 #include "qapi/qmp/qerror.h"
32
33 #include "qapi-types.h"
34 #include "qapi-visit.h"
35 #include "qapi/visitor.h"
36 #include "sysemu/arch_init.h"
37
38 #if defined(CONFIG_KVM)
39 #include <linux/kvm_para.h>
40 #endif
41
42 #include "sysemu/sysemu.h"
43 #include "hw/qdev-properties.h"
44 #include "hw/i386/topology.h"
45 #ifndef CONFIG_USER_ONLY
46 #include "exec/address-spaces.h"
47 #include "hw/hw.h"
48 #include "hw/xen/xen.h"
49 #include "hw/i386/apic_internal.h"
50 #endif
51
52
53 /* Cache topology CPUID constants: */
54
55 /* CPUID Leaf 2 Descriptors */
56
57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
59 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
60 #define CPUID_2_L3_16MB_16WAY_64B 0x4d
61
62
63 /* CPUID Leaf 4 constants: */
64
65 /* EAX: */
66 #define CPUID_4_TYPE_DCACHE 1
67 #define CPUID_4_TYPE_ICACHE 2
68 #define CPUID_4_TYPE_UNIFIED 3
69
70 #define CPUID_4_LEVEL(l) ((l) << 5)
71
72 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
73 #define CPUID_4_FULLY_ASSOC (1 << 9)
74
75 /* EDX: */
76 #define CPUID_4_NO_INVD_SHARING (1 << 0)
77 #define CPUID_4_INCLUSIVE (1 << 1)
78 #define CPUID_4_COMPLEX_IDX (1 << 2)
79
80 #define ASSOC_FULL 0xFF
81
82 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
83 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
84 a == 2 ? 0x2 : \
85 a == 4 ? 0x4 : \
86 a == 8 ? 0x6 : \
87 a == 16 ? 0x8 : \
88 a == 32 ? 0xA : \
89 a == 48 ? 0xB : \
90 a == 64 ? 0xC : \
91 a == 96 ? 0xD : \
92 a == 128 ? 0xE : \
93 a == ASSOC_FULL ? 0xF : \
94 0 /* invalid value */)
95
96
97 /* Definitions of the hardcoded cache entries we expose: */
98
99 /* L1 data cache: */
100 #define L1D_LINE_SIZE 64
101 #define L1D_ASSOCIATIVITY 8
102 #define L1D_SETS 64
103 #define L1D_PARTITIONS 1
104 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
105 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
106 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
107 #define L1D_LINES_PER_TAG 1
108 #define L1D_SIZE_KB_AMD 64
109 #define L1D_ASSOCIATIVITY_AMD 2
110
111 /* L1 instruction cache: */
112 #define L1I_LINE_SIZE 64
113 #define L1I_ASSOCIATIVITY 8
114 #define L1I_SETS 64
115 #define L1I_PARTITIONS 1
116 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
117 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
118 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
119 #define L1I_LINES_PER_TAG 1
120 #define L1I_SIZE_KB_AMD 64
121 #define L1I_ASSOCIATIVITY_AMD 2
122
123 /* Level 2 unified cache: */
124 #define L2_LINE_SIZE 64
125 #define L2_ASSOCIATIVITY 16
126 #define L2_SETS 4096
127 #define L2_PARTITIONS 1
128 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
129 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
130 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
131 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
132 #define L2_LINES_PER_TAG 1
133 #define L2_SIZE_KB_AMD 512
134
135 /* Level 3 unified cache: */
136 #define L3_SIZE_KB 0 /* disabled */
137 #define L3_ASSOCIATIVITY 0 /* disabled */
138 #define L3_LINES_PER_TAG 0 /* disabled */
139 #define L3_LINE_SIZE 0 /* disabled */
140 #define L3_N_LINE_SIZE 64
141 #define L3_N_ASSOCIATIVITY 16
142 #define L3_N_SETS 16384
143 #define L3_N_PARTITIONS 1
144 #define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
145 #define L3_N_LINES_PER_TAG 1
146 #define L3_N_SIZE_KB_AMD 16384
147
148 /* TLB definitions: */
149
150 #define L1_DTLB_2M_ASSOC 1
151 #define L1_DTLB_2M_ENTRIES 255
152 #define L1_DTLB_4K_ASSOC 1
153 #define L1_DTLB_4K_ENTRIES 255
154
155 #define L1_ITLB_2M_ASSOC 1
156 #define L1_ITLB_2M_ENTRIES 255
157 #define L1_ITLB_4K_ASSOC 1
158 #define L1_ITLB_4K_ENTRIES 255
159
160 #define L2_DTLB_2M_ASSOC 0 /* disabled */
161 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
162 #define L2_DTLB_4K_ASSOC 4
163 #define L2_DTLB_4K_ENTRIES 512
164
165 #define L2_ITLB_2M_ASSOC 0 /* disabled */
166 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
167 #define L2_ITLB_4K_ASSOC 4
168 #define L2_ITLB_4K_ENTRIES 512
169
170
171
172 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
173 uint32_t vendor2, uint32_t vendor3)
174 {
175 int i;
176 for (i = 0; i < 4; i++) {
177 dst[i] = vendor1 >> (8 * i);
178 dst[i + 4] = vendor2 >> (8 * i);
179 dst[i + 8] = vendor3 >> (8 * i);
180 }
181 dst[CPUID_VENDOR_SZ] = '\0';
182 }
183
184 /* feature flags taken from "Intel Processor Identification and the CPUID
185 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
186 * between feature naming conventions, aliases may be added.
187 */
188 static const char *feature_name[] = {
189 "fpu", "vme", "de", "pse",
190 "tsc", "msr", "pae", "mce",
191 "cx8", "apic", NULL, "sep",
192 "mtrr", "pge", "mca", "cmov",
193 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
194 NULL, "ds" /* Intel dts */, "acpi", "mmx",
195 "fxsr", "sse", "sse2", "ss",
196 "ht" /* Intel htt */, "tm", "ia64", "pbe",
197 };
198 static const char *ext_feature_name[] = {
199 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
200 "ds_cpl", "vmx", "smx", "est",
201 "tm2", "ssse3", "cid", NULL,
202 "fma", "cx16", "xtpr", "pdcm",
203 NULL, "pcid", "dca", "sse4.1|sse4_1",
204 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
205 "tsc-deadline", "aes", "xsave", "osxsave",
206 "avx", "f16c", "rdrand", "hypervisor",
207 };
208 /* Feature names that are already defined on feature_name[] but are set on
209 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
210 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
211 * if and only if CPU vendor is AMD.
212 */
213 static const char *ext2_feature_name[] = {
214 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
215 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
216 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
217 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
218 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
219 "nx|xd", NULL, "mmxext", NULL /* mmx */,
220 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
221 NULL, "lm|i64", "3dnowext", "3dnow",
222 };
223 static const char *ext3_feature_name[] = {
224 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
225 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
226 "3dnowprefetch", "osvw", "ibs", "xop",
227 "skinit", "wdt", NULL, "lwp",
228 "fma4", "tce", NULL, "nodeid_msr",
229 NULL, "tbm", "topoext", "perfctr_core",
230 "perfctr_nb", NULL, NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 };
233
234 static const char *ext4_feature_name[] = {
235 NULL, NULL, "xstore", "xstore-en",
236 NULL, NULL, "xcrypt", "xcrypt-en",
237 "ace2", "ace2-en", "phe", "phe-en",
238 "pmm", "pmm-en", NULL, NULL,
239 NULL, NULL, NULL, NULL,
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 };
244
245 static const char *kvm_feature_name[] = {
246 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
247 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
248 NULL, NULL, NULL, NULL,
249 NULL, NULL, NULL, NULL,
250 NULL, NULL, NULL, NULL,
251 NULL, NULL, NULL, NULL,
252 "kvmclock-stable-bit", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 };
255
256 static const char *hyperv_priv_feature_name[] = {
257 NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
258 NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
259 NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
260 NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
261 NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
262 NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
263 NULL, NULL, NULL, NULL,
264 NULL, NULL, NULL, NULL,
265 NULL, NULL, NULL, NULL,
266 NULL, NULL, NULL, NULL,
267 NULL, NULL, NULL, NULL,
268 };
269
270 static const char *hyperv_ident_feature_name[] = {
271 NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
272 NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
273 NULL /* hv_post_messages */, NULL /* hv_signal_events */,
274 NULL /* hv_create_port */, NULL /* hv_connect_port */,
275 NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
276 NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
277 NULL, NULL,
278 NULL, NULL, NULL, NULL,
279 NULL, NULL, NULL, NULL,
280 NULL, NULL, NULL, NULL,
281 NULL, NULL, NULL, NULL,
282 };
283
284 static const char *hyperv_misc_feature_name[] = {
285 NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
286 NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
287 NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
288 NULL, NULL,
289 NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
290 NULL, NULL, NULL, NULL,
291 NULL, NULL, NULL, NULL,
292 NULL, NULL, NULL, NULL,
293 NULL, NULL, NULL, NULL,
294 NULL, NULL, NULL, NULL,
295 };
296
297 static const char *svm_feature_name[] = {
298 "npt", "lbrv", "svm_lock", "nrip_save",
299 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
300 NULL, NULL, "pause_filter", NULL,
301 "pfthreshold", NULL, NULL, NULL,
302 NULL, NULL, NULL, NULL,
303 NULL, NULL, NULL, NULL,
304 NULL, NULL, NULL, NULL,
305 NULL, NULL, NULL, NULL,
306 };
307
308 static const char *cpuid_7_0_ebx_feature_name[] = {
309 "fsgsbase", "tsc_adjust", NULL, "bmi1",
310 "hle", "avx2", NULL, "smep",
311 "bmi2", "erms", "invpcid", "rtm",
312 NULL, NULL, "mpx", NULL,
313 "avx512f", "avx512dq", "rdseed", "adx",
314 "smap", "avx512ifma", "pcommit", "clflushopt",
315 "clwb", NULL, "avx512pf", "avx512er",
316 "avx512cd", NULL, "avx512bw", "avx512vl",
317 };
318
319 static const char *cpuid_7_0_ecx_feature_name[] = {
320 NULL, "avx512vbmi", "umip", "pku",
321 "ospke", NULL, NULL, NULL,
322 NULL, NULL, NULL, NULL,
323 NULL, NULL, NULL, NULL,
324 NULL, NULL, NULL, NULL,
325 NULL, NULL, "rdpid", NULL,
326 NULL, NULL, NULL, NULL,
327 NULL, NULL, NULL, NULL,
328 };
329
330 static const char *cpuid_apm_edx_feature_name[] = {
331 NULL, NULL, NULL, NULL,
332 NULL, NULL, NULL, NULL,
333 "invtsc", NULL, NULL, NULL,
334 NULL, NULL, NULL, NULL,
335 NULL, NULL, NULL, NULL,
336 NULL, NULL, NULL, NULL,
337 NULL, NULL, NULL, NULL,
338 NULL, NULL, NULL, NULL,
339 };
340
341 static const char *cpuid_xsave_feature_name[] = {
342 "xsaveopt", "xsavec", "xgetbv1", "xsaves",
343 NULL, NULL, NULL, NULL,
344 NULL, NULL, NULL, NULL,
345 NULL, NULL, NULL, NULL,
346 NULL, NULL, NULL, NULL,
347 NULL, NULL, NULL, NULL,
348 NULL, NULL, NULL, NULL,
349 NULL, NULL, NULL, NULL,
350 };
351
352 static const char *cpuid_6_feature_name[] = {
353 NULL, NULL, "arat", NULL,
354 NULL, NULL, NULL, NULL,
355 NULL, NULL, NULL, NULL,
356 NULL, NULL, NULL, NULL,
357 NULL, NULL, NULL, NULL,
358 NULL, NULL, NULL, NULL,
359 NULL, NULL, NULL, NULL,
360 NULL, NULL, NULL, NULL,
361 };
362
363 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
364 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
365 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
366 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
367 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
368 CPUID_PSE36 | CPUID_FXSR)
369 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
370 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
371 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
372 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
373 CPUID_PAE | CPUID_SEP | CPUID_APIC)
374
375 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
376 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
377 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
378 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
379 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
380 /* partly implemented:
381 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
382 /* missing:
383 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
384 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
385 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
386 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
387 CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
388 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
389 /* missing:
390 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
391 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
392 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
393 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
394 CPUID_EXT_F16C, CPUID_EXT_RDRAND */
395
396 #ifdef TARGET_X86_64
397 #define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
398 #else
399 #define TCG_EXT2_X86_64_FEATURES 0
400 #endif
401
402 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
403 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
404 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
405 TCG_EXT2_X86_64_FEATURES)
406 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
407 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
408 #define TCG_EXT4_FEATURES 0
409 #define TCG_SVM_FEATURES 0
410 #define TCG_KVM_FEATURES 0
411 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
412 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
413 CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
414 CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
415 CPUID_7_0_EBX_ERMS)
416 /* missing:
417 CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
418 CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
419 CPUID_7_0_EBX_RDSEED */
420 #define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
421 #define TCG_APM_FEATURES 0
422 #define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
423 #define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
424 /* missing:
425 CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
426
427 typedef struct FeatureWordInfo {
428 const char **feat_names;
429 uint32_t cpuid_eax; /* Input EAX for CPUID */
430 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
431 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
432 int cpuid_reg; /* output register (R_* constant) */
433 uint32_t tcg_features; /* Feature flags supported by TCG */
434 uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
435 } FeatureWordInfo;
436
437 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
438 [FEAT_1_EDX] = {
439 .feat_names = feature_name,
440 .cpuid_eax = 1, .cpuid_reg = R_EDX,
441 .tcg_features = TCG_FEATURES,
442 },
443 [FEAT_1_ECX] = {
444 .feat_names = ext_feature_name,
445 .cpuid_eax = 1, .cpuid_reg = R_ECX,
446 .tcg_features = TCG_EXT_FEATURES,
447 },
448 [FEAT_8000_0001_EDX] = {
449 .feat_names = ext2_feature_name,
450 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
451 .tcg_features = TCG_EXT2_FEATURES,
452 },
453 [FEAT_8000_0001_ECX] = {
454 .feat_names = ext3_feature_name,
455 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
456 .tcg_features = TCG_EXT3_FEATURES,
457 },
458 [FEAT_C000_0001_EDX] = {
459 .feat_names = ext4_feature_name,
460 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
461 .tcg_features = TCG_EXT4_FEATURES,
462 },
463 [FEAT_KVM] = {
464 .feat_names = kvm_feature_name,
465 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
466 .tcg_features = TCG_KVM_FEATURES,
467 },
468 [FEAT_HYPERV_EAX] = {
469 .feat_names = hyperv_priv_feature_name,
470 .cpuid_eax = 0x40000003, .cpuid_reg = R_EAX,
471 },
472 [FEAT_HYPERV_EBX] = {
473 .feat_names = hyperv_ident_feature_name,
474 .cpuid_eax = 0x40000003, .cpuid_reg = R_EBX,
475 },
476 [FEAT_HYPERV_EDX] = {
477 .feat_names = hyperv_misc_feature_name,
478 .cpuid_eax = 0x40000003, .cpuid_reg = R_EDX,
479 },
480 [FEAT_SVM] = {
481 .feat_names = svm_feature_name,
482 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
483 .tcg_features = TCG_SVM_FEATURES,
484 },
485 [FEAT_7_0_EBX] = {
486 .feat_names = cpuid_7_0_ebx_feature_name,
487 .cpuid_eax = 7,
488 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
489 .cpuid_reg = R_EBX,
490 .tcg_features = TCG_7_0_EBX_FEATURES,
491 },
492 [FEAT_7_0_ECX] = {
493 .feat_names = cpuid_7_0_ecx_feature_name,
494 .cpuid_eax = 7,
495 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
496 .cpuid_reg = R_ECX,
497 .tcg_features = TCG_7_0_ECX_FEATURES,
498 },
499 [FEAT_8000_0007_EDX] = {
500 .feat_names = cpuid_apm_edx_feature_name,
501 .cpuid_eax = 0x80000007,
502 .cpuid_reg = R_EDX,
503 .tcg_features = TCG_APM_FEATURES,
504 .unmigratable_flags = CPUID_APM_INVTSC,
505 },
506 [FEAT_XSAVE] = {
507 .feat_names = cpuid_xsave_feature_name,
508 .cpuid_eax = 0xd,
509 .cpuid_needs_ecx = true, .cpuid_ecx = 1,
510 .cpuid_reg = R_EAX,
511 .tcg_features = TCG_XSAVE_FEATURES,
512 },
513 [FEAT_6_EAX] = {
514 .feat_names = cpuid_6_feature_name,
515 .cpuid_eax = 6, .cpuid_reg = R_EAX,
516 .tcg_features = TCG_6_EAX_FEATURES,
517 },
518 };
519
520 typedef struct X86RegisterInfo32 {
521 /* Name of register */
522 const char *name;
523 /* QAPI enum value register */
524 X86CPURegister32 qapi_enum;
525 } X86RegisterInfo32;
526
527 #define REGISTER(reg) \
528 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
529 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
530 REGISTER(EAX),
531 REGISTER(ECX),
532 REGISTER(EDX),
533 REGISTER(EBX),
534 REGISTER(ESP),
535 REGISTER(EBP),
536 REGISTER(ESI),
537 REGISTER(EDI),
538 };
539 #undef REGISTER
540
541 typedef struct ExtSaveArea {
542 uint32_t feature, bits;
543 uint32_t offset, size;
544 } ExtSaveArea;
545
546 static const ExtSaveArea x86_ext_save_areas[] = {
547 [XSTATE_YMM_BIT] =
548 { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
549 .offset = offsetof(X86XSaveArea, avx_state),
550 .size = sizeof(XSaveAVX) },
551 [XSTATE_BNDREGS_BIT] =
552 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
553 .offset = offsetof(X86XSaveArea, bndreg_state),
554 .size = sizeof(XSaveBNDREG) },
555 [XSTATE_BNDCSR_BIT] =
556 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
557 .offset = offsetof(X86XSaveArea, bndcsr_state),
558 .size = sizeof(XSaveBNDCSR) },
559 [XSTATE_OPMASK_BIT] =
560 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
561 .offset = offsetof(X86XSaveArea, opmask_state),
562 .size = sizeof(XSaveOpmask) },
563 [XSTATE_ZMM_Hi256_BIT] =
564 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
565 .offset = offsetof(X86XSaveArea, zmm_hi256_state),
566 .size = sizeof(XSaveZMM_Hi256) },
567 [XSTATE_Hi16_ZMM_BIT] =
568 { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_AVX512F,
569 .offset = offsetof(X86XSaveArea, hi16_zmm_state),
570 .size = sizeof(XSaveHi16_ZMM) },
571 [XSTATE_PKRU_BIT] =
572 { .feature = FEAT_7_0_ECX, .bits = CPUID_7_0_ECX_PKU,
573 .offset = offsetof(X86XSaveArea, pkru_state),
574 .size = sizeof(XSavePKRU) },
575 };
576
577 const char *get_register_name_32(unsigned int reg)
578 {
579 if (reg >= CPU_NB_REGS32) {
580 return NULL;
581 }
582 return x86_reg_info_32[reg].name;
583 }
584
585 /*
586 * Returns the set of feature flags that are supported and migratable by
587 * QEMU, for a given FeatureWord.
588 */
589 static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
590 {
591 FeatureWordInfo *wi = &feature_word_info[w];
592 uint32_t r = 0;
593 int i;
594
595 for (i = 0; i < 32; i++) {
596 uint32_t f = 1U << i;
597 /* If the feature name is unknown, it is not supported by QEMU yet */
598 if (!wi->feat_names[i]) {
599 continue;
600 }
601 /* Skip features known to QEMU, but explicitly marked as unmigratable */
602 if (wi->unmigratable_flags & f) {
603 continue;
604 }
605 r |= f;
606 }
607 return r;
608 }
609
610 void host_cpuid(uint32_t function, uint32_t count,
611 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
612 {
613 uint32_t vec[4];
614
615 #ifdef __x86_64__
616 asm volatile("cpuid"
617 : "=a"(vec[0]), "=b"(vec[1]),
618 "=c"(vec[2]), "=d"(vec[3])
619 : "0"(function), "c"(count) : "cc");
620 #elif defined(__i386__)
621 asm volatile("pusha \n\t"
622 "cpuid \n\t"
623 "mov %%eax, 0(%2) \n\t"
624 "mov %%ebx, 4(%2) \n\t"
625 "mov %%ecx, 8(%2) \n\t"
626 "mov %%edx, 12(%2) \n\t"
627 "popa"
628 : : "a"(function), "c"(count), "S"(vec)
629 : "memory", "cc");
630 #else
631 abort();
632 #endif
633
634 if (eax)
635 *eax = vec[0];
636 if (ebx)
637 *ebx = vec[1];
638 if (ecx)
639 *ecx = vec[2];
640 if (edx)
641 *edx = vec[3];
642 }
643
644 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
645
646 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
647 * a substring. ex if !NULL points to the first char after a substring,
648 * otherwise the string is assumed to sized by a terminating nul.
649 * Return lexical ordering of *s1:*s2.
650 */
651 static int sstrcmp(const char *s1, const char *e1,
652 const char *s2, const char *e2)
653 {
654 for (;;) {
655 if (!*s1 || !*s2 || *s1 != *s2)
656 return (*s1 - *s2);
657 ++s1, ++s2;
658 if (s1 == e1 && s2 == e2)
659 return (0);
660 else if (s1 == e1)
661 return (*s2);
662 else if (s2 == e2)
663 return (*s1);
664 }
665 }
666
667 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
668 * '|' delimited (possibly empty) strings in which case search for a match
669 * within the alternatives proceeds left to right. Return 0 for success,
670 * non-zero otherwise.
671 */
672 static int altcmp(const char *s, const char *e, const char *altstr)
673 {
674 const char *p, *q;
675
676 for (q = p = altstr; ; ) {
677 while (*p && *p != '|')
678 ++p;
679 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
680 return (0);
681 if (!*p)
682 return (1);
683 else
684 q = ++p;
685 }
686 }
687
688 /* search featureset for flag *[s..e), if found set corresponding bit in
689 * *pval and return true, otherwise return false
690 */
691 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
692 const char **featureset)
693 {
694 uint32_t mask;
695 const char **ppc;
696 bool found = false;
697
698 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
699 if (*ppc && !altcmp(s, e, *ppc)) {
700 *pval |= mask;
701 found = true;
702 }
703 }
704 return found;
705 }
706
707 static void add_flagname_to_bitmaps(const char *flagname,
708 FeatureWordArray words,
709 Error **errp)
710 {
711 FeatureWord w;
712 for (w = 0; w < FEATURE_WORDS; w++) {
713 FeatureWordInfo *wi = &feature_word_info[w];
714 if (wi->feat_names &&
715 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
716 break;
717 }
718 }
719 if (w == FEATURE_WORDS) {
720 error_setg(errp, "CPU feature %s not found", flagname);
721 }
722 }
723
724 /* CPU class name definitions: */
725
726 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
727 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
728
729 /* Return type name for a given CPU model name
730 * Caller is responsible for freeing the returned string.
731 */
732 static char *x86_cpu_type_name(const char *model_name)
733 {
734 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
735 }
736
737 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
738 {
739 ObjectClass *oc;
740 char *typename;
741
742 if (cpu_model == NULL) {
743 return NULL;
744 }
745
746 typename = x86_cpu_type_name(cpu_model);
747 oc = object_class_by_name(typename);
748 g_free(typename);
749 return oc;
750 }
751
752 static char *x86_cpu_class_get_model_name(X86CPUClass *cc)
753 {
754 const char *class_name = object_class_get_name(OBJECT_CLASS(cc));
755 assert(g_str_has_suffix(class_name, X86_CPU_TYPE_SUFFIX));
756 return g_strndup(class_name,
757 strlen(class_name) - strlen(X86_CPU_TYPE_SUFFIX));
758 }
759
760 struct X86CPUDefinition {
761 const char *name;
762 uint32_t level;
763 uint32_t xlevel;
764 uint32_t xlevel2;
765 /* vendor is zero-terminated, 12 character ASCII string */
766 char vendor[CPUID_VENDOR_SZ + 1];
767 int family;
768 int model;
769 int stepping;
770 FeatureWordArray features;
771 char model_id[48];
772 };
773
774 static X86CPUDefinition builtin_x86_defs[] = {
775 {
776 .name = "qemu64",
777 .level = 0xd,
778 .vendor = CPUID_VENDOR_AMD,
779 .family = 6,
780 .model = 6,
781 .stepping = 3,
782 .features[FEAT_1_EDX] =
783 PPRO_FEATURES |
784 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
785 CPUID_PSE36,
786 .features[FEAT_1_ECX] =
787 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
788 .features[FEAT_8000_0001_EDX] =
789 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
790 .features[FEAT_8000_0001_ECX] =
791 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
792 .xlevel = 0x8000000A,
793 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
794 },
795 {
796 .name = "phenom",
797 .level = 5,
798 .vendor = CPUID_VENDOR_AMD,
799 .family = 16,
800 .model = 2,
801 .stepping = 3,
802 /* Missing: CPUID_HT */
803 .features[FEAT_1_EDX] =
804 PPRO_FEATURES |
805 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
806 CPUID_PSE36 | CPUID_VME,
807 .features[FEAT_1_ECX] =
808 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
809 CPUID_EXT_POPCNT,
810 .features[FEAT_8000_0001_EDX] =
811 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
812 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
813 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
814 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
815 CPUID_EXT3_CR8LEG,
816 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
817 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
818 .features[FEAT_8000_0001_ECX] =
819 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
820 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
821 /* Missing: CPUID_SVM_LBRV */
822 .features[FEAT_SVM] =
823 CPUID_SVM_NPT,
824 .xlevel = 0x8000001A,
825 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
826 },
827 {
828 .name = "core2duo",
829 .level = 10,
830 .vendor = CPUID_VENDOR_INTEL,
831 .family = 6,
832 .model = 15,
833 .stepping = 11,
834 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
835 .features[FEAT_1_EDX] =
836 PPRO_FEATURES |
837 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
838 CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
839 /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
840 * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
841 .features[FEAT_1_ECX] =
842 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
843 CPUID_EXT_CX16,
844 .features[FEAT_8000_0001_EDX] =
845 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
846 .features[FEAT_8000_0001_ECX] =
847 CPUID_EXT3_LAHF_LM,
848 .xlevel = 0x80000008,
849 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
850 },
851 {
852 .name = "kvm64",
853 .level = 0xd,
854 .vendor = CPUID_VENDOR_INTEL,
855 .family = 15,
856 .model = 6,
857 .stepping = 1,
858 /* Missing: CPUID_HT */
859 .features[FEAT_1_EDX] =
860 PPRO_FEATURES | CPUID_VME |
861 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
862 CPUID_PSE36,
863 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
864 .features[FEAT_1_ECX] =
865 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
866 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
867 .features[FEAT_8000_0001_EDX] =
868 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
869 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
870 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
871 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
872 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
873 .features[FEAT_8000_0001_ECX] =
874 0,
875 .xlevel = 0x80000008,
876 .model_id = "Common KVM processor"
877 },
878 {
879 .name = "qemu32",
880 .level = 4,
881 .vendor = CPUID_VENDOR_INTEL,
882 .family = 6,
883 .model = 6,
884 .stepping = 3,
885 .features[FEAT_1_EDX] =
886 PPRO_FEATURES,
887 .features[FEAT_1_ECX] =
888 CPUID_EXT_SSE3,
889 .xlevel = 0x80000004,
890 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
891 },
892 {
893 .name = "kvm32",
894 .level = 5,
895 .vendor = CPUID_VENDOR_INTEL,
896 .family = 15,
897 .model = 6,
898 .stepping = 1,
899 .features[FEAT_1_EDX] =
900 PPRO_FEATURES | CPUID_VME |
901 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
902 .features[FEAT_1_ECX] =
903 CPUID_EXT_SSE3,
904 .features[FEAT_8000_0001_ECX] =
905 0,
906 .xlevel = 0x80000008,
907 .model_id = "Common 32-bit KVM processor"
908 },
909 {
910 .name = "coreduo",
911 .level = 10,
912 .vendor = CPUID_VENDOR_INTEL,
913 .family = 6,
914 .model = 14,
915 .stepping = 8,
916 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
917 .features[FEAT_1_EDX] =
918 PPRO_FEATURES | CPUID_VME |
919 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
920 CPUID_SS,
921 /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
922 * CPUID_EXT_PDCM, CPUID_EXT_VMX */
923 .features[FEAT_1_ECX] =
924 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
925 .features[FEAT_8000_0001_EDX] =
926 CPUID_EXT2_NX,
927 .xlevel = 0x80000008,
928 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
929 },
930 {
931 .name = "486",
932 .level = 1,
933 .vendor = CPUID_VENDOR_INTEL,
934 .family = 4,
935 .model = 8,
936 .stepping = 0,
937 .features[FEAT_1_EDX] =
938 I486_FEATURES,
939 .xlevel = 0,
940 },
941 {
942 .name = "pentium",
943 .level = 1,
944 .vendor = CPUID_VENDOR_INTEL,
945 .family = 5,
946 .model = 4,
947 .stepping = 3,
948 .features[FEAT_1_EDX] =
949 PENTIUM_FEATURES,
950 .xlevel = 0,
951 },
952 {
953 .name = "pentium2",
954 .level = 2,
955 .vendor = CPUID_VENDOR_INTEL,
956 .family = 6,
957 .model = 5,
958 .stepping = 2,
959 .features[FEAT_1_EDX] =
960 PENTIUM2_FEATURES,
961 .xlevel = 0,
962 },
963 {
964 .name = "pentium3",
965 .level = 3,
966 .vendor = CPUID_VENDOR_INTEL,
967 .family = 6,
968 .model = 7,
969 .stepping = 3,
970 .features[FEAT_1_EDX] =
971 PENTIUM3_FEATURES,
972 .xlevel = 0,
973 },
974 {
975 .name = "athlon",
976 .level = 2,
977 .vendor = CPUID_VENDOR_AMD,
978 .family = 6,
979 .model = 2,
980 .stepping = 3,
981 .features[FEAT_1_EDX] =
982 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
983 CPUID_MCA,
984 .features[FEAT_8000_0001_EDX] =
985 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
986 .xlevel = 0x80000008,
987 .model_id = "QEMU Virtual CPU version " QEMU_HW_VERSION,
988 },
989 {
990 .name = "n270",
991 .level = 10,
992 .vendor = CPUID_VENDOR_INTEL,
993 .family = 6,
994 .model = 28,
995 .stepping = 2,
996 /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
997 .features[FEAT_1_EDX] =
998 PPRO_FEATURES |
999 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
1000 CPUID_ACPI | CPUID_SS,
1001 /* Some CPUs got no CPUID_SEP */
1002 /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
1003 * CPUID_EXT_XTPR */
1004 .features[FEAT_1_ECX] =
1005 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
1006 CPUID_EXT_MOVBE,
1007 .features[FEAT_8000_0001_EDX] =
1008 CPUID_EXT2_NX,
1009 .features[FEAT_8000_0001_ECX] =
1010 CPUID_EXT3_LAHF_LM,
1011 .xlevel = 0x80000008,
1012 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
1013 },
1014 {
1015 .name = "Conroe",
1016 .level = 10,
1017 .vendor = CPUID_VENDOR_INTEL,
1018 .family = 6,
1019 .model = 15,
1020 .stepping = 3,
1021 .features[FEAT_1_EDX] =
1022 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1023 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1024 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1025 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1026 CPUID_DE | CPUID_FP87,
1027 .features[FEAT_1_ECX] =
1028 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1029 .features[FEAT_8000_0001_EDX] =
1030 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1031 .features[FEAT_8000_0001_ECX] =
1032 CPUID_EXT3_LAHF_LM,
1033 .xlevel = 0x80000008,
1034 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
1035 },
1036 {
1037 .name = "Penryn",
1038 .level = 10,
1039 .vendor = CPUID_VENDOR_INTEL,
1040 .family = 6,
1041 .model = 23,
1042 .stepping = 3,
1043 .features[FEAT_1_EDX] =
1044 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1045 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1046 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1047 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1048 CPUID_DE | CPUID_FP87,
1049 .features[FEAT_1_ECX] =
1050 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1051 CPUID_EXT_SSE3,
1052 .features[FEAT_8000_0001_EDX] =
1053 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
1054 .features[FEAT_8000_0001_ECX] =
1055 CPUID_EXT3_LAHF_LM,
1056 .xlevel = 0x80000008,
1057 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
1058 },
1059 {
1060 .name = "Nehalem",
1061 .level = 11,
1062 .vendor = CPUID_VENDOR_INTEL,
1063 .family = 6,
1064 .model = 26,
1065 .stepping = 3,
1066 .features[FEAT_1_EDX] =
1067 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1068 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1069 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1070 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1071 CPUID_DE | CPUID_FP87,
1072 .features[FEAT_1_ECX] =
1073 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1074 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
1075 .features[FEAT_8000_0001_EDX] =
1076 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1077 .features[FEAT_8000_0001_ECX] =
1078 CPUID_EXT3_LAHF_LM,
1079 .xlevel = 0x80000008,
1080 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
1081 },
1082 {
1083 .name = "Westmere",
1084 .level = 11,
1085 .vendor = CPUID_VENDOR_INTEL,
1086 .family = 6,
1087 .model = 44,
1088 .stepping = 1,
1089 .features[FEAT_1_EDX] =
1090 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1091 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1092 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1093 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1094 CPUID_DE | CPUID_FP87,
1095 .features[FEAT_1_ECX] =
1096 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1097 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1098 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1099 .features[FEAT_8000_0001_EDX] =
1100 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
1101 .features[FEAT_8000_0001_ECX] =
1102 CPUID_EXT3_LAHF_LM,
1103 .features[FEAT_6_EAX] =
1104 CPUID_6_EAX_ARAT,
1105 .xlevel = 0x80000008,
1106 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
1107 },
1108 {
1109 .name = "SandyBridge",
1110 .level = 0xd,
1111 .vendor = CPUID_VENDOR_INTEL,
1112 .family = 6,
1113 .model = 42,
1114 .stepping = 1,
1115 .features[FEAT_1_EDX] =
1116 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1117 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1118 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1119 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1120 CPUID_DE | CPUID_FP87,
1121 .features[FEAT_1_ECX] =
1122 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1123 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1124 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1125 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1126 CPUID_EXT_SSE3,
1127 .features[FEAT_8000_0001_EDX] =
1128 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1129 CPUID_EXT2_SYSCALL,
1130 .features[FEAT_8000_0001_ECX] =
1131 CPUID_EXT3_LAHF_LM,
1132 .features[FEAT_XSAVE] =
1133 CPUID_XSAVE_XSAVEOPT,
1134 .features[FEAT_6_EAX] =
1135 CPUID_6_EAX_ARAT,
1136 .xlevel = 0x80000008,
1137 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
1138 },
1139 {
1140 .name = "IvyBridge",
1141 .level = 0xd,
1142 .vendor = CPUID_VENDOR_INTEL,
1143 .family = 6,
1144 .model = 58,
1145 .stepping = 9,
1146 .features[FEAT_1_EDX] =
1147 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1148 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1149 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1150 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1151 CPUID_DE | CPUID_FP87,
1152 .features[FEAT_1_ECX] =
1153 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1154 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
1155 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1156 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1157 CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1158 .features[FEAT_7_0_EBX] =
1159 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
1160 CPUID_7_0_EBX_ERMS,
1161 .features[FEAT_8000_0001_EDX] =
1162 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1163 CPUID_EXT2_SYSCALL,
1164 .features[FEAT_8000_0001_ECX] =
1165 CPUID_EXT3_LAHF_LM,
1166 .features[FEAT_XSAVE] =
1167 CPUID_XSAVE_XSAVEOPT,
1168 .features[FEAT_6_EAX] =
1169 CPUID_6_EAX_ARAT,
1170 .xlevel = 0x80000008,
1171 .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
1172 },
1173 {
1174 .name = "Haswell-noTSX",
1175 .level = 0xd,
1176 .vendor = CPUID_VENDOR_INTEL,
1177 .family = 6,
1178 .model = 60,
1179 .stepping = 1,
1180 .features[FEAT_1_EDX] =
1181 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1182 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1183 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1184 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1185 CPUID_DE | CPUID_FP87,
1186 .features[FEAT_1_ECX] =
1187 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1188 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1189 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1190 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1191 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1192 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1193 .features[FEAT_8000_0001_EDX] =
1194 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1195 CPUID_EXT2_SYSCALL,
1196 .features[FEAT_8000_0001_ECX] =
1197 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1198 .features[FEAT_7_0_EBX] =
1199 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1200 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1201 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
1202 .features[FEAT_XSAVE] =
1203 CPUID_XSAVE_XSAVEOPT,
1204 .features[FEAT_6_EAX] =
1205 CPUID_6_EAX_ARAT,
1206 .xlevel = 0x80000008,
1207 .model_id = "Intel Core Processor (Haswell, no TSX)",
1208 }, {
1209 .name = "Haswell",
1210 .level = 0xd,
1211 .vendor = CPUID_VENDOR_INTEL,
1212 .family = 6,
1213 .model = 60,
1214 .stepping = 1,
1215 .features[FEAT_1_EDX] =
1216 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1217 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1218 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1219 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1220 CPUID_DE | CPUID_FP87,
1221 .features[FEAT_1_ECX] =
1222 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1223 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1224 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1225 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1226 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1227 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1228 .features[FEAT_8000_0001_EDX] =
1229 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1230 CPUID_EXT2_SYSCALL,
1231 .features[FEAT_8000_0001_ECX] =
1232 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
1233 .features[FEAT_7_0_EBX] =
1234 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1235 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1236 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1237 CPUID_7_0_EBX_RTM,
1238 .features[FEAT_XSAVE] =
1239 CPUID_XSAVE_XSAVEOPT,
1240 .features[FEAT_6_EAX] =
1241 CPUID_6_EAX_ARAT,
1242 .xlevel = 0x80000008,
1243 .model_id = "Intel Core Processor (Haswell)",
1244 },
1245 {
1246 .name = "Broadwell-noTSX",
1247 .level = 0xd,
1248 .vendor = CPUID_VENDOR_INTEL,
1249 .family = 6,
1250 .model = 61,
1251 .stepping = 2,
1252 .features[FEAT_1_EDX] =
1253 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1254 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1255 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1256 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1257 CPUID_DE | CPUID_FP87,
1258 .features[FEAT_1_ECX] =
1259 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1260 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1261 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1262 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1263 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1264 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1265 .features[FEAT_8000_0001_EDX] =
1266 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1267 CPUID_EXT2_SYSCALL,
1268 .features[FEAT_8000_0001_ECX] =
1269 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1270 .features[FEAT_7_0_EBX] =
1271 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1272 CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1273 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1274 CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1275 CPUID_7_0_EBX_SMAP,
1276 .features[FEAT_XSAVE] =
1277 CPUID_XSAVE_XSAVEOPT,
1278 .features[FEAT_6_EAX] =
1279 CPUID_6_EAX_ARAT,
1280 .xlevel = 0x80000008,
1281 .model_id = "Intel Core Processor (Broadwell, no TSX)",
1282 },
1283 {
1284 .name = "Broadwell",
1285 .level = 0xd,
1286 .vendor = CPUID_VENDOR_INTEL,
1287 .family = 6,
1288 .model = 61,
1289 .stepping = 2,
1290 .features[FEAT_1_EDX] =
1291 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1292 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1293 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1294 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1295 CPUID_DE | CPUID_FP87,
1296 .features[FEAT_1_ECX] =
1297 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1298 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1299 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1300 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1301 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1302 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1303 .features[FEAT_8000_0001_EDX] =
1304 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1305 CPUID_EXT2_SYSCALL,
1306 .features[FEAT_8000_0001_ECX] =
1307 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1308 .features[FEAT_7_0_EBX] =
1309 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1310 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1311 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1312 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1313 CPUID_7_0_EBX_SMAP,
1314 .features[FEAT_XSAVE] =
1315 CPUID_XSAVE_XSAVEOPT,
1316 .features[FEAT_6_EAX] =
1317 CPUID_6_EAX_ARAT,
1318 .xlevel = 0x80000008,
1319 .model_id = "Intel Core Processor (Broadwell)",
1320 },
1321 {
1322 .name = "Skylake-Client",
1323 .level = 0xd,
1324 .vendor = CPUID_VENDOR_INTEL,
1325 .family = 6,
1326 .model = 94,
1327 .stepping = 3,
1328 .features[FEAT_1_EDX] =
1329 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1330 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1331 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1332 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1333 CPUID_DE | CPUID_FP87,
1334 .features[FEAT_1_ECX] =
1335 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1336 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
1337 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
1338 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
1339 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
1340 CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
1341 .features[FEAT_8000_0001_EDX] =
1342 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
1343 CPUID_EXT2_SYSCALL,
1344 .features[FEAT_8000_0001_ECX] =
1345 CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
1346 .features[FEAT_7_0_EBX] =
1347 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
1348 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
1349 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
1350 CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
1351 CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
1352 /* Missing: XSAVES (not supported by some Linux versions,
1353 * including v4.1 to v4.6).
1354 * KVM doesn't yet expose any XSAVES state save component,
1355 * and the only one defined in Skylake (processor tracing)
1356 * probably will block migration anyway.
1357 */
1358 .features[FEAT_XSAVE] =
1359 CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
1360 CPUID_XSAVE_XGETBV1,
1361 .features[FEAT_6_EAX] =
1362 CPUID_6_EAX_ARAT,
1363 .xlevel = 0x80000008,
1364 .model_id = "Intel Core Processor (Skylake)",
1365 },
1366 {
1367 .name = "Opteron_G1",
1368 .level = 5,
1369 .vendor = CPUID_VENDOR_AMD,
1370 .family = 15,
1371 .model = 6,
1372 .stepping = 1,
1373 .features[FEAT_1_EDX] =
1374 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1375 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1376 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1377 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1378 CPUID_DE | CPUID_FP87,
1379 .features[FEAT_1_ECX] =
1380 CPUID_EXT_SSE3,
1381 .features[FEAT_8000_0001_EDX] =
1382 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1383 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1384 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1385 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1386 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1387 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1388 .xlevel = 0x80000008,
1389 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
1390 },
1391 {
1392 .name = "Opteron_G2",
1393 .level = 5,
1394 .vendor = CPUID_VENDOR_AMD,
1395 .family = 15,
1396 .model = 6,
1397 .stepping = 1,
1398 .features[FEAT_1_EDX] =
1399 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1400 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1401 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1402 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1403 CPUID_DE | CPUID_FP87,
1404 .features[FEAT_1_ECX] =
1405 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1406 /* Missing: CPUID_EXT2_RDTSCP */
1407 .features[FEAT_8000_0001_EDX] =
1408 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
1409 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1410 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1411 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1412 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1413 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1414 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1415 .features[FEAT_8000_0001_ECX] =
1416 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1417 .xlevel = 0x80000008,
1418 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1419 },
1420 {
1421 .name = "Opteron_G3",
1422 .level = 5,
1423 .vendor = CPUID_VENDOR_AMD,
1424 .family = 15,
1425 .model = 6,
1426 .stepping = 1,
1427 .features[FEAT_1_EDX] =
1428 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1429 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1430 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1431 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1432 CPUID_DE | CPUID_FP87,
1433 .features[FEAT_1_ECX] =
1434 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1435 CPUID_EXT_SSE3,
1436 /* Missing: CPUID_EXT2_RDTSCP */
1437 .features[FEAT_8000_0001_EDX] =
1438 CPUID_EXT2_LM | CPUID_EXT2_FXSR |
1439 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1440 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1441 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1442 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1443 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1444 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1445 .features[FEAT_8000_0001_ECX] =
1446 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1447 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1448 .xlevel = 0x80000008,
1449 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1450 },
1451 {
1452 .name = "Opteron_G4",
1453 .level = 0xd,
1454 .vendor = CPUID_VENDOR_AMD,
1455 .family = 21,
1456 .model = 1,
1457 .stepping = 2,
1458 .features[FEAT_1_EDX] =
1459 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1460 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1461 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1462 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1463 CPUID_DE | CPUID_FP87,
1464 .features[FEAT_1_ECX] =
1465 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1466 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1467 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1468 CPUID_EXT_SSE3,
1469 /* Missing: CPUID_EXT2_RDTSCP */
1470 .features[FEAT_8000_0001_EDX] =
1471 CPUID_EXT2_LM |
1472 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1473 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1474 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1475 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1476 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1477 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1478 .features[FEAT_8000_0001_ECX] =
1479 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1480 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1481 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1482 CPUID_EXT3_LAHF_LM,
1483 /* no xsaveopt! */
1484 .xlevel = 0x8000001A,
1485 .model_id = "AMD Opteron 62xx class CPU",
1486 },
1487 {
1488 .name = "Opteron_G5",
1489 .level = 0xd,
1490 .vendor = CPUID_VENDOR_AMD,
1491 .family = 21,
1492 .model = 2,
1493 .stepping = 0,
1494 .features[FEAT_1_EDX] =
1495 CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1496 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1497 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1498 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1499 CPUID_DE | CPUID_FP87,
1500 .features[FEAT_1_ECX] =
1501 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1502 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1503 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1504 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1505 /* Missing: CPUID_EXT2_RDTSCP */
1506 .features[FEAT_8000_0001_EDX] =
1507 CPUID_EXT2_LM |
1508 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1509 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1510 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1511 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1512 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1513 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1514 .features[FEAT_8000_0001_ECX] =
1515 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1516 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1517 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1518 CPUID_EXT3_LAHF_LM,
1519 /* no xsaveopt! */
1520 .xlevel = 0x8000001A,
1521 .model_id = "AMD Opteron 63xx class CPU",
1522 },
1523 };
1524
1525 typedef struct PropValue {
1526 const char *prop, *value;
1527 } PropValue;
1528
1529 /* KVM-specific features that are automatically added/removed
1530 * from all CPU models when KVM is enabled.
1531 */
1532 static PropValue kvm_default_props[] = {
1533 { "kvmclock", "on" },
1534 { "kvm-nopiodelay", "on" },
1535 { "kvm-asyncpf", "on" },
1536 { "kvm-steal-time", "on" },
1537 { "kvm-pv-eoi", "on" },
1538 { "kvmclock-stable-bit", "on" },
1539 { "x2apic", "on" },
1540 { "acpi", "off" },
1541 { "monitor", "off" },
1542 { "svm", "off" },
1543 { NULL, NULL },
1544 };
1545
1546 void x86_cpu_change_kvm_default(const char *prop, const char *value)
1547 {
1548 PropValue *pv;
1549 for (pv = kvm_default_props; pv->prop; pv++) {
1550 if (!strcmp(pv->prop, prop)) {
1551 pv->value = value;
1552 break;
1553 }
1554 }
1555
1556 /* It is valid to call this function only for properties that
1557 * are already present in the kvm_default_props table.
1558 */
1559 assert(pv->prop);
1560 }
1561
1562 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
1563 bool migratable_only);
1564
1565 #ifdef CONFIG_KVM
1566
1567 static bool lmce_supported(void)
1568 {
1569 uint64_t mce_cap;
1570
1571 if (kvm_ioctl(kvm_state, KVM_X86_GET_MCE_CAP_SUPPORTED, &mce_cap) < 0) {
1572 return false;
1573 }
1574
1575 return !!(mce_cap & MCG_LMCE_P);
1576 }
1577
1578 static int cpu_x86_fill_model_id(char *str)
1579 {
1580 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1581 int i;
1582
1583 for (i = 0; i < 3; i++) {
1584 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1585 memcpy(str + i * 16 + 0, &eax, 4);
1586 memcpy(str + i * 16 + 4, &ebx, 4);
1587 memcpy(str + i * 16 + 8, &ecx, 4);
1588 memcpy(str + i * 16 + 12, &edx, 4);
1589 }
1590 return 0;
1591 }
1592
1593 static X86CPUDefinition host_cpudef;
1594
1595 static Property host_x86_cpu_properties[] = {
1596 DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true),
1597 DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false),
1598 DEFINE_PROP_END_OF_LIST()
1599 };
1600
1601 /* class_init for the "host" CPU model
1602 *
1603 * This function may be called before KVM is initialized.
1604 */
1605 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1606 {
1607 DeviceClass *dc = DEVICE_CLASS(oc);
1608 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1609 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1610
1611 xcc->kvm_required = true;
1612
1613 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1614 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1615
1616 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1617 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1618 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1619 host_cpudef.stepping = eax & 0x0F;
1620
1621 cpu_x86_fill_model_id(host_cpudef.model_id);
1622
1623 xcc->cpu_def = &host_cpudef;
1624
1625 /* level, xlevel, xlevel2, and the feature words are initialized on
1626 * instance_init, because they require KVM to be initialized.
1627 */
1628
1629 dc->props = host_x86_cpu_properties;
1630 /* Reason: host_x86_cpu_initfn() dies when !kvm_enabled() */
1631 dc->cannot_destroy_with_object_finalize_yet = true;
1632 }
1633
1634 static void host_x86_cpu_initfn(Object *obj)
1635 {
1636 X86CPU *cpu = X86_CPU(obj);
1637 CPUX86State *env = &cpu->env;
1638 KVMState *s = kvm_state;
1639
1640 /* We can't fill the features array here because we don't know yet if
1641 * "migratable" is true or false.
1642 */
1643 cpu->host_features = true;
1644
1645 /* If KVM is disabled, x86_cpu_realizefn() will report an error later */
1646 if (kvm_enabled()) {
1647 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1648 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1649 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1650
1651 if (lmce_supported()) {
1652 object_property_set_bool(OBJECT(cpu), true, "lmce", &error_abort);
1653 }
1654 }
1655
1656 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1657 }
1658
1659 static const TypeInfo host_x86_cpu_type_info = {
1660 .name = X86_CPU_TYPE_NAME("host"),
1661 .parent = TYPE_X86_CPU,
1662 .instance_init = host_x86_cpu_initfn,
1663 .class_init = host_x86_cpu_class_init,
1664 };
1665
1666 #endif
1667
1668 static void report_unavailable_features(FeatureWord w, uint32_t mask)
1669 {
1670 FeatureWordInfo *f = &feature_word_info[w];
1671 int i;
1672
1673 for (i = 0; i < 32; ++i) {
1674 if ((1UL << i) & mask) {
1675 const char *reg = get_register_name_32(f->cpuid_reg);
1676 assert(reg);
1677 fprintf(stderr, "warning: %s doesn't support requested feature: "
1678 "CPUID.%02XH:%s%s%s [bit %d]\n",
1679 kvm_enabled() ? "host" : "TCG",
1680 f->cpuid_eax, reg,
1681 f->feat_names[i] ? "." : "",
1682 f->feat_names[i] ? f->feat_names[i] : "", i);
1683 }
1684 }
1685 }
1686
1687 static void x86_cpuid_version_get_family(Object *obj, Visitor *v,
1688 const char *name, void *opaque,
1689 Error **errp)
1690 {
1691 X86CPU *cpu = X86_CPU(obj);
1692 CPUX86State *env = &cpu->env;
1693 int64_t value;
1694
1695 value = (env->cpuid_version >> 8) & 0xf;
1696 if (value == 0xf) {
1697 value += (env->cpuid_version >> 20) & 0xff;
1698 }
1699 visit_type_int(v, name, &value, errp);
1700 }
1701
1702 static void x86_cpuid_version_set_family(Object *obj, Visitor *v,
1703 const char *name, void *opaque,
1704 Error **errp)
1705 {
1706 X86CPU *cpu = X86_CPU(obj);
1707 CPUX86State *env = &cpu->env;
1708 const int64_t min = 0;
1709 const int64_t max = 0xff + 0xf;
1710 Error *local_err = NULL;
1711 int64_t value;
1712
1713 visit_type_int(v, name, &value, &local_err);
1714 if (local_err) {
1715 error_propagate(errp, local_err);
1716 return;
1717 }
1718 if (value < min || value > max) {
1719 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1720 name ? name : "null", value, min, max);
1721 return;
1722 }
1723
1724 env->cpuid_version &= ~0xff00f00;
1725 if (value > 0x0f) {
1726 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1727 } else {
1728 env->cpuid_version |= value << 8;
1729 }
1730 }
1731
1732 static void x86_cpuid_version_get_model(Object *obj, Visitor *v,
1733 const char *name, void *opaque,
1734 Error **errp)
1735 {
1736 X86CPU *cpu = X86_CPU(obj);
1737 CPUX86State *env = &cpu->env;
1738 int64_t value;
1739
1740 value = (env->cpuid_version >> 4) & 0xf;
1741 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1742 visit_type_int(v, name, &value, errp);
1743 }
1744
1745 static void x86_cpuid_version_set_model(Object *obj, Visitor *v,
1746 const char *name, void *opaque,
1747 Error **errp)
1748 {
1749 X86CPU *cpu = X86_CPU(obj);
1750 CPUX86State *env = &cpu->env;
1751 const int64_t min = 0;
1752 const int64_t max = 0xff;
1753 Error *local_err = NULL;
1754 int64_t value;
1755
1756 visit_type_int(v, name, &value, &local_err);
1757 if (local_err) {
1758 error_propagate(errp, local_err);
1759 return;
1760 }
1761 if (value < min || value > max) {
1762 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1763 name ? name : "null", value, min, max);
1764 return;
1765 }
1766
1767 env->cpuid_version &= ~0xf00f0;
1768 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1769 }
1770
1771 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1772 const char *name, void *opaque,
1773 Error **errp)
1774 {
1775 X86CPU *cpu = X86_CPU(obj);
1776 CPUX86State *env = &cpu->env;
1777 int64_t value;
1778
1779 value = env->cpuid_version & 0xf;
1780 visit_type_int(v, name, &value, errp);
1781 }
1782
1783 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1784 const char *name, void *opaque,
1785 Error **errp)
1786 {
1787 X86CPU *cpu = X86_CPU(obj);
1788 CPUX86State *env = &cpu->env;
1789 const int64_t min = 0;
1790 const int64_t max = 0xf;
1791 Error *local_err = NULL;
1792 int64_t value;
1793
1794 visit_type_int(v, name, &value, &local_err);
1795 if (local_err) {
1796 error_propagate(errp, local_err);
1797 return;
1798 }
1799 if (value < min || value > max) {
1800 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1801 name ? name : "null", value, min, max);
1802 return;
1803 }
1804
1805 env->cpuid_version &= ~0xf;
1806 env->cpuid_version |= value & 0xf;
1807 }
1808
1809 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1810 {
1811 X86CPU *cpu = X86_CPU(obj);
1812 CPUX86State *env = &cpu->env;
1813 char *value;
1814
1815 value = g_malloc(CPUID_VENDOR_SZ + 1);
1816 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1817 env->cpuid_vendor3);
1818 return value;
1819 }
1820
1821 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1822 Error **errp)
1823 {
1824 X86CPU *cpu = X86_CPU(obj);
1825 CPUX86State *env = &cpu->env;
1826 int i;
1827
1828 if (strlen(value) != CPUID_VENDOR_SZ) {
1829 error_setg(errp, QERR_PROPERTY_VALUE_BAD, "", "vendor", value);
1830 return;
1831 }
1832
1833 env->cpuid_vendor1 = 0;
1834 env->cpuid_vendor2 = 0;
1835 env->cpuid_vendor3 = 0;
1836 for (i = 0; i < 4; i++) {
1837 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1838 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1839 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1840 }
1841 }
1842
1843 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1844 {
1845 X86CPU *cpu = X86_CPU(obj);
1846 CPUX86State *env = &cpu->env;
1847 char *value;
1848 int i;
1849
1850 value = g_malloc(48 + 1);
1851 for (i = 0; i < 48; i++) {
1852 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1853 }
1854 value[48] = '\0';
1855 return value;
1856 }
1857
1858 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1859 Error **errp)
1860 {
1861 X86CPU *cpu = X86_CPU(obj);
1862 CPUX86State *env = &cpu->env;
1863 int c, len, i;
1864
1865 if (model_id == NULL) {
1866 model_id = "";
1867 }
1868 len = strlen(model_id);
1869 memset(env->cpuid_model, 0, 48);
1870 for (i = 0; i < 48; i++) {
1871 if (i >= len) {
1872 c = '\0';
1873 } else {
1874 c = (uint8_t)model_id[i];
1875 }
1876 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1877 }
1878 }
1879
1880 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, const char *name,
1881 void *opaque, Error **errp)
1882 {
1883 X86CPU *cpu = X86_CPU(obj);
1884 int64_t value;
1885
1886 value = cpu->env.tsc_khz * 1000;
1887 visit_type_int(v, name, &value, errp);
1888 }
1889
1890 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, const char *name,
1891 void *opaque, Error **errp)
1892 {
1893 X86CPU *cpu = X86_CPU(obj);
1894 const int64_t min = 0;
1895 const int64_t max = INT64_MAX;
1896 Error *local_err = NULL;
1897 int64_t value;
1898
1899 visit_type_int(v, name, &value, &local_err);
1900 if (local_err) {
1901 error_propagate(errp, local_err);
1902 return;
1903 }
1904 if (value < min || value > max) {
1905 error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1906 name ? name : "null", value, min, max);
1907 return;
1908 }
1909
1910 cpu->env.tsc_khz = cpu->env.user_tsc_khz = value / 1000;
1911 }
1912
1913 /* Generic getter for "feature-words" and "filtered-features" properties */
1914 static void x86_cpu_get_feature_words(Object *obj, Visitor *v,
1915 const char *name, void *opaque,
1916 Error **errp)
1917 {
1918 uint32_t *array = (uint32_t *)opaque;
1919 FeatureWord w;
1920 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1921 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1922 X86CPUFeatureWordInfoList *list = NULL;
1923
1924 for (w = 0; w < FEATURE_WORDS; w++) {
1925 FeatureWordInfo *wi = &feature_word_info[w];
1926 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1927 qwi->cpuid_input_eax = wi->cpuid_eax;
1928 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1929 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1930 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1931 qwi->features = array[w];
1932
1933 /* List will be in reverse order, but order shouldn't matter */
1934 list_entries[w].next = list;
1935 list_entries[w].value = &word_infos[w];
1936 list = &list_entries[w];
1937 }
1938
1939 visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
1940 }
1941
1942 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1943 void *opaque, Error **errp)
1944 {
1945 X86CPU *cpu = X86_CPU(obj);
1946 int64_t value = cpu->hyperv_spinlock_attempts;
1947
1948 visit_type_int(v, name, &value, errp);
1949 }
1950
1951 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, const char *name,
1952 void *opaque, Error **errp)
1953 {
1954 const int64_t min = 0xFFF;
1955 const int64_t max = UINT_MAX;
1956 X86CPU *cpu = X86_CPU(obj);
1957 Error *err = NULL;
1958 int64_t value;
1959
1960 visit_type_int(v, name, &value, &err);
1961 if (err) {
1962 error_propagate(errp, err);
1963 return;
1964 }
1965
1966 if (value < min || value > max) {
1967 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1968 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1969 object_get_typename(obj), name ? name : "null",
1970 value, min, max);
1971 return;
1972 }
1973 cpu->hyperv_spinlock_attempts = value;
1974 }
1975
1976 static PropertyInfo qdev_prop_spinlocks = {
1977 .name = "int",
1978 .get = x86_get_hv_spinlocks,
1979 .set = x86_set_hv_spinlocks,
1980 };
1981
1982 /* Convert all '_' in a feature string option name to '-', to make feature
1983 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1984 */
1985 static inline void feat2prop(char *s)
1986 {
1987 while ((s = strchr(s, '_'))) {
1988 *s = '-';
1989 }
1990 }
1991
1992 /* Compatibily hack to maintain legacy +-feat semantic,
1993 * where +-feat overwrites any feature set by
1994 * feat=on|feat even if the later is parsed after +-feat
1995 * (i.e. "-x2apic,x2apic=on" will result in x2apic disabled)
1996 */
1997 static FeatureWordArray plus_features = { 0 };
1998 static FeatureWordArray minus_features = { 0 };
1999
2000 /* Parse "+feature,-feature,feature=foo" CPU feature string
2001 */
2002 static void x86_cpu_parse_featurestr(const char *typename, char *features,
2003 Error **errp)
2004 {
2005 char *featurestr; /* Single 'key=value" string being parsed */
2006 Error *local_err = NULL;
2007 static bool cpu_globals_initialized;
2008
2009 if (cpu_globals_initialized) {
2010 return;
2011 }
2012 cpu_globals_initialized = true;
2013
2014 if (!features) {
2015 return;
2016 }
2017
2018 for (featurestr = strtok(features, ",");
2019 featurestr && !local_err;
2020 featurestr = strtok(NULL, ",")) {
2021 const char *name;
2022 const char *val = NULL;
2023 char *eq = NULL;
2024 char num[32];
2025 GlobalProperty *prop;
2026
2027 /* Compatibility syntax: */
2028 if (featurestr[0] == '+') {
2029 add_flagname_to_bitmaps(featurestr + 1, plus_features, &local_err);
2030 continue;
2031 } else if (featurestr[0] == '-') {
2032 add_flagname_to_bitmaps(featurestr + 1, minus_features, &local_err);
2033 continue;
2034 }
2035
2036 eq = strchr(featurestr, '=');
2037 if (eq) {
2038 *eq++ = 0;
2039 val = eq;
2040 } else {
2041 val = "on";
2042 }
2043
2044 feat2prop(featurestr);
2045 name = featurestr;
2046
2047 /* Special case: */
2048 if (!strcmp(name, "tsc-freq")) {
2049 int64_t tsc_freq;
2050 char *err;
2051
2052 tsc_freq = qemu_strtosz_suffix_unit(val, &err,
2053 QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
2054 if (tsc_freq < 0 || *err) {
2055 error_setg(errp, "bad numerical value %s", val);
2056 return;
2057 }
2058 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
2059 val = num;
2060 name = "tsc-frequency";
2061 }
2062
2063 prop = g_new0(typeof(*prop), 1);
2064 prop->driver = typename;
2065 prop->property = g_strdup(name);
2066 prop->value = g_strdup(val);
2067 prop->errp = &error_fatal;
2068 qdev_prop_register_global(prop);
2069 }
2070
2071 if (local_err) {
2072 error_propagate(errp, local_err);
2073 }
2074 }
2075
2076 /* Print all cpuid feature names in featureset
2077 */
2078 static void listflags(FILE *f, fprintf_function print, const char **featureset)
2079 {
2080 int bit;
2081 bool first = true;
2082
2083 for (bit = 0; bit < 32; bit++) {
2084 if (featureset[bit]) {
2085 print(f, "%s%s", first ? "" : " ", featureset[bit]);
2086 first = false;
2087 }
2088 }
2089 }
2090
2091 /* generate CPU information. */
2092 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2093 {
2094 X86CPUDefinition *def;
2095 char buf[256];
2096 int i;
2097
2098 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2099 def = &builtin_x86_defs[i];
2100 snprintf(buf, sizeof(buf), "%s", def->name);
2101 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
2102 }
2103 #ifdef CONFIG_KVM
2104 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
2105 "KVM processor with all supported host features "
2106 "(only available in KVM mode)");
2107 #endif
2108
2109 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
2110 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
2111 FeatureWordInfo *fw = &feature_word_info[i];
2112
2113 (*cpu_fprintf)(f, " ");
2114 listflags(f, cpu_fprintf, fw->feat_names);
2115 (*cpu_fprintf)(f, "\n");
2116 }
2117 }
2118
2119 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2120 {
2121 CpuDefinitionInfoList *cpu_list = NULL;
2122 X86CPUDefinition *def;
2123 int i;
2124
2125 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2126 CpuDefinitionInfoList *entry;
2127 CpuDefinitionInfo *info;
2128
2129 def = &builtin_x86_defs[i];
2130 info = g_malloc0(sizeof(*info));
2131 info->name = g_strdup(def->name);
2132
2133 entry = g_malloc0(sizeof(*entry));
2134 entry->value = info;
2135 entry->next = cpu_list;
2136 cpu_list = entry;
2137 }
2138
2139 return cpu_list;
2140 }
2141
2142 static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
2143 bool migratable_only)
2144 {
2145 FeatureWordInfo *wi = &feature_word_info[w];
2146 uint32_t r;
2147
2148 if (kvm_enabled()) {
2149 r = kvm_arch_get_supported_cpuid(kvm_state, wi->cpuid_eax,
2150 wi->cpuid_ecx,
2151 wi->cpuid_reg);
2152 } else if (tcg_enabled()) {
2153 r = wi->tcg_features;
2154 } else {
2155 return ~0;
2156 }
2157 if (migratable_only) {
2158 r &= x86_cpu_get_migratable_flags(w);
2159 }
2160 return r;
2161 }
2162
2163 /*
2164 * Filters CPU feature words based on host availability of each feature.
2165 *
2166 * Returns: 0 if all flags are supported by the host, non-zero otherwise.
2167 */
2168 static int x86_cpu_filter_features(X86CPU *cpu)
2169 {
2170 CPUX86State *env = &cpu->env;
2171 FeatureWord w;
2172 int rv = 0;
2173
2174 for (w = 0; w < FEATURE_WORDS; w++) {
2175 uint32_t host_feat =
2176 x86_cpu_get_supported_feature_word(w, cpu->migratable);
2177 uint32_t requested_features = env->features[w];
2178 env->features[w] &= host_feat;
2179 cpu->filtered_features[w] = requested_features & ~env->features[w];
2180 if (cpu->filtered_features[w]) {
2181 if (cpu->check_cpuid || cpu->enforce_cpuid) {
2182 report_unavailable_features(w, cpu->filtered_features[w]);
2183 }
2184 rv = 1;
2185 }
2186 }
2187
2188 return rv;
2189 }
2190
2191 static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
2192 {
2193 PropValue *pv;
2194 for (pv = props; pv->prop; pv++) {
2195 if (!pv->value) {
2196 continue;
2197 }
2198 object_property_parse(OBJECT(cpu), pv->value, pv->prop,
2199 &error_abort);
2200 }
2201 }
2202
2203 /* Load data from X86CPUDefinition
2204 */
2205 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
2206 {
2207 CPUX86State *env = &cpu->env;
2208 const char *vendor;
2209 char host_vendor[CPUID_VENDOR_SZ + 1];
2210 FeatureWord w;
2211
2212 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
2213 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
2214 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
2215 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
2216 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
2217 object_property_set_int(OBJECT(cpu), def->xlevel2, "xlevel2", errp);
2218 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
2219 for (w = 0; w < FEATURE_WORDS; w++) {
2220 env->features[w] = def->features[w];
2221 }
2222
2223 /* Special cases not set in the X86CPUDefinition structs: */
2224 if (kvm_enabled()) {
2225 if (!kvm_irqchip_in_kernel()) {
2226 x86_cpu_change_kvm_default("x2apic", "off");
2227 }
2228
2229 x86_cpu_apply_props(cpu, kvm_default_props);
2230 }
2231
2232 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
2233
2234 /* sysenter isn't supported in compatibility mode on AMD,
2235 * syscall isn't supported in compatibility mode on Intel.
2236 * Normally we advertise the actual CPU vendor, but you can
2237 * override this using the 'vendor' property if you want to use
2238 * KVM's sysenter/syscall emulation in compatibility mode and
2239 * when doing cross vendor migration
2240 */
2241 vendor = def->vendor;
2242 if (kvm_enabled()) {
2243 uint32_t ebx = 0, ecx = 0, edx = 0;
2244 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
2245 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
2246 vendor = host_vendor;
2247 }
2248
2249 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
2250
2251 }
2252
2253 X86CPU *cpu_x86_init(const char *cpu_model)
2254 {
2255 return X86_CPU(cpu_generic_init(TYPE_X86_CPU, cpu_model));
2256 }
2257
2258 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
2259 {
2260 X86CPUDefinition *cpudef = data;
2261 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2262
2263 xcc->cpu_def = cpudef;
2264 }
2265
2266 static void x86_register_cpudef_type(X86CPUDefinition *def)
2267 {
2268 char *typename = x86_cpu_type_name(def->name);
2269 TypeInfo ti = {
2270 .name = typename,
2271 .parent = TYPE_X86_CPU,
2272 .class_init = x86_cpu_cpudef_class_init,
2273 .class_data = def,
2274 };
2275
2276 type_register(&ti);
2277 g_free(typename);
2278 }
2279
2280 #if !defined(CONFIG_USER_ONLY)
2281
2282 void cpu_clear_apic_feature(CPUX86State *env)
2283 {
2284 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2285 }
2286
2287 #endif /* !CONFIG_USER_ONLY */
2288
2289 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2290 uint32_t *eax, uint32_t *ebx,
2291 uint32_t *ecx, uint32_t *edx)
2292 {
2293 X86CPU *cpu = x86_env_get_cpu(env);
2294 CPUState *cs = CPU(cpu);
2295 uint32_t pkg_offset;
2296
2297 /* test if maximum index reached */
2298 if (index & 0x80000000) {
2299 if (index > env->cpuid_xlevel) {
2300 if (env->cpuid_xlevel2 > 0) {
2301 /* Handle the Centaur's CPUID instruction. */
2302 if (index > env->cpuid_xlevel2) {
2303 index = env->cpuid_xlevel2;
2304 } else if (index < 0xC0000000) {
2305 index = env->cpuid_xlevel;
2306 }
2307 } else {
2308 /* Intel documentation states that invalid EAX input will
2309 * return the same information as EAX=cpuid_level
2310 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2311 */
2312 index = env->cpuid_level;
2313 }
2314 }
2315 } else {
2316 if (index > env->cpuid_level)
2317 index = env->cpuid_level;
2318 }
2319
2320 switch(index) {
2321 case 0:
2322 *eax = env->cpuid_level;
2323 *ebx = env->cpuid_vendor1;
2324 *edx = env->cpuid_vendor2;
2325 *ecx = env->cpuid_vendor3;
2326 break;
2327 case 1:
2328 *eax = env->cpuid_version;
2329 *ebx = (cpu->apic_id << 24) |
2330 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2331 *ecx = env->features[FEAT_1_ECX];
2332 if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
2333 *ecx |= CPUID_EXT_OSXSAVE;
2334 }
2335 *edx = env->features[FEAT_1_EDX];
2336 if (cs->nr_cores * cs->nr_threads > 1) {
2337 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2338 *edx |= CPUID_HT;
2339 }
2340 break;
2341 case 2:
2342 /* cache info: needed for Pentium Pro compatibility */
2343 if (cpu->cache_info_passthrough) {
2344 host_cpuid(index, 0, eax, ebx, ecx, edx);
2345 break;
2346 }
2347 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2348 *ebx = 0;
2349 if (!cpu->enable_l3_cache) {
2350 *ecx = 0;
2351 } else {
2352 *ecx = L3_N_DESCRIPTOR;
2353 }
2354 *edx = (L1D_DESCRIPTOR << 16) | \
2355 (L1I_DESCRIPTOR << 8) | \
2356 (L2_DESCRIPTOR);
2357 break;
2358 case 4:
2359 /* cache info: needed for Core compatibility */
2360 if (cpu->cache_info_passthrough) {
2361 host_cpuid(index, count, eax, ebx, ecx, edx);
2362 *eax &= ~0xFC000000;
2363 } else {
2364 *eax = 0;
2365 switch (count) {
2366 case 0: /* L1 dcache info */
2367 *eax |= CPUID_4_TYPE_DCACHE | \
2368 CPUID_4_LEVEL(1) | \
2369 CPUID_4_SELF_INIT_LEVEL;
2370 *ebx = (L1D_LINE_SIZE - 1) | \
2371 ((L1D_PARTITIONS - 1) << 12) | \
2372 ((L1D_ASSOCIATIVITY - 1) << 22);
2373 *ecx = L1D_SETS - 1;
2374 *edx = CPUID_4_NO_INVD_SHARING;
2375 break;
2376 case 1: /* L1 icache info */
2377 *eax |= CPUID_4_TYPE_ICACHE | \
2378 CPUID_4_LEVEL(1) | \
2379 CPUID_4_SELF_INIT_LEVEL;
2380 *ebx = (L1I_LINE_SIZE - 1) | \
2381 ((L1I_PARTITIONS - 1) << 12) | \
2382 ((L1I_ASSOCIATIVITY - 1) << 22);
2383 *ecx = L1I_SETS - 1;
2384 *edx = CPUID_4_NO_INVD_SHARING;
2385 break;
2386 case 2: /* L2 cache info */
2387 *eax |= CPUID_4_TYPE_UNIFIED | \
2388 CPUID_4_LEVEL(2) | \
2389 CPUID_4_SELF_INIT_LEVEL;
2390 if (cs->nr_threads > 1) {
2391 *eax |= (cs->nr_threads - 1) << 14;
2392 }
2393 *ebx = (L2_LINE_SIZE - 1) | \
2394 ((L2_PARTITIONS - 1) << 12) | \
2395 ((L2_ASSOCIATIVITY - 1) << 22);
2396 *ecx = L2_SETS - 1;
2397 *edx = CPUID_4_NO_INVD_SHARING;
2398 break;
2399 case 3: /* L3 cache info */
2400 if (!cpu->enable_l3_cache) {
2401 *eax = 0;
2402 *ebx = 0;
2403 *ecx = 0;
2404 *edx = 0;
2405 break;
2406 }
2407 *eax |= CPUID_4_TYPE_UNIFIED | \
2408 CPUID_4_LEVEL(3) | \
2409 CPUID_4_SELF_INIT_LEVEL;
2410 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
2411 *eax |= ((1 << pkg_offset) - 1) << 14;
2412 *ebx = (L3_N_LINE_SIZE - 1) | \
2413 ((L3_N_PARTITIONS - 1) << 12) | \
2414 ((L3_N_ASSOCIATIVITY - 1) << 22);
2415 *ecx = L3_N_SETS - 1;
2416 *edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
2417 break;
2418 default: /* end of info */
2419 *eax = 0;
2420 *ebx = 0;
2421 *ecx = 0;
2422 *edx = 0;
2423 break;
2424 }
2425 }
2426
2427 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2428 if ((*eax & 31) && cs->nr_cores > 1) {
2429 *eax |= (cs->nr_cores - 1) << 26;
2430 }
2431 break;
2432 case 5:
2433 /* mwait info: needed for Core compatibility */
2434 *eax = 0; /* Smallest monitor-line size in bytes */
2435 *ebx = 0; /* Largest monitor-line size in bytes */
2436 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2437 *edx = 0;
2438 break;
2439 case 6:
2440 /* Thermal and Power Leaf */
2441 *eax = env->features[FEAT_6_EAX];
2442 *ebx = 0;
2443 *ecx = 0;
2444 *edx = 0;
2445 break;
2446 case 7:
2447 /* Structured Extended Feature Flags Enumeration Leaf */
2448 if (count == 0) {
2449 *eax = 0; /* Maximum ECX value for sub-leaves */
2450 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2451 *ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
2452 if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
2453 *ecx |= CPUID_7_0_ECX_OSPKE;
2454 }
2455 *edx = 0; /* Reserved */
2456 } else {
2457 *eax = 0;
2458 *ebx = 0;
2459 *ecx = 0;
2460 *edx = 0;
2461 }
2462 break;
2463 case 9:
2464 /* Direct Cache Access Information Leaf */
2465 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2466 *ebx = 0;
2467 *ecx = 0;
2468 *edx = 0;
2469 break;
2470 case 0xA:
2471 /* Architectural Performance Monitoring Leaf */
2472 if (kvm_enabled() && cpu->enable_pmu) {
2473 KVMState *s = cs->kvm_state;
2474
2475 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2476 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2477 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2478 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2479 } else {
2480 *eax = 0;
2481 *ebx = 0;
2482 *ecx = 0;
2483 *edx = 0;
2484 }
2485 break;
2486 case 0xB:
2487 /* Extended Topology Enumeration Leaf */
2488 if (!cpu->enable_cpuid_0xb) {
2489 *eax = *ebx = *ecx = *edx = 0;
2490 break;
2491 }
2492
2493 *ecx = count & 0xff;
2494 *edx = cpu->apic_id;
2495
2496 switch (count) {
2497 case 0:
2498 *eax = apicid_core_offset(smp_cores, smp_threads);
2499 *ebx = smp_threads;
2500 *ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
2501 break;
2502 case 1:
2503 *eax = apicid_pkg_offset(smp_cores, smp_threads);
2504 *ebx = smp_cores * smp_threads;
2505 *ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
2506 break;
2507 default:
2508 *eax = 0;
2509 *ebx = 0;
2510 *ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
2511 }
2512
2513 assert(!(*eax & ~0x1f));
2514 *ebx &= 0xffff; /* The count doesn't need to be reliable. */
2515 break;
2516 case 0xD: {
2517 KVMState *s = cs->kvm_state;
2518 uint64_t ena_mask;
2519 int i;
2520
2521 /* Processor Extended State */
2522 *eax = 0;
2523 *ebx = 0;
2524 *ecx = 0;
2525 *edx = 0;
2526 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
2527 break;
2528 }
2529 if (kvm_enabled()) {
2530 ena_mask = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX);
2531 ena_mask <<= 32;
2532 ena_mask |= kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
2533 } else {
2534 ena_mask = -1;
2535 }
2536
2537 if (count == 0) {
2538 *ecx = 0x240;
2539 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2540 const ExtSaveArea *esa = &x86_ext_save_areas[i];
2541 if ((env->features[esa->feature] & esa->bits) == esa->bits
2542 && ((ena_mask >> i) & 1) != 0) {
2543 if (i < 32) {
2544 *eax |= 1u << i;
2545 } else {
2546 *edx |= 1u << (i - 32);
2547 }
2548 *ecx = MAX(*ecx, esa->offset + esa->size);
2549 }
2550 }
2551 *eax |= ena_mask & (XSTATE_FP_MASK | XSTATE_SSE_MASK);
2552 *ebx = *ecx;
2553 } else if (count == 1) {
2554 *eax = env->features[FEAT_XSAVE];
2555 } else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
2556 const ExtSaveArea *esa = &x86_ext_save_areas[count];
2557 if ((env->features[esa->feature] & esa->bits) == esa->bits
2558 && ((ena_mask >> count) & 1) != 0) {
2559 *eax = esa->size;
2560 *ebx = esa->offset;
2561 }
2562 }
2563 break;
2564 }
2565 case 0x80000000:
2566 *eax = env->cpuid_xlevel;
2567 *ebx = env->cpuid_vendor1;
2568 *edx = env->cpuid_vendor2;
2569 *ecx = env->cpuid_vendor3;
2570 break;
2571 case 0x80000001:
2572 *eax = env->cpuid_version;
2573 *ebx = 0;
2574 *ecx = env->features[FEAT_8000_0001_ECX];
2575 *edx = env->features[FEAT_8000_0001_EDX];
2576
2577 /* The Linux kernel checks for the CMPLegacy bit and
2578 * discards multiple thread information if it is set.
2579 * So don't set it here for Intel to make Linux guests happy.
2580 */
2581 if (cs->nr_cores * cs->nr_threads > 1) {
2582 if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
2583 env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
2584 env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
2585 *ecx |= 1 << 1; /* CmpLegacy bit */
2586 }
2587 }
2588 break;
2589 case 0x80000002:
2590 case 0x80000003:
2591 case 0x80000004:
2592 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2593 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2594 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2595 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2596 break;
2597 case 0x80000005:
2598 /* cache info (L1 cache) */
2599 if (cpu->cache_info_passthrough) {
2600 host_cpuid(index, 0, eax, ebx, ecx, edx);
2601 break;
2602 }
2603 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2604 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2605 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2606 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2607 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2608 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2609 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2610 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2611 break;
2612 case 0x80000006:
2613 /* cache info (L2 cache) */
2614 if (cpu->cache_info_passthrough) {
2615 host_cpuid(index, 0, eax, ebx, ecx, edx);
2616 break;
2617 }
2618 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2619 (L2_DTLB_2M_ENTRIES << 16) | \
2620 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2621 (L2_ITLB_2M_ENTRIES);
2622 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2623 (L2_DTLB_4K_ENTRIES << 16) | \
2624 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2625 (L2_ITLB_4K_ENTRIES);
2626 *ecx = (L2_SIZE_KB_AMD << 16) | \
2627 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2628 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2629 if (!cpu->enable_l3_cache) {
2630 *edx = ((L3_SIZE_KB / 512) << 18) | \
2631 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2632 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2633 } else {
2634 *edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
2635 (AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
2636 (L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
2637 }
2638 break;
2639 case 0x80000007:
2640 *eax = 0;
2641 *ebx = 0;
2642 *ecx = 0;
2643 *edx = env->features[FEAT_8000_0007_EDX];
2644 break;
2645 case 0x80000008:
2646 /* virtual & phys address size in low 2 bytes. */
2647 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2648 /* 64 bit processor, 48 bits virtual, configurable
2649 * physical bits.
2650 */
2651 *eax = 0x00003000 + cpu->phys_bits;
2652 } else {
2653 *eax = cpu->phys_bits;
2654 }
2655 *ebx = 0;
2656 *ecx = 0;
2657 *edx = 0;
2658 if (cs->nr_cores * cs->nr_threads > 1) {
2659 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2660 }
2661 break;
2662 case 0x8000000A:
2663 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2664 *eax = 0x00000001; /* SVM Revision */
2665 *ebx = 0x00000010; /* nr of ASIDs */
2666 *ecx = 0;
2667 *edx = env->features[FEAT_SVM]; /* optional features */
2668 } else {
2669 *eax = 0;
2670 *ebx = 0;
2671 *ecx = 0;
2672 *edx = 0;
2673 }
2674 break;
2675 case 0xC0000000:
2676 *eax = env->cpuid_xlevel2;
2677 *ebx = 0;
2678 *ecx = 0;
2679 *edx = 0;
2680 break;
2681 case 0xC0000001:
2682 /* Support for VIA CPU's CPUID instruction */
2683 *eax = env->cpuid_version;
2684 *ebx = 0;
2685 *ecx = 0;
2686 *edx = env->features[FEAT_C000_0001_EDX];
2687 break;
2688 case 0xC0000002:
2689 case 0xC0000003:
2690 case 0xC0000004:
2691 /* Reserved for the future, and now filled with zero */
2692 *eax = 0;
2693 *ebx = 0;
2694 *ecx = 0;
2695 *edx = 0;
2696 break;
2697 default:
2698 /* reserved values: zero */
2699 *eax = 0;
2700 *ebx = 0;
2701 *ecx = 0;
2702 *edx = 0;
2703 break;
2704 }
2705 }
2706
2707 /* CPUClass::reset() */
2708 static void x86_cpu_reset(CPUState *s)
2709 {
2710 X86CPU *cpu = X86_CPU(s);
2711 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2712 CPUX86State *env = &cpu->env;
2713 target_ulong cr4;
2714 uint64_t xcr0;
2715 int i;
2716
2717 xcc->parent_reset(s);
2718
2719 memset(env, 0, offsetof(CPUX86State, cpuid_level));
2720
2721 tlb_flush(s, 1);
2722
2723 env->old_exception = -1;
2724
2725 /* init to reset state */
2726
2727 env->hflags2 |= HF2_GIF_MASK;
2728
2729 cpu_x86_update_cr0(env, 0x60000010);
2730 env->a20_mask = ~0x0;
2731 env->smbase = 0x30000;
2732
2733 env->idt.limit = 0xffff;
2734 env->gdt.limit = 0xffff;
2735 env->ldt.limit = 0xffff;
2736 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2737 env->tr.limit = 0xffff;
2738 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2739
2740 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2741 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2742 DESC_R_MASK | DESC_A_MASK);
2743 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2744 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2745 DESC_A_MASK);
2746 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2747 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2748 DESC_A_MASK);
2749 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2750 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2751 DESC_A_MASK);
2752 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2753 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2754 DESC_A_MASK);
2755 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2756 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2757 DESC_A_MASK);
2758
2759 env->eip = 0xfff0;
2760 env->regs[R_EDX] = env->cpuid_version;
2761
2762 env->eflags = 0x2;
2763
2764 /* FPU init */
2765 for (i = 0; i < 8; i++) {
2766 env->fptags[i] = 1;
2767 }
2768 cpu_set_fpuc(env, 0x37f);
2769
2770 env->mxcsr = 0x1f80;
2771 /* All units are in INIT state. */
2772 env->xstate_bv = 0;
2773
2774 env->pat = 0x0007040600070406ULL;
2775 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2776
2777 memset(env->dr, 0, sizeof(env->dr));
2778 env->dr[6] = DR6_FIXED_1;
2779 env->dr[7] = DR7_FIXED_1;
2780 cpu_breakpoint_remove_all(s, BP_CPU);
2781 cpu_watchpoint_remove_all(s, BP_CPU);
2782
2783 cr4 = 0;
2784 xcr0 = XSTATE_FP_MASK;
2785
2786 #ifdef CONFIG_USER_ONLY
2787 /* Enable all the features for user-mode. */
2788 if (env->features[FEAT_1_EDX] & CPUID_SSE) {
2789 xcr0 |= XSTATE_SSE_MASK;
2790 }
2791 for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
2792 const ExtSaveArea *esa = &x86_ext_save_areas[i];
2793 if ((env->features[esa->feature] & esa->bits) == esa->bits) {
2794 xcr0 |= 1ull << i;
2795 }
2796 }
2797
2798 if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
2799 cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
2800 }
2801 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
2802 cr4 |= CR4_FSGSBASE_MASK;
2803 }
2804 #endif
2805
2806 env->xcr0 = xcr0;
2807 cpu_x86_update_cr4(env, cr4);
2808
2809 /*
2810 * SDM 11.11.5 requires:
2811 * - IA32_MTRR_DEF_TYPE MSR.E = 0
2812 * - IA32_MTRR_PHYSMASKn.V = 0
2813 * All other bits are undefined. For simplification, zero it all.
2814 */
2815 env->mtrr_deftype = 0;
2816 memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
2817 memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
2818
2819 #if !defined(CONFIG_USER_ONLY)
2820 /* We hard-wire the BSP to the first CPU. */
2821 apic_designate_bsp(cpu->apic_state, s->cpu_index == 0);
2822
2823 s->halted = !cpu_is_bsp(cpu);
2824
2825 if (kvm_enabled()) {
2826 kvm_arch_reset_vcpu(cpu);
2827 }
2828 #endif
2829 }
2830
2831 #ifndef CONFIG_USER_ONLY
2832 bool cpu_is_bsp(X86CPU *cpu)
2833 {
2834 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2835 }
2836
2837 /* TODO: remove me, when reset over QOM tree is implemented */
2838 static void x86_cpu_machine_reset_cb(void *opaque)
2839 {
2840 X86CPU *cpu = opaque;
2841 cpu_reset(CPU(cpu));
2842 }
2843 #endif
2844
2845 static void mce_init(X86CPU *cpu)
2846 {
2847 CPUX86State *cenv = &cpu->env;
2848 unsigned int bank;
2849
2850 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2851 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2852 (CPUID_MCE | CPUID_MCA)) {
2853 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
2854 (cpu->enable_lmce ? MCG_LMCE_P : 0);
2855 cenv->mcg_ctl = ~(uint64_t)0;
2856 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2857 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2858 }
2859 }
2860 }
2861
2862 #ifndef CONFIG_USER_ONLY
2863 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2864 {
2865 APICCommonState *apic;
2866 const char *apic_type = "apic";
2867
2868 if (kvm_apic_in_kernel()) {
2869 apic_type = "kvm-apic";
2870 } else if (xen_enabled()) {
2871 apic_type = "xen-apic";
2872 }
2873
2874 cpu->apic_state = DEVICE(object_new(apic_type));
2875
2876 object_property_add_child(OBJECT(cpu), "lapic",
2877 OBJECT(cpu->apic_state), &error_abort);
2878 object_unref(OBJECT(cpu->apic_state));
2879
2880 qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
2881 /* TODO: convert to link<> */
2882 apic = APIC_COMMON(cpu->apic_state);
2883 apic->cpu = cpu;
2884 apic->apicbase = APIC_DEFAULT_ADDRESS | MSR_IA32_APICBASE_ENABLE;
2885 }
2886
2887 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2888 {
2889 APICCommonState *apic;
2890 static bool apic_mmio_map_once;
2891
2892 if (cpu->apic_state == NULL) {
2893 return;
2894 }
2895 object_property_set_bool(OBJECT(cpu->apic_state), true, "realized",
2896 errp);
2897
2898 /* Map APIC MMIO area */
2899 apic = APIC_COMMON(cpu->apic_state);
2900 if (!apic_mmio_map_once) {
2901 memory_region_add_subregion_overlap(get_system_memory(),
2902 apic->apicbase &
2903 MSR_IA32_APICBASE_BASE,
2904 &apic->io_memory,
2905 0x1000);
2906 apic_mmio_map_once = true;
2907 }
2908 }
2909
2910 static void x86_cpu_machine_done(Notifier *n, void *unused)
2911 {
2912 X86CPU *cpu = container_of(n, X86CPU, machine_done);
2913 MemoryRegion *smram =
2914 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
2915
2916 if (smram) {
2917 cpu->smram = g_new(MemoryRegion, 1);
2918 memory_region_init_alias(cpu->smram, OBJECT(cpu), "smram",
2919 smram, 0, 1ull << 32);
2920 memory_region_set_enabled(cpu->smram, false);
2921 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->smram, 1);
2922 }
2923 }
2924 #else
2925 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2926 {
2927 }
2928 #endif
2929
2930 /* Note: Only safe for use on x86(-64) hosts */
2931 static uint32_t x86_host_phys_bits(void)
2932 {
2933 uint32_t eax;
2934 uint32_t host_phys_bits;
2935
2936 host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
2937 if (eax >= 0x80000008) {
2938 host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
2939 /* Note: According to AMD doc 25481 rev 2.34 they have a field
2940 * at 23:16 that can specify a maximum physical address bits for
2941 * the guest that can override this value; but I've not seen
2942 * anything with that set.
2943 */
2944 host_phys_bits = eax & 0xff;
2945 } else {
2946 /* It's an odd 64 bit machine that doesn't have the leaf for
2947 * physical address bits; fall back to 36 that's most older
2948 * Intel.
2949 */
2950 host_phys_bits = 36;
2951 }
2952
2953 return host_phys_bits;
2954 }
2955
2956 #define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
2957 (env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
2958 (env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
2959 #define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
2960 (env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
2961 (env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
2962 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2963 {
2964 CPUState *cs = CPU(dev);
2965 X86CPU *cpu = X86_CPU(dev);
2966 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2967 CPUX86State *env = &cpu->env;
2968 Error *local_err = NULL;
2969 static bool ht_warned;
2970 FeatureWord w;
2971
2972 if (xcc->kvm_required && !kvm_enabled()) {
2973 char *name = x86_cpu_class_get_model_name(xcc);
2974 error_setg(&local_err, "CPU model '%s' requires KVM", name);
2975 g_free(name);
2976 goto out;
2977 }
2978
2979 if (cpu->apic_id == UNASSIGNED_APIC_ID) {
2980 error_setg(errp, "apic-id property was not initialized properly");
2981 return;
2982 }
2983
2984 /*TODO: cpu->host_features incorrectly overwrites features
2985 * set using "feat=on|off". Once we fix this, we can convert
2986 * plus_features & minus_features to global properties
2987 * inside x86_cpu_parse_featurestr() too.
2988 */
2989 if (cpu->host_features) {
2990 for (w = 0; w < FEATURE_WORDS; w++) {
2991 env->features[w] =
2992 x86_cpu_get_supported_feature_word(w, cpu->migratable);
2993 }
2994 }
2995
2996 for (w = 0; w < FEATURE_WORDS; w++) {
2997 cpu->env.features[w] |= plus_features[w];
2998 cpu->env.features[w] &= ~minus_features[w];
2999 }
3000
3001 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
3002 env->cpuid_level = 7;
3003 }
3004
3005 if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
3006 error_setg(&local_err,
3007 kvm_enabled() ?
3008 "Host doesn't support requested features" :
3009 "TCG doesn't support requested features");
3010 goto out;
3011 }
3012
3013 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
3014 * CPUID[1].EDX.
3015 */
3016 if (IS_AMD_CPU(env)) {
3017 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
3018 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
3019 & CPUID_EXT2_AMD_ALIASES);
3020 }
3021
3022 /* For 64bit systems think about the number of physical bits to present.
3023 * ideally this should be the same as the host; anything other than matching
3024 * the host can cause incorrect guest behaviour.
3025 * QEMU used to pick the magic value of 40 bits that corresponds to
3026 * consumer AMD devices but nothing else.
3027 */
3028 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
3029 if (kvm_enabled()) {
3030 uint32_t host_phys_bits = x86_host_phys_bits();
3031 static bool warned;
3032
3033 if (cpu->host_phys_bits) {
3034 /* The user asked for us to use the host physical bits */
3035 cpu->phys_bits = host_phys_bits;
3036 }
3037
3038 /* Print a warning if the user set it to a value that's not the
3039 * host value.
3040 */
3041 if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 &&
3042 !warned) {
3043 error_report("Warning: Host physical bits (%u)"
3044 " does not match phys-bits property (%u)",
3045 host_phys_bits, cpu->phys_bits);
3046 warned = true;
3047 }
3048
3049 if (cpu->phys_bits &&
3050 (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS ||
3051 cpu->phys_bits < 32)) {
3052 error_setg(errp, "phys-bits should be between 32 and %u "
3053 " (but is %u)",
3054 TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits);
3055 return;
3056 }
3057 } else {
3058 if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
3059 error_setg(errp, "TCG only supports phys-bits=%u",
3060 TCG_PHYS_ADDR_BITS);
3061 return;
3062 }
3063 }
3064 /* 0 means it was not explicitly set by the user (or by machine
3065 * compat_props or by the host code above). In this case, the default
3066 * is the value used by TCG (40).
3067 */
3068 if (cpu->phys_bits == 0) {
3069 cpu->phys_bits = TCG_PHYS_ADDR_BITS;
3070 }
3071 } else {
3072 /* For 32 bit systems don't use the user set value, but keep
3073 * phys_bits consistent with what we tell the guest.
3074 */
3075 if (cpu->phys_bits != 0) {
3076 error_setg(errp, "phys-bits is not user-configurable in 32 bit");
3077 return;
3078 }
3079
3080 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
3081 cpu->phys_bits = 36;
3082 } else {
3083 cpu->phys_bits = 32;
3084 }
3085 }
3086 cpu_exec_init(cs, &error_abort);
3087
3088 if (tcg_enabled()) {
3089 tcg_x86_init();
3090 }
3091
3092 #ifndef CONFIG_USER_ONLY
3093 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
3094
3095 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
3096 x86_cpu_apic_create(cpu, &local_err);
3097 if (local_err != NULL) {
3098 goto out;
3099 }
3100 }
3101 #endif
3102
3103 mce_init(cpu);
3104
3105 #ifndef CONFIG_USER_ONLY
3106 if (tcg_enabled()) {
3107 AddressSpace *newas = g_new(AddressSpace, 1);
3108
3109 cpu->cpu_as_mem = g_new(MemoryRegion, 1);
3110 cpu->cpu_as_root = g_new(MemoryRegion, 1);
3111
3112 /* Outer container... */
3113 memory_region_init(cpu->cpu_as_root, OBJECT(cpu), "memory", ~0ull);
3114 memory_region_set_enabled(cpu->cpu_as_root, true);
3115
3116 /* ... with two regions inside: normal system memory with low
3117 * priority, and...
3118 */
3119 memory_region_init_alias(cpu->cpu_as_mem, OBJECT(cpu), "memory",
3120 get_system_memory(), 0, ~0ull);
3121 memory_region_add_subregion_overlap(cpu->cpu_as_root, 0, cpu->cpu_as_mem, 0);
3122 memory_region_set_enabled(cpu->cpu_as_mem, true);
3123 address_space_init(newas, cpu->cpu_as_root, "CPU");
3124 cs->num_ases = 1;
3125 cpu_address_space_init(cs, newas, 0);
3126
3127 /* ... SMRAM with higher priority, linked from /machine/smram. */
3128 cpu->machine_done.notify = x86_cpu_machine_done;
3129 qemu_add_machine_init_done_notifier(&cpu->machine_done);
3130 }
3131 #endif
3132
3133 qemu_init_vcpu(cs);
3134
3135 /* Only Intel CPUs support hyperthreading. Even though QEMU fixes this
3136 * issue by adjusting CPUID_0000_0001_EBX and CPUID_8000_0008_ECX
3137 * based on inputs (sockets,cores,threads), it is still better to gives
3138 * users a warning.
3139 *
3140 * NOTE: the following code has to follow qemu_init_vcpu(). Otherwise
3141 * cs->nr_threads hasn't be populated yet and the checking is incorrect.
3142 */
3143 if (!IS_INTEL_CPU(env) && cs->nr_threads > 1 && !ht_warned) {
3144 error_report("AMD CPU doesn't support hyperthreading. Please configure"
3145 " -smp options properly.");
3146 ht_warned = true;
3147 }
3148
3149 x86_cpu_apic_realize(cpu, &local_err);
3150 if (local_err != NULL) {
3151 goto out;
3152 }
3153 cpu_reset(cs);
3154
3155 xcc->parent_realize(dev, &local_err);
3156
3157 out:
3158 if (local_err != NULL) {
3159 error_propagate(errp, local_err);
3160 return;
3161 }
3162 }
3163
3164 static void x86_cpu_unrealizefn(DeviceState *dev, Error **errp)
3165 {
3166 X86CPU *cpu = X86_CPU(dev);
3167
3168 #ifndef CONFIG_USER_ONLY
3169 cpu_remove_sync(CPU(dev));
3170 qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
3171 #endif
3172
3173 if (cpu->apic_state) {
3174 object_unparent(OBJECT(cpu->apic_state));
3175 cpu->apic_state = NULL;
3176 }
3177 }
3178
3179 typedef struct BitProperty {
3180 uint32_t *ptr;
3181 uint32_t mask;
3182 } BitProperty;
3183
3184 static void x86_cpu_get_bit_prop(Object *obj, Visitor *v, const char *name,
3185 void *opaque, Error **errp)
3186 {
3187 BitProperty *fp = opaque;
3188 bool value = (*fp->ptr & fp->mask) == fp->mask;
3189 visit_type_bool(v, name, &value, errp);
3190 }
3191
3192 static void x86_cpu_set_bit_prop(Object *obj, Visitor *v, const char *name,
3193 void *opaque, Error **errp)
3194 {
3195 DeviceState *dev = DEVICE(obj);
3196 BitProperty *fp = opaque;
3197 Error *local_err = NULL;
3198 bool value;
3199
3200 if (dev->realized) {
3201 qdev_prop_set_after_realize(dev, name, errp);
3202 return;
3203 }
3204
3205 visit_type_bool(v, name, &value, &local_err);
3206 if (local_err) {
3207 error_propagate(errp, local_err);
3208 return;
3209 }
3210
3211 if (value) {
3212 *fp->ptr |= fp->mask;
3213 } else {
3214 *fp->ptr &= ~fp->mask;
3215 }
3216 }
3217
3218 static void x86_cpu_release_bit_prop(Object *obj, const char *name,
3219 void *opaque)
3220 {
3221 BitProperty *prop = opaque;
3222 g_free(prop);
3223 }
3224
3225 /* Register a boolean property to get/set a single bit in a uint32_t field.
3226 *
3227 * The same property name can be registered multiple times to make it affect
3228 * multiple bits in the same FeatureWord. In that case, the getter will return
3229 * true only if all bits are set.
3230 */
3231 static void x86_cpu_register_bit_prop(X86CPU *cpu,
3232 const char *prop_name,
3233 uint32_t *field,
3234 int bitnr)
3235 {
3236 BitProperty *fp;
3237 ObjectProperty *op;
3238 uint32_t mask = (1UL << bitnr);
3239
3240 op = object_property_find(OBJECT(cpu), prop_name, NULL);
3241 if (op) {
3242 fp = op->opaque;
3243 assert(fp->ptr == field);
3244 fp->mask |= mask;
3245 } else {
3246 fp = g_new0(BitProperty, 1);
3247 fp->ptr = field;
3248 fp->mask = mask;
3249 object_property_add(OBJECT(cpu), prop_name, "bool",
3250 x86_cpu_get_bit_prop,
3251 x86_cpu_set_bit_prop,
3252 x86_cpu_release_bit_prop, fp, &error_abort);
3253 }
3254 }
3255
3256 static void x86_cpu_register_feature_bit_props(X86CPU *cpu,
3257 FeatureWord w,
3258 int bitnr)
3259 {
3260 Object *obj = OBJECT(cpu);
3261 int i;
3262 char **names;
3263 FeatureWordInfo *fi = &feature_word_info[w];
3264
3265 if (!fi->feat_names) {
3266 return;
3267 }
3268 if (!fi->feat_names[bitnr]) {
3269 return;
3270 }
3271
3272 names = g_strsplit(fi->feat_names[bitnr], "|", 0);
3273
3274 feat2prop(names[0]);
3275 x86_cpu_register_bit_prop(cpu, names[0], &cpu->env.features[w], bitnr);
3276
3277 for (i = 1; names[i]; i++) {
3278 feat2prop(names[i]);
3279 object_property_add_alias(obj, names[i], obj, names[0],
3280 &error_abort);
3281 }
3282
3283 g_strfreev(names);
3284 }
3285
3286 static void x86_cpu_initfn(Object *obj)
3287 {
3288 CPUState *cs = CPU(obj);
3289 X86CPU *cpu = X86_CPU(obj);
3290 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
3291 CPUX86State *env = &cpu->env;
3292 FeatureWord w;
3293
3294 cs->env_ptr = env;
3295
3296 object_property_add(obj, "family", "int",
3297 x86_cpuid_version_get_family,
3298 x86_cpuid_version_set_family, NULL, NULL, NULL);
3299 object_property_add(obj, "model", "int",
3300 x86_cpuid_version_get_model,
3301 x86_cpuid_version_set_model, NULL, NULL, NULL);
3302 object_property_add(obj, "stepping", "int",
3303 x86_cpuid_version_get_stepping,
3304 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
3305 object_property_add_str(obj, "vendor",
3306 x86_cpuid_get_vendor,
3307 x86_cpuid_set_vendor, NULL);
3308 object_property_add_str(obj, "model-id",
3309 x86_cpuid_get_model_id,
3310 x86_cpuid_set_model_id, NULL);
3311 object_property_add(obj, "tsc-frequency", "int",
3312 x86_cpuid_get_tsc_freq,
3313 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
3314 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
3315 x86_cpu_get_feature_words,
3316 NULL, NULL, (void *)env->features, NULL);
3317 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
3318 x86_cpu_get_feature_words,
3319 NULL, NULL, (void *)cpu->filtered_features, NULL);
3320
3321 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
3322
3323 for (w = 0; w < FEATURE_WORDS; w++) {
3324 int bitnr;
3325
3326 for (bitnr = 0; bitnr < 32; bitnr++) {
3327 x86_cpu_register_feature_bit_props(cpu, w, bitnr);
3328 }
3329 }
3330
3331 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
3332 }
3333
3334 static int64_t x86_cpu_get_arch_id(CPUState *cs)
3335 {
3336 X86CPU *cpu = X86_CPU(cs);
3337
3338 return cpu->apic_id;
3339 }
3340
3341 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
3342 {
3343 X86CPU *cpu = X86_CPU(cs);
3344
3345 return cpu->env.cr[0] & CR0_PG_MASK;
3346 }
3347
3348 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
3349 {
3350 X86CPU *cpu = X86_CPU(cs);
3351
3352 cpu->env.eip = value;
3353 }
3354
3355 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
3356 {
3357 X86CPU *cpu = X86_CPU(cs);
3358
3359 cpu->env.eip = tb->pc - tb->cs_base;
3360 }
3361
3362 static bool x86_cpu_has_work(CPUState *cs)
3363 {
3364 X86CPU *cpu = X86_CPU(cs);
3365 CPUX86State *env = &cpu->env;
3366
3367 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
3368 CPU_INTERRUPT_POLL)) &&
3369 (env->eflags & IF_MASK)) ||
3370 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
3371 CPU_INTERRUPT_INIT |
3372 CPU_INTERRUPT_SIPI |
3373 CPU_INTERRUPT_MCE)) ||
3374 ((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
3375 !(env->hflags & HF_SMM_MASK));
3376 }
3377
3378 static Property x86_cpu_properties[] = {
3379 #ifdef CONFIG_USER_ONLY
3380 /* apic_id = 0 by default for *-user, see commit 9886e834 */
3381 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, 0),
3382 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, 0),
3383 DEFINE_PROP_INT32("core-id", X86CPU, core_id, 0),
3384 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, 0),
3385 #else
3386 DEFINE_PROP_UINT32("apic-id", X86CPU, apic_id, UNASSIGNED_APIC_ID),
3387 DEFINE_PROP_INT32("thread-id", X86CPU, thread_id, -1),
3388 DEFINE_PROP_INT32("core-id", X86CPU, core_id, -1),
3389 DEFINE_PROP_INT32("socket-id", X86CPU, socket_id, -1),
3390 #endif
3391 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
3392 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
3393 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
3394 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
3395 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
3396 DEFINE_PROP_BOOL("hv-crash", X86CPU, hyperv_crash, false),
3397 DEFINE_PROP_BOOL("hv-reset", X86CPU, hyperv_reset, false),
3398 DEFINE_PROP_BOOL("hv-vpindex", X86CPU, hyperv_vpindex, false),
3399 DEFINE_PROP_BOOL("hv-runtime", X86CPU, hyperv_runtime, false),
3400 DEFINE_PROP_BOOL("hv-synic", X86CPU, hyperv_synic, false),
3401 DEFINE_PROP_BOOL("hv-stimer", X86CPU, hyperv_stimer, false),
3402 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, true),
3403 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
3404 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
3405 DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0),
3406 DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false),
3407 DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true),
3408 DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0),
3409 DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0),
3410 DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0),
3411 DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id),
3412 DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true),
3413 DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false),
3414 DEFINE_PROP_BOOL("l3-cache", X86CPU, enable_l3_cache, true),
3415 DEFINE_PROP_END_OF_LIST()
3416 };
3417
3418 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
3419 {
3420 X86CPUClass *xcc = X86_CPU_CLASS(oc);
3421 CPUClass *cc = CPU_CLASS(oc);
3422 DeviceClass *dc = DEVICE_CLASS(oc);
3423
3424 xcc->parent_realize = dc->realize;
3425 dc->realize = x86_cpu_realizefn;
3426 dc->unrealize = x86_cpu_unrealizefn;
3427 dc->props = x86_cpu_properties;
3428
3429 xcc->parent_reset = cc->reset;
3430 cc->reset = x86_cpu_reset;
3431 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
3432
3433 cc->class_by_name = x86_cpu_class_by_name;
3434 cc->parse_features = x86_cpu_parse_featurestr;
3435 cc->has_work = x86_cpu_has_work;
3436 cc->do_interrupt = x86_cpu_do_interrupt;
3437 cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
3438 cc->dump_state = x86_cpu_dump_state;
3439 cc->set_pc = x86_cpu_set_pc;
3440 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
3441 cc->gdb_read_register = x86_cpu_gdb_read_register;
3442 cc->gdb_write_register = x86_cpu_gdb_write_register;
3443 cc->get_arch_id = x86_cpu_get_arch_id;
3444 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
3445 #ifdef CONFIG_USER_ONLY
3446 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
3447 #else
3448 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
3449 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
3450 cc->write_elf64_note = x86_cpu_write_elf64_note;
3451 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
3452 cc->write_elf32_note = x86_cpu_write_elf32_note;
3453 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
3454 cc->vmsd = &vmstate_x86_cpu;
3455 #endif
3456 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
3457 #ifndef CONFIG_USER_ONLY
3458 cc->debug_excp_handler = breakpoint_handler;
3459 #endif
3460 cc->cpu_exec_enter = x86_cpu_exec_enter;
3461 cc->cpu_exec_exit = x86_cpu_exec_exit;
3462
3463 dc->cannot_instantiate_with_device_add_yet = false;
3464 /*
3465 * Reason: x86_cpu_initfn() calls cpu_exec_init(), which saves the
3466 * object in cpus -> dangling pointer after final object_unref().
3467 */
3468 dc->cannot_destroy_with_object_finalize_yet = true;
3469 }
3470
3471 static const TypeInfo x86_cpu_type_info = {
3472 .name = TYPE_X86_CPU,
3473 .parent = TYPE_CPU,
3474 .instance_size = sizeof(X86CPU),
3475 .instance_init = x86_cpu_initfn,
3476 .abstract = true,
3477 .class_size = sizeof(X86CPUClass),
3478 .class_init = x86_cpu_common_class_init,
3479 };
3480
3481 static void x86_cpu_register_types(void)
3482 {
3483 int i;
3484
3485 type_register_static(&x86_cpu_type_info);
3486 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
3487 x86_register_cpudef_type(&builtin_x86_defs[i]);
3488 }
3489 #ifdef CONFIG_KVM
3490 type_register_static(&host_x86_cpu_type_info);
3491 #endif
3492 }
3493
3494 type_init(x86_cpu_register_types)
QEmu