xilinx: Inline usages of xilinx_axi*_init()
[qemu.git] / hw / ide / isa.c
blobd2cabc142f96a7156a21cf22dd3ee2506f7c645a
1 /*
2 * QEMU IDE Emulation: ISA Bus support.
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
25 #include <hw/hw.h>
26 #include <hw/i386/pc.h>
27 #include <hw/isa/isa.h>
28 #include "block/block.h"
29 #include "sysemu/dma.h"
31 #include <hw/ide/internal.h>
33 /***********************************************************/
34 /* ISA IDE definitions */
36 #define TYPE_ISA_IDE "isa-ide"
37 #define ISA_IDE(obj) OBJECT_CHECK(ISAIDEState, (obj), TYPE_ISA_IDE)
39 typedef struct ISAIDEState {
40 ISADevice parent_obj;
42 IDEBus bus;
43 uint32_t iobase;
44 uint32_t iobase2;
45 uint32_t isairq;
46 qemu_irq irq;
47 } ISAIDEState;
49 static void isa_ide_reset(DeviceState *d)
51 ISAIDEState *s = ISA_IDE(d);
53 ide_bus_reset(&s->bus);
56 static const VMStateDescription vmstate_ide_isa = {
57 .name = "isa-ide",
58 .version_id = 3,
59 .minimum_version_id = 0,
60 .minimum_version_id_old = 0,
61 .fields = (VMStateField []) {
62 VMSTATE_IDE_BUS(bus, ISAIDEState),
63 VMSTATE_IDE_DRIVES(bus.ifs, ISAIDEState),
64 VMSTATE_END_OF_LIST()
68 static void isa_ide_realizefn(DeviceState *dev, Error **errp)
70 ISADevice *isadev = ISA_DEVICE(dev);
71 ISAIDEState *s = ISA_IDE(dev);
73 ide_bus_new(&s->bus, sizeof(s->bus), dev, 0, 2);
74 ide_init_ioport(&s->bus, isadev, s->iobase, s->iobase2);
75 isa_init_irq(isadev, &s->irq, s->isairq);
76 ide_init2(&s->bus, s->irq);
77 vmstate_register(dev, 0, &vmstate_ide_isa, s);
80 ISADevice *isa_ide_init(ISABus *bus, int iobase, int iobase2, int isairq,
81 DriveInfo *hd0, DriveInfo *hd1)
83 DeviceState *dev;
84 ISADevice *isadev;
85 ISAIDEState *s;
87 isadev = isa_create(bus, TYPE_ISA_IDE);
88 dev = DEVICE(isadev);
89 qdev_prop_set_uint32(dev, "iobase", iobase);
90 qdev_prop_set_uint32(dev, "iobase2", iobase2);
91 qdev_prop_set_uint32(dev, "irq", isairq);
92 if (qdev_init(dev) < 0) {
93 return NULL;
96 s = ISA_IDE(dev);
97 if (hd0) {
98 ide_create_drive(&s->bus, 0, hd0);
100 if (hd1) {
101 ide_create_drive(&s->bus, 1, hd1);
103 return isadev;
106 static Property isa_ide_properties[] = {
107 DEFINE_PROP_UINT32("iobase", ISAIDEState, iobase, 0x1f0),
108 DEFINE_PROP_UINT32("iobase2", ISAIDEState, iobase2, 0x3f6),
109 DEFINE_PROP_UINT32("irq", ISAIDEState, isairq, 14),
110 DEFINE_PROP_END_OF_LIST(),
113 static void isa_ide_class_initfn(ObjectClass *klass, void *data)
115 DeviceClass *dc = DEVICE_CLASS(klass);
117 dc->realize = isa_ide_realizefn;
118 dc->fw_name = "ide";
119 dc->reset = isa_ide_reset;
120 dc->props = isa_ide_properties;
121 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
124 static const TypeInfo isa_ide_info = {
125 .name = TYPE_ISA_IDE,
126 .parent = TYPE_ISA_DEVICE,
127 .instance_size = sizeof(ISAIDEState),
128 .class_init = isa_ide_class_initfn,
131 static void isa_ide_register_types(void)
133 type_register_static(&isa_ide_info);
136 type_init(isa_ide_register_types)