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qdev: add qdev_prop_exists()
[qemu.git] / tcg / ppc64 / tcg-target.c
blob1bb13e6b0e12c947fca7562b0d708813e098ea0c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #define TCG_CT_CONST_U32 0x100
26
27 static uint8_t *tb_ret_addr;
28
29 #define FAST_PATH
30
31 #if TARGET_PHYS_ADDR_BITS == 32
32 #define LD_ADDEND LWZ
33 #else
34 #define LD_ADDEND LD
35 #endif
36
37 #if TARGET_LONG_BITS == 32
38 #define LD_ADDR LWZU
39 #define CMP_L 0
40 #else
41 #define LD_ADDR LDU
42 #define CMP_L (1<<21)
43 #endif
44
45 #ifndef GUEST_BASE
46 #define GUEST_BASE 0
47 #endif
48
49 #ifdef CONFIG_USE_GUEST_BASE
50 #define TCG_GUEST_BASE_REG 30
51 #else
52 #define TCG_GUEST_BASE_REG 0
53 #endif
54
55 #ifndef NDEBUG
56 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
57 "r0",
58 "r1",
59 "rp",
60 "r3",
61 "r4",
62 "r5",
63 "r6",
64 "r7",
65 "r8",
66 "r9",
67 "r10",
68 "r11",
69 "r12",
70 "r13",
71 "r14",
72 "r15",
73 "r16",
74 "r17",
75 "r18",
76 "r19",
77 "r20",
78 "r21",
79 "r22",
80 "r23",
81 "r24",
82 "r25",
83 "r26",
84 "r27",
85 "r28",
86 "r29",
87 "r30",
88 "r31"
89 };
90 #endif
91
92 static const int tcg_target_reg_alloc_order[] = {
93 TCG_REG_R14,
94 TCG_REG_R15,
95 TCG_REG_R16,
96 TCG_REG_R17,
97 TCG_REG_R18,
98 TCG_REG_R19,
99 TCG_REG_R20,
100 TCG_REG_R21,
101 TCG_REG_R22,
102 TCG_REG_R23,
103 TCG_REG_R28,
104 TCG_REG_R29,
105 TCG_REG_R30,
106 TCG_REG_R31,
107 TCG_REG_R3,
108 TCG_REG_R4,
109 TCG_REG_R5,
110 TCG_REG_R6,
111 TCG_REG_R7,
112 TCG_REG_R8,
113 TCG_REG_R9,
114 TCG_REG_R10,
115 TCG_REG_R11,
116 TCG_REG_R12,
117 TCG_REG_R24,
118 TCG_REG_R25,
119 TCG_REG_R26,
120 TCG_REG_R27
121 };
122
123 static const int tcg_target_call_iarg_regs[] = {
124 TCG_REG_R3,
125 TCG_REG_R4,
126 TCG_REG_R5,
127 TCG_REG_R6,
128 TCG_REG_R7,
129 TCG_REG_R8,
130 TCG_REG_R9,
131 TCG_REG_R10
132 };
133
134 static const int tcg_target_call_oarg_regs[2] = {
135 TCG_REG_R3
136 };
137
138 static const int tcg_target_callee_save_regs[] = {
139 TCG_REG_R14,
140 TCG_REG_R15,
141 TCG_REG_R16,
142 TCG_REG_R17,
143 TCG_REG_R18,
144 TCG_REG_R19,
145 TCG_REG_R20,
146 TCG_REG_R21,
147 TCG_REG_R22,
148 TCG_REG_R23,
149 TCG_REG_R24,
150 TCG_REG_R25,
151 TCG_REG_R26,
152 /* TCG_REG_R27, */ /* currently used for the global env, so no
153 need to save */
154 TCG_REG_R28,
155 TCG_REG_R29,
156 TCG_REG_R30,
157 TCG_REG_R31
158 };
159
160 static uint32_t reloc_pc24_val (void *pc, tcg_target_long target)
161 {
162 tcg_target_long disp;
163
164 disp = target - (tcg_target_long) pc;
165 if ((disp << 38) >> 38 != disp)
166 tcg_abort ();
167
168 return disp & 0x3fffffc;
169 }
170
171 static void reloc_pc24 (void *pc, tcg_target_long target)
172 {
173 *(uint32_t *) pc = (*(uint32_t *) pc & ~0x3fffffc)
174 | reloc_pc24_val (pc, target);
175 }
176
177 static uint16_t reloc_pc14_val (void *pc, tcg_target_long target)
178 {
179 tcg_target_long disp;
180
181 disp = target - (tcg_target_long) pc;
182 if (disp != (int16_t) disp)
183 tcg_abort ();
184
185 return disp & 0xfffc;
186 }
187
188 static void reloc_pc14 (void *pc, tcg_target_long target)
189 {
190 *(uint32_t *) pc = (*(uint32_t *) pc & ~0xfffc)
191 | reloc_pc14_val (pc, target);
192 }
193
194 static void patch_reloc (uint8_t *code_ptr, int type,
195 tcg_target_long value, tcg_target_long addend)
196 {
197 value += addend;
198 switch (type) {
199 case R_PPC_REL14:
200 reloc_pc14 (code_ptr, value);
201 break;
202 case R_PPC_REL24:
203 reloc_pc24 (code_ptr, value);
204 break;
205 default:
206 tcg_abort ();
207 }
208 }
209
210 /* maximum number of register used for input function arguments */
211 static int tcg_target_get_call_iarg_regs_count (int flags)
212 {
213 return ARRAY_SIZE (tcg_target_call_iarg_regs);
214 }
215
216 /* parse target specific constraints */
217 static int target_parse_constraint (TCGArgConstraint *ct, const char **pct_str)
218 {
219 const char *ct_str;
220
221 ct_str = *pct_str;
222 switch (ct_str[0]) {
223 case 'A': case 'B': case 'C': case 'D':
224 ct->ct |= TCG_CT_REG;
225 tcg_regset_set_reg (ct->u.regs, 3 + ct_str[0] - 'A');
226 break;
227 case 'r':
228 ct->ct |= TCG_CT_REG;
229 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
230 break;
231 case 'L': /* qemu_ld constraint */
232 ct->ct |= TCG_CT_REG;
233 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
234 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
235 #ifdef CONFIG_SOFTMMU
236 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
237 #endif
238 break;
239 case 'S': /* qemu_st constraint */
240 ct->ct |= TCG_CT_REG;
241 tcg_regset_set32 (ct->u.regs, 0, 0xffffffff);
242 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R3);
243 #ifdef CONFIG_SOFTMMU
244 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R4);
245 tcg_regset_reset_reg (ct->u.regs, TCG_REG_R5);
246 #endif
247 break;
248 case 'Z':
249 ct->ct |= TCG_CT_CONST_U32;
250 break;
251 default:
252 return -1;
253 }
254 ct_str++;
255 *pct_str = ct_str;
256 return 0;
257 }
258
259 /* test if a constant matches the constraint */
260 static int tcg_target_const_match (tcg_target_long val,
261 const TCGArgConstraint *arg_ct)
262 {
263 int ct;
264
265 ct = arg_ct->ct;
266 if (ct & TCG_CT_CONST)
267 return 1;
268 else if ((ct & TCG_CT_CONST_U32) && (val == (uint32_t) val))
269 return 1;
270 return 0;
271 }
272
273 #define OPCD(opc) ((opc)<<26)
274 #define XO19(opc) (OPCD(19)|((opc)<<1))
275 #define XO30(opc) (OPCD(30)|((opc)<<2))
276 #define XO31(opc) (OPCD(31)|((opc)<<1))
277 #define XO58(opc) (OPCD(58)|(opc))
278 #define XO62(opc) (OPCD(62)|(opc))
279
280 #define B OPCD( 18)
281 #define BC OPCD( 16)
282 #define LBZ OPCD( 34)
283 #define LHZ OPCD( 40)
284 #define LHA OPCD( 42)
285 #define LWZ OPCD( 32)
286 #define STB OPCD( 38)
287 #define STH OPCD( 44)
288 #define STW OPCD( 36)
289
290 #define STD XO62( 0)
291 #define STDU XO62( 1)
292 #define STDX XO31(149)
293
294 #define LD XO58( 0)
295 #define LDX XO31( 21)
296 #define LDU XO58( 1)
297 #define LWA XO58( 2)
298 #define LWAX XO31(341)
299
300 #define ADDI OPCD( 14)
301 #define ADDIS OPCD( 15)
302 #define ORI OPCD( 24)
303 #define ORIS OPCD( 25)
304 #define XORI OPCD( 26)
305 #define XORIS OPCD( 27)
306 #define ANDI OPCD( 28)
307 #define ANDIS OPCD( 29)
308 #define MULLI OPCD( 7)
309 #define CMPLI OPCD( 10)
310 #define CMPI OPCD( 11)
311
312 #define LWZU OPCD( 33)
313 #define STWU OPCD( 37)
314
315 #define RLWINM OPCD( 21)
316
317 #define RLDICL XO30( 0)
318 #define RLDICR XO30( 1)
319 #define RLDIMI XO30( 3)
320
321 #define BCLR XO19( 16)
322 #define BCCTR XO19(528)
323 #define CRAND XO19(257)
324 #define CRANDC XO19(129)
325 #define CRNAND XO19(225)
326 #define CROR XO19(449)
327
328 #define EXTSB XO31(954)
329 #define EXTSH XO31(922)
330 #define EXTSW XO31(986)
331 #define ADD XO31(266)
332 #define ADDE XO31(138)
333 #define ADDC XO31( 10)
334 #define AND XO31( 28)
335 #define SUBF XO31( 40)
336 #define SUBFC XO31( 8)
337 #define SUBFE XO31(136)
338 #define OR XO31(444)
339 #define XOR XO31(316)
340 #define MULLW XO31(235)
341 #define MULHWU XO31( 11)
342 #define DIVW XO31(491)
343 #define DIVWU XO31(459)
344 #define CMP XO31( 0)
345 #define CMPL XO31( 32)
346 #define LHBRX XO31(790)
347 #define LWBRX XO31(534)
348 #define STHBRX XO31(918)
349 #define STWBRX XO31(662)
350 #define MFSPR XO31(339)
351 #define MTSPR XO31(467)
352 #define SRAWI XO31(824)
353 #define NEG XO31(104)
354
355 #define MULLD XO31(233)
356 #define MULHD XO31( 73)
357 #define MULHDU XO31( 9)
358 #define DIVD XO31(489)
359 #define DIVDU XO31(457)
360
361 #define LBZX XO31( 87)
362 #define LHZX XO31(279)
363 #define LHAX XO31(343)
364 #define LWZX XO31( 23)
365 #define STBX XO31(215)
366 #define STHX XO31(407)
367 #define STWX XO31(151)
368
369 #define SPR(a,b) ((((a)<<5)|(b))<<11)
370 #define LR SPR(8, 0)
371 #define CTR SPR(9, 0)
372
373 #define SLW XO31( 24)
374 #define SRW XO31(536)
375 #define SRAW XO31(792)
376
377 #define SLD XO31( 27)
378 #define SRD XO31(539)
379 #define SRAD XO31(794)
380 #define SRADI XO31(413<<1)
381
382 #define TW XO31( 4)
383 #define TRAP (TW | TO (31))
384
385 #define RT(r) ((r)<<21)
386 #define RS(r) ((r)<<21)
387 #define RA(r) ((r)<<16)
388 #define RB(r) ((r)<<11)
389 #define TO(t) ((t)<<21)
390 #define SH(s) ((s)<<11)
391 #define MB(b) ((b)<<6)
392 #define ME(e) ((e)<<1)
393 #define BO(o) ((o)<<21)
394 #define MB64(b) ((b)<<5)
395
396 #define LK 1
397
398 #define TAB(t,a,b) (RT(t) | RA(a) | RB(b))
399 #define SAB(s,a,b) (RS(s) | RA(a) | RB(b))
400
401 #define BF(n) ((n)<<23)
402 #define BI(n, c) (((c)+((n)*4))<<16)
403 #define BT(n, c) (((c)+((n)*4))<<21)
404 #define BA(n, c) (((c)+((n)*4))<<16)
405 #define BB(n, c) (((c)+((n)*4))<<11)
406
407 #define BO_COND_TRUE BO (12)
408 #define BO_COND_FALSE BO ( 4)
409 #define BO_ALWAYS BO (20)
410
411 enum {
412 CR_LT,
413 CR_GT,
414 CR_EQ,
415 CR_SO
416 };
417
418 static const uint32_t tcg_to_bc[10] = {
419 [TCG_COND_EQ] = BC | BI (7, CR_EQ) | BO_COND_TRUE,
420 [TCG_COND_NE] = BC | BI (7, CR_EQ) | BO_COND_FALSE,
421 [TCG_COND_LT] = BC | BI (7, CR_LT) | BO_COND_TRUE,
422 [TCG_COND_GE] = BC | BI (7, CR_LT) | BO_COND_FALSE,
423 [TCG_COND_LE] = BC | BI (7, CR_GT) | BO_COND_FALSE,
424 [TCG_COND_GT] = BC | BI (7, CR_GT) | BO_COND_TRUE,
425 [TCG_COND_LTU] = BC | BI (7, CR_LT) | BO_COND_TRUE,
426 [TCG_COND_GEU] = BC | BI (7, CR_LT) | BO_COND_FALSE,
427 [TCG_COND_LEU] = BC | BI (7, CR_GT) | BO_COND_FALSE,
428 [TCG_COND_GTU] = BC | BI (7, CR_GT) | BO_COND_TRUE,
429 };
430
431 static void tcg_out_mov (TCGContext *s, int ret, int arg)
432 {
433 tcg_out32 (s, OR | SAB (arg, ret, arg));
434 }
435
436 static void tcg_out_rld (TCGContext *s, int op, int ra, int rs, int sh, int mb)
437 {
438 sh = SH (sh & 0x1f) | (((sh >> 5) & 1) << 1);
439 mb = MB64 ((mb >> 5) | ((mb << 1) & 0x3f));
440 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
441 }
442
443 static void tcg_out_movi32 (TCGContext *s, int ret, int32_t arg)
444 {
445 if (arg == (int16_t) arg)
446 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
447 else {
448 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
449 if (arg & 0xffff)
450 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
451 }
452 }
453
454 static void tcg_out_movi (TCGContext *s, TCGType type,
455 int ret, tcg_target_long arg)
456 {
457 int32_t arg32 = arg;
458
459 if (type == TCG_TYPE_I32 || arg == arg32) {
460 tcg_out_movi32 (s, ret, arg32);
461 }
462 else {
463 if ((uint64_t) arg >> 32) {
464 uint16_t h16 = arg >> 16;
465 uint16_t l16 = arg;
466
467 tcg_out_movi32 (s, ret, arg >> 32);
468 tcg_out_rld (s, RLDICR, ret, ret, 32, 31);
469 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
470 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
471 }
472 else {
473 tcg_out_movi32 (s, ret, arg32);
474 if (arg32 < 0)
475 tcg_out_rld (s, RLDICL, ret, ret, 0, 32);
476 }
477 }
478 }
479
480 static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg)
481 {
482 int reg;
483
484 if (const_arg) {
485 reg = 2;
486 tcg_out_movi (s, TCG_TYPE_I64, reg, arg);
487 }
488 else reg = arg;
489
490 tcg_out32 (s, LD | RT (0) | RA (reg));
491 tcg_out32 (s, MTSPR | RA (0) | CTR);
492 tcg_out32 (s, LD | RT (11) | RA (reg) | 16);
493 tcg_out32 (s, LD | RT (2) | RA (reg) | 8);
494 tcg_out32 (s, BCCTR | BO_ALWAYS | LK);
495 }
496
497 static void tcg_out_ldst (TCGContext *s, int ret, int addr,
498 int offset, int op1, int op2)
499 {
500 if (offset == (int16_t) offset)
501 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
502 else {
503 tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
504 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
505 }
506 }
507
508 static void tcg_out_ldsta (TCGContext *s, int ret, int addr,
509 int offset, int op1, int op2)
510 {
511 if (offset == (int16_t) (offset & ~3))
512 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
513 else {
514 tcg_out_movi (s, TCG_TYPE_I64, 0, offset);
515 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
516 }
517 }
518
519 static void tcg_out_b (TCGContext *s, int mask, tcg_target_long target)
520 {
521 tcg_target_long disp;
522
523 disp = target - (tcg_target_long) s->code_ptr;
524 if ((disp << 38) >> 38 == disp)
525 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
526 else {
527 tcg_out_movi (s, TCG_TYPE_I64, 0, (tcg_target_long) target);
528 tcg_out32 (s, MTSPR | RS (0) | CTR);
529 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
530 }
531 }
532
533 #if defined (CONFIG_SOFTMMU)
534
535 #include "../../softmmu_defs.h"
536
537 static void *qemu_ld_helpers[4] = {
538 __ldb_mmu,
539 __ldw_mmu,
540 __ldl_mmu,
541 __ldq_mmu,
542 };
543
544 static void *qemu_st_helpers[4] = {
545 __stb_mmu,
546 __stw_mmu,
547 __stl_mmu,
548 __stq_mmu,
549 };
550
551 static void tcg_out_tlb_read (TCGContext *s, int r0, int r1, int r2,
552 int addr_reg, int s_bits, int offset)
553 {
554 #if TARGET_LONG_BITS == 32
555 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
556
557 tcg_out32 (s, (RLWINM
558 | RA (r0)
559 | RS (addr_reg)
560 | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
561 | MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
562 | ME (31 - CPU_TLB_ENTRY_BITS)
563 )
564 );
565 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
566 tcg_out32 (s, (LWZU | RT (r1) | RA (r0) | offset));
567 tcg_out32 (s, (RLWINM
568 | RA (r2)
569 | RS (addr_reg)
570 | SH (0)
571 | MB ((32 - s_bits) & 31)
572 | ME (31 - TARGET_PAGE_BITS)
573 )
574 );
575 #else
576 tcg_out_rld (s, RLDICL, r0, addr_reg,
577 64 - TARGET_PAGE_BITS,
578 64 - CPU_TLB_BITS);
579 tcg_out_rld (s, RLDICR, r0, r0,
580 CPU_TLB_ENTRY_BITS,
581 63 - CPU_TLB_ENTRY_BITS);
582
583 tcg_out32 (s, ADD | TAB (r0, r0, TCG_AREG0));
584 tcg_out32 (s, LD_ADDR | RT (r1) | RA (r0) | offset);
585
586 if (!s_bits) {
587 tcg_out_rld (s, RLDICR, r2, addr_reg, 0, 63 - TARGET_PAGE_BITS);
588 }
589 else {
590 tcg_out_rld (s, RLDICL, r2, addr_reg,
591 64 - TARGET_PAGE_BITS,
592 TARGET_PAGE_BITS - s_bits);
593 tcg_out_rld (s, RLDICL, r2, r2, TARGET_PAGE_BITS, 0);
594 }
595 #endif
596 }
597 #endif
598
599 static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
600 {
601 int addr_reg, data_reg, r0, r1, rbase, mem_index, s_bits, bswap;
602 #ifdef CONFIG_SOFTMMU
603 int r2;
604 void *label1_ptr, *label2_ptr;
605 #endif
606
607 data_reg = *args++;
608 addr_reg = *args++;
609 mem_index = *args;
610 s_bits = opc & 3;
611
612 #ifdef CONFIG_SOFTMMU
613 r0 = 3;
614 r1 = 4;
615 r2 = 0;
616 rbase = 0;
617
618 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, s_bits,
619 offsetof (CPUState, tlb_table[mem_index][0].addr_read));
620
621 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
622
623 label1_ptr = s->code_ptr;
624 #ifdef FAST_PATH
625 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
626 #endif
627
628 /* slow path */
629 tcg_out_mov (s, 3, addr_reg);
630 tcg_out_movi (s, TCG_TYPE_I64, 4, mem_index);
631
632 tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
633
634 switch (opc) {
635 case 0|4:
636 tcg_out32 (s, EXTSB | RA (data_reg) | RS (3));
637 break;
638 case 1|4:
639 tcg_out32 (s, EXTSH | RA (data_reg) | RS (3));
640 break;
641 case 2|4:
642 tcg_out32 (s, EXTSW | RA (data_reg) | RS (3));
643 break;
644 case 0:
645 case 1:
646 case 2:
647 case 3:
648 if (data_reg != 3)
649 tcg_out_mov (s, data_reg, 3);
650 break;
651 }
652 label2_ptr = s->code_ptr;
653 tcg_out32 (s, B);
654
655 /* label1: fast path */
656 #ifdef FAST_PATH
657 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
658 #endif
659
660 /* r0 now contains &env->tlb_table[mem_index][index].addr_read */
661 tcg_out32 (s, (LD_ADDEND
662 | RT (r0)
663 | RA (r0)
664 | (offsetof (CPUTLBEntry, addend)
665 - offsetof (CPUTLBEntry, addr_read))
666 ));
667 /* r0 = env->tlb_table[mem_index][index].addend */
668 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
669 /* r0 = env->tlb_table[mem_index][index].addend + addr */
670
671 #else /* !CONFIG_SOFTMMU */
672 #if TARGET_LONG_BITS == 32
673 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
674 #endif
675 r0 = addr_reg;
676 r1 = 3;
677 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
678 #endif
679
680 #ifdef TARGET_WORDS_BIGENDIAN
681 bswap = 0;
682 #else
683 bswap = 1;
684 #endif
685 switch (opc) {
686 default:
687 case 0:
688 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
689 break;
690 case 0|4:
691 tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
692 tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
693 break;
694 case 1:
695 if (bswap)
696 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
697 else
698 tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
699 break;
700 case 1|4:
701 if (bswap) {
702 tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
703 tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
704 }
705 else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
706 break;
707 case 2:
708 if (bswap)
709 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
710 else
711 tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
712 break;
713 case 2|4:
714 if (bswap) {
715 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
716 tcg_out32 (s, EXTSW | RA (data_reg) | RS (data_reg));
717 }
718 else tcg_out32 (s, LWAX | TAB (data_reg, rbase, r0));
719 break;
720 case 3:
721 #ifdef CONFIG_USE_GUEST_BASE
722 if (bswap) {
723 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
724 tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
725 tcg_out32 (s, LWBRX | TAB ( r1, rbase, r1));
726 tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
727 }
728 else tcg_out32 (s, LDX | TAB (data_reg, rbase, r0));
729 #else
730 if (bswap) {
731 tcg_out_movi32 (s, 0, 4);
732 tcg_out32 (s, LWBRX | RT (data_reg) | RB (r0));
733 tcg_out32 (s, LWBRX | RT ( r1) | RA (r0));
734 tcg_out_rld (s, RLDIMI, data_reg, r1, 32, 0);
735 }
736 else tcg_out32 (s, LD | RT (data_reg) | RA (r0));
737 #endif
738 break;
739 }
740
741 #ifdef CONFIG_SOFTMMU
742 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
743 #endif
744 }
745
746 static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
747 {
748 int addr_reg, r0, r1, rbase, data_reg, mem_index, bswap;
749 #ifdef CONFIG_SOFTMMU
750 int r2;
751 void *label1_ptr, *label2_ptr;
752 #endif
753
754 data_reg = *args++;
755 addr_reg = *args++;
756 mem_index = *args;
757
758 #ifdef CONFIG_SOFTMMU
759 r0 = 3;
760 r1 = 4;
761 r2 = 0;
762 rbase = 0;
763
764 tcg_out_tlb_read (s, r0, r1, r2, addr_reg, opc,
765 offsetof (CPUState, tlb_table[mem_index][0].addr_write));
766
767 tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1) | CMP_L);
768
769 label1_ptr = s->code_ptr;
770 #ifdef FAST_PATH
771 tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE);
772 #endif
773
774 /* slow path */
775 tcg_out_mov (s, 3, addr_reg);
776 tcg_out_rld (s, RLDICL, 4, data_reg, 0, 64 - (1 << (3 + opc)));
777 tcg_out_movi (s, TCG_TYPE_I64, 5, mem_index);
778
779 tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
780
781 label2_ptr = s->code_ptr;
782 tcg_out32 (s, B);
783
784 /* label1: fast path */
785 #ifdef FAST_PATH
786 reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr);
787 #endif
788
789 tcg_out32 (s, (LD_ADDEND
790 | RT (r0)
791 | RA (r0)
792 | (offsetof (CPUTLBEntry, addend)
793 - offsetof (CPUTLBEntry, addr_write))
794 ));
795 /* r0 = env->tlb_table[mem_index][index].addend */
796 tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
797 /* r0 = env->tlb_table[mem_index][index].addend + addr */
798
799 #else /* !CONFIG_SOFTMMU */
800 #if TARGET_LONG_BITS == 32
801 tcg_out_rld (s, RLDICL, addr_reg, addr_reg, 0, 32);
802 #endif
803 r1 = 3;
804 r0 = addr_reg;
805 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
806 #endif
807
808 #ifdef TARGET_WORDS_BIGENDIAN
809 bswap = 0;
810 #else
811 bswap = 1;
812 #endif
813 switch (opc) {
814 case 0:
815 tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
816 break;
817 case 1:
818 if (bswap)
819 tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
820 else
821 tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
822 break;
823 case 2:
824 if (bswap)
825 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
826 else
827 tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
828 break;
829 case 3:
830 if (bswap) {
831 tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
832 tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
833 tcg_out_rld (s, RLDICL, 0, data_reg, 32, 0);
834 tcg_out32 (s, STWBRX | SAB (0, rbase, r1));
835 }
836 else tcg_out32 (s, STDX | SAB (data_reg, rbase, r0));
837 break;
838 }
839
840 #ifdef CONFIG_SOFTMMU
841 reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr);
842 #endif
843 }
844
845 void tcg_target_qemu_prologue (TCGContext *s)
846 {
847 int i, frame_size;
848 uint64_t addr;
849
850 frame_size = 0
851 + 8 /* back chain */
852 + 8 /* CR */
853 + 8 /* LR */
854 + 8 /* compiler doubleword */
855 + 8 /* link editor doubleword */
856 + 8 /* TOC save area */
857 + TCG_STATIC_CALL_ARGS_SIZE
858 + ARRAY_SIZE (tcg_target_callee_save_regs) * 8
859 ;
860 frame_size = (frame_size + 15) & ~15;
861
862 /* First emit adhoc function descriptor */
863 addr = (uint64_t) s->code_ptr + 24;
864 tcg_out32 (s, addr >> 32); tcg_out32 (s, addr); /* entry point */
865 s->code_ptr += 16; /* skip TOC and environment pointer */
866
867 /* Prologue */
868 tcg_out32 (s, MFSPR | RT (0) | LR);
869 tcg_out32 (s, STDU | RS (1) | RA (1) | (-frame_size & 0xffff));
870 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
871 tcg_out32 (s, (STD
872 | RS (tcg_target_callee_save_regs[i])
873 | RA (1)
874 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
875 )
876 );
877 tcg_out32 (s, STD | RS (0) | RA (1) | (frame_size + 16));
878
879 #ifdef CONFIG_USE_GUEST_BASE
880 tcg_out_movi (s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE);
881 #endif
882
883 tcg_out32 (s, MTSPR | RS (3) | CTR);
884 tcg_out32 (s, BCCTR | BO_ALWAYS);
885
886 /* Epilogue */
887 tb_ret_addr = s->code_ptr;
888
889 for (i = 0; i < ARRAY_SIZE (tcg_target_callee_save_regs); ++i)
890 tcg_out32 (s, (LD
891 | RT (tcg_target_callee_save_regs[i])
892 | RA (1)
893 | (i * 8 + 48 + TCG_STATIC_CALL_ARGS_SIZE)
894 )
895 );
896 tcg_out32 (s, LD | RT (0) | RA (1) | (frame_size + 16));
897 tcg_out32 (s, MTSPR | RS (0) | LR);
898 tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
899 tcg_out32 (s, BCLR | BO_ALWAYS);
900 }
901
902 static void tcg_out_ld (TCGContext *s, TCGType type, int ret, int arg1,
903 tcg_target_long arg2)
904 {
905 if (type == TCG_TYPE_I32)
906 tcg_out_ldst (s, ret, arg1, arg2, LWZ, LWZX);
907 else
908 tcg_out_ldsta (s, ret, arg1, arg2, LD, LDX);
909 }
910
911 static void tcg_out_st (TCGContext *s, TCGType type, int arg, int arg1,
912 tcg_target_long arg2)
913 {
914 if (type == TCG_TYPE_I32)
915 tcg_out_ldst (s, arg, arg1, arg2, STW, STWX);
916 else
917 tcg_out_ldsta (s, arg, arg1, arg2, STD, STDX);
918 }
919
920 static void ppc_addi32 (TCGContext *s, int rt, int ra, tcg_target_long si)
921 {
922 if (!si && rt == ra)
923 return;
924
925 if (si == (int16_t) si)
926 tcg_out32 (s, ADDI | RT (rt) | RA (ra) | (si & 0xffff));
927 else {
928 uint16_t h = ((si >> 16) & 0xffff) + ((uint16_t) si >> 15);
929 tcg_out32 (s, ADDIS | RT (rt) | RA (ra) | h);
930 tcg_out32 (s, ADDI | RT (rt) | RA (rt) | (si & 0xffff));
931 }
932 }
933
934 static void ppc_addi64 (TCGContext *s, int rt, int ra, tcg_target_long si)
935 {
936 /* XXX: suboptimal */
937 if (si == (int16_t) si
938 || ((((uint64_t) si >> 31) == 0) && (si & 0x8000) == 0))
939 ppc_addi32 (s, rt, ra, si);
940 else {
941 tcg_out_movi (s, TCG_TYPE_I64, 0, si);
942 tcg_out32 (s, ADD | RT (rt) | RA (ra));
943 }
944 }
945
946 static void tcg_out_addi (TCGContext *s, int reg, tcg_target_long val)
947 {
948 ppc_addi64 (s, reg, reg, val);
949 }
950
951 static void tcg_out_cmp (TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
952 int const_arg2, int cr, int arch64)
953 {
954 int imm;
955 uint32_t op;
956
957 switch (cond) {
958 case TCG_COND_EQ:
959 case TCG_COND_NE:
960 if (const_arg2) {
961 if ((int16_t) arg2 == arg2) {
962 op = CMPI;
963 imm = 1;
964 break;
965 }
966 else if ((uint16_t) arg2 == arg2) {
967 op = CMPLI;
968 imm = 1;
969 break;
970 }
971 }
972 op = CMPL;
973 imm = 0;
974 break;
975
976 case TCG_COND_LT:
977 case TCG_COND_GE:
978 case TCG_COND_LE:
979 case TCG_COND_GT:
980 if (const_arg2) {
981 if ((int16_t) arg2 == arg2) {
982 op = CMPI;
983 imm = 1;
984 break;
985 }
986 }
987 op = CMP;
988 imm = 0;
989 break;
990
991 case TCG_COND_LTU:
992 case TCG_COND_GEU:
993 case TCG_COND_LEU:
994 case TCG_COND_GTU:
995 if (const_arg2) {
996 if ((uint16_t) arg2 == arg2) {
997 op = CMPLI;
998 imm = 1;
999 break;
1000 }
1001 }
1002 op = CMPL;
1003 imm = 0;
1004 break;
1005
1006 default:
1007 tcg_abort ();
1008 }
1009 op |= BF (cr) | (arch64 << 21);
1010
1011 if (imm)
1012 tcg_out32 (s, op | RA (arg1) | (arg2 & 0xffff));
1013 else {
1014 if (const_arg2) {
1015 tcg_out_movi (s, TCG_TYPE_I64, 0, arg2);
1016 tcg_out32 (s, op | RA (arg1) | RB (0));
1017 }
1018 else
1019 tcg_out32 (s, op | RA (arg1) | RB (arg2));
1020 }
1021
1022 }
1023
1024 static void tcg_out_bc (TCGContext *s, int bc, int label_index)
1025 {
1026 TCGLabel *l = &s->labels[label_index];
1027
1028 if (l->has_value)
1029 tcg_out32 (s, bc | reloc_pc14_val (s->code_ptr, l->u.value));
1030 else {
1031 uint16_t val = *(uint16_t *) &s->code_ptr[2];
1032
1033 /* Thanks to Andrzej Zaborowski */
1034 tcg_out32 (s, bc | (val & 0xfffc));
1035 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL14, label_index, 0);
1036 }
1037 }
1038
1039 static void tcg_out_brcond (TCGContext *s, int cond,
1040 TCGArg arg1, TCGArg arg2, int const_arg2,
1041 int label_index, int arch64)
1042 {
1043 tcg_out_cmp (s, cond, arg1, arg2, const_arg2, 7, arch64);
1044 tcg_out_bc (s, tcg_to_bc[cond], label_index);
1045 }
1046
1047 void ppc_tb_set_jmp_target (unsigned long jmp_addr, unsigned long addr)
1048 {
1049 TCGContext s;
1050 unsigned long patch_size;
1051
1052 s.code_ptr = (uint8_t *) jmp_addr;
1053 tcg_out_b (&s, 0, addr);
1054 patch_size = s.code_ptr - (uint8_t *) jmp_addr;
1055 flush_icache_range (jmp_addr, jmp_addr + patch_size);
1056 }
1057
1058 static void tcg_out_op (TCGContext *s, int opc, const TCGArg *args,
1059 const int *const_args)
1060 {
1061 int c;
1062
1063 switch (opc) {
1064 case INDEX_op_exit_tb:
1065 tcg_out_movi (s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
1066 tcg_out_b (s, 0, (tcg_target_long) tb_ret_addr);
1067 break;
1068 case INDEX_op_goto_tb:
1069 if (s->tb_jmp_offset) {
1070 /* direct jump method */
1071
1072 s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1073 s->code_ptr += 28;
1074 }
1075 else {
1076 tcg_abort ();
1077 }
1078 s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1079 break;
1080 case INDEX_op_br:
1081 {
1082 TCGLabel *l = &s->labels[args[0]];
1083
1084 if (l->has_value) {
1085 tcg_out_b (s, 0, l->u.value);
1086 }
1087 else {
1088 uint32_t val = *(uint32_t *) s->code_ptr;
1089
1090 /* Thanks to Andrzej Zaborowski */
1091 tcg_out32 (s, B | (val & 0x3fffffc));
1092 tcg_out_reloc (s, s->code_ptr - 4, R_PPC_REL24, args[0], 0);
1093 }
1094 }
1095 break;
1096 case INDEX_op_call:
1097 tcg_out_call (s, args[0], const_args[0]);
1098 break;
1099 case INDEX_op_jmp:
1100 if (const_args[0]) {
1101 tcg_out_b (s, 0, args[0]);
1102 }
1103 else {
1104 tcg_out32 (s, MTSPR | RS (args[0]) | CTR);
1105 tcg_out32 (s, BCCTR | BO_ALWAYS);
1106 }
1107 break;
1108 case INDEX_op_movi_i32:
1109 tcg_out_movi (s, TCG_TYPE_I32, args[0], args[1]);
1110 break;
1111 case INDEX_op_movi_i64:
1112 tcg_out_movi (s, TCG_TYPE_I64, args[0], args[1]);
1113 break;
1114 case INDEX_op_ld8u_i32:
1115 case INDEX_op_ld8u_i64:
1116 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1117 break;
1118 case INDEX_op_ld8s_i32:
1119 case INDEX_op_ld8s_i64:
1120 tcg_out_ldst (s, args[0], args[1], args[2], LBZ, LBZX);
1121 tcg_out32 (s, EXTSB | RS (args[0]) | RA (args[0]));
1122 break;
1123 case INDEX_op_ld16u_i32:
1124 case INDEX_op_ld16u_i64:
1125 tcg_out_ldst (s, args[0], args[1], args[2], LHZ, LHZX);
1126 break;
1127 case INDEX_op_ld16s_i32:
1128 case INDEX_op_ld16s_i64:
1129 tcg_out_ldst (s, args[0], args[1], args[2], LHA, LHAX);
1130 break;
1131 case INDEX_op_ld_i32:
1132 case INDEX_op_ld32u_i64:
1133 tcg_out_ldst (s, args[0], args[1], args[2], LWZ, LWZX);
1134 break;
1135 case INDEX_op_ld32s_i64:
1136 tcg_out_ldsta (s, args[0], args[1], args[2], LWA, LWAX);
1137 break;
1138 case INDEX_op_ld_i64:
1139 tcg_out_ldsta (s, args[0], args[1], args[2], LD, LDX);
1140 break;
1141 case INDEX_op_st8_i32:
1142 case INDEX_op_st8_i64:
1143 tcg_out_ldst (s, args[0], args[1], args[2], STB, STBX);
1144 break;
1145 case INDEX_op_st16_i32:
1146 case INDEX_op_st16_i64:
1147 tcg_out_ldst (s, args[0], args[1], args[2], STH, STHX);
1148 break;
1149 case INDEX_op_st_i32:
1150 case INDEX_op_st32_i64:
1151 tcg_out_ldst (s, args[0], args[1], args[2], STW, STWX);
1152 break;
1153 case INDEX_op_st_i64:
1154 tcg_out_ldsta (s, args[0], args[1], args[2], STD, STDX);
1155 break;
1156
1157 case INDEX_op_add_i32:
1158 if (const_args[2])
1159 ppc_addi32 (s, args[0], args[1], args[2]);
1160 else
1161 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1162 break;
1163 case INDEX_op_sub_i32:
1164 if (const_args[2])
1165 ppc_addi32 (s, args[0], args[1], -args[2]);
1166 else
1167 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1168 break;
1169
1170 case INDEX_op_and_i64:
1171 case INDEX_op_and_i32:
1172 if (const_args[2]) {
1173 if ((args[2] & 0xffff) == args[2])
1174 tcg_out32 (s, ANDI | RS (args[1]) | RA (args[0]) | args[2]);
1175 else if ((args[2] & 0xffff0000) == args[2])
1176 tcg_out32 (s, ANDIS | RS (args[1]) | RA (args[0])
1177 | ((args[2] >> 16) & 0xffff));
1178 else {
1179 tcg_out_movi (s, (opc == INDEX_op_and_i32
1180 ? TCG_TYPE_I32
1181 : TCG_TYPE_I64),
1182 0, args[2]);
1183 tcg_out32 (s, AND | SAB (args[1], args[0], 0));
1184 }
1185 }
1186 else
1187 tcg_out32 (s, AND | SAB (args[1], args[0], args[2]));
1188 break;
1189 case INDEX_op_or_i64:
1190 case INDEX_op_or_i32:
1191 if (const_args[2]) {
1192 if (args[2] & 0xffff) {
1193 tcg_out32 (s, ORI | RS (args[1]) | RA (args[0])
1194 | (args[2] & 0xffff));
1195 if (args[2] >> 16)
1196 tcg_out32 (s, ORIS | RS (args[0]) | RA (args[0])
1197 | ((args[2] >> 16) & 0xffff));
1198 }
1199 else {
1200 tcg_out32 (s, ORIS | RS (args[1]) | RA (args[0])
1201 | ((args[2] >> 16) & 0xffff));
1202 }
1203 }
1204 else
1205 tcg_out32 (s, OR | SAB (args[1], args[0], args[2]));
1206 break;
1207 case INDEX_op_xor_i64:
1208 case INDEX_op_xor_i32:
1209 if (const_args[2]) {
1210 if ((args[2] & 0xffff) == args[2])
1211 tcg_out32 (s, XORI | RS (args[1]) | RA (args[0])
1212 | (args[2] & 0xffff));
1213 else if ((args[2] & 0xffff0000) == args[2])
1214 tcg_out32 (s, XORIS | RS (args[1]) | RA (args[0])
1215 | ((args[2] >> 16) & 0xffff));
1216 else {
1217 tcg_out_movi (s, (opc == INDEX_op_and_i32
1218 ? TCG_TYPE_I32
1219 : TCG_TYPE_I64),
1220 0, args[2]);
1221 tcg_out32 (s, XOR | SAB (args[1], args[0], 0));
1222 }
1223 }
1224 else
1225 tcg_out32 (s, XOR | SAB (args[1], args[0], args[2]));
1226 break;
1227
1228 case INDEX_op_mul_i32:
1229 if (const_args[2]) {
1230 if (args[2] == (int16_t) args[2])
1231 tcg_out32 (s, MULLI | RT (args[0]) | RA (args[1])
1232 | (args[2] & 0xffff));
1233 else {
1234 tcg_out_movi (s, TCG_TYPE_I32, 0, args[2]);
1235 tcg_out32 (s, MULLW | TAB (args[0], args[1], 0));
1236 }
1237 }
1238 else
1239 tcg_out32 (s, MULLW | TAB (args[0], args[1], args[2]));
1240 break;
1241
1242 case INDEX_op_div_i32:
1243 tcg_out32 (s, DIVW | TAB (args[0], args[1], args[2]));
1244 break;
1245
1246 case INDEX_op_divu_i32:
1247 tcg_out32 (s, DIVWU | TAB (args[0], args[1], args[2]));
1248 break;
1249
1250 case INDEX_op_rem_i32:
1251 tcg_out32 (s, DIVW | TAB (0, args[1], args[2]));
1252 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1253 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1254 break;
1255
1256 case INDEX_op_remu_i32:
1257 tcg_out32 (s, DIVWU | TAB (0, args[1], args[2]));
1258 tcg_out32 (s, MULLW | TAB (0, 0, args[2]));
1259 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1260 break;
1261
1262 case INDEX_op_shl_i32:
1263 if (const_args[2]) {
1264 tcg_out32 (s, (RLWINM
1265 | RA (args[0])
1266 | RS (args[1])
1267 | SH (args[2])
1268 | MB (0)
1269 | ME (31 - args[2])
1270 )
1271 );
1272 }
1273 else
1274 tcg_out32 (s, SLW | SAB (args[1], args[0], args[2]));
1275 break;
1276 case INDEX_op_shr_i32:
1277 if (const_args[2]) {
1278 tcg_out32 (s, (RLWINM
1279 | RA (args[0])
1280 | RS (args[1])
1281 | SH (32 - args[2])
1282 | MB (args[2])
1283 | ME (31)
1284 )
1285 );
1286 }
1287 else
1288 tcg_out32 (s, SRW | SAB (args[1], args[0], args[2]));
1289 break;
1290 case INDEX_op_sar_i32:
1291 if (const_args[2])
1292 tcg_out32 (s, SRAWI | RS (args[1]) | RA (args[0]) | SH (args[2]));
1293 else
1294 tcg_out32 (s, SRAW | SAB (args[1], args[0], args[2]));
1295 break;
1296
1297 case INDEX_op_brcond_i32:
1298 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 0);
1299 break;
1300
1301 case INDEX_op_brcond_i64:
1302 tcg_out_brcond (s, args[2], args[0], args[1], const_args[1], args[3], 1);
1303 break;
1304
1305 case INDEX_op_neg_i32:
1306 case INDEX_op_neg_i64:
1307 tcg_out32 (s, NEG | RT (args[0]) | RA (args[1]));
1308 break;
1309
1310 case INDEX_op_add_i64:
1311 if (const_args[2])
1312 ppc_addi64 (s, args[0], args[1], args[2]);
1313 else
1314 tcg_out32 (s, ADD | TAB (args[0], args[1], args[2]));
1315 break;
1316 case INDEX_op_sub_i64:
1317 if (const_args[2])
1318 ppc_addi64 (s, args[0], args[1], -args[2]);
1319 else
1320 tcg_out32 (s, SUBF | TAB (args[0], args[2], args[1]));
1321 break;
1322
1323 case INDEX_op_shl_i64:
1324 if (const_args[2])
1325 tcg_out_rld (s, RLDICR, args[0], args[1], args[2], 63 - args[2]);
1326 else
1327 tcg_out32 (s, SLD | SAB (args[1], args[0], args[2]));
1328 break;
1329 case INDEX_op_shr_i64:
1330 if (const_args[2])
1331 tcg_out_rld (s, RLDICL, args[0], args[1], 64 - args[2], args[2]);
1332 else
1333 tcg_out32 (s, SRD | SAB (args[1], args[0], args[2]));
1334 break;
1335 case INDEX_op_sar_i64:
1336 if (const_args[2]) {
1337 int sh = SH (args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1338 tcg_out32 (s, SRADI | RA (args[0]) | RS (args[1]) | sh);
1339 }
1340 else
1341 tcg_out32 (s, SRAD | SAB (args[1], args[0], args[2]));
1342 break;
1343
1344 case INDEX_op_mul_i64:
1345 tcg_out32 (s, MULLD | TAB (args[0], args[1], args[2]));
1346 break;
1347 case INDEX_op_div_i64:
1348 tcg_out32 (s, DIVD | TAB (args[0], args[1], args[2]));
1349 break;
1350 case INDEX_op_divu_i64:
1351 tcg_out32 (s, DIVDU | TAB (args[0], args[1], args[2]));
1352 break;
1353 case INDEX_op_rem_i64:
1354 tcg_out32 (s, DIVD | TAB (0, args[1], args[2]));
1355 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1356 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1357 break;
1358 case INDEX_op_remu_i64:
1359 tcg_out32 (s, DIVDU | TAB (0, args[1], args[2]));
1360 tcg_out32 (s, MULLD | TAB (0, 0, args[2]));
1361 tcg_out32 (s, SUBF | TAB (args[0], 0, args[1]));
1362 break;
1363
1364 case INDEX_op_qemu_ld8u:
1365 tcg_out_qemu_ld (s, args, 0);
1366 break;
1367 case INDEX_op_qemu_ld8s:
1368 tcg_out_qemu_ld (s, args, 0 | 4);
1369 break;
1370 case INDEX_op_qemu_ld16u:
1371 tcg_out_qemu_ld (s, args, 1);
1372 break;
1373 case INDEX_op_qemu_ld16s:
1374 tcg_out_qemu_ld (s, args, 1 | 4);
1375 break;
1376 case INDEX_op_qemu_ld32u:
1377 tcg_out_qemu_ld (s, args, 2);
1378 break;
1379 case INDEX_op_qemu_ld32s:
1380 tcg_out_qemu_ld (s, args, 2 | 4);
1381 break;
1382 case INDEX_op_qemu_ld64:
1383 tcg_out_qemu_ld (s, args, 3);
1384 break;
1385 case INDEX_op_qemu_st8:
1386 tcg_out_qemu_st (s, args, 0);
1387 break;
1388 case INDEX_op_qemu_st16:
1389 tcg_out_qemu_st (s, args, 1);
1390 break;
1391 case INDEX_op_qemu_st32:
1392 tcg_out_qemu_st (s, args, 2);
1393 break;
1394 case INDEX_op_qemu_st64:
1395 tcg_out_qemu_st (s, args, 3);
1396 break;
1397
1398 case INDEX_op_ext8s_i32:
1399 case INDEX_op_ext8s_i64:
1400 c = EXTSB;
1401 goto gen_ext;
1402 case INDEX_op_ext16s_i32:
1403 case INDEX_op_ext16s_i64:
1404 c = EXTSH;
1405 goto gen_ext;
1406 case INDEX_op_ext32s_i64:
1407 c = EXTSW;
1408 goto gen_ext;
1409 gen_ext:
1410 tcg_out32 (s, c | RS (args[1]) | RA (args[0]));
1411 break;
1412
1413 default:
1414 tcg_dump_ops (s, stderr);
1415 tcg_abort ();
1416 }
1417 }
1418
1419 static const TCGTargetOpDef ppc_op_defs[] = {
1420 { INDEX_op_exit_tb, { } },
1421 { INDEX_op_goto_tb, { } },
1422 { INDEX_op_call, { "ri" } },
1423 { INDEX_op_jmp, { "ri" } },
1424 { INDEX_op_br, { } },
1425
1426 { INDEX_op_mov_i32, { "r", "r" } },
1427 { INDEX_op_mov_i64, { "r", "r" } },
1428 { INDEX_op_movi_i32, { "r" } },
1429 { INDEX_op_movi_i64, { "r" } },
1430
1431 { INDEX_op_ld8u_i32, { "r", "r" } },
1432 { INDEX_op_ld8s_i32, { "r", "r" } },
1433 { INDEX_op_ld16u_i32, { "r", "r" } },
1434 { INDEX_op_ld16s_i32, { "r", "r" } },
1435 { INDEX_op_ld_i32, { "r", "r" } },
1436 { INDEX_op_ld_i64, { "r", "r" } },
1437 { INDEX_op_st8_i32, { "r", "r" } },
1438 { INDEX_op_st8_i64, { "r", "r" } },
1439 { INDEX_op_st16_i32, { "r", "r" } },
1440 { INDEX_op_st16_i64, { "r", "r" } },
1441 { INDEX_op_st_i32, { "r", "r" } },
1442 { INDEX_op_st_i64, { "r", "r" } },
1443 { INDEX_op_st32_i64, { "r", "r" } },
1444
1445 { INDEX_op_ld8u_i64, { "r", "r" } },
1446 { INDEX_op_ld8s_i64, { "r", "r" } },
1447 { INDEX_op_ld16u_i64, { "r", "r" } },
1448 { INDEX_op_ld16s_i64, { "r", "r" } },
1449 { INDEX_op_ld32u_i64, { "r", "r" } },
1450 { INDEX_op_ld32s_i64, { "r", "r" } },
1451 { INDEX_op_ld_i64, { "r", "r" } },
1452
1453 { INDEX_op_add_i32, { "r", "r", "ri" } },
1454 { INDEX_op_mul_i32, { "r", "r", "ri" } },
1455 { INDEX_op_div_i32, { "r", "r", "r" } },
1456 { INDEX_op_divu_i32, { "r", "r", "r" } },
1457 { INDEX_op_rem_i32, { "r", "r", "r" } },
1458 { INDEX_op_remu_i32, { "r", "r", "r" } },
1459 { INDEX_op_sub_i32, { "r", "r", "ri" } },
1460 { INDEX_op_and_i32, { "r", "r", "ri" } },
1461 { INDEX_op_or_i32, { "r", "r", "ri" } },
1462 { INDEX_op_xor_i32, { "r", "r", "ri" } },
1463
1464 { INDEX_op_shl_i32, { "r", "r", "ri" } },
1465 { INDEX_op_shr_i32, { "r", "r", "ri" } },
1466 { INDEX_op_sar_i32, { "r", "r", "ri" } },
1467
1468 { INDEX_op_brcond_i32, { "r", "ri" } },
1469 { INDEX_op_brcond_i64, { "r", "ri" } },
1470
1471 { INDEX_op_neg_i32, { "r", "r" } },
1472
1473 { INDEX_op_add_i64, { "r", "r", "ri" } },
1474 { INDEX_op_sub_i64, { "r", "r", "ri" } },
1475 { INDEX_op_and_i64, { "r", "r", "rZ" } },
1476 { INDEX_op_or_i64, { "r", "r", "rZ" } },
1477 { INDEX_op_xor_i64, { "r", "r", "rZ" } },
1478
1479 { INDEX_op_shl_i64, { "r", "r", "ri" } },
1480 { INDEX_op_shr_i64, { "r", "r", "ri" } },
1481 { INDEX_op_sar_i64, { "r", "r", "ri" } },
1482
1483 { INDEX_op_mul_i64, { "r", "r", "r" } },
1484 { INDEX_op_div_i64, { "r", "r", "r" } },
1485 { INDEX_op_divu_i64, { "r", "r", "r" } },
1486 { INDEX_op_rem_i64, { "r", "r", "r" } },
1487 { INDEX_op_remu_i64, { "r", "r", "r" } },
1488
1489 { INDEX_op_neg_i64, { "r", "r" } },
1490
1491 { INDEX_op_qemu_ld8u, { "r", "L" } },
1492 { INDEX_op_qemu_ld8s, { "r", "L" } },
1493 { INDEX_op_qemu_ld16u, { "r", "L" } },
1494 { INDEX_op_qemu_ld16s, { "r", "L" } },
1495 { INDEX_op_qemu_ld32u, { "r", "L" } },
1496 { INDEX_op_qemu_ld32s, { "r", "L" } },
1497 { INDEX_op_qemu_ld64, { "r", "L" } },
1498
1499 { INDEX_op_qemu_st8, { "S", "S" } },
1500 { INDEX_op_qemu_st16, { "S", "S" } },
1501 { INDEX_op_qemu_st32, { "S", "S" } },
1502 { INDEX_op_qemu_st64, { "S", "S", "S" } },
1503
1504 { INDEX_op_ext8s_i32, { "r", "r" } },
1505 { INDEX_op_ext16s_i32, { "r", "r" } },
1506 { INDEX_op_ext8s_i64, { "r", "r" } },
1507 { INDEX_op_ext16s_i64, { "r", "r" } },
1508 { INDEX_op_ext32s_i64, { "r", "r" } },
1509
1510 { -1 },
1511 };
1512
1513 void tcg_target_init (TCGContext *s)
1514 {
1515 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
1516 tcg_regset_set32 (tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
1517 tcg_regset_set32 (tcg_target_call_clobber_regs, 0,
1518 (1 << TCG_REG_R0) |
1519 (1 << TCG_REG_R3) |
1520 (1 << TCG_REG_R4) |
1521 (1 << TCG_REG_R5) |
1522 (1 << TCG_REG_R6) |
1523 (1 << TCG_REG_R7) |
1524 (1 << TCG_REG_R8) |
1525 (1 << TCG_REG_R9) |
1526 (1 << TCG_REG_R10) |
1527 (1 << TCG_REG_R11) |
1528 (1 << TCG_REG_R12)
1529 );
1530
1531 tcg_regset_clear (s->reserved_regs);
1532 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R0);
1533 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R1);
1534 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R2);
1535 tcg_regset_set_reg (s->reserved_regs, TCG_REG_R13);
1536
1537 #ifdef CONFIG_USE_GUEST_BASE
1538 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1539 #endif
1540
1541 tcg_add_target_add_op_defs (ppc_op_defs);
1542 }
QEmu