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target-unicore32: Use cpu_exec_interrupt qom hook
[qemu.git] / target-tricore / tricore-opcodes.h
blob9c6ec013ac10d6cc4b97ee3f859eaec560441584
1 /*
2 * Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
3 *
4 * This library is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU Lesser General Public
6 * License as published by the Free Software Foundation; either
7 * version 2 of the License, or (at your option) any later version.
8 *
9 * This library is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * Lesser General Public License for more details.
13 *
14 * You should have received a copy of the GNU Lesser General Public
15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
16 */
17
18 /*
19 * Opcode Masks for Tricore
20 * Format MASK_OP_InstrFormatName_Field
21 */
22
23 /* This creates a mask with bits start .. end set to 1 and applies it to op */
24 #define MASK_BITS_SHIFT(op, start, end) (extract32(op, (start), \
25 (end) - (start) + 1))
26 #define MASK_BITS_SHIFT_SEXT(op, start, end) (sextract32(op, (start),\
27 (end) - (start) + 1))
28
29 /* new opcode masks */
30
31 #define MASK_OP_MAJOR(op) MASK_BITS_SHIFT(op, 0, 7)
32
33 /* 16-Bit Formats */
34 #define MASK_OP_SB_DISP8(op) MASK_BITS_SHIFT(op, 8, 15)
35 #define MASK_OP_SB_DISP8_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 8, 15)
36
37 #define MASK_OP_SBC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
38 #define MASK_OP_SBC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
39 #define MASK_OP_SBC_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
40
41 #define MASK_OP_SBR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
42 #define MASK_OP_SBR_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
43
44 #define MASK_OP_SBRN_N(op) MASK_BITS_SHIFT(op, 12, 15)
45 #define MASK_OP_SBRN_DISP4(op) MASK_BITS_SHIFT(op, 8, 11)
46
47 #define MASK_OP_SC_CONST8(op) MASK_BITS_SHIFT(op, 8, 15)
48
49 #define MASK_OP_SLR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
50 #define MASK_OP_SLR_D(op) MASK_BITS_SHIFT(op, 8, 11)
51
52 #define MASK_OP_SLRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
53 #define MASK_OP_SLRO_D(op) MASK_BITS_SHIFT(op, 8, 11)
54
55 #define MASK_OP_SR_OP2(op) MASK_BITS_SHIFT(op, 12, 15)
56 #define MASK_OP_SR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
57
58 #define MASK_OP_SRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
59 #define MASK_OP_SRC_CONST4_SEXT(op) MASK_BITS_SHIFT_SEXT(op, 12, 15)
60 #define MASK_OP_SRC_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
61
62 #define MASK_OP_SRO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
63 #define MASK_OP_SRO_OFF4(op) MASK_BITS_SHIFT(op, 8, 11)
64
65 #define MASK_OP_SRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
66 #define MASK_OP_SRR_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
67
68 #define MASK_OP_SRRS_S2(op) MASK_BITS_SHIFT(op, 12, 15)
69 #define MASK_OP_SRRS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
70 #define MASK_OP_SRRS_N(op) MASK_BITS_SHIFT(op, 6, 7)
71
72 #define MASK_OP_SSR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
73 #define MASK_OP_SSR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
74
75 #define MASK_OP_SSRO_OFF4(op) MASK_BITS_SHIFT(op, 12, 15)
76 #define MASK_OP_SSRO_S1(op) MASK_BITS_SHIFT(op, 8, 11)
77
78 /* 32-Bit Formats */
79
80 /* ABS Format */
81 #define MASK_OP_ABS_OFF18(op) (MASK_BITS_SHIFT(op, 16, 21) + \
82 (MASK_BITS_SHIFT(op, 28, 31) << 6) + \
83 (MASK_BITS_SHIFT(op, 22, 25) << 10) +\
84 (MASK_BITS_SHIFT(op, 12, 15) << 14))
85 #define MASK_OP_ABS_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
86 #define MASK_OP_ABS_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
87
88 /* ABSB Format */
89 #define MASK_OP_ABSB_OFF18(op) MASK_OP_ABS_OFF18(op)
90 #define MASK_OP_ABSB_OP2(op) MASK_BITS_SHIFT(op, 26, 27)
91 #define MASK_OP_ABSB_B(op) MASK_BITS_SHIFT(op, 11, 11)
92 #define MASK_OP_ABSB_BPOS(op) MASK_BITS_SHIFT(op, 7, 10)
93
94 /* B Format */
95 #define MASK_OP_B_DISP24(op) (MASK_BITS_SHIFT(op, 16, 31) + \
96 (MASK_BITS_SHIFT(op, 8, 15) << 16))
97 /* BIT Format */
98 #define MASK_OP_BIT_D(op) MASK_BITS_SHIFT(op, 28, 31)
99 #define MASK_OP_BIT_POS2(op) MASK_BITS_SHIFT(op, 23, 27)
100 #define MASK_OP_BIT_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
101 #define MASK_OP_BIT_POS1(op) MASK_BITS_SHIFT(op, 16, 20)
102 #define MASK_OP_BIT_S2(op) MASK_BITS_SHIFT(op, 12, 15)
103 #define MASK_OP_BIT_S1(op) MASK_BITS_SHIFT(op, 8, 11)
104
105 /* BO Format */
106 #define MASK_OP_BO_OFF10(op) (MASK_BITS_SHIFT(op, 16, 21) + \
107 (MASK_BITS_SHIFT(op, 28, 31) << 6))
108 #define MASK_OP_BO_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
109 #define MASK_OP_BO_S2(op) MASK_BITS_SHIFT(op, 12, 15)
110 #define MASK_OP_BO_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
111
112 /* BOL Format */
113 #define MASK_OP_BOL_OFF16(op) ((MASK_BITS_SHIFT(op, 16, 21) + \
114 (MASK_BITS_SHIFT(op, 28, 31) << 6)) + \
115 (MASK_BITS_SHIFT(op, 22, 27) >> 10))
116
117 #define MASK_OP_BOL_S2(op) MASK_BITS_SHIFT(op, 12, 15)
118 #define MASK_OP_BOL_S1D(op) MASK_BITS_SHIFT(op, 8, 11)
119
120 /* BRC Format */
121 #define MASK_OP_BRC_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
122 #define MASK_OP_BRC_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
123 #define MASK_OP_BRC_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
124 #define MASK_OP_BRC_S1(op) MASK_BITS_SHIFT(op, 8, 11)
125
126 /* BRN Format */
127 #define MASK_OP_BRN_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
128 #define MASK_OP_BRN_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
129 #define MASK_OP_BRN_N(op) (MASK_BITS_SHIFT(op, 12, 15) + \
130 (MASK_BITS_SHIFT(op, 7, 7) << 4))
131 #define MASK_OP_BRN_S1(op) MASK_BITS_SHIFT(op, 8, 11)
132 /* BRR Format */
133 #define MASK_OP_BRR_OP2(op) MASK_BITS_SHIFT(op, 31, 31)
134 #define MASK_OP_BRR_DISP15(op) MASK_BITS_SHIFT(op, 16, 30)
135 #define MASK_OP_BRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
136 #define MASK_OP_BRR_S1(op) MASK_BITS_SHIFT(op, 8, 11)
137
138 /* META MASK for similar instr Formats */
139 #define MASK_OP_META_D(op) MASK_BITS_SHIFT(op, 28, 31)
140 #define MASK_OP_META_S1(op) MASK_BITS_SHIFT(op, 8, 11)
141
142 /* RC Format */
143 #define MASK_OP_RC_D(op) MASK_OP_META_D(op)
144 #define MASK_OP_RC_OP2(op) MASK_BITS_SHIFT(op, 21, 27)
145 #define MASK_OP_RC_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
146 #define MASK_OP_RC_S1(op) MASK_OP_META_S1(op)
147
148 /* RCPW Format */
149
150 #define MASK_OP_RCPW_D(op) MASK_OP_META_D(op)
151 #define MASK_OP_RCPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
152 #define MASK_OP_RCPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
153 #define MASK_OP_RCPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
154 #define MASK_OP_RCPW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
155 #define MASK_OP_RCPW_S1(op) MASK_OP_META_S1(op)
156
157 /* RCR Format */
158
159 #define MASK_OP_RCR_D(op) MASK_OP_META_D(op)
160 #define MASK_OP_RCR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
161 #define MASK_OP_RCR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
162 #define MASK_OP_RCR_CONST9(op) MASK_BITS_SHIFT(op, 12, 20)
163 #define MASK_OP_RCR_S1(op) MASK_OP_META_S1(op)
164
165 /* RCRR Format */
166
167 #define MASK_OP_RCRR_D(op) MASK_OP_META_D(op)
168 #define MASK_OP_RCRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
169 #define MASK_OP_RCRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
170 #define MASK_OP_RCRR_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
171 #define MASK_OP_RCRR_S1(op) MASK_OP_META_S1(op)
172
173 /* RCRW Format */
174
175 #define MASK_OP_RCRW_D(op) MASK_OP_META_D(op)
176 #define MASK_OP_RCRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
177 #define MASK_OP_RCRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
178 #define MASK_OP_RCRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
179 #define MASK_OP_RCRW_CONST4(op) MASK_BITS_SHIFT(op, 12, 15)
180 #define MASK_OP_RCRW_S1(op) MASK_OP_META_S1(op)
181
182 /* RLC Format */
183
184 #define MASK_OP_RLC_D(op) MASK_OP_META_D(op)
185 #define MASK_OP_RLC_CONST16(op) MASK_BITS_SHIFT(op, 12, 27)
186 #define MASK_OP_RLC_S1(op) MASK_OP_META_S1(op)
187
188 /* RR Format */
189 #define MASK_OP_RR_D(op) MASK_OP_META_D(op)
190 #define MASK_OP_RR_OP2(op) MASK_BITS_SHIFT(op, 20, 27)
191 #define MASK_OP_RR_N(op) MASK_BITS_SHIFT(op, 16, 17)
192 #define MASK_OP_RR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
193 #define MASK_OP_RR_S1(op) MASK_OP_META_S1(op)
194
195 /* RR1 Format */
196 #define MASK_OP_RR1_D(op) MASK_OP_META_D(op)
197 #define MASK_OP_RR1_OP2(op) MASK_BITS_SHIFT(op, 18, 27)
198 #define MASK_OP_RR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
199 #define MASK_OP_RR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
200 #define MASK_OP_RR1_S1(op) MASK_OP_META_S1(op)
201
202 /* RR2 Format */
203 #define MASK_OP_RR2_D(op) MASK_OP_META_D(op)
204 #define MASK_OP_RR2_OP2(op) MASK_BITS_SHIFT(op, 16, 27)
205 #define MASK_OP_RR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
206 #define MASK_OP_RR2_S1(op) MASK_OP_META_S1(op)
207
208 /* RRPW Format */
209 #define MASK_OP_RRPW_D(op) MASK_OP_META_D(op)
210 #define MASK_OP_RRPW_POS(op) MASK_BITS_SHIFT(op, 23, 27)
211 #define MASK_OP_RRPW_OP2(op) MASK_BITS_SHIFT(op, 21, 22)
212 #define MASK_OP_RRPW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
213 #define MASK_OP_RRPW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
214 #define MASK_OP_RRPW_S1(op) MASK_OP_META_S1(op)
215
216 /* RRR Format */
217 #define MASK_OP_RRR_D(op) MASK_OP_META_D(op)
218 #define MASK_OP_RRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
219 #define MASK_OP_RRR_OP2(op) MASK_BITS_SHIFT(op, 20, 23)
220 #define MASK_OP_RRR_N(op) MASK_BITS_SHIFT(op, 16, 17)
221 #define MASK_OP_RRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
222 #define MASK_OP_RRR_S1(op) MASK_OP_META_S1(op)
223
224 /* RRR1 Format */
225 #define MASK_OP_RRR1_D(op) MASK_OP_META_D(op)
226 #define MASK_OP_RRR1_S3(op) MASK_BITS_SHIFT(op, 24, 27)
227 #define MASK_OP_RRR1_OP2(op) MASK_BITS_SHIFT(op, 18, 23)
228 #define MASK_OP_RRR1_N(op) MASK_BITS_SHIFT(op, 16, 17)
229 #define MASK_OP_RRR1_S2(op) MASK_BITS_SHIFT(op, 12, 15)
230 #define MASK_OP_RRR1_S1(op) MASK_OP_META_S1(op)
231
232 /* RRR2 Format */
233 #define MASK_OP_RRR2_D(op) MASK_OP_META_D(op)
234 #define MASK_OP_RRR2_S3(op) MASK_BITS_SHIFT(op, 24, 27)
235 #define MASK_OP_RRR2_OP2(op) MASK_BITS_SHIFT(op, 16, 23)
236 #define MASK_OP_RRR2_S2(op) MASK_BITS_SHIFT(op, 12, 15)
237 #define MASK_OP_RRR2_S1(op) MASK_OP_META_S1(op)
238
239 /* RRRR Format */
240 #define MASK_OP_RRRR_D(op) MASK_OP_META_D(op)
241 #define MASK_OP_RRRR_S3(op) MASK_BITS_SHIFT(op, 24, 27)
242 #define MASK_OP_RRRR_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
243 #define MASK_OP_RRRR_S2(op) MASK_BITS_SHIFT(op, 12, 15)
244 #define MASK_OP_RRRR_S1(op) MASK_OP_META_S1(op)
245
246 /* RRRW Format */
247 #define MASK_OP_RRRW_D(op) MASK_OP_META_D(op)
248 #define MASK_OP_RRRW_S3(op) MASK_BITS_SHIFT(op, 24, 27)
249 #define MASK_OP_RRRW_OP2(op) MASK_BITS_SHIFT(op, 21, 23)
250 #define MASK_OP_RRRW_WIDTH(op) MASK_BITS_SHIFT(op, 16, 20)
251 #define MASK_OP_RRRW_S2(op) MASK_BITS_SHIFT(op, 12, 15)
252 #define MASK_OP_RRRW_S1(op) MASK_OP_META_S1(op)
253
254 /* SYS Format */
255 #define MASK_OP_SYS_OP2(op) MASK_BITS_SHIFT(op, 22, 27)
256 #define MASK_OP_SYS_S1D(op) MASK_OP_META_S1(op)
257
258
259
260 /*
261 * Tricore Opcodes Enums
262 *
263 * Format: OPC(1|2|M)_InstrLen_Name
264 * OPC1 = only op1 field is used
265 * OPC2 = op1 and op2 field used part of OPCM
266 * OPCM = op1 field used to group Instr
267 * InstrLen = 16|32
268 * Name = Name of Instr
269 */
270
271 /* 16-Bit */
272 enum {
273
274 OPCM_16_SR_SYSTEM = 0x00,
275 OPCM_16_SR_ACCU = 0x32,
276
277 OPC1_16_SRC_ADD = 0xc2,
278 OPC1_16_SRC_ADD_A15 = 0x92,
279 OPC1_16_SRC_ADD_15A = 0x9a,
280 OPC1_16_SRR_ADD = 0x42,
281 OPC1_16_SRR_ADD_A15 = 0x12,
282 OPC1_16_SRR_ADD_15A = 0x1a,
283 OPC1_16_SRC_ADD_A = 0xb0,
284 OPC1_16_SRR_ADD_A = 0x30,
285 OPC1_16_SRR_ADDS = 0x22,
286 OPC1_16_SRRS_ADDSC_A = 0x10,
287 OPC1_16_SC_AND = 0x16,
288 OPC1_16_SRR_AND = 0x26,
289 OPC1_16_SC_BISR = 0xe0,
290 OPC1_16_SRC_CADD = 0x8a,
291 OPC1_16_SRC_CADDN = 0xca,
292 OPC1_16_SB_CALL = 0x5c,
293 OPC1_16_SRC_CMOV = 0xaa,
294 OPC1_16_SRR_CMOV = 0x2a,
295 OPC1_16_SRC_CMOVN = 0xea,
296 OPC1_16_SRR_CMOVN = 0x6a,
297 OPC1_16_SRC_EQ = 0xba,
298 OPC1_16_SRR_EQ = 0x3a,
299 OPC1_16_SB_J = 0x3c,
300 OPC1_16_SBC_JEQ = 0x1e,
301 OPC1_16_SBR_JEQ = 0x3e,
302 OPC1_16_SBR_JGEZ = 0xce,
303 OPC1_16_SBR_JGTZ = 0x4e,
304 OPC1_16_SR_JI = 0xdc,
305 OPC1_16_SBR_JLEZ = 0x8e,
306 OPC1_16_SBR_JLTZ = 0x0e,
307 OPC1_16_SBC_JNE = 0x5e,
308 OPC1_16_SBR_JNE = 0x7e,
309 OPC1_16_SB_JNZ = 0xee,
310 OPC1_16_SBR_JNZ = 0xf6,
311 OPC1_16_SBR_JNZ_A = 0x7c,
312 OPC1_16_SBRN_JNZ_T = 0xae,
313 OPC1_16_SB_JZ = 0x6e,
314 OPC1_16_SBR_JZ = 0x76,
315 OPC1_16_SBR_JZ_A = 0xbc,
316 OPC1_16_SBRN_JZ_T = 0x2e,
317 OPC1_16_SC_LD_A = 0xd8,
318 OPC1_16_SLR_LD_A = 0xd4,
319 OPC1_16_SLR_LD_A_POSTINC = 0xc4,
320 OPC1_16_SLRO_LD_A = 0xc8,
321 OPC1_16_SRO_LD_A = 0xcc,
322 OPC1_16_SLR_LD_BU = 0x14,
323 OPC1_16_SLR_LD_BU_POSTINC = 0x04,
324 OPC1_16_SLRO_LD_BU = 0x08,
325 OPC1_16_SRO_LD_BU = 0x0c,
326 OPC1_16_SLR_LD_H = 0x94,
327 OPC1_16_SLR_LD_H_POSTINC = 0x84,
328 OPC1_16_SLRO_LD_H = 0x88,
329 OPC1_16_SRO_LD_H = 0x8c,
330 OPC1_16_SC_LD_W = 0x58,
331 OPC1_16_SLR_LD_W = 0x54,
332 OPC1_16_SLR_LD_W_POSTINC = 0x44,
333 OPC1_16_SLRO_LD_W = 0x48,
334 OPC1_16_SRO_LD_W = 0x4c,
335 OPC1_16_SBR_LOOP = 0xfc,
336 OPC1_16_SRC_LT = 0xfa,
337 OPC1_16_SRR_LT = 0x7a,
338 OPC1_16_SC_MOV = 0xda,
339 OPC1_16_SRC_MOV = 0x82,
340 OPC1_16_SRR_MOV = 0x02,
341 OPC1_16_SRC_MOV_E = 0xd2,/* 1.6 only */
342 OPC1_16_SRC_MOV_A = 0xa0,
343 OPC1_16_SRR_MOV_A = 0x60,
344 OPC1_16_SRR_MOV_AA = 0x40,
345 OPC1_16_SRR_MOV_D = 0x80,
346 OPC1_16_SRR_MUL = 0xe2,
347 OPC1_16_SR_NOT = 0x46,
348 OPC1_16_SC_OR = 0x96,
349 OPC1_16_SRR_OR = 0xa6,
350 OPC1_16_SRC_SH = 0x06,
351 OPC1_16_SRC_SHA = 0x86,
352 OPC1_16_SC_ST_A = 0xf8,
353 OPC1_16_SRO_ST_A = 0xec,
354 OPC1_16_SSR_ST_A = 0xf4,
355 OPC1_16_SSR_ST_A_POSTINC = 0xe4,
356 OPC1_16_SSRO_ST_A = 0xe8,
357 OPC1_16_SRO_ST_B = 0x2c,
358 OPC1_16_SSR_ST_B = 0x34,
359 OPC1_16_SSR_ST_B_POSTINC = 0x24,
360 OPC1_16_SSRO_ST_B = 0x28,
361 OPC1_16_SRO_ST_H = 0xac,
362 OPC1_16_SSR_ST_H = 0xb4,
363 OPC1_16_SSR_ST_H_POSTINC = 0xa4,
364 OPC1_16_SSRO_ST_H = 0xa8,
365 OPC1_16_SC_ST_W = 0x78,
366 OPC1_16_SRO_ST_W = 0x6c,
367 OPC1_16_SSR_ST_W = 0x74,
368 OPC1_16_SSR_ST_W_POSTINC = 0x64,
369 OPC1_16_SSRO_ST_W = 0x68,
370 OPC1_16_SRR_SUB = 0xa2,
371 OPC1_16_SRR_SUB_A15B = 0x52,
372 OPC1_16_SRR_SUB_15AB = 0x5a,
373 OPC1_16_SC_SUB_A = 0x20,
374 OPC1_16_SRR_SUBS = 0x62,
375 OPC1_16_SRR_XOR = 0xc6,
376
377 };
378
379 /*
380 * SR Format
381 */
382 /* OPCM_16_SR_SYSTEM */
383 enum {
384
385 OPC2_16_SR_NOP = 0x00,
386 OPC2_16_SR_RET = 0x09,
387 OPC2_16_SR_RFE = 0x08,
388 OPC2_16_SR_DEBUG = 0x0a,
389 };
390 /* OPCM_16_SR_ACCU */
391 enum {
392 OPC2_16_SR_RSUB = 0x05,
393 OPC2_16_SR_SAT_B = 0x00,
394 OPC2_16_SR_SAT_BU = 0x01,
395 OPC2_16_SR_SAT_H = 0x02,
396 OPC2_16_SR_SAT_HU = 0x03,
397
398 };
399
400 /* 32-Bit */
401
402 enum {
403 /* ABS Format 1, M */
404 OPCM_32_ABS_LDW = 0x85,
405 OPCM_32_ABS_LDB = 0x05,
406 OPCM_32_ABS_LDMST_SWAP = 0xe5,
407 OPCM_32_ABS_LDST_CONTEXT = 0x15,
408 OPCM_32_ABS_STORE = 0xa5,
409 OPCM_32_ABS_STOREB_H = 0x25,
410 OPC1_32_ABS_STOREQ = 0x65,
411 OPC1_32_ABS_LD_Q = 0x45,
412 OPC1_32_ABS_LEA = 0xc5,
413 /* ABSB Format */
414 OPC1_32_ABSB_ST_T = 0xd5,
415 /* B Format */
416 OPC1_32_B_CALL = 0x6d,
417 OPC1_32_B_CALLA = 0xed,
418 OPC1_32_B_J = 0x1d,
419 OPC1_32_B_JA = 0x9d,
420 OPC1_32_B_JL = 0x5d,
421 OPC1_32_B_JLA = 0xdd,
422 /* Bit Format */
423 OPCM_32_BIT_ANDACC = 0x47,
424 OPCM_32_BIT_LOGICAL_T1 = 0x87,
425 OPCM_32_BIT_INSERT = 0x67,
426 OPCM_32_BIT_LOGICAL_T2 = 0x07,
427 OPCM_32_BIT_ORAND = 0xc7,
428 OPCM_32_BIT_SH_LOGIC1 = 0x27,
429 OPCM_32_BIT_SH_LOGIC2 = 0xa7,
430 /* BO Format */
431 OPCM_32_BO_ADDRMODE_POST_PRE_BASE = 0x89,
432 OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR = 0xa9,
433 OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE = 0x09,
434 OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR = 0x29,
435 OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE = 0x49,
436 OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR = 0x69,
437 /* BOL Format */
438 OPC1_32_BOL_LD_A_LONGOFF = 0x99,
439 OPC1_32_BOL_LD_W_LONFOFF = 0x19,
440 OPC1_32_BOL_LEA_LONGOFF = 0xd9,
441 OPC1_32_BOL_ST_W_LONGOFF = 0x59,
442 OPC1_32_BOL_ST_A_LONGOFF = 0xb5, /* 1.6 only */
443 /* BRC Format */
444 OPCM_32_BRC_EQ_NEQ = 0xdf,
445 OPCM_32_BRC_GE = 0xff,
446 OPCM_32_BRC_JLT = 0xbf,
447 OPCM_32_BRC_JNE = 0x9f,
448 /* BRN Format */
449 OPCM_32_BRN_JTT = 0x6f,
450 /* BRR Format */
451 OPCM_32_BRR_EQ_NEQ = 0x5f,
452 OPCM_32_BRR_ADDR_EQ_NEQ = 0x7d,
453 OPCM_32_BRR_GE = 0x7f,
454 OPCM_32_BRR_JLT = 0x3f,
455 OPCM_32_BRR_JNE = 0x1f,
456 OPCM_32_BRR_JNZ = 0xbd,
457 OPCM_32_BRR_LOOP = 0xfd,
458 /* RC Format */
459 OPCM_32_RC_LOGICAL_SHIFT = 0x8f,
460 OPCM_32_RC_ACCUMULATOR = 0x8b,
461 OPCM_32_RC_SERVICEROUTINE = 0xad,
462 OPCM_32_RC_MUL = 0x53,
463 /* RCPW Format */
464 OPCM_32_RCPW_MASK_INSERT = 0xb7,
465 /* RCR Format */
466 OPCM_32_RCR_COND_SELECT = 0xab,
467 OPCM_32_RCR_MADD = 0x13,
468 OPCM_32_RCR_MSUB = 0x33,
469 /* RCRR Format */
470 OPC1_32_RCRR_INSERT = 0x97,
471 /* RCRW Format */
472 OPCM_32_RCRW_MASK_INSERT = 0xd7,
473 /* RLC Format */
474 OPC1_32_RLC_ADDI = 0x1b,
475 OPC1_32_RLC_ADDIH = 0x9b,
476 OPC1_32_RLC_ADDIH_A = 0x11,
477 OPC1_32_RLC_MFCR = 0x4d,
478 OPC1_32_RLC_MOV = 0x3b,
479 OPC1_32_RLC_MOV_U = 0xbb,
480 OPC1_32_RLC_MOV_H = 0x7b,
481 OPC1_32_RLC_MOVH_A = 0x91,
482 OPC1_32_RLC_MTCR = 0xcd,
483 /* RR Format */
484 OPCM_32_RR_LOGICAL_SHIFT = 0x0f,
485 OPCM_32_RR_ACCUMULATOR = 0x0b,
486 OPCM_32_RR_ADRESS = 0x01,
487 OPCM_32_RR_FLOAT = 0x4b,
488 OPCM_32_RR_IDIRECT = 0x2d,
489 /* RR1 Format */
490 OPCM_32_RR1_MUL = 0xb3,
491 OPCM_32_RR1_MULQ = 0x93,
492 /* RR2 Format */
493 OPCM_32_RR2_MUL = 0x73,
494 /* RRPW Format */
495 OPCM_32_RRPW_EXTRACT_INSERT = 0x37,
496 OPC1_32_RRPW_DEXTR = 0x77,
497 /* RRR Format */
498 OPCM_32_RRR_COND_SELECT = 0x2b,
499 OPCM_32_RRR_FLOAT = 0x6b,
500 /* RRR1 Format */
501 OPCM_32_RRR1_MADD = 0x83,
502 OPCM_32_RRR1_MADDQ_H = 0x43,
503 OPCM_32_RRR1_MADDSU_H = 0xc3,
504 OPCM_32_RRR1_MSUB_H = 0xa3,
505 OPCM_32_RRR1_MSUB_Q = 0x63,
506 OPCM_32_RRR1_MSUBADS_H = 0xe3,
507 /* RRR2 Format */
508 OPCM_32_RRR2_MADD = 0x03,
509 OPCM_32_RRR2_MSUB = 0x23,
510 /* RRRR Format */
511 OPCM_32_RRRR_EXTRACT_INSERT = 0x17,
512 /* RRRW Format */
513 OPCM_32_RRRW_EXTRACT_INSERT = 0x57,
514 /* SYS Format */
515 OPCM_32_SYS_INTERRUPTS = 0x0d,
516 OPC1_32_SYS_RSTV = 0x2f,
517 };
518
519
520
521 /*
522 * ABS Format
523 */
524
525 /* OPCM_32_ABS_LDW */
526 enum {
527
528 OPC2_32_ABS_LD_A = 0x02,
529 OPC2_32_ABS_LD_D = 0x01,
530 OPC2_32_ABS_LD_DA = 0x03,
531 OPC2_32_ABS_LD_W = 0x00,
532 };
533
534 /* OPCM_32_ABS_LDB */
535 enum {
536 OPC2_32_ABS_LD_B = 0x00,
537 OPC2_32_ABS_LD_BU = 0x01,
538 OPC2_32_ABS_LD_H = 0x02,
539 OPC2_32_ABS_LD_HU = 0x03,
540 };
541 /* OPCM_32_ABS_LDMST_SWAP */
542 enum {
543 OPC2_32_ABS_LDMST = 0x01,
544 OPC2_32_ABS_SWAP_W = 0x00,
545 };
546 /* OPCM_32_ABS_LDST_CONTEXT */
547 enum {
548 OPC2_32_ABS_LDLCX = 0x02,
549 OPC2_32_ABS_LDUCX = 0x03,
550 OPC2_32_ABS_STLCX = 0x00,
551 OPC2_32_ABS_STUCX = 0x01,
552 };
553 /* OPCM_32_ABS_STORE */
554 enum {
555 OPC2_32_ABS_ST_A = 0x02,
556 OPC2_32_ABS_ST_D = 0x01,
557 OPC2_32_ABS_ST_DA = 0x03,
558 OPC2_32_ABS_ST_W = 0x00,
559 };
560 /* OPCM_32_ABS_STOREB_H */
561 enum {
562 OPC2_32_ABS_ST_B = 0x00,
563 OPC2_32_ABS_ST_H = 0x02,
564 };
565 /*
566 * Bit Format
567 */
568 /* OPCM_32_BIT_ANDACC */
569 enum {
570 OPC2_32_BIT_AND_AND_T = 0x00,
571 OPC2_32_BIT_AND_ANDN_T = 0x03,
572 OPC2_32_BIT_AND_NOR_T = 0x02,
573 OPC2_32_BIT_AND_OR_T = 0x01,
574 };
575 /* OPCM_32_BIT_LOGICAL_T */
576 enum {
577 OPC2_32_BIT_AND_T = 0x00,
578 OPC2_32_BIT_ANDN_T = 0x03,
579 OPC2_32_BIT_NOR_T = 0x02,
580 OPC2_32_BIT_OR_T = 0x01,
581 };
582 /* OPCM_32_BIT_INSERT */
583 enum {
584 OPC2_32_BIT_INS_T = 0x00,
585 OPC2_32_BIT_INSN_T = 0x01,
586 };
587 /* OPCM_32_BIT_LOGICAL_T2 */
588 enum {
589 OPC2_32_BIT_NAND_T = 0x00,
590 OPC2_32_BIT_ORN_T = 0x01,
591 OPC2_32_BIT_XNOR_T = 0x02,
592 OPC2_32_BIT_XOR_T = 0x03,
593 };
594 /* OPCM_32_BIT_ORAND */
595 enum {
596 OPC2_32_BIT_OR_AND_T = 0x00,
597 OPC2_32_BIT_OR_ANDN_T = 0x03,
598 OPC2_32_BIT_OR_NOR_T = 0x02,
599 OPC2_32_BIT_OR_OR_T = 0x01,
600 };
601 /*OPCM_32_BIT_SH_LOGIC1 */
602 enum {
603 OPC2_32_BIT_SH_AND_T = 0x00,
604 OPC2_32_BIT_SH_ANDN_T = 0x03,
605 OPC2_32_BIT_SH_NOR_T = 0x02,
606 OPC2_32_BIT_SH_OR_T = 0x01,
607 };
608 /* OPCM_32_BIT_SH_LOGIC2 */
609 enum {
610 OPC2_32_BIT_SH_NAND_T = 0x00,
611 OPC2_32_BIT_SH_ORN_T = 0x01,
612 OPC2_32_BIT_SH_XNOR_T = 0x02,
613 OPC2_32_BIT_SH_XOR_T = 0x03,
614 };
615 /*
616 * BO Format
617 */
618 /* OPCM_32_BO_ADDRMODE_POST_PRE_BASE */
619 enum {
620 OPC2_32_BO_CACHEA_I_SHORTOFF = 0x2e,
621 OPC2_32_BO_CACHEA_I_POSTINC = 0x0e,
622 OPC2_32_BO_CACHEA_I_PREINC = 0x1e,
623 OPC2_32_BO_CACHEA_W_SHORTOFF = 0x2c,
624 OPC2_32_BO_CACHEA_W_POSTINC = 0x0c,
625 OPC2_32_BO_CACHEA_W_PREINC = 0x1c,
626 OPC2_32_BO_CACHEA_WI_SHORTOFF = 0x2d,
627 OPC2_32_BO_CACHEA_WI_POSTINC = 0x0d,
628 OPC2_32_BO_CACHEA_WI_PREINC = 0x1d,
629 /* 1.3.1 only */
630 OPC2_32_BO_CACHEI_W_SHORTOFF = 0x2b,
631 OPC2_32_BO_CACHEI_W_POSTINC = 0x0b,
632 OPC2_32_BO_CACHEI_W_PREINC = 0x1b,
633 OPC2_32_BO_CACHEI_WI_SHORTOFF = 0x2f,
634 OPC2_32_BO_CACHEI_WI_POSTINC = 0x0f,
635 OPC2_32_BO_CACHEI_WI_PREINC = 0x1f,
636 /* end 1.3.1 only */
637 OPC2_32_BO_ST_A_SHORTOFF = 0x26,
638 OPC2_32_BO_ST_A_POSTINC = 0x06,
639 OPC2_32_BO_ST_A_PREINC = 0x16,
640 OPC2_32_BO_ST_B_SHORTOFF = 0x20,
641 OPC2_32_BO_ST_B_POSTINC = 0x00,
642 OPC2_32_BO_ST_B_PREINC = 0x10,
643 OPC2_32_BO_ST_D_SHORTOFF = 0x25,
644 OPC2_32_BO_ST_D_POSTINC = 0x05,
645 OPC2_32_BO_ST_D_PREINC = 0x15,
646 OPC2_32_BO_ST_DA_SHORTOFF = 0x27,
647 OPC2_32_BO_ST_DA_POSTINC = 0x07,
648 OPC2_32_BO_ST_DA_PREINC = 0x17,
649 OPC2_32_BO_ST_H_SHORTOFF = 0x22,
650 OPC2_32_BO_ST_H_POSTINC = 0x02,
651 OPC2_32_BO_ST_H_PREINC = 0x12,
652 OPC2_32_BO_ST_Q_SHORTOFF = 0x28,
653 OPC2_32_BO_ST_Q_POSTINC = 0x08,
654 OPC2_32_BO_ST_Q_PREINC = 0x18,
655 OPC2_32_BO_ST_W_SHORTOFF = 0x24,
656 OPC2_32_BO_ST_W_POSTINC = 0x04,
657 OPC2_32_BO_ST_W_PREINC = 0x14,
658 };
659 /* OPCM_32_BO_ADDRMODE_BITREVERSE_CIRCULAR */
660 enum {
661 OPC2_32_BO_CACHEA_I_BR = 0x0e,
662 OPC2_32_BO_CACHEA_I_CIRC = 0x1e,
663 OPC2_32_BO_CACHEA_W_BR = 0x0c,
664 OPC2_32_BO_CACHEA_W_CIRC = 0x1c,
665 OPC2_32_BO_CACHEA_WI_BR = 0x0d,
666 OPC2_32_BO_CACHEA_WI_CIRC = 0x1d,
667 OPC2_32_BO_ST_A_BR = 0x06,
668 OPC2_32_BO_ST_A_CIRC = 0x16,
669 OPC2_32_BO_ST_B_BR = 0x00,
670 OPC2_32_BO_ST_B_CIRC = 0x10,
671 OPC2_32_BO_ST_D_BR = 0x05,
672 OPC2_32_BO_ST_D_CIRC = 0x15,
673 OPC2_32_BO_ST_DA_BR = 0x07,
674 OPC2_32_BO_ST_DA_CIRC = 0x17,
675 OPC2_32_BO_ST_H_BR = 0x02,
676 OPC2_32_BO_ST_H_CIRC = 0x12,
677 OPC2_32_BO_ST_Q_BR = 0x08,
678 OPC2_32_BO_ST_Q_CIRC = 0x18,
679 OPC2_32_BO_ST_W_BR = 0x04,
680 OPC2_32_BO_ST_W_CIRC = 0x14,
681 };
682 /* OPCM_32_BO_ADDRMODE_LD_POST_PRE_BASE */
683 enum {
684 OPC2_32_BO_LD_A_SHORTOFF = 0x26,
685 OPC2_32_BO_LD_A_POSTINC = 0x06,
686 OPC2_32_BO_LD_A_PREINC = 0x16,
687 OPC2_32_BO_LD_B_SHORTOFF = 0x20,
688 OPC2_32_BO_LD_B_POSTINC = 0x00,
689 OPC2_32_BO_LD_B_PREINC = 0x10,
690 OPC2_32_BO_LD_BU_SHORTOFF = 0x21,
691 OPC2_32_BO_LD_BU_POSTINC = 0x01,
692 OPC2_32_BO_LD_BU_PREINC = 0x11,
693 OPC2_32_BO_LD_D_SHORTOFF = 0x25,
694 OPC2_32_BO_LD_D_POSTINC = 0x05,
695 OPC2_32_BO_LD_D_PREINC = 0x15,
696 OPC2_32_BO_LD_DA_SHORTOFF = 0x27,
697 OPC2_32_BO_LD_DA_POSTINC = 0x07,
698 OPC2_32_BO_LD_DA_PREINC = 0x17,
699 OPC2_32_BO_LD_H_SHORTOFF = 0x22,
700 OPC2_32_BO_LD_H_POSTINC = 0x02,
701 OPC2_32_BO_LD_H_PREINC = 0x12,
702 OPC2_32_BO_LD_HU_SHORTOFF = 0x23,
703 OPC2_32_BO_LD_HU_POSTINC = 0x03,
704 OPC2_32_BO_LD_HU_PREINC = 0x13,
705 OPC2_32_BO_LD_Q_SHORTOFF = 0x28,
706 OPC2_32_BO_LD_Q_POSTINC = 0x08,
707 OPC2_32_BO_LD_Q_PREINC = 0x18,
708 OPC2_32_BO_LD_W_SHORTOFF = 0x24,
709 OPC2_32_BO_LD_W_POSTINC = 0x04,
710 OPC2_32_BO_LD_W_PREINC = 0x14,
711 };
712 /* OPCM_32_BO_ADDRMODE_LD_BITREVERSE_CIRCULAR */
713 enum {
714 OPC2_32_BO_LD_A_BR = 0x06,
715 OPC2_32_BO_LD_A_CIRC = 0x16,
716 OPC2_32_BO_LD_B_BR = 0x00,
717 OPC2_32_BO_LD_B_CIRC = 0x10,
718 OPC2_32_BO_LD_BU_BR = 0x01,
719 OPC2_32_BO_LD_BU_CIRC = 0x11,
720 OPC2_32_BO_LD_D_BR = 0x05,
721 OPC2_32_BO_LD_D_CIRC = 0x15,
722 OPC2_32_BO_LD_DA_BR = 0x07,
723 OPC2_32_BO_LD_DA_CIRC = 0x17,
724 OPC2_32_BO_LD_H_BR = 0x02,
725 OPC2_32_BO_LD_H_CIRC = 0x12,
726 OPC2_32_BO_LD_HU_BR = 0x03,
727 OPC2_32_BO_LD_HU_CIRC = 0x13,
728 OPC2_32_BO_LD_Q_BR = 0x08,
729 OPC2_32_BO_LD_Q_CIRC = 0x18,
730 OPC2_32_BO_LD_W_BR = 0x04,
731 OPC2_32_BO_LD_W_CIRC = 0x14,
732 };
733 /* OPCM_32_BO_ADDRMODE_STCTX_POST_PRE_BASE */
734 enum {
735 OPC2_32_BO_LDLCX_SHORTOFF = 0x24,
736 OPC2_32_BO_LDMST_SHORTOFF = 0x21,
737 OPC2_32_BO_LDMST_POSTINC = 0x01,
738 OPC2_32_BO_LDMST_PREINC = 0x11,
739 OPC2_32_BO_LDUCX_SHORTOFF = 0x25,
740 OPC2_32_BO_LEA_SHORTOFF = 0x28,
741 OPC2_32_BO_STLCX_SHORTOFF = 0x26,
742 OPC2_32_BO_STUCX_SHORTOFF = 0x27,
743 OPC2_32_BO_SWAP_W_SHORTOFF = 0x20,
744 OPC2_32_BO_SWAP_W_POSTINC = 0x00,
745 OPC2_32_BO_SWAP_W_PREINC = 0x10,
746 };
747 /*OPCM_32_BO_ADDRMODE_LDMST_BITREVERSE_CIRCULAR */
748 enum {
749 OPC2_32_BO_LDMST_BR = 0x01,
750 OPC2_32_BO_LDMST_CIRC = 0x11,
751 OPC2_32_BO_SWAP_W_BR = 0x00,
752 OPC2_32_BO_SWAP_W_CIRC = 0x10,
753 };
754 /*
755 * BRC Format
756 */
757 /*OPCM_32_BRC_EQ_NEQ */
758 enum {
759 OPC2_32_BRC_JEQ = 0x00,
760 OPC2_32_BRC_JNE = 0x01,
761 };
762 /* OPCM_32_BRC_GE */
763 enum {
764 OP2_BRC_JGE = 0x00,
765 OPC_BRC_JGE_U = 0x01,
766 };
767 /* OPCM_32_BRC_JLT */
768 enum {
769 OPC2_32_BRC_JLT = 0x00,
770 OPC2_32_BRC_JLT_U = 0x01,
771 };
772 /* OPCM_32_BRC_JNE */
773 enum {
774 OPC2_32_BRC_JNED = 0x01,
775 OPC2_32_BRC_JNEI = 0x00,
776 };
777 /*
778 * BRN Format
779 */
780 /* OPCM_32_BRN_JTT */
781 enum {
782 OPC2_32_BRN_JNZ_T = 0x01,
783 OPC2_32_BRN_JZ_T = 0x00,
784 };
785 /*
786 * BRR Format
787 */
788 /* OPCM_32_BRR_EQ_NEQ */
789 enum {
790 OPC2_32_BRR_JEQ = 0x00,
791 OPC2_32_BRR_JNE = 0x01,
792 };
793 /* OPCM_32_BRR_ADDR_EQ_NEQ */
794 enum {
795 OPC2_32_BRR_JEQ_A = 0x00,
796 OPC2_32_BRR_JNE_A = 0x01,
797 };
798 /*OPCM_32_BRR_GE */
799 enum {
800 OPC2_32_BRR_JGE = 0x00,
801 OPC2_32_BRR_JGE_U = 0x01,
802 };
803 /* OPCM_32_BRR_JLT */
804 enum {
805 OPC2_32_BRR_JLT = 0x00,
806 OPC2_32_BRR_JLT_U = 0x01,
807 };
808 /* OPCM_32_BRR_JNE */
809 enum {
810 OPC2_32_BRR_JNED = 0x01,
811 OPC2_32_BRR_JNEI = 0x00,
812 };
813 /* OPCM_32_BRR_JNZ */
814 enum {
815 OPC2_32_BRR_JNZ_A = 0x01,
816 OPC2_32_BRR_JZ_A = 0x00,
817 };
818 /* OPCM_32_BRR_LOOP */
819 enum {
820 OPC2_32_BRR_LOOP = 0x00,
821 OPC2_32_BRR_LOOPU = 0x01,
822 };
823 /*
824 * RC Format
825 */
826 /* OPCM_32_RC_LOGICAL_SHIFT */
827 enum {
828 OPC2_32_RC_AND = 0x08,
829 OPC2_32_RC_ANDN = 0x0e,
830 OPC2_32_RC_NAND = 0x09,
831 OPC2_32_RC_NOR = 0x0b,
832 OPC2_32_RC_OR = 0x0a,
833 OPC2_32_RC_ORN = 0x0f,
834 OPC2_32_RC_SH = 0x00,
835 OPC2_32_RC_SH_H = 0x40,
836 OPC2_32_RC_SHA = 0x01,
837 OPC2_32_RC_SHA_H = 0x41,
838 OPC2_32_RC_SHAS = 0x02,
839 OPC2_32_RC_XNOR = 0x0d,
840 OPC2_32_RC_XOR = 0x0c,
841 };
842 /* OPCM_32_RC_ACCUMULATOR */
843 enum {
844 OPC2_32_RC_ABSDIF = 0x0e,
845 OPC2_32_RC_ABSDIFS = 0x0f,
846 OPC2_32_RC_ADD = 0x00,
847 OPC2_32_RC_ADDC = 0x05,
848 OPC2_32_RC_ADDS = 0x02,
849 OPC2_32_RC_ADDS_U = 0x03,
850 OPC2_32_RC_ADDX = 0x04,
851 OPC2_32_RC_AND_EQ = 0x20,
852 OPC2_32_RC_AND_GE = 0x24,
853 OPC2_32_RC_AND_GE_U = 0x25,
854 OPC2_32_RC_AND_LT = 0x22,
855 OPC2_32_RC_AND_LT_U = 0x23,
856 OPC2_32_RC_AND_NE = 0x21,
857 OPC2_32_RC_EQ = 0x10,
858 OPC2_32_RC_EQANY_B = 0x56,
859 OPC2_32_RC_EQANY_H = 0x76,
860 OPC2_32_RC_GE = 0x14,
861 OPC2_32_RC_GE_U = 0x15,
862 OPC2_32_RC_LT = 0x12,
863 OPC2_32_RC_LT_U = 0x13,
864 OPC2_32_RC_MAX = 0x1a,
865 OPC2_32_RC_MAX_U = 0x1b,
866 OPC2_32_RC_MIN = 0x18,
867 OPC2_32_RC_MIN_U = 0x19,
868 OPC2_32_RC_NE = 0x11,
869 OPC2_32_RC_OR_EQ = 0x27,
870 OPC2_32_RC_OR_GE = 0x2b,
871 OPC2_32_RC_OR_GE_U = 0x2c,
872 OPC2_32_RC_OR_LT = 0x29,
873 OPC2_32_RC_OR_LT_U = 0x2a,
874 OPC2_32_RC_OR_NE = 0x28,
875 OPC2_32_RC_RSUB = 0x08,
876 OPC2_32_RC_RSUBS = 0x0a,
877 OPC2_32_RC_RSUBS_U = 0x0b,
878 OPC2_32_RC_SH_EQ = 0x37,
879 OPC2_32_RC_SH_GE = 0x3b,
880 OPC2_32_RC_SH_GE_U = 0x3c,
881 OPC2_32_RC_SH_LT = 0x39,
882 OPC2_32_RC_SH_LT_U = 0x3a,
883 OPC2_32_RC_SH_NE = 0x38,
884 OPC2_32_RC_XOR_EQ = 0x2f,
885 OPC2_32_RC_XOR_GE = 0x33,
886 OPC2_32_RC_XOR_GE_U = 0x34,
887 OPC2_32_RC_XOR_LT = 0x31,
888 OPC2_32_RC_XOR_LT_U = 0x32,
889 OPC2_32_RC_XOR_NE = 0x30,
890 };
891 /* OPCM_32_RC_SERVICEROUTINE */
892 enum {
893 OPC2_32_RC_BISR = 0x00,
894 OPC2_32_RC_SYSCALL = 0x04,
895 };
896 /* OPCM_32_RC_MUL */
897 enum {
898 OPC2_32_RC_MUL_32 = 0x01,
899 OPC2_32_RC_MUL_64 = 0x03,
900 OPC2_32_RC_MULS_32 = 0x05,
901 OPC2_32_RC_MUL_U_64 = 0x02,
902 OPC2_32_RC_MULS_U_32 = 0x04,
903 };
904 /*
905 * RCPW Format
906 */
907 /* OPCM_32_RCPW_MASK_INSERT */
908 enum {
909 OPC2_32_RCPW_IMASK = 0x01,
910 OPC2_32_RCPW_INSERT = 0x00,
911 };
912 /*
913 * RCR Format
914 */
915 /* OPCM_32_RCR_COND_SELECT */
916 enum {
917 OPC2_32_RCR_CADD = 0x00,
918 OPC2_32_RCR_CADDN = 0x01,
919 OPC2_32_RCR_SEL = 0x04,
920 OPC2_32_RCR_SELN = 0x05,
921 };
922 /* OPCM_32_RCR_MADD */
923 enum {
924 OPC2_32_RCR_MADD_32 = 0x01,
925 OPC2_32_RCR_MADD_64 = 0x03,
926 OPC2_32_RCR_MADDS_32 = 0x05,
927 OPC2_32_RCR_MADDS_64 = 0x07,
928 OPC2_32_RCR_MADD_U_64 = 0x02,
929 OPC2_32_RCR_MADDS_U_32 = 0x04,
930 OPC2_32_RCR_MADDS_U_64 = 0x06,
931 };
932 /* OPCM_32_RCR_MSUB */
933 enum {
934 OPC2_32_RCR_MSUB_32 = 0x01,
935 OPC2_32_RCR_MSUB_64 = 0x03,
936 OPC2_32_RCR_MSUBS_32 = 0x05,
937 OPC2_32_RCR_MSUBS_64 = 0x07,
938 OPC2_32_RCR_MSUB_U_32 = 0x02,
939 OPC2_32_RCR_MSUBS_U_32 = 0x04,
940 OPC2_32_RCR_MSUBS_U_64 = 0x06,
941 };
942 /*
943 * RCRW Format
944 */
945 /* OPCM_32_RCRW_MASK_INSERT */
946 enum {
947 OPC2_32_RCRW_IMASK = 0x01,
948 OPC2_32_RCRW_INSERT = 0x00,
949 };
950
951 /*
952 * RR Format
953 */
954 /* OPCM_32_RR_LOGICAL_SHIFT */
955 enum {
956 OPC2_32_RR_AND = 0x08,
957 OPC2_32_RR_ANDN = 0x0e,
958 OPC2_32_RR_CLO = 0x1c,
959 OPC2_32_RR_CLO_H = 0x7d,
960 OPC2_32_RR_CLS = 0x1d,
961 OPC2_32_RR_CLS_H = 0x7e,
962 OPC2_32_RR_CLZ = 0x1b,
963 OPC2_32_RR_CLZ_H = 0x7c,
964 OPC2_32_RR_NAND = 0x09,
965 OPC2_32_RR_NOR = 0x0b,
966 OPC2_32_RR_OR = 0x0a,
967 OPC2_32_RR_ORN = 0x0f,
968 OPC2_32_RR_SH = 0x00,
969 OPC2_32_RR_SH_H = 0x40,
970 OPC2_32_RR_SHA = 0x01,
971 OPC2_32_RR_SHA_H = 0x41,
972 OPC2_32_RR_SHAS = 0x02,
973 OPC2_32_RR_XNOR = 0x0d,
974 OPC2_32_RR_XOR = 0x0c,
975 };
976 /* OPCM_32_RR_ACCUMULATOR */
977 enum {
978 OPC2_32_RR_ABS = 0x1c,
979 OPC2_32_RR_ABS_B = 0x5c,
980 OPC2_32_RR_ABS_H = 0x7c,
981 OPC2_32_RR_ABSDIF = 0x0e,
982 OPC2_32_RR_ABSDIF_B = 0x4e,
983 OPC2_32_RR_ABSDIF_H = 0x6e,
984 OPC2_32_RR_ABSDIFS = 0x0f,
985 OPC2_32_RR_ABSDIFS_H = 0x6f,
986 OPC2_32_RR_ABSS = 0x1d,
987 OPC2_32_RR_ABSS_H = 0x7d,
988 OPC2_32_RR_ADD = 0x00,
989 OPC2_32_RR_ADD_B = 0x40,
990 OPC2_32_RR_ADD_H = 0x60,
991 OPC2_32_RR_ADDC = 0x05,
992 OPC2_32_RR_ADDS = 0x02,
993 OPC2_32_RR_ADDS_H = 0x62,
994 OPC2_32_RR_ADDS_HU = 0x63,
995 OPC2_32_RR_ADDS_U = 0x03,
996 OPC2_32_RR_ADDX = 0x04,
997 OPC2_32_RR_AND_EQ = 0x20,
998 OPC2_32_RR_AND_GE = 0x24,
999 OPC2_32_RR_AND_GE_U = 0x25,
1000 OPC2_32_RR_AND_LT = 0x22,
1001 OPC2_32_RR_AND_LT_U = 0x23,
1002 OPC2_32_RR_AND_NE = 0x21,
1003 OPC2_32_RR_EQ = 0x10,
1004 OPC2_32_RR_EQ_B = 0x50,
1005 OPC2_32_RR_EQ_H = 0x70,
1006 OPC2_32_RR_EQ_W = 0x90,
1007 OPC2_32_RR_EQANY_B = 0x56,
1008 OPC2_32_RR_EQANY_H = 0x76,
1009 OPC2_32_RR_GE = 0x14,
1010 OPC2_32_RR_GE_U = 0x15,
1011 OPC2_32_RR_LT = 0x12,
1012 OPC2_32_RR_LT_U = 0x13,
1013 OPC2_32_RR_LT_B = 0x52,
1014 OPC2_32_RR_LT_BU = 0x53,
1015 OPC2_32_RR_LT_H = 0x72,
1016 OPC2_32_RR_LT_HU = 0x73,
1017 OPC2_32_RR_LT_W = 0x92,
1018 OPC2_32_RR_LT_WU = 0x93,
1019 OPC2_32_RR_MAX = 0x1a,
1020 OPC2_32_RR_MAX_U = 0x1b,
1021 OPC2_32_RR_MAX_B = 0x5a,
1022 OPC2_32_RR_MAX_BU = 0x5b,
1023 OPC2_32_RR_MAX_H = 0x7a,
1024 OPC2_32_RR_MAX_HU = 0x7b,
1025 OPC2_32_RR_MIN = 0x19,
1026 OPC2_32_RR_MIN_U = 0x18,
1027 OPC2_32_RR_MIN_B = 0x58,
1028 OPC2_32_RR_MIN_BU = 0x59,
1029 OPC2_32_RR_MIN_H = 0x78,
1030 OPC2_32_RR_MIN_HU = 0x79,
1031 OPC2_32_RR_MOV = 0x1f,
1032 OPC2_32_RR_NE = 0x11,
1033 OPC2_32_RR_OR_EQ = 0x27,
1034 OPC2_32_RR_OR_GE = 0x2b,
1035 OPC2_32_RR_OR_GE_U = 0x2c,
1036 OPC2_32_RR_OR_LT = 0x29,
1037 OPC2_32_RR_OR_LT_U = 0x2a,
1038 OPC2_32_RR_OR_NE = 0x28,
1039 OPC2_32_RR_SAT_B = 0x5e,
1040 OPC2_32_RR_SAT_BU = 0x5f,
1041 OPC2_32_RR_SAT_H = 0x7e,
1042 OPC2_32_RR_SAT_HU = 0x7f,
1043 OPC2_32_RR_SH_EQ = 0x37,
1044 OPC2_32_RR_SH_GE = 0x3b,
1045 OPC2_32_RR_SH_GE_U = 0x3c,
1046 OPC2_32_RR_SH_LT = 0x39,
1047 OPC2_32_RR_SH_LT_U = 0x3a,
1048 OPC2_32_RR_SH_NE = 0x38,
1049 OPC2_32_RR_SUB = 0x08,
1050 OPC2_32_RR_SUB_B = 0x48,
1051 OPC2_32_RR_SUB_H = 0x68,
1052 OPC2_32_RR_SUBC = 0x0d,
1053 OPC2_32_RR_SUBS = 0x0a,
1054 OPC2_32_RR_SUBS_U = 0x0b,
1055 OPC2_32_RR_SUBS_H = 0x6a,
1056 OPC2_32_RR_SUBS_HU = 0x6b,
1057 OPC2_32_RR_SUBX = 0x0c,
1058 OPC2_32_RR_XOR_EQ = 0x2f,
1059 OPC2_32_RR_XOR_GE = 0x33,
1060 OPC2_32_RR_XOR_GE_U = 0x34,
1061 OPC2_32_RR_XOR_LT = 0x31,
1062 OPC2_32_RR_XOR_LT_U = 0x32,
1063 OPC2_32_RR_XOR_NE = 0x30,
1064 };
1065 /* OPCM_32_RR_ADRESS */
1066 enum {
1067 OPC2_32_RR_ADD_A = 0x01,
1068 OPC2_32_RR_ADDSC_A = 0x60,
1069 OPC2_32_RR_ADDSC_AT = 0x62,
1070 OPC2_32_RR_EQ_A = 0x40,
1071 OPC2_32_RR_EQZ = 0x48,
1072 OPC2_32_RR_GE_A = 0x43,
1073 OPC2_32_RR_LT_A = 0x42,
1074 OPC2_32_RR_MOV_A = 0x63,
1075 OPC2_32_RR_MOV_AA = 0x00,
1076 OPC2_32_RR_MOV_D = 0x4c,
1077 OPC2_32_RR_NE_A = 0x41,
1078 OPC2_32_RR_NEZ_A = 0x49,
1079 OPC2_32_RR_SUB_A = 0x02,
1080 };
1081 /* OPCM_32_RR_FLOAT */
1082 enum {
1083 OPC2_32_RR_BMERGE = 0x01,
1084 OPC2_32_RR_BSPLIT = 0x09,
1085 OPC2_32_RR_DVINIT_B = 0x5a,
1086 OPC2_32_RR_DVINIT_BU = 0x4a,
1087 OPC2_32_RR_DVINIT_H = 0x3a,
1088 OPC2_32_RR_DVINIT_HU = 0x2a,
1089 OPC2_32_RR_DVINIT = 0x1a,
1090 OPC2_32_RR_DVINIT_U = 0x0a,
1091 OPC2_32_RR_PARITY = 0x02,
1092 OPC2_32_RR_UNPACK = 0x08,
1093 };
1094 /* OPCM_32_RR_IDIRECT */
1095 enum {
1096 OPC2_32_RR_JI = 0x03,
1097 OPC2_32_RR_JLI = 0x02,
1098 OPC2_32_RR_CALLI = 0x00,
1099 };
1100 /*
1101 * RR1 Format
1102 */
1103 /* OPCM_32_RR1_MUL */
1104 enum {
1105 OPC2_32_RR1_MUL_H_32_LL = 0x1a,
1106 OPC2_32_RR1_MUL_H_32_LU = 0x19,
1107 OPC2_32_RR1_MUL_H_32_UL = 0x18,
1108 OPC2_32_RR1_MUL_H_32_UU = 0x1b,
1109 OPC2_32_RR1_MULM_H_64_LL = 0x1e,
1110 OPC2_32_RR1_MULM_H_64_LU = 0x1d,
1111 OPC2_32_RR1_MULM_H_64_UL = 0x1c,
1112 OPC2_32_RR1_MULM_H_64_UU = 0x1f,
1113 OPC2_32_RR1_MULR_H_16_LL = 0x0e,
1114 OPC2_32_RR1_MULR_H_16_LU = 0x0d,
1115 OPC2_32_RR1_MULR_H_16_UL = 0x0c,
1116 OPC2_32_RR1_MULR_H_16_UU = 0x0f,
1117 };
1118 /* OPCM_32_RR1_MULQ */
1119 enum {
1120 OPC2_32_RR1_MUL_Q_32 = 0x02,
1121 OPC2_32_RR1_MUL_Q_64 = 0x1b,
1122 OPC2_32_RR1_MUL_Q_32_L = 0x01,
1123 OPC2_32_RR1_MUL_Q_64_L = 0x19,
1124 OPC2_32_RR1_MUL_Q_32_U = 0x00,
1125 OPC2_32_RR1_MUL_Q_64_U = 0x18,
1126 OPC2_32_RR1_MUL_Q_32_LL = 0x05,
1127 OPC2_32_RR1_MUL_Q_32_UU = 0x04,
1128 OPC2_32_RR1_MULR_Q_32_L = 0x07,
1129 OPC2_32_RR1_MULR_Q_32_U = 0x06,
1130 };
1131 /*
1132 * RR2 Format
1133 */
1134 /* OPCM_32_RR2_MUL */
1135 enum {
1136 OPC2_32_RR2_MUL_32 = 0x0a,
1137 OPC2_32_RR2_MUL_64 = 0x6a,
1138 OPC2_32_RR2_MULS_32 = 0x8a,
1139 OPC2_32_RR2_MUL_U_64 = 0x68,
1140 OPC2_32_RR2_MULS_U_32 = 0x88,
1141 };
1142 /*
1143 * RRPW Format
1144 */
1145 /* OPCM_32_RRPW_EXTRACT_INSERT */
1146 enum {
1147
1148 OPC2_32_RRPW_EXTR = 0x02,
1149 OPC2_32_RRPW_EXTR_U = 0x03,
1150 OPC2_32_RRPW_IMASK = 0x01,
1151 OPC2_32_RRPW_INSERT = 0x00,
1152 };
1153 /*
1154 * RRR Format
1155 */
1156 /* OPCM_32_RRR_COND_SELECT */
1157 enum {
1158 OPC2_32_RRR_CADD = 0x00,
1159 OPC2_32_RRR_CADDN = 0x01,
1160 OPC2_32_RRR_CSUB = 0x02,
1161 OPC2_32_RRR_CSUBN = 0x03,
1162 OPC2_32_RRR_SEL = 0x04,
1163 OPC2_32_RRR_SELN = 0x05,
1164 };
1165 /* OPCM_32_RRR_FLOAT */
1166 enum {
1167 OPC2_32_RRR_DVADJ = 0x0d,
1168 OPC2_32_RRR_DVSTEP = 0x0f,
1169 OPC2_32_RRR_DVSTEP_U = 0x0e,
1170 OPC2_32_RRR_IXMAX = 0x0a,
1171 OPC2_32_RRR_IXMAX_U = 0x0b,
1172 OPC2_32_RRR_IXMIN = 0x08,
1173 OPC2_32_RRR_IXMIN_U = 0x09,
1174 OPC2_32_RRR_PACK = 0x00,
1175 };
1176 /*
1177 * RRR1 Format
1178 */
1179 /* OPCM_32_RRR1_MADD */
1180 enum {
1181 OPC2_32_RRR1_MADD_H_LL = 0x1a,
1182 OPC2_32_RRR1_MADD_H_LU = 0x19,
1183 OPC2_32_RRR1_MADD_H_UL = 0x18,
1184 OPC2_32_RRR1_MADD_H_UU = 0x1b,
1185 OPC2_32_RRR1_MADDS_H_LL = 0x3a,
1186 OPC2_32_RRR1_MADDS_H_LU = 0x39,
1187 OPC2_32_RRR1_MADDS_H_UL = 0x38,
1188 OPC2_32_RRR1_MADDS_H_UU = 0x3b,
1189 OPC2_32_RRR1_MADDM_H_LL = 0x1e,
1190 OPC2_32_RRR1_MADDM_H_LU = 0x1d,
1191 OPC2_32_RRR1_MADDM_H_UL = 0x1c,
1192 OPC2_32_RRR1_MADDM_H_UU = 0x1f,
1193 OPC2_32_RRR1_MADDMS_H_LL = 0x3e,
1194 OPC2_32_RRR1_MADDMS_H_LU = 0x3d,
1195 OPC2_32_RRR1_MADDMS_H_UL = 0x3c,
1196 OPC2_32_RRR1_MADDMS_H_UU = 0x3f,
1197 OPC2_32_RRR1_MADDR_H_LL = 0x0e,
1198 OPC2_32_RRR1_MADDR_H_LU = 0x0d,
1199 OPC2_32_RRR1_MADDR_H_UL = 0x0c,
1200 OPC2_32_RRR1_MADDR_H_UU = 0x0f,
1201 OPC2_32_RRR1_MADDRS_H_LL = 0x2e,
1202 OPC2_32_RRR1_MADDRS_H_LU = 0x2d,
1203 OPC2_32_RRR1_MADDRS_H_UL = 0x2c,
1204 OPC2_32_RRR1_MADDRS_H_UU = 0x2f,
1205 };
1206 /* OPCM_32_RRR1_MADDQ_H */
1207 enum {
1208 OPC2_32_RRR1_MADD_Q_32 = 0x02,
1209 OPC2_32_RRR1_MADD_Q_64 = 0x1b,
1210 OPC2_32_RRR1_MADD_Q_32_L = 0x01,
1211 OPC2_32_RRR1_MADD_Q_64_L = 0x19,
1212 OPC2_32_RRR1_MADD_Q_32_U = 0x00,
1213 OPC2_32_RRR1_MADD_Q_64_U = 0x18,
1214 OPC2_32_RRR1_MADD_Q_32_LL = 0x05,
1215 OPC2_32_RRR1_MADD_Q_64_LL = 0x1d,
1216 OPC2_32_RRR1_MADD_Q_32_UU = 0x04,
1217 OPC2_32_RRR1_MADD_Q_64_UU = 0x1c,
1218 OPC2_32_RRR1_MADDS_Q_32 = 0x22,
1219 OPC2_32_RRR1_MADDS_Q_64 = 0x3b,
1220 OPC2_32_RRR1_MADDS_Q_32_L = 0x21,
1221 OPC2_32_RRR1_MADDS_Q_64_L = 0x39,
1222 OPC2_32_RRR1_MADDS_Q_32_U = 0x20,
1223 OPC2_32_RRR1_MADDS_Q_64_U = 0x38,
1224 OPC2_32_RRR1_MADDS_Q_32_LL = 0x25,
1225 OPC2_32_RRR1_MADDS_Q_64_LL = 0x3d,
1226 OPC2_32_RRR1_MADDS_Q_32_UU = 0x24,
1227 OPC2_32_RRR1_MADDS_Q_64_UU = 0x3c,
1228 OPC2_32_RRR1_MADDR_H_16_UL = 0x1e,
1229 OPC2_32_RRR1_MADDRS_H_16_UL = 0x3e,
1230 OPC2_32_RRR1_MADDR_Q_32_L = 0x07,
1231 OPC2_32_RRR1_MADDR_Q_32_U = 0x06,
1232 OPC2_32_RRR1_MADDRS_Q_32_LL = 0x27,
1233 OPC2_32_RRR1_MADDRS_Q_32_UU = 0x26,
1234 };
1235 /* OPCM_32_RRR1_MADDSU_H */
1236 enum {
1237 OPC2_32_RRR1_MADDSU_H_32_LL = 0x1a,
1238 OPC2_32_RRR1_MADDSU_H_32_LU = 0x19,
1239 OPC2_32_RRR1_MADDSU_H_32_UL = 0x18,
1240 OPC2_32_RRR1_MADDSU_H_32_UU = 0x1b,
1241 OPC2_32_RRR1_MADDSUS_H_32_LL = 0x3a,
1242 OPC2_32_RRR1_MADDSUS_H_32_LU = 0x39,
1243 OPC2_32_RRR1_MADDSUS_H_32_UL = 0x38,
1244 OPC2_32_RRR1_MADDSUS_H_32_UU = 0x3b,
1245 OPC2_32_RRR1_MADDSUM_H_64_LL = 0x1e,
1246 OPC2_32_RRR1_MADDSUM_H_64_LU = 0x1d,
1247 OPC2_32_RRR1_MADDSUM_H_64_UL = 0x1c,
1248 OPC2_32_RRR1_MADDSUM_H_64_UU = 0x1f,
1249 OPC2_32_RRR1_MADDSUMS_H_64_LL = 0x3e,
1250 OPC2_32_RRR1_MADDSUMS_H_64_LU = 0x3d,
1251 OPC2_32_RRR1_MADDSUMS_H_64_UL = 0x3c,
1252 OPC2_32_RRR1_MADDSUMS_H_64_UU = 0x3f,
1253 OPC2_32_RRR1_MADDSUR_H_16_LL = 0x0e,
1254 OPC2_32_RRR1_MADDSUR_H_16_LU = 0x0d,
1255 OPC2_32_RRR1_MADDSUR_H_16_UL = 0x0c,
1256 OPC2_32_RRR1_MADDSUR_H_16_UU = 0x0f,
1257 OPC2_32_RRR1_MADDSURS_H_16_LL = 0x2e,
1258 OPC2_32_RRR1_MADDSURS_H_16_LU = 0x2d,
1259 OPC2_32_RRR1_MADDSURS_H_16_UL = 0x2c,
1260 OPC2_32_RRR1_MADDSURS_H_16_UU = 0x2f,
1261 };
1262 /* OPCM_32_RRR1_MSUB_H */
1263 enum {
1264 OPC2_32_RRR1_MSUB_H_32_LL = 0x1a,
1265 OPC2_32_RRR1_MSUB_H_32_LU = 0x19,
1266 OPC2_32_RRR1_MSUB_H_32_UL = 0x18,
1267 OPC2_32_RRR1_MSUB_H_32_UU = 0x1b,
1268 OPC2_32_RRR1_MSUBS_H_32_LL = 0x3a,
1269 OPC2_32_RRR1_MSUBS_H_32_LU = 0x39,
1270 OPC2_32_RRR1_MSUBS_H_32_UL = 0x38,
1271 OPC2_32_RRR1_MSUBS_H_32_UU = 0x3b,
1272 OPC2_32_RRR1_MSUBM_H_64_LL = 0x1e,
1273 OPC2_32_RRR1_MSUBM_H_64_LU = 0x1d,
1274 OPC2_32_RRR1_MSUBM_H_64_UL = 0x1c,
1275 OPC2_32_RRR1_MSUBM_H_64_UU = 0x1f,
1276 OPC2_32_RRR1_MSUBMS_H_64_LL = 0x3e,
1277 OPC2_32_RRR1_MSUBMS_H_64_LU = 0x3d,
1278 OPC2_32_RRR1_MSUBMS_H_64_UL = 0x3c,
1279 OPC2_32_RRR1_MSUBMS_H_64_UU = 0x3f,
1280 OPC2_32_RRR1_MSUBR_H_16_LL = 0x0e,
1281 OPC2_32_RRR1_MSUBR_H_16_LU = 0x0d,
1282 OPC2_32_RRR1_MSUBR_H_16_UL = 0x0c,
1283 OPC2_32_RRR1_MSUBR_H_16_UU = 0x0f,
1284 OPC2_32_RRR1_MSUBRS_H_16_LL = 0x2e,
1285 OPC2_32_RRR1_MSUBRS_H_16_LU = 0x2d,
1286 OPC2_32_RRR1_MSUBRS_H_16_UL = 0x2c,
1287 OPC2_32_RRR1_MSUBRS_H_16_UU = 0x2f,
1288 };
1289 /* OPCM_32_RRR1_MSUB_Q */
1290 enum {
1291 OPC2_32_RRR1_MSUB_Q_32 = 0x02,
1292 OPC2_32_RRR1_MSUB_Q_64 = 0x1b,
1293 OPC2_32_RRR1_MSUB_Q_32_L = 0x01,
1294 OPC2_32_RRR1_MSUB_Q_64_L = 0x19,
1295 OPC2_32_RRR1_MSUB_Q_32_U = 0x00,
1296 OPC2_32_RRR1_MSUB_Q_64_U = 0x18,
1297 OPC2_32_RRR1_MSUB_Q_32_LL = 0x05,
1298 OPC2_32_RRR1_MSUB_Q_64_LL = 0x1d,
1299 OPC2_32_RRR1_MSUB_Q_32_UU = 0x04,
1300 OPC2_32_RRR1_MSUB_Q_64_UU = 0x1c,
1301 OPC2_32_RRR1_MSUBS_Q_32 = 0x22,
1302 OPC2_32_RRR1_MSUBS_Q_64 = 0x3b,
1303 OPC2_32_RRR1_MSUBS_Q_32_L = 0x21,
1304 OPC2_32_RRR1_MSUBS_Q_64_L = 0x39,
1305 OPC2_32_RRR1_MSUBS_Q_32_U = 0x20,
1306 OPC2_32_RRR1_MSUBS_Q_64_U = 0x38,
1307 OPC2_32_RRR1_MSUBS_Q_32_LL = 0x25,
1308 OPC2_32_RRR1_MSUBS_Q_64_LL = 0x3d,
1309 OPC2_32_RRR1_MSUBS_Q_32_UU = 0x24,
1310 OPC2_32_RRR1_MSUBS_Q_64_UU = 0x3c,
1311 OPC2_32_RRR1_MSUBR_H_32_UL = 0x1e,
1312 OPC2_32_RRR1_MSUBRS_H_32_UL = 0x3e,
1313 OPC2_32_RRR1_MSUBR_Q_32_LL = 0x07,
1314 OPC2_32_RRR1_MSUBR_Q_32_UU = 0x06,
1315 OPC2_32_RRR1_MSUBRS_Q_32_LL = 0x27,
1316 OPC2_32_RRR1_MSUBRS_Q_32_UU = 0x26,
1317 };
1318 /* OPCM_32_RRR1_MSUBADS_H */
1319 enum {
1320 OPC2_32_RRR1_MSUBAD_H_32_LL = 0x1a,
1321 OPC2_32_RRR1_MSUBAD_H_32_LU = 0x19,
1322 OPC2_32_RRR1_MSUBAD_H_32_UL = 0x18,
1323 OPC2_32_RRR1_MSUBAD_H_32_UU = 0x1b,
1324 OPC2_32_RRR1_MSUBADS_H_32_LL = 0x3a,
1325 OPC2_32_RRR1_MSUBADS_H_32_LU = 0x39,
1326 OPC2_32_RRR1_MSUBADS_H_32_UL = 0x38,
1327 OPC2_32_RRR1_MSUBADS_H_32_UU = 0x3b,
1328 OPC2_32_RRR1_MSUBADM_H_64_LL = 0x1e,
1329 OPC2_32_RRR1_MSUBADM_H_64_LU = 0x1d,
1330 OPC2_32_RRR1_MSUBADM_H_64_UL = 0x1c,
1331 OPC2_32_RRR1_MSUBADM_H_64_UU = 0x1f,
1332 OPC2_32_RRR1_MSUBADMS_H_64_LL = 0x3e,
1333 OPC2_32_RRR1_MSUBADMS_H_64_LU = 0x3d,
1334 OPC2_32_RRR1_MSUBADMS_H_64_UL = 0x3c,
1335 OPC2_32_RRR1_MSUBADMS_H_16_UU = 0x3f,
1336 OPC2_32_RRR1_MSUBADR_H_16_LL = 0x0e,
1337 OPC2_32_RRR1_MSUBADR_H_16_LU = 0x0d,
1338 OPC2_32_RRR1_MSUBADR_H_16_UL = 0x0c,
1339 OPC2_32_RRR1_MSUBADR_H_16_UU = 0x0f,
1340 OPC2_32_RRR1_MSUBADRS_H_16_LL = 0x2e,
1341 OPC2_32_RRR1_MSUBADRS_H_16_LU = 0x2d,
1342 OPC2_32_RRR1_MSUBADRS_H_16_UL = 0x2c,
1343 OPC2_32_RRR1_MSUBADRS_H_16_UU = 0x2f,
1344 };
1345 /*
1346 * RRR2 Format
1347 */
1348 /* OPCM_32_RRR2_MADD */
1349 enum {
1350 OPC2_32_RRR2_MADD_32 = 0x0a,
1351 OPC2_32_RRR2_MADD_64 = 0x6a,
1352 OPC2_32_RRR2_MADDS_32 = 0x8a,
1353 OPC2_32_RRR2_MADDS_64 = 0xea,
1354 OPC2_32_RRR2_MADD_U_32 = 0x68,
1355 OPC2_32_RRR2_MADDS_U_32 = 0x88,
1356 OPC2_32_RRR2_MADDS_U_64 = 0xe8,
1357 };
1358 /* OPCM_32_RRR2_MSUB */
1359 enum {
1360 OPC2_32_RRR2_MSUB_32 = 0x0a,
1361 OPC2_32_RRR2_MSUB_64 = 0x6a,
1362 OPC2_32_RRR2_MSUBS_32 = 0x8a,
1363 OPC2_32_RRR2_MSUBS_64 = 0xea,
1364 OPC2_32_RRR2_MSUB_U_64 = 0x68,
1365 OPC2_32_RRR2_MSUBS_U_32 = 0x88,
1366 OPC2_32_RRR2_MSUBS_U_64 = 0xe8,
1367 };
1368 /*
1369 * RRRR Format
1370 */
1371 /* OPCM_32_RRRR_EXTRACT_INSERT */
1372 enum {
1373 OPC2_32_RRRR_DEXTR = 0x04,
1374 OPC2_32_RRRR_EXTR = 0x02,
1375 OPC2_32_RRRR_EXTR_U = 0x03,
1376 OPC2_32_RRRR_INSERT = 0x00,
1377 };
1378 /*
1379 * RRRW Format
1380 */
1381 /* OPCM_32_RRRW_EXTRACT_INSERT */
1382 enum {
1383 OPC2_32_RRRW_EXTR = 0x02,
1384 OPC2_32_RRRW_EXTR_U = 0x03,
1385 OPC2_32_RRRW_IMASK = 0x01,
1386 OPC2_32_RRRW_INSERT = 0x00,
1387 };
1388 /*
1389 * SYS Format
1390 */
1391 /* OPCM_32_SYS_INTERRUPTS */
1392 enum {
1393 OPC2_32_SYS_DEBUG = 0x04,
1394 OPC2_32_SYS_DISABLE = 0x0d,
1395 OPC2_32_SYS_DSYNC = 0x12,
1396 OPC2_32_SYS_ENABLE = 0x0c,
1397 OPC2_32_SYS_ISYNC = 0x13,
1398 OPC2_32_SYS_NOP = 0x00,
1399 OPC2_32_SYS_RET = 0x06,
1400 OPC2_32_SYS_RFE = 0x07,
1401 OPC2_32_SYS_RFM = 0x05,
1402 OPC2_32_SYS_RSLCX = 0x09,
1403 OPC2_32_SYS_SVLCX = 0x08,
1404 OPC2_32_SYS_TRAPSV = 0x15,
1405 OPC2_32_SYS_TRAPV = 0x14,
1406 };
QEmu