2 * QEMU Malta board support
4 * Copyright (c) 2006 Aurelien Jarno
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
34 #include "mips_cpudevs.h"
37 #include "vmware_vga.h"
38 #include "qemu-char.h"
40 #include "arch_init.h"
43 #include "mips-bios.h"
47 #include "mc146818rtc.h"
49 #include "exec-memory.h"
51 //#define DEBUG_BOARD_INIT
53 #define ENVP_ADDR 0x80002000l
54 #define ENVP_NB_ENTRIES 16
55 #define ENVP_ENTRY_SIZE 256
67 CharDriverState
*display
;
72 static ISADevice
*pit
;
74 static struct _loaderparams
{
76 const char *kernel_filename
;
77 const char *kernel_cmdline
;
78 const char *initrd_filename
;
82 static void malta_fpga_update_display(void *opaque
)
86 MaltaFPGAState
*s
= opaque
;
88 for (i
= 7 ; i
>= 0 ; i
--) {
89 if (s
->leds
& (1 << i
))
96 qemu_chr_fe_printf(s
->display
, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text
);
97 qemu_chr_fe_printf(s
->display
, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s
->display_text
);
101 * EEPROM 24C01 / 24C02 emulation.
103 * Emulation for serial EEPROMs:
104 * 24C01 - 1024 bit (128 x 8)
105 * 24C02 - 2048 bit (256 x 8)
107 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
113 # define logout(fmt, ...) fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
115 # define logout(fmt, ...) ((void)0)
118 struct _eeprom24c0x_t
{
127 uint8_t contents
[256];
130 typedef struct _eeprom24c0x_t eeprom24c0x_t
;
132 static eeprom24c0x_t eeprom
= {
134 /* 00000000: */ 0x80,0x08,0x04,0x0D,0x0A,0x01,0x40,0x00,
135 /* 00000008: */ 0x01,0x75,0x54,0x00,0x82,0x08,0x00,0x01,
136 /* 00000010: */ 0x8F,0x04,0x02,0x01,0x01,0x00,0x0E,0x00,
137 /* 00000018: */ 0x00,0x00,0x00,0x14,0x0F,0x14,0x2D,0x40,
138 /* 00000020: */ 0x15,0x08,0x15,0x08,0x00,0x00,0x00,0x00,
139 /* 00000028: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
140 /* 00000030: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
141 /* 00000038: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x12,0xD0,
142 /* 00000040: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
143 /* 00000048: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
144 /* 00000050: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
145 /* 00000058: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
146 /* 00000060: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
147 /* 00000068: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
148 /* 00000070: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
149 /* 00000078: */ 0x00,0x00,0x00,0x00,0x00,0x00,0x64,0xF4,
153 static uint8_t eeprom24c0x_read(void)
155 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
156 eeprom
.tick
, eeprom
.scl
, eeprom
.sda
, eeprom
.data
);
160 static void eeprom24c0x_write(int scl
, int sda
)
162 if (eeprom
.scl
&& scl
&& (eeprom
.sda
!= sda
)) {
163 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
164 eeprom
.tick
, eeprom
.scl
, scl
, eeprom
.sda
, sda
, sda
? "stop" : "start");
169 } else if (eeprom
.tick
== 0 && !eeprom
.ack
) {
170 /* Waiting for start. */
171 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
172 eeprom
.tick
, eeprom
.scl
, scl
, eeprom
.sda
, sda
);
173 } else if (!eeprom
.scl
&& scl
) {
174 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
175 eeprom
.tick
, eeprom
.scl
, scl
, eeprom
.sda
, sda
);
177 logout("\ti2c ack bit = 0\n");
180 } else if (eeprom
.sda
== sda
) {
181 uint8_t bit
= (sda
!= 0);
182 logout("\ti2c bit = %d\n", bit
);
183 if (eeprom
.tick
< 9) {
184 eeprom
.command
<<= 1;
185 eeprom
.command
+= bit
;
187 if (eeprom
.tick
== 9) {
188 logout("\tcommand 0x%04x, %s\n", eeprom
.command
, bit
? "read" : "write");
191 } else if (eeprom
.tick
< 17) {
192 if (eeprom
.command
& 1) {
193 sda
= ((eeprom
.data
& 0x80) != 0);
195 eeprom
.address
<<= 1;
196 eeprom
.address
+= bit
;
199 if (eeprom
.tick
== 17) {
200 eeprom
.data
= eeprom
.contents
[eeprom
.address
];
201 logout("\taddress 0x%04x, data 0x%02x\n", eeprom
.address
, eeprom
.data
);
205 } else if (eeprom
.tick
>= 17) {
209 logout("\tsda changed with raising scl\n");
212 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom
.tick
, eeprom
.scl
, scl
, eeprom
.sda
, sda
);
218 static uint32_t malta_fpga_readl(void *opaque
, target_phys_addr_t addr
)
220 MaltaFPGAState
*s
= opaque
;
224 saddr
= (addr
& 0xfffff);
228 /* SWITCH Register */
230 val
= 0x00000000; /* All switches closed */
233 /* STATUS Register */
235 #ifdef TARGET_WORDS_BIGENDIAN
247 /* LEDBAR Register */
252 /* BRKRES Register */
257 /* UART Registers are handled directly by the serial device */
264 /* XXX: implement a real I2C controller */
268 /* IN = OUT until a real I2C control is implemented */
275 /* I2CINP Register */
277 val
= ((s
->i2cin
& ~1) | eeprom24c0x_read());
285 /* I2COUT Register */
290 /* I2CSEL Register */
297 printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx
"\n",
305 static void malta_fpga_writel(void *opaque
, target_phys_addr_t addr
,
308 MaltaFPGAState
*s
= opaque
;
311 saddr
= (addr
& 0xfffff);
315 /* SWITCH Register */
323 /* LEDBAR Register */
324 /* XXX: implement a 8-LED array */
326 s
->leds
= val
& 0xff;
329 /* ASCIIWORD Register */
331 snprintf(s
->display_text
, 9, "%08X", val
);
332 malta_fpga_update_display(s
);
335 /* ASCIIPOS0 to ASCIIPOS7 Registers */
344 s
->display_text
[(saddr
- 0x00418) >> 3] = (char) val
;
345 malta_fpga_update_display(s
);
348 /* SOFTRES Register */
351 qemu_system_reset_request ();
354 /* BRKRES Register */
359 /* UART Registers are handled directly by the serial device */
363 s
->gpout
= val
& 0xff;
368 s
->i2coe
= val
& 0x03;
371 /* I2COUT Register */
373 eeprom24c0x_write(val
& 0x02, val
& 0x01);
377 /* I2CSEL Register */
379 s
->i2csel
= val
& 0x01;
384 printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx
"\n",
391 static CPUReadMemoryFunc
* const malta_fpga_read
[] = {
397 static CPUWriteMemoryFunc
* const malta_fpga_write
[] = {
403 static void malta_fpga_reset(void *opaque
)
405 MaltaFPGAState
*s
= opaque
;
415 s
->display_text
[8] = '\0';
416 snprintf(s
->display_text
, 9, " ");
419 static void malta_fpga_led_init(CharDriverState
*chr
)
421 qemu_chr_fe_printf(chr
, "\e[HMalta LEDBAR\r\n");
422 qemu_chr_fe_printf(chr
, "+--------+\r\n");
423 qemu_chr_fe_printf(chr
, "+ +\r\n");
424 qemu_chr_fe_printf(chr
, "+--------+\r\n");
425 qemu_chr_fe_printf(chr
, "\n");
426 qemu_chr_fe_printf(chr
, "Malta ASCII\r\n");
427 qemu_chr_fe_printf(chr
, "+--------+\r\n");
428 qemu_chr_fe_printf(chr
, "+ +\r\n");
429 qemu_chr_fe_printf(chr
, "+--------+\r\n");
432 static MaltaFPGAState
*malta_fpga_init(target_phys_addr_t base
, qemu_irq uart_irq
, CharDriverState
*uart_chr
)
437 s
= (MaltaFPGAState
*)g_malloc0(sizeof(MaltaFPGAState
));
439 malta
= cpu_register_io_memory(malta_fpga_read
,
441 DEVICE_NATIVE_ENDIAN
);
443 cpu_register_physical_memory(base
, 0x900, malta
);
444 /* 0xa00 is less than a page, so will still get the right offsets. */
445 cpu_register_physical_memory(base
+ 0xa00, 0x100000 - 0xa00, malta
);
447 s
->display
= qemu_chr_new("fpga", "vc:320x200", malta_fpga_led_init
);
449 #ifdef TARGET_WORDS_BIGENDIAN
450 s
->uart
= serial_mm_init(base
+ 0x900, 3, uart_irq
, 230400, uart_chr
, 1, 1);
452 s
->uart
= serial_mm_init(base
+ 0x900, 3, uart_irq
, 230400, uart_chr
, 1, 0);
456 qemu_register_reset(malta_fpga_reset
, s
);
461 /* Network support */
462 static void network_init(void)
466 for(i
= 0; i
< nb_nics
; i
++) {
467 NICInfo
*nd
= &nd_table
[i
];
468 const char *default_devaddr
= NULL
;
470 if (i
== 0 && (!nd
->model
|| strcmp(nd
->model
, "pcnet") == 0))
471 /* The malta board has a PCNet card using PCI SLOT 11 */
472 default_devaddr
= "0b";
474 pci_nic_init_nofail(nd
, "pcnet", default_devaddr
);
478 /* ROM and pseudo bootloader
480 The following code implements a very very simple bootloader. It first
481 loads the registers a0 to a3 to the values expected by the OS, and
482 then jump at the kernel address.
484 The bootloader should pass the locations of the kernel arguments and
485 environment variables tables. Those tables contain the 32-bit address
486 of NULL terminated strings. The environment variables table should be
487 terminated by a NULL address.
489 For a simpler implementation, the number of kernel arguments is fixed
490 to two (the name of the kernel and the command line), and the two
491 tables are actually the same one.
493 The registers a0 to a3 should contain the following values:
494 a0 - number of kernel arguments
495 a1 - 32-bit address of the kernel arguments table
496 a2 - 32-bit address of the environment variables table
497 a3 - RAM size in bytes
500 static void write_bootloader (CPUState
*env
, uint8_t *base
,
501 int64_t kernel_entry
)
505 /* Small bootloader */
506 p
= (uint32_t *)base
;
507 stl_raw(p
++, 0x0bf00160); /* j 0x1fc00580 */
508 stl_raw(p
++, 0x00000000); /* nop */
510 /* YAMON service vector */
511 stl_raw(base
+ 0x500, 0xbfc00580); /* start: */
512 stl_raw(base
+ 0x504, 0xbfc0083c); /* print_count: */
513 stl_raw(base
+ 0x520, 0xbfc00580); /* start: */
514 stl_raw(base
+ 0x52c, 0xbfc00800); /* flush_cache: */
515 stl_raw(base
+ 0x534, 0xbfc00808); /* print: */
516 stl_raw(base
+ 0x538, 0xbfc00800); /* reg_cpu_isr: */
517 stl_raw(base
+ 0x53c, 0xbfc00800); /* unred_cpu_isr: */
518 stl_raw(base
+ 0x540, 0xbfc00800); /* reg_ic_isr: */
519 stl_raw(base
+ 0x544, 0xbfc00800); /* unred_ic_isr: */
520 stl_raw(base
+ 0x548, 0xbfc00800); /* reg_esr: */
521 stl_raw(base
+ 0x54c, 0xbfc00800); /* unreg_esr: */
522 stl_raw(base
+ 0x550, 0xbfc00800); /* getchar: */
523 stl_raw(base
+ 0x554, 0xbfc00800); /* syscon_read: */
526 /* Second part of the bootloader */
527 p
= (uint32_t *) (base
+ 0x580);
528 stl_raw(p
++, 0x24040002); /* addiu a0, zero, 2 */
529 stl_raw(p
++, 0x3c1d0000 | (((ENVP_ADDR
- 64) >> 16) & 0xffff)); /* lui sp, high(ENVP_ADDR) */
530 stl_raw(p
++, 0x37bd0000 | ((ENVP_ADDR
- 64) & 0xffff)); /* ori sp, sp, low(ENVP_ADDR) */
531 stl_raw(p
++, 0x3c050000 | ((ENVP_ADDR
>> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */
532 stl_raw(p
++, 0x34a50000 | (ENVP_ADDR
& 0xffff)); /* ori a1, a1, low(ENVP_ADDR) */
533 stl_raw(p
++, 0x3c060000 | (((ENVP_ADDR
+ 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */
534 stl_raw(p
++, 0x34c60000 | ((ENVP_ADDR
+ 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */
535 stl_raw(p
++, 0x3c070000 | (loaderparams
.ram_size
>> 16)); /* lui a3, high(ram_size) */
536 stl_raw(p
++, 0x34e70000 | (loaderparams
.ram_size
& 0xffff)); /* ori a3, a3, low(ram_size) */
538 /* Load BAR registers as done by YAMON */
539 stl_raw(p
++, 0x3c09b400); /* lui t1, 0xb400 */
541 #ifdef TARGET_WORDS_BIGENDIAN
542 stl_raw(p
++, 0x3c08df00); /* lui t0, 0xdf00 */
544 stl_raw(p
++, 0x340800df); /* ori t0, r0, 0x00df */
546 stl_raw(p
++, 0xad280068); /* sw t0, 0x0068(t1) */
548 stl_raw(p
++, 0x3c09bbe0); /* lui t1, 0xbbe0 */
550 #ifdef TARGET_WORDS_BIGENDIAN
551 stl_raw(p
++, 0x3c08c000); /* lui t0, 0xc000 */
553 stl_raw(p
++, 0x340800c0); /* ori t0, r0, 0x00c0 */
555 stl_raw(p
++, 0xad280048); /* sw t0, 0x0048(t1) */
556 #ifdef TARGET_WORDS_BIGENDIAN
557 stl_raw(p
++, 0x3c084000); /* lui t0, 0x4000 */
559 stl_raw(p
++, 0x34080040); /* ori t0, r0, 0x0040 */
561 stl_raw(p
++, 0xad280050); /* sw t0, 0x0050(t1) */
563 #ifdef TARGET_WORDS_BIGENDIAN
564 stl_raw(p
++, 0x3c088000); /* lui t0, 0x8000 */
566 stl_raw(p
++, 0x34080080); /* ori t0, r0, 0x0080 */
568 stl_raw(p
++, 0xad280058); /* sw t0, 0x0058(t1) */
569 #ifdef TARGET_WORDS_BIGENDIAN
570 stl_raw(p
++, 0x3c083f00); /* lui t0, 0x3f00 */
572 stl_raw(p
++, 0x3408003f); /* ori t0, r0, 0x003f */
574 stl_raw(p
++, 0xad280060); /* sw t0, 0x0060(t1) */
576 #ifdef TARGET_WORDS_BIGENDIAN
577 stl_raw(p
++, 0x3c08c100); /* lui t0, 0xc100 */
579 stl_raw(p
++, 0x340800c1); /* ori t0, r0, 0x00c1 */
581 stl_raw(p
++, 0xad280080); /* sw t0, 0x0080(t1) */
582 #ifdef TARGET_WORDS_BIGENDIAN
583 stl_raw(p
++, 0x3c085e00); /* lui t0, 0x5e00 */
585 stl_raw(p
++, 0x3408005e); /* ori t0, r0, 0x005e */
587 stl_raw(p
++, 0xad280088); /* sw t0, 0x0088(t1) */
589 /* Jump to kernel code */
590 stl_raw(p
++, 0x3c1f0000 | ((kernel_entry
>> 16) & 0xffff)); /* lui ra, high(kernel_entry) */
591 stl_raw(p
++, 0x37ff0000 | (kernel_entry
& 0xffff)); /* ori ra, ra, low(kernel_entry) */
592 stl_raw(p
++, 0x03e00008); /* jr ra */
593 stl_raw(p
++, 0x00000000); /* nop */
595 /* YAMON subroutines */
596 p
= (uint32_t *) (base
+ 0x800);
597 stl_raw(p
++, 0x03e00008); /* jr ra */
598 stl_raw(p
++, 0x24020000); /* li v0,0 */
599 /* 808 YAMON print */
600 stl_raw(p
++, 0x03e06821); /* move t5,ra */
601 stl_raw(p
++, 0x00805821); /* move t3,a0 */
602 stl_raw(p
++, 0x00a05021); /* move t2,a1 */
603 stl_raw(p
++, 0x91440000); /* lbu a0,0(t2) */
604 stl_raw(p
++, 0x254a0001); /* addiu t2,t2,1 */
605 stl_raw(p
++, 0x10800005); /* beqz a0,834 */
606 stl_raw(p
++, 0x00000000); /* nop */
607 stl_raw(p
++, 0x0ff0021c); /* jal 870 */
608 stl_raw(p
++, 0x00000000); /* nop */
609 stl_raw(p
++, 0x08000205); /* j 814 */
610 stl_raw(p
++, 0x00000000); /* nop */
611 stl_raw(p
++, 0x01a00008); /* jr t5 */
612 stl_raw(p
++, 0x01602021); /* move a0,t3 */
613 /* 0x83c YAMON print_count */
614 stl_raw(p
++, 0x03e06821); /* move t5,ra */
615 stl_raw(p
++, 0x00805821); /* move t3,a0 */
616 stl_raw(p
++, 0x00a05021); /* move t2,a1 */
617 stl_raw(p
++, 0x00c06021); /* move t4,a2 */
618 stl_raw(p
++, 0x91440000); /* lbu a0,0(t2) */
619 stl_raw(p
++, 0x0ff0021c); /* jal 870 */
620 stl_raw(p
++, 0x00000000); /* nop */
621 stl_raw(p
++, 0x254a0001); /* addiu t2,t2,1 */
622 stl_raw(p
++, 0x258cffff); /* addiu t4,t4,-1 */
623 stl_raw(p
++, 0x1580fffa); /* bnez t4,84c */
624 stl_raw(p
++, 0x00000000); /* nop */
625 stl_raw(p
++, 0x01a00008); /* jr t5 */
626 stl_raw(p
++, 0x01602021); /* move a0,t3 */
628 stl_raw(p
++, 0x3c08b800); /* lui t0,0xb400 */
629 stl_raw(p
++, 0x350803f8); /* ori t0,t0,0x3f8 */
630 stl_raw(p
++, 0x91090005); /* lbu t1,5(t0) */
631 stl_raw(p
++, 0x00000000); /* nop */
632 stl_raw(p
++, 0x31290040); /* andi t1,t1,0x40 */
633 stl_raw(p
++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
634 stl_raw(p
++, 0x00000000); /* nop */
635 stl_raw(p
++, 0x03e00008); /* jr ra */
636 stl_raw(p
++, 0xa1040000); /* sb a0,0(t0) */
640 static void GCC_FMT_ATTR(3, 4) prom_set(uint32_t* prom_buf
, int index
,
641 const char *string
, ...)
646 if (index
>= ENVP_NB_ENTRIES
)
649 if (string
== NULL
) {
654 table_addr
= sizeof(int32_t) * ENVP_NB_ENTRIES
+ index
* ENVP_ENTRY_SIZE
;
655 prom_buf
[index
] = tswap32(ENVP_ADDR
+ table_addr
);
657 va_start(ap
, string
);
658 vsnprintf((char *)prom_buf
+ table_addr
, ENVP_ENTRY_SIZE
, string
, ap
);
663 static int64_t load_kernel (void)
665 int64_t kernel_entry
, kernel_high
;
667 ram_addr_t initrd_offset
;
673 #ifdef TARGET_WORDS_BIGENDIAN
679 if (load_elf(loaderparams
.kernel_filename
, cpu_mips_kseg0_to_phys
, NULL
,
680 (uint64_t *)&kernel_entry
, NULL
, (uint64_t *)&kernel_high
,
681 big_endian
, ELF_MACHINE
, 1) < 0) {
682 fprintf(stderr
, "qemu: could not load kernel '%s'\n",
683 loaderparams
.kernel_filename
);
690 if (loaderparams
.initrd_filename
) {
691 initrd_size
= get_image_size (loaderparams
.initrd_filename
);
692 if (initrd_size
> 0) {
693 initrd_offset
= (kernel_high
+ ~TARGET_PAGE_MASK
) & TARGET_PAGE_MASK
;
694 if (initrd_offset
+ initrd_size
> ram_size
) {
696 "qemu: memory too small for initial ram disk '%s'\n",
697 loaderparams
.initrd_filename
);
700 initrd_size
= load_image_targphys(loaderparams
.initrd_filename
,
702 ram_size
- initrd_offset
);
704 if (initrd_size
== (target_ulong
) -1) {
705 fprintf(stderr
, "qemu: could not load initial ram disk '%s'\n",
706 loaderparams
.initrd_filename
);
711 /* Setup prom parameters. */
712 prom_size
= ENVP_NB_ENTRIES
* (sizeof(int32_t) + ENVP_ENTRY_SIZE
);
713 prom_buf
= g_malloc(prom_size
);
715 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_filename
);
716 if (initrd_size
> 0) {
717 prom_set(prom_buf
, prom_index
++, "rd_start=0x%" PRIx64
" rd_size=%li %s",
718 cpu_mips_phys_to_kseg0(NULL
, initrd_offset
), initrd_size
,
719 loaderparams
.kernel_cmdline
);
721 prom_set(prom_buf
, prom_index
++, "%s", loaderparams
.kernel_cmdline
);
724 prom_set(prom_buf
, prom_index
++, "memsize");
725 prom_set(prom_buf
, prom_index
++, "%i", loaderparams
.ram_size
);
726 prom_set(prom_buf
, prom_index
++, "modetty0");
727 prom_set(prom_buf
, prom_index
++, "38400n8r");
728 prom_set(prom_buf
, prom_index
++, NULL
);
730 rom_add_blob_fixed("prom", prom_buf
, prom_size
,
731 cpu_mips_kseg0_to_phys(NULL
, ENVP_ADDR
));
736 static void malta_mips_config(CPUState
*env
)
738 env
->mvp
->CP0_MVPConf0
|= ((smp_cpus
- 1) << CP0MVPC0_PVPE
) |
739 ((smp_cpus
* env
->nr_threads
- 1) << CP0MVPC0_PTC
);
742 static void main_cpu_reset(void *opaque
)
744 CPUState
*env
= opaque
;
747 /* The bootloader does not need to be rewritten as it is located in a
748 read only location. The kernel location and the arguments table
749 location does not change. */
750 if (loaderparams
.kernel_filename
) {
751 env
->CP0_Status
&= ~((1 << CP0St_BEV
) | (1 << CP0St_ERL
));
754 malta_mips_config(env
);
757 static void cpu_request_exit(void *opaque
, int irq
, int level
)
759 CPUState
*env
= cpu_single_env
;
767 void mips_malta_init (ram_addr_t ram_size
,
768 const char *boot_device
,
769 const char *kernel_filename
, const char *kernel_cmdline
,
770 const char *initrd_filename
, const char *cpu_model
)
774 ram_addr_t ram_offset
;
775 MemoryRegion
*system_memory
= get_system_memory();
776 MemoryRegion
*bios
, *bios_alias
= g_new(MemoryRegion
, 1);
777 target_long bios_size
;
778 int64_t kernel_entry
;
782 qemu_irq
*cpu_exit_irq
;
787 DriveInfo
*hd
[MAX_IDE_BUS
* MAX_IDE_DEVS
];
788 DriveInfo
*fd
[MAX_FD
];
793 /* Make sure the first 3 serial ports are associated with a device. */
794 for(i
= 0; i
< 3; i
++) {
795 if (!serial_hds
[i
]) {
797 snprintf(label
, sizeof(label
), "serial%d", i
);
798 serial_hds
[i
] = qemu_chr_new(label
, "null", NULL
);
803 if (cpu_model
== NULL
) {
811 for (i
= 0; i
< smp_cpus
; i
++) {
812 env
= cpu_init(cpu_model
);
814 fprintf(stderr
, "Unable to find CPU definition\n");
817 /* Init internal devices */
818 cpu_mips_irq_init_cpu(env
);
819 cpu_mips_clock_init(env
);
820 qemu_register_reset(main_cpu_reset
, env
);
825 if (ram_size
> (256 << 20)) {
827 "qemu: Too much memory for this machine: %d MB, maximum 256 MB\n",
828 ((unsigned int)ram_size
/ (1 << 20)));
831 ram_offset
= qemu_ram_alloc(NULL
, "mips_malta.ram", ram_size
);
833 cpu_register_physical_memory(0, ram_size
, ram_offset
| IO_MEM_RAM
);
835 #ifdef TARGET_WORDS_BIGENDIAN
841 malta_fpga_init(0x1f000000LL
, env
->irq
[2], serial_hds
[2]);
843 /* Load firmware in flash / BIOS unless we boot directly into a kernel. */
844 if (kernel_filename
) {
845 /* Write a small bootloader to the flash location. */
846 bios
= g_new(MemoryRegion
, 1);
847 memory_region_init_ram(bios
, NULL
, "mips_malta.bios", BIOS_SIZE
);
848 memory_region_set_readonly(bios
, true);
849 memory_region_init_alias(bios_alias
, "bios.1fc", bios
, 0, BIOS_SIZE
);
850 /* Map the bios at two physical locations, as on the real board. */
851 memory_region_add_subregion(system_memory
, 0x1e000000LL
, bios
);
852 memory_region_add_subregion(system_memory
, 0x1fc00000LL
, bios_alias
);
853 loaderparams
.ram_size
= ram_size
;
854 loaderparams
.kernel_filename
= kernel_filename
;
855 loaderparams
.kernel_cmdline
= kernel_cmdline
;
856 loaderparams
.initrd_filename
= initrd_filename
;
857 kernel_entry
= load_kernel();
858 write_bootloader(env
, memory_region_get_ram_ptr(bios
), kernel_entry
);
860 dinfo
= drive_get(IF_PFLASH
, 0, fl_idx
);
862 /* Load firmware from flash. */
863 bios_size
= 0x400000;
864 fl_sectors
= bios_size
>> 16;
865 #ifdef DEBUG_BOARD_INIT
866 printf("Register parallel flash %d size " TARGET_FMT_lx
" at "
867 "addr %08llx '%s' %x\n",
868 fl_idx
, bios_size
, 0x1e000000LL
,
869 bdrv_get_device_name(dinfo
->bdrv
), fl_sectors
);
871 fl
= pflash_cfi01_register(0x1e000000LL
,
872 NULL
, "mips_malta.bios", BIOS_SIZE
,
873 dinfo
->bdrv
, 65536, fl_sectors
,
874 4, 0x0000, 0x0000, 0x0000, 0x0000, be
);
875 bios
= pflash_cfi01_get_memory(fl
);
876 /* Map the bios at two physical locations, as on the real board. */
877 memory_region_init_alias(bios_alias
, "bios.1fc",
879 memory_region_add_subregion(system_memory
, 0x1fc00000LL
,
883 bios
= g_new(MemoryRegion
, 1);
884 memory_region_init_ram(bios
, NULL
, "mips_malta.bios", BIOS_SIZE
);
885 memory_region_set_readonly(bios
, true);
886 memory_region_init_alias(bios_alias
, "bios.1fc",
888 /* Map the bios at two physical locations, as on the real board. */
889 memory_region_add_subregion(system_memory
, 0x1e000000LL
, bios
);
890 memory_region_add_subregion(system_memory
, 0x1fc00000LL
,
892 /* Load a BIOS image. */
893 if (bios_name
== NULL
)
894 bios_name
= BIOS_FILENAME
;
895 filename
= qemu_find_file(QEMU_FILE_TYPE_BIOS
, bios_name
);
897 bios_size
= load_image_targphys(filename
, 0x1fc00000LL
,
903 if ((bios_size
< 0 || bios_size
> BIOS_SIZE
) && !kernel_filename
) {
905 "qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
910 /* In little endian mode the 32bit words in the bios are swapped,
911 a neat trick which allows bi-endian firmware. */
912 #ifndef TARGET_WORDS_BIGENDIAN
914 uint32_t *addr
= memory_region_get_ram_ptr(bios
);
915 uint32_t *end
= addr
+ bios_size
;
923 /* Board ID = 0x420 (Malta Board with CoreLV)
924 XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
925 map to the board ID. */
926 stl_p(memory_region_get_ram_ptr(bios
) + 0x10, 0x00000420);
928 /* Init internal devices */
929 cpu_mips_irq_init_cpu(env
);
930 cpu_mips_clock_init(env
);
932 /* Interrupt controller */
933 /* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
934 i8259
= i8259_init(env
->irq
[2]);
937 pci_bus
= gt64120_register(i8259
);
940 ide_drive_get(hd
, MAX_IDE_BUS
);
942 piix4_devfn
= piix4_init(pci_bus
, 80);
944 pci_piix4_ide_init(pci_bus
, hd
, piix4_devfn
+ 1);
945 usb_uhci_piix4_init(pci_bus
, piix4_devfn
+ 2);
946 smbus
= piix4_pm_init(pci_bus
, piix4_devfn
+ 3, 0x1100, isa_get_irq(9),
948 /* TODO: Populate SPD eeprom data. */
949 smbus_eeprom_init(smbus
, 8, NULL
, 0);
950 pit
= pit_init(0x40, 0);
951 cpu_exit_irq
= qemu_allocate_irqs(cpu_request_exit
, NULL
, 1);
952 DMA_init(0, cpu_exit_irq
);
955 isa_create_simple("i8042");
957 rtc_init(2000, NULL
);
958 serial_isa_init(0, serial_hds
[0]);
959 serial_isa_init(1, serial_hds
[1]);
961 parallel_init(0, parallel_hds
[0]);
962 for(i
= 0; i
< MAX_FD
; i
++) {
963 fd
[i
] = drive_get(IF_FLOPPY
, 0, i
);
968 audio_init(NULL
, pci_bus
);
973 /* Optional PCI video card */
974 if (cirrus_vga_enabled
) {
975 pci_cirrus_vga_init(pci_bus
);
976 } else if (vmsvga_enabled
) {
977 if (!pci_vmsvga_init(pci_bus
)) {
978 fprintf(stderr
, "Warning: vmware_vga not available,"
979 " using standard VGA instead\n");
980 pci_vga_init(pci_bus
);
982 } else if (std_vga_enabled
) {
983 pci_vga_init(pci_bus
);
987 static QEMUMachine mips_malta_machine
= {
989 .desc
= "MIPS Malta Core LV",
990 .init
= mips_malta_init
,
995 static void mips_malta_machine_init(void)
997 qemu_register_machine(&mips_malta_machine
);
1000 machine_init(mips_malta_machine_init
);