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x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES
[qemu.git] / target / i386 / kvm.c
blob796a049a0dc97bb658789ba0585a9f5f50fdbc62
1 /*
2 * QEMU KVM support
3 *
4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
6 *
7 * Authors:
8 * Anthony Liguori <aliguori@us.ibm.com>
9 *
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
12 *
13 */
14
15 #include "qemu/osdep.h"
16 #include "qapi/error.h"
17 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
19
20 #include <linux/kvm.h>
21 #include "standard-headers/asm-x86/kvm_para.h"
22
23 #include "qemu-common.h"
24 #include "cpu.h"
25 #include "sysemu/sysemu.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/kvm_int.h"
28 #include "kvm_i386.h"
29 #include "hyperv.h"
30 #include "hyperv-proto.h"
31
32 #include "exec/gdbstub.h"
33 #include "qemu/host-utils.h"
34 #include "qemu/config-file.h"
35 #include "qemu/error-report.h"
36 #include "hw/i386/pc.h"
37 #include "hw/i386/apic.h"
38 #include "hw/i386/apic_internal.h"
39 #include "hw/i386/apic-msidef.h"
40 #include "hw/i386/intel_iommu.h"
41 #include "hw/i386/x86-iommu.h"
42
43 #include "hw/pci/pci.h"
44 #include "hw/pci/msi.h"
45 #include "hw/pci/msix.h"
46 #include "migration/blocker.h"
47 #include "exec/memattrs.h"
48 #include "trace.h"
49
50 //#define DEBUG_KVM
51
52 #ifdef DEBUG_KVM
53 #define DPRINTF(fmt, ...) \
54 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
55 #else
56 #define DPRINTF(fmt, ...) \
57 do { } while (0)
58 #endif
59
60 #define MSR_KVM_WALL_CLOCK 0x11
61 #define MSR_KVM_SYSTEM_TIME 0x12
62
63 /* A 4096-byte buffer can hold the 8-byte kvm_msrs header, plus
64 * 255 kvm_msr_entry structs */
65 #define MSR_BUF_SIZE 4096
66
67 const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
68 KVM_CAP_INFO(SET_TSS_ADDR),
69 KVM_CAP_INFO(EXT_CPUID),
70 KVM_CAP_INFO(MP_STATE),
71 KVM_CAP_LAST_INFO
72 };
73
74 static bool has_msr_star;
75 static bool has_msr_hsave_pa;
76 static bool has_msr_tsc_aux;
77 static bool has_msr_tsc_adjust;
78 static bool has_msr_tsc_deadline;
79 static bool has_msr_feature_control;
80 static bool has_msr_misc_enable;
81 static bool has_msr_smbase;
82 static bool has_msr_bndcfgs;
83 static int lm_capable_kernel;
84 static bool has_msr_hv_hypercall;
85 static bool has_msr_hv_crash;
86 static bool has_msr_hv_reset;
87 static bool has_msr_hv_vpindex;
88 static bool hv_vpindex_settable;
89 static bool has_msr_hv_runtime;
90 static bool has_msr_hv_synic;
91 static bool has_msr_hv_stimer;
92 static bool has_msr_hv_frequencies;
93 static bool has_msr_hv_reenlightenment;
94 static bool has_msr_xss;
95 static bool has_msr_spec_ctrl;
96 static bool has_msr_virt_ssbd;
97 static bool has_msr_smi_count;
98
99 static uint32_t has_architectural_pmu_version;
100 static uint32_t num_architectural_pmu_gp_counters;
101 static uint32_t num_architectural_pmu_fixed_counters;
102
103 static int has_xsave;
104 static int has_xcrs;
105 static int has_pit_state2;
106
107 static bool has_msr_mcg_ext_ctl;
108
109 static struct kvm_cpuid2 *cpuid_cache;
110 static struct kvm_msr_list *kvm_feature_msrs;
111
112 int kvm_has_pit_state2(void)
113 {
114 return has_pit_state2;
115 }
116
117 bool kvm_has_smm(void)
118 {
119 return kvm_check_extension(kvm_state, KVM_CAP_X86_SMM);
120 }
121
122 bool kvm_has_adjust_clock_stable(void)
123 {
124 int ret = kvm_check_extension(kvm_state, KVM_CAP_ADJUST_CLOCK);
125
126 return (ret == KVM_CLOCK_TSC_STABLE);
127 }
128
129 bool kvm_allows_irq0_override(void)
130 {
131 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
132 }
133
134 static bool kvm_x2apic_api_set_flags(uint64_t flags)
135 {
136 KVMState *s = KVM_STATE(current_machine->accelerator);
137
138 return !kvm_vm_enable_cap(s, KVM_CAP_X2APIC_API, 0, flags);
139 }
140
141 #define MEMORIZE(fn, _result) \
142 ({ \
143 static bool _memorized; \
144 \
145 if (_memorized) { \
146 return _result; \
147 } \
148 _memorized = true; \
149 _result = fn; \
150 })
151
152 static bool has_x2apic_api;
153
154 bool kvm_has_x2apic_api(void)
155 {
156 return has_x2apic_api;
157 }
158
159 bool kvm_enable_x2apic(void)
160 {
161 return MEMORIZE(
162 kvm_x2apic_api_set_flags(KVM_X2APIC_API_USE_32BIT_IDS |
163 KVM_X2APIC_API_DISABLE_BROADCAST_QUIRK),
164 has_x2apic_api);
165 }
166
167 bool kvm_hv_vpindex_settable(void)
168 {
169 return hv_vpindex_settable;
170 }
171
172 static int kvm_get_tsc(CPUState *cs)
173 {
174 X86CPU *cpu = X86_CPU(cs);
175 CPUX86State *env = &cpu->env;
176 struct {
177 struct kvm_msrs info;
178 struct kvm_msr_entry entries[1];
179 } msr_data;
180 int ret;
181
182 if (env->tsc_valid) {
183 return 0;
184 }
185
186 msr_data.info.nmsrs = 1;
187 msr_data.entries[0].index = MSR_IA32_TSC;
188 env->tsc_valid = !runstate_is_running();
189
190 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, &msr_data);
191 if (ret < 0) {
192 return ret;
193 }
194
195 assert(ret == 1);
196 env->tsc = msr_data.entries[0].data;
197 return 0;
198 }
199
200 static inline void do_kvm_synchronize_tsc(CPUState *cpu, run_on_cpu_data arg)
201 {
202 kvm_get_tsc(cpu);
203 }
204
205 void kvm_synchronize_all_tsc(void)
206 {
207 CPUState *cpu;
208
209 if (kvm_enabled()) {
210 CPU_FOREACH(cpu) {
211 run_on_cpu(cpu, do_kvm_synchronize_tsc, RUN_ON_CPU_NULL);
212 }
213 }
214 }
215
216 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
217 {
218 struct kvm_cpuid2 *cpuid;
219 int r, size;
220
221 size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
222 cpuid = g_malloc0(size);
223 cpuid->nent = max;
224 r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
225 if (r == 0 && cpuid->nent >= max) {
226 r = -E2BIG;
227 }
228 if (r < 0) {
229 if (r == -E2BIG) {
230 g_free(cpuid);
231 return NULL;
232 } else {
233 fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
234 strerror(-r));
235 exit(1);
236 }
237 }
238 return cpuid;
239 }
240
241 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
242 * for all entries.
243 */
244 static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)
245 {
246 struct kvm_cpuid2 *cpuid;
247 int max = 1;
248
249 if (cpuid_cache != NULL) {
250 return cpuid_cache;
251 }
252 while ((cpuid = try_get_cpuid(s, max)) == NULL) {
253 max *= 2;
254 }
255 cpuid_cache = cpuid;
256 return cpuid;
257 }
258
259 static const struct kvm_para_features {
260 int cap;
261 int feature;
262 } para_features[] = {
263 { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
264 { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
265 { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
266 { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },
267 };
268
269 static int get_para_features(KVMState *s)
270 {
271 int i, features = 0;
272
273 for (i = 0; i < ARRAY_SIZE(para_features); i++) {
274 if (kvm_check_extension(s, para_features[i].cap)) {
275 features |= (1 << para_features[i].feature);
276 }
277 }
278
279 return features;
280 }
281
282 static bool host_tsx_blacklisted(void)
283 {
284 int family, model, stepping;\
285 char vendor[CPUID_VENDOR_SZ + 1];
286
287 host_vendor_fms(vendor, &family, &model, &stepping);
288
289 /* Check if we are running on a Haswell host known to have broken TSX */
290 return !strcmp(vendor, CPUID_VENDOR_INTEL) &&
291 (family == 6) &&
292 ((model == 63 && stepping < 4) ||
293 model == 60 || model == 69 || model == 70);
294 }
295
296 /* Returns the value for a specific register on the cpuid entry
297 */
298 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)
299 {
300 uint32_t ret = 0;
301 switch (reg) {
302 case R_EAX:
303 ret = entry->eax;
304 break;
305 case R_EBX:
306 ret = entry->ebx;
307 break;
308 case R_ECX:
309 ret = entry->ecx;
310 break;
311 case R_EDX:
312 ret = entry->edx;
313 break;
314 }
315 return ret;
316 }
317
318 /* Find matching entry for function/index on kvm_cpuid2 struct
319 */
320 static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,
321 uint32_t function,
322 uint32_t index)
323 {
324 int i;
325 for (i = 0; i < cpuid->nent; ++i) {
326 if (cpuid->entries[i].function == function &&
327 cpuid->entries[i].index == index) {
328 return &cpuid->entries[i];
329 }
330 }
331 /* not found: */
332 return NULL;
333 }
334
335 uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,
336 uint32_t index, int reg)
337 {
338 struct kvm_cpuid2 *cpuid;
339 uint32_t ret = 0;
340 uint32_t cpuid_1_edx;
341 bool found = false;
342
343 cpuid = get_supported_cpuid(s);
344
345 struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);
346 if (entry) {
347 found = true;
348 ret = cpuid_entry_get_reg(entry, reg);
349 }
350
351 /* Fixups for the data returned by KVM, below */
352
353 if (function == 1 && reg == R_EDX) {
354 /* KVM before 2.6.30 misreports the following features */
355 ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
356 } else if (function == 1 && reg == R_ECX) {
357 /* We can set the hypervisor flag, even if KVM does not return it on
358 * GET_SUPPORTED_CPUID
359 */
360 ret |= CPUID_EXT_HYPERVISOR;
361 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
362 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
363 * and the irqchip is in the kernel.
364 */
365 if (kvm_irqchip_in_kernel() &&
366 kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {
367 ret |= CPUID_EXT_TSC_DEADLINE_TIMER;
368 }
369
370 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
371 * without the in-kernel irqchip
372 */
373 if (!kvm_irqchip_in_kernel()) {
374 ret &= ~CPUID_EXT_X2APIC;
375 }
376
377 if (enable_cpu_pm) {
378 int disable_exits = kvm_check_extension(s,
379 KVM_CAP_X86_DISABLE_EXITS);
380
381 if (disable_exits & KVM_X86_DISABLE_EXITS_MWAIT) {
382 ret |= CPUID_EXT_MONITOR;
383 }
384 }
385 } else if (function == 6 && reg == R_EAX) {
386 ret |= CPUID_6_EAX_ARAT; /* safe to allow because of emulated APIC */
387 } else if (function == 7 && index == 0 && reg == R_EBX) {
388 if (host_tsx_blacklisted()) {
389 ret &= ~(CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_HLE);
390 }
391 } else if (function == 0x80000001 && reg == R_ECX) {
392 /*
393 * It's safe to enable TOPOEXT even if it's not returned by
394 * GET_SUPPORTED_CPUID. Unconditionally enabling TOPOEXT here allows
395 * us to keep CPU models including TOPOEXT runnable on older kernels.
396 */
397 ret |= CPUID_EXT3_TOPOEXT;
398 } else if (function == 0x80000001 && reg == R_EDX) {
399 /* On Intel, kvm returns cpuid according to the Intel spec,
400 * so add missing bits according to the AMD spec:
401 */
402 cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);
403 ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;
404 } else if (function == KVM_CPUID_FEATURES && reg == R_EAX) {
405 /* kvm_pv_unhalt is reported by GET_SUPPORTED_CPUID, but it can't
406 * be enabled without the in-kernel irqchip
407 */
408 if (!kvm_irqchip_in_kernel()) {
409 ret &= ~(1U << KVM_FEATURE_PV_UNHALT);
410 }
411 } else if (function == KVM_CPUID_FEATURES && reg == R_EDX) {
412 ret |= 1U << KVM_HINTS_REALTIME;
413 found = 1;
414 }
415
416 /* fallback for older kernels */
417 if ((function == KVM_CPUID_FEATURES) && !found) {
418 ret = get_para_features(s);
419 }
420
421 return ret;
422 }
423
424 uint32_t kvm_arch_get_supported_msr_feature(KVMState *s, uint32_t index)
425 {
426 struct {
427 struct kvm_msrs info;
428 struct kvm_msr_entry entries[1];
429 } msr_data;
430 uint32_t ret;
431
432 if (kvm_feature_msrs == NULL) { /* Host doesn't support feature MSRs */
433 return 0;
434 }
435
436 /* Check if requested MSR is supported feature MSR */
437 int i;
438 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
439 if (kvm_feature_msrs->indices[i] == index) {
440 break;
441 }
442 if (i == kvm_feature_msrs->nmsrs) {
443 return 0; /* if the feature MSR is not supported, simply return 0 */
444 }
445
446 msr_data.info.nmsrs = 1;
447 msr_data.entries[0].index = index;
448
449 ret = kvm_ioctl(s, KVM_GET_MSRS, &msr_data);
450 if (ret != 1) {
451 error_report("KVM get MSR (index=0x%x) feature failed, %s",
452 index, strerror(-ret));
453 exit(1);
454 }
455
456 return msr_data.entries[0].data;
457 }
458
459
460 typedef struct HWPoisonPage {
461 ram_addr_t ram_addr;
462 QLIST_ENTRY(HWPoisonPage) list;
463 } HWPoisonPage;
464
465 static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =
466 QLIST_HEAD_INITIALIZER(hwpoison_page_list);
467
468 static void kvm_unpoison_all(void *param)
469 {
470 HWPoisonPage *page, *next_page;
471
472 QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {
473 QLIST_REMOVE(page, list);
474 qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);
475 g_free(page);
476 }
477 }
478
479 static void kvm_hwpoison_page_add(ram_addr_t ram_addr)
480 {
481 HWPoisonPage *page;
482
483 QLIST_FOREACH(page, &hwpoison_page_list, list) {
484 if (page->ram_addr == ram_addr) {
485 return;
486 }
487 }
488 page = g_new(HWPoisonPage, 1);
489 page->ram_addr = ram_addr;
490 QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);
491 }
492
493 static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,
494 int *max_banks)
495 {
496 int r;
497
498 r = kvm_check_extension(s, KVM_CAP_MCE);
499 if (r > 0) {
500 *max_banks = r;
501 return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);
502 }
503 return -ENOSYS;
504 }
505
506 static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)
507 {
508 CPUState *cs = CPU(cpu);
509 CPUX86State *env = &cpu->env;
510 uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
511 MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;
512 uint64_t mcg_status = MCG_STATUS_MCIP;
513 int flags = 0;
514
515 if (code == BUS_MCEERR_AR) {
516 status |= MCI_STATUS_AR | 0x134;
517 mcg_status |= MCG_STATUS_EIPV;
518 } else {
519 status |= 0xc0;
520 mcg_status |= MCG_STATUS_RIPV;
521 }
522
523 flags = cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0;
524 /* We need to read back the value of MSR_EXT_MCG_CTL that was set by the
525 * guest kernel back into env->mcg_ext_ctl.
526 */
527 cpu_synchronize_state(cs);
528 if (env->mcg_ext_ctl & MCG_EXT_CTL_LMCE_EN) {
529 mcg_status |= MCG_STATUS_LMCE;
530 flags = 0;
531 }
532
533 cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,
534 (MCM_ADDR_PHYS << 6) | 0xc, flags);
535 }
536
537 static void hardware_memory_error(void)
538 {
539 fprintf(stderr, "Hardware memory error!\n");
540 exit(1);
541 }
542
543 void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)
544 {
545 X86CPU *cpu = X86_CPU(c);
546 CPUX86State *env = &cpu->env;
547 ram_addr_t ram_addr;
548 hwaddr paddr;
549
550 /* If we get an action required MCE, it has been injected by KVM
551 * while the VM was running. An action optional MCE instead should
552 * be coming from the main thread, which qemu_init_sigbus identifies
553 * as the "early kill" thread.
554 */
555 assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO);
556
557 if ((env->mcg_cap & MCG_SER_P) && addr) {
558 ram_addr = qemu_ram_addr_from_host(addr);
559 if (ram_addr != RAM_ADDR_INVALID &&
560 kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {
561 kvm_hwpoison_page_add(ram_addr);
562 kvm_mce_inject(cpu, paddr, code);
563 return;
564 }
565
566 fprintf(stderr, "Hardware memory error for memory used by "
567 "QEMU itself instead of guest system!\n");
568 }
569
570 if (code == BUS_MCEERR_AR) {
571 hardware_memory_error();
572 }
573
574 /* Hope we are lucky for AO MCE */
575 }
576
577 static int kvm_inject_mce_oldstyle(X86CPU *cpu)
578 {
579 CPUX86State *env = &cpu->env;
580
581 if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {
582 unsigned int bank, bank_num = env->mcg_cap & 0xff;
583 struct kvm_x86_mce mce;
584
585 env->exception_injected = -1;
586
587 /*
588 * There must be at least one bank in use if an MCE is pending.
589 * Find it and use its values for the event injection.
590 */
591 for (bank = 0; bank < bank_num; bank++) {
592 if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {
593 break;
594 }
595 }
596 assert(bank < bank_num);
597
598 mce.bank = bank;
599 mce.status = env->mce_banks[bank * 4 + 1];
600 mce.mcg_status = env->mcg_status;
601 mce.addr = env->mce_banks[bank * 4 + 2];
602 mce.misc = env->mce_banks[bank * 4 + 3];
603
604 return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);
605 }
606 return 0;
607 }
608
609 static void cpu_update_state(void *opaque, int running, RunState state)
610 {
611 CPUX86State *env = opaque;
612
613 if (running) {
614 env->tsc_valid = false;
615 }
616 }
617
618 unsigned long kvm_arch_vcpu_id(CPUState *cs)
619 {
620 X86CPU *cpu = X86_CPU(cs);
621 return cpu->apic_id;
622 }
623
624 #ifndef KVM_CPUID_SIGNATURE_NEXT
625 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
626 #endif
627
628 static bool hyperv_hypercall_available(X86CPU *cpu)
629 {
630 return cpu->hyperv_vapic ||
631 (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);
632 }
633
634 static bool hyperv_enabled(X86CPU *cpu)
635 {
636 CPUState *cs = CPU(cpu);
637 return kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV) > 0 &&
638 (hyperv_hypercall_available(cpu) ||
639 cpu->hyperv_time ||
640 cpu->hyperv_relaxed_timing ||
641 cpu->hyperv_crash ||
642 cpu->hyperv_reset ||
643 cpu->hyperv_vpindex ||
644 cpu->hyperv_runtime ||
645 cpu->hyperv_synic ||
646 cpu->hyperv_stimer ||
647 cpu->hyperv_reenlightenment ||
648 cpu->hyperv_tlbflush ||
649 cpu->hyperv_ipi);
650 }
651
652 static int kvm_arch_set_tsc_khz(CPUState *cs)
653 {
654 X86CPU *cpu = X86_CPU(cs);
655 CPUX86State *env = &cpu->env;
656 int r;
657
658 if (!env->tsc_khz) {
659 return 0;
660 }
661
662 r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL) ?
663 kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz) :
664 -ENOTSUP;
665 if (r < 0) {
666 /* When KVM_SET_TSC_KHZ fails, it's an error only if the current
667 * TSC frequency doesn't match the one we want.
668 */
669 int cur_freq = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
670 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
671 -ENOTSUP;
672 if (cur_freq <= 0 || cur_freq != env->tsc_khz) {
673 warn_report("TSC frequency mismatch between "
674 "VM (%" PRId64 " kHz) and host (%d kHz), "
675 "and TSC scaling unavailable",
676 env->tsc_khz, cur_freq);
677 return r;
678 }
679 }
680
681 return 0;
682 }
683
684 static bool tsc_is_stable_and_known(CPUX86State *env)
685 {
686 if (!env->tsc_khz) {
687 return false;
688 }
689 return (env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC)
690 || env->user_tsc_khz;
691 }
692
693 static int hyperv_handle_properties(CPUState *cs)
694 {
695 X86CPU *cpu = X86_CPU(cs);
696 CPUX86State *env = &cpu->env;
697
698 if (cpu->hyperv_relaxed_timing) {
699 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
700 }
701 if (cpu->hyperv_vapic) {
702 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
703 env->features[FEAT_HYPERV_EAX] |= HV_APIC_ACCESS_AVAILABLE;
704 }
705 if (cpu->hyperv_time) {
706 if (kvm_check_extension(cs->kvm_state, KVM_CAP_HYPERV_TIME) <= 0) {
707 fprintf(stderr, "Hyper-V clocksources "
708 "(requested by 'hv-time' cpu flag) "
709 "are not supported by kernel\n");
710 return -ENOSYS;
711 }
712 env->features[FEAT_HYPERV_EAX] |= HV_HYPERCALL_AVAILABLE;
713 env->features[FEAT_HYPERV_EAX] |= HV_TIME_REF_COUNT_AVAILABLE;
714 env->features[FEAT_HYPERV_EAX] |= HV_REFERENCE_TSC_AVAILABLE;
715 }
716 if (cpu->hyperv_frequencies) {
717 if (!has_msr_hv_frequencies) {
718 fprintf(stderr, "Hyper-V frequency MSRs "
719 "(requested by 'hv-frequencies' cpu flag) "
720 "are not supported by kernel\n");
721 return -ENOSYS;
722 }
723 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_FREQUENCY_MSRS;
724 env->features[FEAT_HYPERV_EDX] |= HV_FREQUENCY_MSRS_AVAILABLE;
725 }
726 if (cpu->hyperv_crash) {
727 if (!has_msr_hv_crash) {
728 fprintf(stderr, "Hyper-V crash MSRs "
729 "(requested by 'hv-crash' cpu flag) "
730 "are not supported by kernel\n");
731 return -ENOSYS;
732 }
733 env->features[FEAT_HYPERV_EDX] |= HV_GUEST_CRASH_MSR_AVAILABLE;
734 }
735 if (cpu->hyperv_reenlightenment) {
736 if (!has_msr_hv_reenlightenment) {
737 fprintf(stderr,
738 "Hyper-V Reenlightenment MSRs "
739 "(requested by 'hv-reenlightenment' cpu flag) "
740 "are not supported by kernel\n");
741 return -ENOSYS;
742 }
743 env->features[FEAT_HYPERV_EAX] |= HV_ACCESS_REENLIGHTENMENTS_CONTROL;
744 }
745 env->features[FEAT_HYPERV_EDX] |= HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE;
746 if (cpu->hyperv_reset) {
747 if (!has_msr_hv_reset) {
748 fprintf(stderr, "Hyper-V reset MSR "
749 "(requested by 'hv-reset' cpu flag) "
750 "is not supported by kernel\n");
751 return -ENOSYS;
752 }
753 env->features[FEAT_HYPERV_EAX] |= HV_RESET_AVAILABLE;
754 }
755 if (cpu->hyperv_vpindex) {
756 if (!has_msr_hv_vpindex) {
757 fprintf(stderr, "Hyper-V VP_INDEX MSR "
758 "(requested by 'hv-vpindex' cpu flag) "
759 "is not supported by kernel\n");
760 return -ENOSYS;
761 }
762 env->features[FEAT_HYPERV_EAX] |= HV_VP_INDEX_AVAILABLE;
763 }
764 if (cpu->hyperv_runtime) {
765 if (!has_msr_hv_runtime) {
766 fprintf(stderr, "Hyper-V VP_RUNTIME MSR "
767 "(requested by 'hv-runtime' cpu flag) "
768 "is not supported by kernel\n");
769 return -ENOSYS;
770 }
771 env->features[FEAT_HYPERV_EAX] |= HV_VP_RUNTIME_AVAILABLE;
772 }
773 if (cpu->hyperv_synic) {
774 unsigned int cap = KVM_CAP_HYPERV_SYNIC;
775 if (!cpu->hyperv_synic_kvm_only) {
776 if (!cpu->hyperv_vpindex) {
777 fprintf(stderr, "Hyper-V SynIC "
778 "(requested by 'hv-synic' cpu flag) "
779 "requires Hyper-V VP_INDEX ('hv-vpindex')\n");
780 return -ENOSYS;
781 }
782 cap = KVM_CAP_HYPERV_SYNIC2;
783 }
784
785 if (!has_msr_hv_synic || !kvm_check_extension(cs->kvm_state, cap)) {
786 fprintf(stderr, "Hyper-V SynIC (requested by 'hv-synic' cpu flag) "
787 "is not supported by kernel\n");
788 return -ENOSYS;
789 }
790
791 env->features[FEAT_HYPERV_EAX] |= HV_SYNIC_AVAILABLE;
792 }
793 if (cpu->hyperv_stimer) {
794 if (!has_msr_hv_stimer) {
795 fprintf(stderr, "Hyper-V timers aren't supported by kernel\n");
796 return -ENOSYS;
797 }
798 env->features[FEAT_HYPERV_EAX] |= HV_SYNTIMERS_AVAILABLE;
799 }
800 return 0;
801 }
802
803 static int hyperv_init_vcpu(X86CPU *cpu)
804 {
805 CPUState *cs = CPU(cpu);
806 int ret;
807
808 if (cpu->hyperv_vpindex && !hv_vpindex_settable) {
809 /*
810 * the kernel doesn't support setting vp_index; assert that its value
811 * is in sync
812 */
813 struct {
814 struct kvm_msrs info;
815 struct kvm_msr_entry entries[1];
816 } msr_data = {
817 .info.nmsrs = 1,
818 .entries[0].index = HV_X64_MSR_VP_INDEX,
819 };
820
821 ret = kvm_vcpu_ioctl(cs, KVM_GET_MSRS, &msr_data);
822 if (ret < 0) {
823 return ret;
824 }
825 assert(ret == 1);
826
827 if (msr_data.entries[0].data != hyperv_vp_index(CPU(cpu))) {
828 error_report("kernel's vp_index != QEMU's vp_index");
829 return -ENXIO;
830 }
831 }
832
833 if (cpu->hyperv_synic) {
834 uint32_t synic_cap = cpu->hyperv_synic_kvm_only ?
835 KVM_CAP_HYPERV_SYNIC : KVM_CAP_HYPERV_SYNIC2;
836 ret = kvm_vcpu_enable_cap(cs, synic_cap, 0);
837 if (ret < 0) {
838 error_report("failed to turn on HyperV SynIC in KVM: %s",
839 strerror(-ret));
840 return ret;
841 }
842
843 if (!cpu->hyperv_synic_kvm_only) {
844 ret = hyperv_x86_synic_add(cpu);
845 if (ret < 0) {
846 error_report("failed to create HyperV SynIC: %s",
847 strerror(-ret));
848 return ret;
849 }
850 }
851 }
852
853 return 0;
854 }
855
856 static Error *invtsc_mig_blocker;
857
858 #define KVM_MAX_CPUID_ENTRIES 100
859
860 int kvm_arch_init_vcpu(CPUState *cs)
861 {
862 struct {
863 struct kvm_cpuid2 cpuid;
864 struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];
865 } QEMU_PACKED cpuid_data;
866 X86CPU *cpu = X86_CPU(cs);
867 CPUX86State *env = &cpu->env;
868 uint32_t limit, i, j, cpuid_i;
869 uint32_t unused;
870 struct kvm_cpuid_entry2 *c;
871 uint32_t signature[3];
872 int kvm_base = KVM_CPUID_SIGNATURE;
873 int r;
874 Error *local_err = NULL;
875
876 memset(&cpuid_data, 0, sizeof(cpuid_data));
877
878 cpuid_i = 0;
879
880 r = kvm_arch_set_tsc_khz(cs);
881 if (r < 0) {
882 goto fail;
883 }
884
885 /* vcpu's TSC frequency is either specified by user, or following
886 * the value used by KVM if the former is not present. In the
887 * latter case, we query it from KVM and record in env->tsc_khz,
888 * so that vcpu's TSC frequency can be migrated later via this field.
889 */
890 if (!env->tsc_khz) {
891 r = kvm_check_extension(cs->kvm_state, KVM_CAP_GET_TSC_KHZ) ?
892 kvm_vcpu_ioctl(cs, KVM_GET_TSC_KHZ) :
893 -ENOTSUP;
894 if (r > 0) {
895 env->tsc_khz = r;
896 }
897 }
898
899 /* Paravirtualization CPUIDs */
900 if (hyperv_enabled(cpu)) {
901 c = &cpuid_data.entries[cpuid_i++];
902 c->function = HV_CPUID_VENDOR_AND_MAX_FUNCTIONS;
903 if (!cpu->hyperv_vendor_id) {
904 memcpy(signature, "Microsoft Hv", 12);
905 } else {
906 size_t len = strlen(cpu->hyperv_vendor_id);
907
908 if (len > 12) {
909 error_report("hv-vendor-id truncated to 12 characters");
910 len = 12;
911 }
912 memset(signature, 0, 12);
913 memcpy(signature, cpu->hyperv_vendor_id, len);
914 }
915 c->eax = HV_CPUID_MIN;
916 c->ebx = signature[0];
917 c->ecx = signature[1];
918 c->edx = signature[2];
919
920 c = &cpuid_data.entries[cpuid_i++];
921 c->function = HV_CPUID_INTERFACE;
922 memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);
923 c->eax = signature[0];
924 c->ebx = 0;
925 c->ecx = 0;
926 c->edx = 0;
927
928 c = &cpuid_data.entries[cpuid_i++];
929 c->function = HV_CPUID_VERSION;
930 c->eax = 0x00001bbc;
931 c->ebx = 0x00060001;
932
933 c = &cpuid_data.entries[cpuid_i++];
934 c->function = HV_CPUID_FEATURES;
935 r = hyperv_handle_properties(cs);
936 if (r) {
937 return r;
938 }
939 c->eax = env->features[FEAT_HYPERV_EAX];
940 c->ebx = env->features[FEAT_HYPERV_EBX];
941 c->edx = env->features[FEAT_HYPERV_EDX];
942
943 c = &cpuid_data.entries[cpuid_i++];
944 c->function = HV_CPUID_ENLIGHTMENT_INFO;
945 if (cpu->hyperv_relaxed_timing) {
946 c->eax |= HV_RELAXED_TIMING_RECOMMENDED;
947 }
948 if (cpu->hyperv_vapic) {
949 c->eax |= HV_APIC_ACCESS_RECOMMENDED;
950 }
951 if (cpu->hyperv_tlbflush) {
952 if (kvm_check_extension(cs->kvm_state,
953 KVM_CAP_HYPERV_TLBFLUSH) <= 0) {
954 fprintf(stderr, "Hyper-V TLB flush support "
955 "(requested by 'hv-tlbflush' cpu flag) "
956 " is not supported by kernel\n");
957 return -ENOSYS;
958 }
959 c->eax |= HV_REMOTE_TLB_FLUSH_RECOMMENDED;
960 c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
961 }
962 if (cpu->hyperv_ipi) {
963 if (kvm_check_extension(cs->kvm_state,
964 KVM_CAP_HYPERV_SEND_IPI) <= 0) {
965 fprintf(stderr, "Hyper-V IPI send support "
966 "(requested by 'hv-ipi' cpu flag) "
967 " is not supported by kernel\n");
968 return -ENOSYS;
969 }
970 c->eax |= HV_CLUSTER_IPI_RECOMMENDED;
971 c->eax |= HV_EX_PROCESSOR_MASKS_RECOMMENDED;
972 }
973
974 c->ebx = cpu->hyperv_spinlock_attempts;
975
976 c = &cpuid_data.entries[cpuid_i++];
977 c->function = HV_CPUID_IMPLEMENT_LIMITS;
978
979 c->eax = cpu->hv_max_vps;
980 c->ebx = 0x40;
981
982 kvm_base = KVM_CPUID_SIGNATURE_NEXT;
983 has_msr_hv_hypercall = true;
984 }
985
986 if (cpu->expose_kvm) {
987 memcpy(signature, "KVMKVMKVM\0\0\0", 12);
988 c = &cpuid_data.entries[cpuid_i++];
989 c->function = KVM_CPUID_SIGNATURE | kvm_base;
990 c->eax = KVM_CPUID_FEATURES | kvm_base;
991 c->ebx = signature[0];
992 c->ecx = signature[1];
993 c->edx = signature[2];
994
995 c = &cpuid_data.entries[cpuid_i++];
996 c->function = KVM_CPUID_FEATURES | kvm_base;
997 c->eax = env->features[FEAT_KVM];
998 c->edx = env->features[FEAT_KVM_HINTS];
999 }
1000
1001 cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
1002
1003 for (i = 0; i <= limit; i++) {
1004 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1005 fprintf(stderr, "unsupported level value: 0x%x\n", limit);
1006 abort();
1007 }
1008 c = &cpuid_data.entries[cpuid_i++];
1009
1010 switch (i) {
1011 case 2: {
1012 /* Keep reading function 2 till all the input is received */
1013 int times;
1014
1015 c->function = i;
1016 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
1017 KVM_CPUID_FLAG_STATE_READ_NEXT;
1018 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1019 times = c->eax & 0xff;
1020
1021 for (j = 1; j < times; ++j) {
1022 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1023 fprintf(stderr, "cpuid_data is full, no space for "
1024 "cpuid(eax:2):eax & 0xf = 0x%x\n", times);
1025 abort();
1026 }
1027 c = &cpuid_data.entries[cpuid_i++];
1028 c->function = i;
1029 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
1030 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1031 }
1032 break;
1033 }
1034 case 4:
1035 case 0xb:
1036 case 0xd:
1037 for (j = 0; ; j++) {
1038 if (i == 0xd && j == 64) {
1039 break;
1040 }
1041 c->function = i;
1042 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1043 c->index = j;
1044 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1045
1046 if (i == 4 && c->eax == 0) {
1047 break;
1048 }
1049 if (i == 0xb && !(c->ecx & 0xff00)) {
1050 break;
1051 }
1052 if (i == 0xd && c->eax == 0) {
1053 continue;
1054 }
1055 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1056 fprintf(stderr, "cpuid_data is full, no space for "
1057 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1058 abort();
1059 }
1060 c = &cpuid_data.entries[cpuid_i++];
1061 }
1062 break;
1063 case 0x14: {
1064 uint32_t times;
1065
1066 c->function = i;
1067 c->index = 0;
1068 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1069 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1070 times = c->eax;
1071
1072 for (j = 1; j <= times; ++j) {
1073 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1074 fprintf(stderr, "cpuid_data is full, no space for "
1075 "cpuid(eax:0x14,ecx:0x%x)\n", j);
1076 abort();
1077 }
1078 c = &cpuid_data.entries[cpuid_i++];
1079 c->function = i;
1080 c->index = j;
1081 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1082 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1083 }
1084 break;
1085 }
1086 default:
1087 c->function = i;
1088 c->flags = 0;
1089 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1090 break;
1091 }
1092 }
1093
1094 if (limit >= 0x0a) {
1095 uint32_t eax, edx;
1096
1097 cpu_x86_cpuid(env, 0x0a, 0, &eax, &unused, &unused, &edx);
1098
1099 has_architectural_pmu_version = eax & 0xff;
1100 if (has_architectural_pmu_version > 0) {
1101 num_architectural_pmu_gp_counters = (eax & 0xff00) >> 8;
1102
1103 /* Shouldn't be more than 32, since that's the number of bits
1104 * available in EBX to tell us _which_ counters are available.
1105 * Play it safe.
1106 */
1107 if (num_architectural_pmu_gp_counters > MAX_GP_COUNTERS) {
1108 num_architectural_pmu_gp_counters = MAX_GP_COUNTERS;
1109 }
1110
1111 if (has_architectural_pmu_version > 1) {
1112 num_architectural_pmu_fixed_counters = edx & 0x1f;
1113
1114 if (num_architectural_pmu_fixed_counters > MAX_FIXED_COUNTERS) {
1115 num_architectural_pmu_fixed_counters = MAX_FIXED_COUNTERS;
1116 }
1117 }
1118 }
1119 }
1120
1121 cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
1122
1123 for (i = 0x80000000; i <= limit; i++) {
1124 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1125 fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);
1126 abort();
1127 }
1128 c = &cpuid_data.entries[cpuid_i++];
1129
1130 switch (i) {
1131 case 0x8000001d:
1132 /* Query for all AMD cache information leaves */
1133 for (j = 0; ; j++) {
1134 c->function = i;
1135 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1136 c->index = j;
1137 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
1138
1139 if (c->eax == 0) {
1140 break;
1141 }
1142 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1143 fprintf(stderr, "cpuid_data is full, no space for "
1144 "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);
1145 abort();
1146 }
1147 c = &cpuid_data.entries[cpuid_i++];
1148 }
1149 break;
1150 default:
1151 c->function = i;
1152 c->flags = 0;
1153 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1154 break;
1155 }
1156 }
1157
1158 /* Call Centaur's CPUID instructions they are supported. */
1159 if (env->cpuid_xlevel2 > 0) {
1160 cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);
1161
1162 for (i = 0xC0000000; i <= limit; i++) {
1163 if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {
1164 fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);
1165 abort();
1166 }
1167 c = &cpuid_data.entries[cpuid_i++];
1168
1169 c->function = i;
1170 c->flags = 0;
1171 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
1172 }
1173 }
1174
1175 cpuid_data.cpuid.nent = cpuid_i;
1176
1177 if (((env->cpuid_version >> 8)&0xF) >= 6
1178 && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
1179 (CPUID_MCE | CPUID_MCA)
1180 && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {
1181 uint64_t mcg_cap, unsupported_caps;
1182 int banks;
1183 int ret;
1184
1185 ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);
1186 if (ret < 0) {
1187 fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));
1188 return ret;
1189 }
1190
1191 if (banks < (env->mcg_cap & MCG_CAP_BANKS_MASK)) {
1192 error_report("kvm: Unsupported MCE bank count (QEMU = %d, KVM = %d)",
1193 (int)(env->mcg_cap & MCG_CAP_BANKS_MASK), banks);
1194 return -ENOTSUP;
1195 }
1196
1197 unsupported_caps = env->mcg_cap & ~(mcg_cap | MCG_CAP_BANKS_MASK);
1198 if (unsupported_caps) {
1199 if (unsupported_caps & MCG_LMCE_P) {
1200 error_report("kvm: LMCE not supported");
1201 return -ENOTSUP;
1202 }
1203 warn_report("Unsupported MCG_CAP bits: 0x%" PRIx64,
1204 unsupported_caps);
1205 }
1206
1207 env->mcg_cap &= mcg_cap | MCG_CAP_BANKS_MASK;
1208 ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &env->mcg_cap);
1209 if (ret < 0) {
1210 fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));
1211 return ret;
1212 }
1213 }
1214
1215 qemu_add_vm_change_state_handler(cpu_update_state, env);
1216
1217 c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);
1218 if (c) {
1219 has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||
1220 !!(c->ecx & CPUID_EXT_SMX);
1221 }
1222
1223 if (env->mcg_cap & MCG_LMCE_P) {
1224 has_msr_mcg_ext_ctl = has_msr_feature_control = true;
1225 }
1226
1227 if (!env->user_tsc_khz) {
1228 if ((env->features[FEAT_8000_0007_EDX] & CPUID_APM_INVTSC) &&
1229 invtsc_mig_blocker == NULL) {
1230 /* for migration */
1231 error_setg(&invtsc_mig_blocker,
1232 "State blocked by non-migratable CPU device"
1233 " (invtsc flag)");
1234 r = migrate_add_blocker(invtsc_mig_blocker, &local_err);
1235 if (local_err) {
1236 error_report_err(local_err);
1237 error_free(invtsc_mig_blocker);
1238 return r;
1239 }
1240 /* for savevm */
1241 vmstate_x86_cpu.unmigratable = 1;
1242 }
1243 }
1244
1245 if (cpu->vmware_cpuid_freq
1246 /* Guests depend on 0x40000000 to detect this feature, so only expose
1247 * it if KVM exposes leaf 0x40000000. (Conflicts with Hyper-V) */
1248 && cpu->expose_kvm
1249 && kvm_base == KVM_CPUID_SIGNATURE
1250 /* TSC clock must be stable and known for this feature. */
1251 && tsc_is_stable_and_known(env)) {
1252
1253 c = &cpuid_data.entries[cpuid_i++];
1254 c->function = KVM_CPUID_SIGNATURE | 0x10;
1255 c->eax = env->tsc_khz;
1256 /* LAPIC resolution of 1ns (freq: 1GHz) is hardcoded in KVM's
1257 * APIC_BUS_CYCLE_NS */
1258 c->ebx = 1000000;
1259 c->ecx = c->edx = 0;
1260
1261 c = cpuid_find_entry(&cpuid_data.cpuid, kvm_base, 0);
1262 c->eax = MAX(c->eax, KVM_CPUID_SIGNATURE | 0x10);
1263 }
1264
1265 cpuid_data.cpuid.nent = cpuid_i;
1266
1267 cpuid_data.cpuid.padding = 0;
1268 r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);
1269 if (r) {
1270 goto fail;
1271 }
1272
1273 if (has_xsave) {
1274 env->xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));
1275 }
1276 cpu->kvm_msr_buf = g_malloc0(MSR_BUF_SIZE);
1277
1278 if (!(env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_RDTSCP)) {
1279 has_msr_tsc_aux = false;
1280 }
1281
1282 r = hyperv_init_vcpu(cpu);
1283 if (r) {
1284 goto fail;
1285 }
1286
1287 return 0;
1288
1289 fail:
1290 migrate_del_blocker(invtsc_mig_blocker);
1291 return r;
1292 }
1293
1294 void kvm_arch_reset_vcpu(X86CPU *cpu)
1295 {
1296 CPUX86State *env = &cpu->env;
1297
1298 env->xcr0 = 1;
1299 if (kvm_irqchip_in_kernel()) {
1300 env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :
1301 KVM_MP_STATE_UNINITIALIZED;
1302 } else {
1303 env->mp_state = KVM_MP_STATE_RUNNABLE;
1304 }
1305
1306 if (cpu->hyperv_synic) {
1307 int i;
1308 for (i = 0; i < ARRAY_SIZE(env->msr_hv_synic_sint); i++) {
1309 env->msr_hv_synic_sint[i] = HV_SINT_MASKED;
1310 }
1311
1312 hyperv_x86_synic_reset(cpu);
1313 }
1314 }
1315
1316 void kvm_arch_do_init_vcpu(X86CPU *cpu)
1317 {
1318 CPUX86State *env = &cpu->env;
1319
1320 /* APs get directly into wait-for-SIPI state. */
1321 if (env->mp_state == KVM_MP_STATE_UNINITIALIZED) {
1322 env->mp_state = KVM_MP_STATE_INIT_RECEIVED;
1323 }
1324 }
1325
1326 static int kvm_get_supported_feature_msrs(KVMState *s)
1327 {
1328 int ret = 0;
1329
1330 if (kvm_feature_msrs != NULL) {
1331 return 0;
1332 }
1333
1334 if (!kvm_check_extension(s, KVM_CAP_GET_MSR_FEATURES)) {
1335 return 0;
1336 }
1337
1338 struct kvm_msr_list msr_list;
1339
1340 msr_list.nmsrs = 0;
1341 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, &msr_list);
1342 if (ret < 0 && ret != -E2BIG) {
1343 error_report("Fetch KVM feature MSR list failed: %s",
1344 strerror(-ret));
1345 return ret;
1346 }
1347
1348 assert(msr_list.nmsrs > 0);
1349 kvm_feature_msrs = (struct kvm_msr_list *) \
1350 g_malloc0(sizeof(msr_list) +
1351 msr_list.nmsrs * sizeof(msr_list.indices[0]));
1352
1353 kvm_feature_msrs->nmsrs = msr_list.nmsrs;
1354 ret = kvm_ioctl(s, KVM_GET_MSR_FEATURE_INDEX_LIST, kvm_feature_msrs);
1355
1356 if (ret < 0) {
1357 error_report("Fetch KVM feature MSR list failed: %s",
1358 strerror(-ret));
1359 g_free(kvm_feature_msrs);
1360 kvm_feature_msrs = NULL;
1361 return ret;
1362 }
1363
1364 return 0;
1365 }
1366
1367 static int kvm_get_supported_msrs(KVMState *s)
1368 {
1369 static int kvm_supported_msrs;
1370 int ret = 0;
1371
1372 /* first time */
1373 if (kvm_supported_msrs == 0) {
1374 struct kvm_msr_list msr_list, *kvm_msr_list;
1375
1376 kvm_supported_msrs = -1;
1377
1378 /* Obtain MSR list from KVM. These are the MSRs that we must
1379 * save/restore */
1380 msr_list.nmsrs = 0;
1381 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);
1382 if (ret < 0 && ret != -E2BIG) {
1383 return ret;
1384 }
1385 /* Old kernel modules had a bug and could write beyond the provided
1386 memory. Allocate at least a safe amount of 1K. */
1387 kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +
1388 msr_list.nmsrs *
1389 sizeof(msr_list.indices[0])));
1390
1391 kvm_msr_list->nmsrs = msr_list.nmsrs;
1392 ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
1393 if (ret >= 0) {
1394 int i;
1395
1396 for (i = 0; i < kvm_msr_list->nmsrs; i++) {
1397 switch (kvm_msr_list->indices[i]) {
1398 case MSR_STAR:
1399 has_msr_star = true;
1400 break;
1401 case MSR_VM_HSAVE_PA:
1402 has_msr_hsave_pa = true;
1403 break;
1404 case MSR_TSC_AUX:
1405 has_msr_tsc_aux = true;
1406 break;
1407 case MSR_TSC_ADJUST:
1408 has_msr_tsc_adjust = true;
1409 break;
1410 case MSR_IA32_TSCDEADLINE:
1411 has_msr_tsc_deadline = true;
1412 break;
1413 case MSR_IA32_SMBASE:
1414 has_msr_smbase = true;
1415 break;
1416 case MSR_SMI_COUNT:
1417 has_msr_smi_count = true;
1418 break;
1419 case MSR_IA32_MISC_ENABLE:
1420 has_msr_misc_enable = true;
1421 break;
1422 case MSR_IA32_BNDCFGS:
1423 has_msr_bndcfgs = true;
1424 break;
1425 case MSR_IA32_XSS:
1426 has_msr_xss = true;
1427 break;
1428 case HV_X64_MSR_CRASH_CTL:
1429 has_msr_hv_crash = true;
1430 break;
1431 case HV_X64_MSR_RESET:
1432 has_msr_hv_reset = true;
1433 break;
1434 case HV_X64_MSR_VP_INDEX:
1435 has_msr_hv_vpindex = true;
1436 break;
1437 case HV_X64_MSR_VP_RUNTIME:
1438 has_msr_hv_runtime = true;
1439 break;
1440 case HV_X64_MSR_SCONTROL:
1441 has_msr_hv_synic = true;
1442 break;
1443 case HV_X64_MSR_STIMER0_CONFIG:
1444 has_msr_hv_stimer = true;
1445 break;
1446 case HV_X64_MSR_TSC_FREQUENCY:
1447 has_msr_hv_frequencies = true;
1448 break;
1449 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
1450 has_msr_hv_reenlightenment = true;
1451 break;
1452 case MSR_IA32_SPEC_CTRL:
1453 has_msr_spec_ctrl = true;
1454 break;
1455 case MSR_VIRT_SSBD:
1456 has_msr_virt_ssbd = true;
1457 break;
1458 }
1459 }
1460 }
1461
1462 g_free(kvm_msr_list);
1463 }
1464
1465 return ret;
1466 }
1467
1468 static Notifier smram_machine_done;
1469 static KVMMemoryListener smram_listener;
1470 static AddressSpace smram_address_space;
1471 static MemoryRegion smram_as_root;
1472 static MemoryRegion smram_as_mem;
1473
1474 static void register_smram_listener(Notifier *n, void *unused)
1475 {
1476 MemoryRegion *smram =
1477 (MemoryRegion *) object_resolve_path("/machine/smram", NULL);
1478
1479 /* Outer container... */
1480 memory_region_init(&smram_as_root, OBJECT(kvm_state), "mem-container-smram", ~0ull);
1481 memory_region_set_enabled(&smram_as_root, true);
1482
1483 /* ... with two regions inside: normal system memory with low
1484 * priority, and...
1485 */
1486 memory_region_init_alias(&smram_as_mem, OBJECT(kvm_state), "mem-smram",
1487 get_system_memory(), 0, ~0ull);
1488 memory_region_add_subregion_overlap(&smram_as_root, 0, &smram_as_mem, 0);
1489 memory_region_set_enabled(&smram_as_mem, true);
1490
1491 if (smram) {
1492 /* ... SMRAM with higher priority */
1493 memory_region_add_subregion_overlap(&smram_as_root, 0, smram, 10);
1494 memory_region_set_enabled(smram, true);
1495 }
1496
1497 address_space_init(&smram_address_space, &smram_as_root, "KVM-SMRAM");
1498 kvm_memory_listener_register(kvm_state, &smram_listener,
1499 &smram_address_space, 1);
1500 }
1501
1502 int kvm_arch_init(MachineState *ms, KVMState *s)
1503 {
1504 uint64_t identity_base = 0xfffbc000;
1505 uint64_t shadow_mem;
1506 int ret;
1507 struct utsname utsname;
1508
1509 has_xsave = kvm_check_extension(s, KVM_CAP_XSAVE);
1510 has_xcrs = kvm_check_extension(s, KVM_CAP_XCRS);
1511 has_pit_state2 = kvm_check_extension(s, KVM_CAP_PIT_STATE2);
1512
1513 hv_vpindex_settable = kvm_check_extension(s, KVM_CAP_HYPERV_VP_INDEX);
1514
1515 ret = kvm_get_supported_msrs(s);
1516 if (ret < 0) {
1517 return ret;
1518 }
1519
1520 kvm_get_supported_feature_msrs(s);
1521
1522 uname(&utsname);
1523 lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;
1524
1525 /*
1526 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
1527 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
1528 * Since these must be part of guest physical memory, we need to allocate
1529 * them, both by setting their start addresses in the kernel and by
1530 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
1531 *
1532 * Older KVM versions may not support setting the identity map base. In
1533 * that case we need to stick with the default, i.e. a 256K maximum BIOS
1534 * size.
1535 */
1536 if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
1537 /* Allows up to 16M BIOSes. */
1538 identity_base = 0xfeffc000;
1539
1540 ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);
1541 if (ret < 0) {
1542 return ret;
1543 }
1544 }
1545
1546 /* Set TSS base one page after EPT identity map. */
1547 ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);
1548 if (ret < 0) {
1549 return ret;
1550 }
1551
1552 /* Tell fw_cfg to notify the BIOS to reserve the range. */
1553 ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);
1554 if (ret < 0) {
1555 fprintf(stderr, "e820_add_entry() table is full\n");
1556 return ret;
1557 }
1558 qemu_register_reset(kvm_unpoison_all, NULL);
1559
1560 shadow_mem = machine_kvm_shadow_mem(ms);
1561 if (shadow_mem != -1) {
1562 shadow_mem /= 4096;
1563 ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);
1564 if (ret < 0) {
1565 return ret;
1566 }
1567 }
1568
1569 if (kvm_check_extension(s, KVM_CAP_X86_SMM) &&
1570 object_dynamic_cast(OBJECT(ms), TYPE_PC_MACHINE) &&
1571 pc_machine_is_smm_enabled(PC_MACHINE(ms))) {
1572 smram_machine_done.notify = register_smram_listener;
1573 qemu_add_machine_init_done_notifier(&smram_machine_done);
1574 }
1575
1576 if (enable_cpu_pm) {
1577 int disable_exits = kvm_check_extension(s, KVM_CAP_X86_DISABLE_EXITS);
1578 int ret;
1579
1580 /* Work around for kernel header with a typo. TODO: fix header and drop. */
1581 #if defined(KVM_X86_DISABLE_EXITS_HTL) && !defined(KVM_X86_DISABLE_EXITS_HLT)
1582 #define KVM_X86_DISABLE_EXITS_HLT KVM_X86_DISABLE_EXITS_HTL
1583 #endif
1584 if (disable_exits) {
1585 disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT |
1586 KVM_X86_DISABLE_EXITS_HLT |
1587 KVM_X86_DISABLE_EXITS_PAUSE);
1588 }
1589
1590 ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0,
1591 disable_exits);
1592 if (ret < 0) {
1593 error_report("kvm: guest stopping CPU not supported: %s",
1594 strerror(-ret));
1595 }
1596 }
1597
1598 return 0;
1599 }
1600
1601 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1602 {
1603 lhs->selector = rhs->selector;
1604 lhs->base = rhs->base;
1605 lhs->limit = rhs->limit;
1606 lhs->type = 3;
1607 lhs->present = 1;
1608 lhs->dpl = 3;
1609 lhs->db = 0;
1610 lhs->s = 1;
1611 lhs->l = 0;
1612 lhs->g = 0;
1613 lhs->avl = 0;
1614 lhs->unusable = 0;
1615 }
1616
1617 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
1618 {
1619 unsigned flags = rhs->flags;
1620 lhs->selector = rhs->selector;
1621 lhs->base = rhs->base;
1622 lhs->limit = rhs->limit;
1623 lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
1624 lhs->present = (flags & DESC_P_MASK) != 0;
1625 lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;
1626 lhs->db = (flags >> DESC_B_SHIFT) & 1;
1627 lhs->s = (flags & DESC_S_MASK) != 0;
1628 lhs->l = (flags >> DESC_L_SHIFT) & 1;
1629 lhs->g = (flags & DESC_G_MASK) != 0;
1630 lhs->avl = (flags & DESC_AVL_MASK) != 0;
1631 lhs->unusable = !lhs->present;
1632 lhs->padding = 0;
1633 }
1634
1635 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
1636 {
1637 lhs->selector = rhs->selector;
1638 lhs->base = rhs->base;
1639 lhs->limit = rhs->limit;
1640 lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |
1641 ((rhs->present && !rhs->unusable) * DESC_P_MASK) |
1642 (rhs->dpl << DESC_DPL_SHIFT) |
1643 (rhs->db << DESC_B_SHIFT) |
1644 (rhs->s * DESC_S_MASK) |
1645 (rhs->l << DESC_L_SHIFT) |
1646 (rhs->g * DESC_G_MASK) |
1647 (rhs->avl * DESC_AVL_MASK);
1648 }
1649
1650 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
1651 {
1652 if (set) {
1653 *kvm_reg = *qemu_reg;
1654 } else {
1655 *qemu_reg = *kvm_reg;
1656 }
1657 }
1658
1659 static int kvm_getput_regs(X86CPU *cpu, int set)
1660 {
1661 CPUX86State *env = &cpu->env;
1662 struct kvm_regs regs;
1663 int ret = 0;
1664
1665 if (!set) {
1666 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_REGS, &regs);
1667 if (ret < 0) {
1668 return ret;
1669 }
1670 }
1671
1672 kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
1673 kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
1674 kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
1675 kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
1676 kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
1677 kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
1678 kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
1679 kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
1680 #ifdef TARGET_X86_64
1681 kvm_getput_reg(&regs.r8, &env->regs[8], set);
1682 kvm_getput_reg(&regs.r9, &env->regs[9], set);
1683 kvm_getput_reg(&regs.r10, &env->regs[10], set);
1684 kvm_getput_reg(&regs.r11, &env->regs[11], set);
1685 kvm_getput_reg(&regs.r12, &env->regs[12], set);
1686 kvm_getput_reg(&regs.r13, &env->regs[13], set);
1687 kvm_getput_reg(&regs.r14, &env->regs[14], set);
1688 kvm_getput_reg(&regs.r15, &env->regs[15], set);
1689 #endif
1690
1691 kvm_getput_reg(&regs.rflags, &env->eflags, set);
1692 kvm_getput_reg(&regs.rip, &env->eip, set);
1693
1694 if (set) {
1695 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_REGS, &regs);
1696 }
1697
1698 return ret;
1699 }
1700
1701 static int kvm_put_fpu(X86CPU *cpu)
1702 {
1703 CPUX86State *env = &cpu->env;
1704 struct kvm_fpu fpu;
1705 int i;
1706
1707 memset(&fpu, 0, sizeof fpu);
1708 fpu.fsw = env->fpus & ~(7 << 11);
1709 fpu.fsw |= (env->fpstt & 7) << 11;
1710 fpu.fcw = env->fpuc;
1711 fpu.last_opcode = env->fpop;
1712 fpu.last_ip = env->fpip;
1713 fpu.last_dp = env->fpdp;
1714 for (i = 0; i < 8; ++i) {
1715 fpu.ftwx |= (!env->fptags[i]) << i;
1716 }
1717 memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
1718 for (i = 0; i < CPU_NB_REGS; i++) {
1719 stq_p(&fpu.xmm[i][0], env->xmm_regs[i].ZMM_Q(0));
1720 stq_p(&fpu.xmm[i][8], env->xmm_regs[i].ZMM_Q(1));
1721 }
1722 fpu.mxcsr = env->mxcsr;
1723
1724 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_FPU, &fpu);
1725 }
1726
1727 #define XSAVE_FCW_FSW 0
1728 #define XSAVE_FTW_FOP 1
1729 #define XSAVE_CWD_RIP 2
1730 #define XSAVE_CWD_RDP 4
1731 #define XSAVE_MXCSR 6
1732 #define XSAVE_ST_SPACE 8
1733 #define XSAVE_XMM_SPACE 40
1734 #define XSAVE_XSTATE_BV 128
1735 #define XSAVE_YMMH_SPACE 144
1736 #define XSAVE_BNDREGS 240
1737 #define XSAVE_BNDCSR 256
1738 #define XSAVE_OPMASK 272
1739 #define XSAVE_ZMM_Hi256 288
1740 #define XSAVE_Hi16_ZMM 416
1741 #define XSAVE_PKRU 672
1742
1743 #define XSAVE_BYTE_OFFSET(word_offset) \
1744 ((word_offset) * sizeof_field(struct kvm_xsave, region[0]))
1745
1746 #define ASSERT_OFFSET(word_offset, field) \
1747 QEMU_BUILD_BUG_ON(XSAVE_BYTE_OFFSET(word_offset) != \
1748 offsetof(X86XSaveArea, field))
1749
1750 ASSERT_OFFSET(XSAVE_FCW_FSW, legacy.fcw);
1751 ASSERT_OFFSET(XSAVE_FTW_FOP, legacy.ftw);
1752 ASSERT_OFFSET(XSAVE_CWD_RIP, legacy.fpip);
1753 ASSERT_OFFSET(XSAVE_CWD_RDP, legacy.fpdp);
1754 ASSERT_OFFSET(XSAVE_MXCSR, legacy.mxcsr);
1755 ASSERT_OFFSET(XSAVE_ST_SPACE, legacy.fpregs);
1756 ASSERT_OFFSET(XSAVE_XMM_SPACE, legacy.xmm_regs);
1757 ASSERT_OFFSET(XSAVE_XSTATE_BV, header.xstate_bv);
1758 ASSERT_OFFSET(XSAVE_YMMH_SPACE, avx_state);
1759 ASSERT_OFFSET(XSAVE_BNDREGS, bndreg_state);
1760 ASSERT_OFFSET(XSAVE_BNDCSR, bndcsr_state);
1761 ASSERT_OFFSET(XSAVE_OPMASK, opmask_state);
1762 ASSERT_OFFSET(XSAVE_ZMM_Hi256, zmm_hi256_state);
1763 ASSERT_OFFSET(XSAVE_Hi16_ZMM, hi16_zmm_state);
1764 ASSERT_OFFSET(XSAVE_PKRU, pkru_state);
1765
1766 static int kvm_put_xsave(X86CPU *cpu)
1767 {
1768 CPUX86State *env = &cpu->env;
1769 X86XSaveArea *xsave = env->xsave_buf;
1770
1771 if (!has_xsave) {
1772 return kvm_put_fpu(cpu);
1773 }
1774 x86_cpu_xsave_all_areas(cpu, xsave);
1775
1776 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XSAVE, xsave);
1777 }
1778
1779 static int kvm_put_xcrs(X86CPU *cpu)
1780 {
1781 CPUX86State *env = &cpu->env;
1782 struct kvm_xcrs xcrs = {};
1783
1784 if (!has_xcrs) {
1785 return 0;
1786 }
1787
1788 xcrs.nr_xcrs = 1;
1789 xcrs.flags = 0;
1790 xcrs.xcrs[0].xcr = 0;
1791 xcrs.xcrs[0].value = env->xcr0;
1792 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_XCRS, &xcrs);
1793 }
1794
1795 static int kvm_put_sregs(X86CPU *cpu)
1796 {
1797 CPUX86State *env = &cpu->env;
1798 struct kvm_sregs sregs;
1799
1800 memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
1801 if (env->interrupt_injected >= 0) {
1802 sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
1803 (uint64_t)1 << (env->interrupt_injected % 64);
1804 }
1805
1806 if ((env->eflags & VM_MASK)) {
1807 set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
1808 set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
1809 set_v8086_seg(&sregs.es, &env->segs[R_ES]);
1810 set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
1811 set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
1812 set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
1813 } else {
1814 set_seg(&sregs.cs, &env->segs[R_CS]);
1815 set_seg(&sregs.ds, &env->segs[R_DS]);
1816 set_seg(&sregs.es, &env->segs[R_ES]);
1817 set_seg(&sregs.fs, &env->segs[R_FS]);
1818 set_seg(&sregs.gs, &env->segs[R_GS]);
1819 set_seg(&sregs.ss, &env->segs[R_SS]);
1820 }
1821
1822 set_seg(&sregs.tr, &env->tr);
1823 set_seg(&sregs.ldt, &env->ldt);
1824
1825 sregs.idt.limit = env->idt.limit;
1826 sregs.idt.base = env->idt.base;
1827 memset(sregs.idt.padding, 0, sizeof sregs.idt.padding);
1828 sregs.gdt.limit = env->gdt.limit;
1829 sregs.gdt.base = env->gdt.base;
1830 memset(sregs.gdt.padding, 0, sizeof sregs.gdt.padding);
1831
1832 sregs.cr0 = env->cr[0];
1833 sregs.cr2 = env->cr[2];
1834 sregs.cr3 = env->cr[3];
1835 sregs.cr4 = env->cr[4];
1836
1837 sregs.cr8 = cpu_get_apic_tpr(cpu->apic_state);
1838 sregs.apic_base = cpu_get_apic_base(cpu->apic_state);
1839
1840 sregs.efer = env->efer;
1841
1842 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs);
1843 }
1844
1845 static void kvm_msr_buf_reset(X86CPU *cpu)
1846 {
1847 memset(cpu->kvm_msr_buf, 0, MSR_BUF_SIZE);
1848 }
1849
1850 static void kvm_msr_entry_add(X86CPU *cpu, uint32_t index, uint64_t value)
1851 {
1852 struct kvm_msrs *msrs = cpu->kvm_msr_buf;
1853 void *limit = ((void *)msrs) + MSR_BUF_SIZE;
1854 struct kvm_msr_entry *entry = &msrs->entries[msrs->nmsrs];
1855
1856 assert((void *)(entry + 1) <= limit);
1857
1858 entry->index = index;
1859 entry->reserved = 0;
1860 entry->data = value;
1861 msrs->nmsrs++;
1862 }
1863
1864 static int kvm_put_one_msr(X86CPU *cpu, int index, uint64_t value)
1865 {
1866 kvm_msr_buf_reset(cpu);
1867 kvm_msr_entry_add(cpu, index, value);
1868
1869 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
1870 }
1871
1872 void kvm_put_apicbase(X86CPU *cpu, uint64_t value)
1873 {
1874 int ret;
1875
1876 ret = kvm_put_one_msr(cpu, MSR_IA32_APICBASE, value);
1877 assert(ret == 1);
1878 }
1879
1880 static int kvm_put_tscdeadline_msr(X86CPU *cpu)
1881 {
1882 CPUX86State *env = &cpu->env;
1883 int ret;
1884
1885 if (!has_msr_tsc_deadline) {
1886 return 0;
1887 }
1888
1889 ret = kvm_put_one_msr(cpu, MSR_IA32_TSCDEADLINE, env->tsc_deadline);
1890 if (ret < 0) {
1891 return ret;
1892 }
1893
1894 assert(ret == 1);
1895 return 0;
1896 }
1897
1898 /*
1899 * Provide a separate write service for the feature control MSR in order to
1900 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1901 * before writing any other state because forcibly leaving nested mode
1902 * invalidates the VCPU state.
1903 */
1904 static int kvm_put_msr_feature_control(X86CPU *cpu)
1905 {
1906 int ret;
1907
1908 if (!has_msr_feature_control) {
1909 return 0;
1910 }
1911
1912 ret = kvm_put_one_msr(cpu, MSR_IA32_FEATURE_CONTROL,
1913 cpu->env.msr_ia32_feature_control);
1914 if (ret < 0) {
1915 return ret;
1916 }
1917
1918 assert(ret == 1);
1919 return 0;
1920 }
1921
1922 static int kvm_put_msrs(X86CPU *cpu, int level)
1923 {
1924 CPUX86State *env = &cpu->env;
1925 int i;
1926 int ret;
1927
1928 kvm_msr_buf_reset(cpu);
1929
1930 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, env->sysenter_cs);
1931 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
1932 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
1933 kvm_msr_entry_add(cpu, MSR_PAT, env->pat);
1934 if (has_msr_star) {
1935 kvm_msr_entry_add(cpu, MSR_STAR, env->star);
1936 }
1937 if (has_msr_hsave_pa) {
1938 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, env->vm_hsave);
1939 }
1940 if (has_msr_tsc_aux) {
1941 kvm_msr_entry_add(cpu, MSR_TSC_AUX, env->tsc_aux);
1942 }
1943 if (has_msr_tsc_adjust) {
1944 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, env->tsc_adjust);
1945 }
1946 if (has_msr_misc_enable) {
1947 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE,
1948 env->msr_ia32_misc_enable);
1949 }
1950 if (has_msr_smbase) {
1951 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, env->smbase);
1952 }
1953 if (has_msr_smi_count) {
1954 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, env->msr_smi_count);
1955 }
1956 if (has_msr_bndcfgs) {
1957 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, env->msr_bndcfgs);
1958 }
1959 if (has_msr_xss) {
1960 kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
1961 }
1962 if (has_msr_spec_ctrl) {
1963 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
1964 }
1965 if (has_msr_virt_ssbd) {
1966 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
1967 }
1968
1969 #ifdef TARGET_X86_64
1970 if (lm_capable_kernel) {
1971 kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
1972 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, env->kernelgsbase);
1973 kvm_msr_entry_add(cpu, MSR_FMASK, env->fmask);
1974 kvm_msr_entry_add(cpu, MSR_LSTAR, env->lstar);
1975 }
1976 #endif
1977
1978 /* If host supports feature MSR, write down. */
1979 if (kvm_feature_msrs) {
1980 int i;
1981 for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
1982 if (kvm_feature_msrs->indices[i] == MSR_IA32_ARCH_CAPABILITIES) {
1983 kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
1984 env->features[FEAT_ARCH_CAPABILITIES]);
1985 break;
1986 }
1987 }
1988
1989 /*
1990 * The following MSRs have side effects on the guest or are too heavy
1991 * for normal writeback. Limit them to reset or full state updates.
1992 */
1993 if (level >= KVM_PUT_RESET_STATE) {
1994 kvm_msr_entry_add(cpu, MSR_IA32_TSC, env->tsc);
1995 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, env->system_time_msr);
1996 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
1997 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
1998 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, env->async_pf_en_msr);
1999 }
2000 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2001 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, env->pv_eoi_en_msr);
2002 }
2003 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2004 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, env->steal_time_msr);
2005 }
2006 if (has_architectural_pmu_version > 0) {
2007 if (has_architectural_pmu_version > 1) {
2008 /* Stop the counter. */
2009 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2010 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2011 }
2012
2013 /* Set the counter values. */
2014 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2015 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
2016 env->msr_fixed_counters[i]);
2017 }
2018 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2019 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i,
2020 env->msr_gp_counters[i]);
2021 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i,
2022 env->msr_gp_evtsel[i]);
2023 }
2024 if (has_architectural_pmu_version > 1) {
2025 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS,
2026 env->msr_global_status);
2027 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL,
2028 env->msr_global_ovf_ctrl);
2029
2030 /* Now start the PMU. */
2031 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL,
2032 env->msr_fixed_ctr_ctrl);
2033 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL,
2034 env->msr_global_ctrl);
2035 }
2036 }
2037 /*
2038 * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-add,
2039 * only sync them to KVM on the first cpu
2040 */
2041 if (current_cpu == first_cpu) {
2042 if (has_msr_hv_hypercall) {
2043 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID,
2044 env->msr_hv_guest_os_id);
2045 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL,
2046 env->msr_hv_hypercall);
2047 }
2048 if (cpu->hyperv_time) {
2049 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC,
2050 env->msr_hv_tsc);
2051 }
2052 if (cpu->hyperv_reenlightenment) {
2053 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL,
2054 env->msr_hv_reenlightenment_control);
2055 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL,
2056 env->msr_hv_tsc_emulation_control);
2057 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS,
2058 env->msr_hv_tsc_emulation_status);
2059 }
2060 }
2061 if (cpu->hyperv_vapic) {
2062 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE,
2063 env->msr_hv_vapic);
2064 }
2065 if (has_msr_hv_crash) {
2066 int j;
2067
2068 for (j = 0; j < HV_CRASH_PARAMS; j++)
2069 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j,
2070 env->msr_hv_crash_params[j]);
2071
2072 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_CTL, HV_CRASH_CTL_NOTIFY);
2073 }
2074 if (has_msr_hv_runtime) {
2075 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, env->msr_hv_runtime);
2076 }
2077 if (cpu->hyperv_vpindex && hv_vpindex_settable) {
2078 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_INDEX,
2079 hyperv_vp_index(CPU(cpu)));
2080 }
2081 if (cpu->hyperv_synic) {
2082 int j;
2083
2084 kvm_msr_entry_add(cpu, HV_X64_MSR_SVERSION, HV_SYNIC_VERSION);
2085
2086 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL,
2087 env->msr_hv_synic_control);
2088 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP,
2089 env->msr_hv_synic_evt_page);
2090 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP,
2091 env->msr_hv_synic_msg_page);
2092
2093 for (j = 0; j < ARRAY_SIZE(env->msr_hv_synic_sint); j++) {
2094 kvm_msr_entry_add(cpu, HV_X64_MSR_SINT0 + j,
2095 env->msr_hv_synic_sint[j]);
2096 }
2097 }
2098 if (has_msr_hv_stimer) {
2099 int j;
2100
2101 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_config); j++) {
2102 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_CONFIG + j * 2,
2103 env->msr_hv_stimer_config[j]);
2104 }
2105
2106 for (j = 0; j < ARRAY_SIZE(env->msr_hv_stimer_count); j++) {
2107 kvm_msr_entry_add(cpu, HV_X64_MSR_STIMER0_COUNT + j * 2,
2108 env->msr_hv_stimer_count[j]);
2109 }
2110 }
2111 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2112 uint64_t phys_mask = MAKE_64BIT_MASK(0, cpu->phys_bits);
2113
2114 kvm_msr_entry_add(cpu, MSR_MTRRdefType, env->mtrr_deftype);
2115 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, env->mtrr_fixed[0]);
2116 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, env->mtrr_fixed[1]);
2117 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, env->mtrr_fixed[2]);
2118 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, env->mtrr_fixed[3]);
2119 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, env->mtrr_fixed[4]);
2120 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, env->mtrr_fixed[5]);
2121 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, env->mtrr_fixed[6]);
2122 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, env->mtrr_fixed[7]);
2123 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, env->mtrr_fixed[8]);
2124 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, env->mtrr_fixed[9]);
2125 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, env->mtrr_fixed[10]);
2126 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2127 /* The CPU GPs if we write to a bit above the physical limit of
2128 * the host CPU (and KVM emulates that)
2129 */
2130 uint64_t mask = env->mtrr_var[i].mask;
2131 mask &= phys_mask;
2132
2133 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i),
2134 env->mtrr_var[i].base);
2135 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), mask);
2136 }
2137 }
2138 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2139 int addr_num = kvm_arch_get_supported_cpuid(kvm_state,
2140 0x14, 1, R_EAX) & 0x7;
2141
2142 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL,
2143 env->msr_rtit_ctrl);
2144 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS,
2145 env->msr_rtit_status);
2146 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE,
2147 env->msr_rtit_output_base);
2148 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK,
2149 env->msr_rtit_output_mask);
2150 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH,
2151 env->msr_rtit_cr3_match);
2152 for (i = 0; i < addr_num; i++) {
2153 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i,
2154 env->msr_rtit_addrs[i]);
2155 }
2156 }
2157
2158 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
2159 * kvm_put_msr_feature_control. */
2160 }
2161 if (env->mcg_cap) {
2162 int i;
2163
2164 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, env->mcg_status);
2165 kvm_msr_entry_add(cpu, MSR_MCG_CTL, env->mcg_ctl);
2166 if (has_msr_mcg_ext_ctl) {
2167 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, env->mcg_ext_ctl);
2168 }
2169 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2170 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, env->mce_banks[i]);
2171 }
2172 }
2173
2174 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, cpu->kvm_msr_buf);
2175 if (ret < 0) {
2176 return ret;
2177 }
2178
2179 if (ret < cpu->kvm_msr_buf->nmsrs) {
2180 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2181 error_report("error: failed to set MSR 0x%" PRIx32 " to 0x%" PRIx64,
2182 (uint32_t)e->index, (uint64_t)e->data);
2183 }
2184
2185 assert(ret == cpu->kvm_msr_buf->nmsrs);
2186 return 0;
2187 }
2188
2189
2190 static int kvm_get_fpu(X86CPU *cpu)
2191 {
2192 CPUX86State *env = &cpu->env;
2193 struct kvm_fpu fpu;
2194 int i, ret;
2195
2196 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_FPU, &fpu);
2197 if (ret < 0) {
2198 return ret;
2199 }
2200
2201 env->fpstt = (fpu.fsw >> 11) & 7;
2202 env->fpus = fpu.fsw;
2203 env->fpuc = fpu.fcw;
2204 env->fpop = fpu.last_opcode;
2205 env->fpip = fpu.last_ip;
2206 env->fpdp = fpu.last_dp;
2207 for (i = 0; i < 8; ++i) {
2208 env->fptags[i] = !((fpu.ftwx >> i) & 1);
2209 }
2210 memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
2211 for (i = 0; i < CPU_NB_REGS; i++) {
2212 env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.xmm[i][0]);
2213 env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.xmm[i][8]);
2214 }
2215 env->mxcsr = fpu.mxcsr;
2216
2217 return 0;
2218 }
2219
2220 static int kvm_get_xsave(X86CPU *cpu)
2221 {
2222 CPUX86State *env = &cpu->env;
2223 X86XSaveArea *xsave = env->xsave_buf;
2224 int ret;
2225
2226 if (!has_xsave) {
2227 return kvm_get_fpu(cpu);
2228 }
2229
2230 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave);
2231 if (ret < 0) {
2232 return ret;
2233 }
2234 x86_cpu_xrstor_all_areas(cpu, xsave);
2235
2236 return 0;
2237 }
2238
2239 static int kvm_get_xcrs(X86CPU *cpu)
2240 {
2241 CPUX86State *env = &cpu->env;
2242 int i, ret;
2243 struct kvm_xcrs xcrs;
2244
2245 if (!has_xcrs) {
2246 return 0;
2247 }
2248
2249 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XCRS, &xcrs);
2250 if (ret < 0) {
2251 return ret;
2252 }
2253
2254 for (i = 0; i < xcrs.nr_xcrs; i++) {
2255 /* Only support xcr0 now */
2256 if (xcrs.xcrs[i].xcr == 0) {
2257 env->xcr0 = xcrs.xcrs[i].value;
2258 break;
2259 }
2260 }
2261 return 0;
2262 }
2263
2264 static int kvm_get_sregs(X86CPU *cpu)
2265 {
2266 CPUX86State *env = &cpu->env;
2267 struct kvm_sregs sregs;
2268 int bit, i, ret;
2269
2270 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs);
2271 if (ret < 0) {
2272 return ret;
2273 }
2274
2275 /* There can only be one pending IRQ set in the bitmap at a time, so try
2276 to find it and save its number instead (-1 for none). */
2277 env->interrupt_injected = -1;
2278 for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
2279 if (sregs.interrupt_bitmap[i]) {
2280 bit = ctz64(sregs.interrupt_bitmap[i]);
2281 env->interrupt_injected = i * 64 + bit;
2282 break;
2283 }
2284 }
2285
2286 get_seg(&env->segs[R_CS], &sregs.cs);
2287 get_seg(&env->segs[R_DS], &sregs.ds);
2288 get_seg(&env->segs[R_ES], &sregs.es);
2289 get_seg(&env->segs[R_FS], &sregs.fs);
2290 get_seg(&env->segs[R_GS], &sregs.gs);
2291 get_seg(&env->segs[R_SS], &sregs.ss);
2292
2293 get_seg(&env->tr, &sregs.tr);
2294 get_seg(&env->ldt, &sregs.ldt);
2295
2296 env->idt.limit = sregs.idt.limit;
2297 env->idt.base = sregs.idt.base;
2298 env->gdt.limit = sregs.gdt.limit;
2299 env->gdt.base = sregs.gdt.base;
2300
2301 env->cr[0] = sregs.cr0;
2302 env->cr[2] = sregs.cr2;
2303 env->cr[3] = sregs.cr3;
2304 env->cr[4] = sregs.cr4;
2305
2306 env->efer = sregs.efer;
2307
2308 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
2309 x86_update_hflags(env);
2310
2311 return 0;
2312 }
2313
2314 static int kvm_get_msrs(X86CPU *cpu)
2315 {
2316 CPUX86State *env = &cpu->env;
2317 struct kvm_msr_entry *msrs = cpu->kvm_msr_buf->entries;
2318 int ret, i;
2319 uint64_t mtrr_top_bits;
2320
2321 kvm_msr_buf_reset(cpu);
2322
2323 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_CS, 0);
2324 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_ESP, 0);
2325 kvm_msr_entry_add(cpu, MSR_IA32_SYSENTER_EIP, 0);
2326 kvm_msr_entry_add(cpu, MSR_PAT, 0);
2327 if (has_msr_star) {
2328 kvm_msr_entry_add(cpu, MSR_STAR, 0);
2329 }
2330 if (has_msr_hsave_pa) {
2331 kvm_msr_entry_add(cpu, MSR_VM_HSAVE_PA, 0);
2332 }
2333 if (has_msr_tsc_aux) {
2334 kvm_msr_entry_add(cpu, MSR_TSC_AUX, 0);
2335 }
2336 if (has_msr_tsc_adjust) {
2337 kvm_msr_entry_add(cpu, MSR_TSC_ADJUST, 0);
2338 }
2339 if (has_msr_tsc_deadline) {
2340 kvm_msr_entry_add(cpu, MSR_IA32_TSCDEADLINE, 0);
2341 }
2342 if (has_msr_misc_enable) {
2343 kvm_msr_entry_add(cpu, MSR_IA32_MISC_ENABLE, 0);
2344 }
2345 if (has_msr_smbase) {
2346 kvm_msr_entry_add(cpu, MSR_IA32_SMBASE, 0);
2347 }
2348 if (has_msr_smi_count) {
2349 kvm_msr_entry_add(cpu, MSR_SMI_COUNT, 0);
2350 }
2351 if (has_msr_feature_control) {
2352 kvm_msr_entry_add(cpu, MSR_IA32_FEATURE_CONTROL, 0);
2353 }
2354 if (has_msr_bndcfgs) {
2355 kvm_msr_entry_add(cpu, MSR_IA32_BNDCFGS, 0);
2356 }
2357 if (has_msr_xss) {
2358 kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
2359 }
2360 if (has_msr_spec_ctrl) {
2361 kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
2362 }
2363 if (has_msr_virt_ssbd) {
2364 kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
2365 }
2366 if (!env->tsc_valid) {
2367 kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
2368 env->tsc_valid = !runstate_is_running();
2369 }
2370
2371 #ifdef TARGET_X86_64
2372 if (lm_capable_kernel) {
2373 kvm_msr_entry_add(cpu, MSR_CSTAR, 0);
2374 kvm_msr_entry_add(cpu, MSR_KERNELGSBASE, 0);
2375 kvm_msr_entry_add(cpu, MSR_FMASK, 0);
2376 kvm_msr_entry_add(cpu, MSR_LSTAR, 0);
2377 }
2378 #endif
2379 kvm_msr_entry_add(cpu, MSR_KVM_SYSTEM_TIME, 0);
2380 kvm_msr_entry_add(cpu, MSR_KVM_WALL_CLOCK, 0);
2381 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_ASYNC_PF)) {
2382 kvm_msr_entry_add(cpu, MSR_KVM_ASYNC_PF_EN, 0);
2383 }
2384 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_PV_EOI)) {
2385 kvm_msr_entry_add(cpu, MSR_KVM_PV_EOI_EN, 0);
2386 }
2387 if (env->features[FEAT_KVM] & (1 << KVM_FEATURE_STEAL_TIME)) {
2388 kvm_msr_entry_add(cpu, MSR_KVM_STEAL_TIME, 0);
2389 }
2390 if (has_architectural_pmu_version > 0) {
2391 if (has_architectural_pmu_version > 1) {
2392 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR_CTRL, 0);
2393 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
2394 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
2395 kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_OVF_CTRL, 0);
2396 }
2397 for (i = 0; i < num_architectural_pmu_fixed_counters; i++) {
2398 kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
2399 }
2400 for (i = 0; i < num_architectural_pmu_gp_counters; i++) {
2401 kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0);
2402 kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0);
2403 }
2404 }
2405
2406 if (env->mcg_cap) {
2407 kvm_msr_entry_add(cpu, MSR_MCG_STATUS, 0);
2408 kvm_msr_entry_add(cpu, MSR_MCG_CTL, 0);
2409 if (has_msr_mcg_ext_ctl) {
2410 kvm_msr_entry_add(cpu, MSR_MCG_EXT_CTL, 0);
2411 }
2412 for (i = 0; i < (env->mcg_cap & 0xff) * 4; i++) {
2413 kvm_msr_entry_add(cpu, MSR_MC0_CTL + i, 0);
2414 }
2415 }
2416
2417 if (has_msr_hv_hypercall) {
2418 kvm_msr_entry_add(cpu, HV_X64_MSR_HYPERCALL, 0);
2419 kvm_msr_entry_add(cpu, HV_X64_MSR_GUEST_OS_ID, 0);
2420 }
2421 if (cpu->hyperv_vapic) {
2422 kvm_msr_entry_add(cpu, HV_X64_MSR_APIC_ASSIST_PAGE, 0);
2423 }
2424 if (cpu->hyperv_time) {
2425 kvm_msr_entry_add(cpu, HV_X64_MSR_REFERENCE_TSC, 0);
2426 }
2427 if (cpu->hyperv_reenlightenment) {
2428 kvm_msr_entry_add(cpu, HV_X64_MSR_REENLIGHTENMENT_CONTROL, 0);
2429 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_CONTROL, 0);
2430 kvm_msr_entry_add(cpu, HV_X64_MSR_TSC_EMULATION_STATUS, 0);
2431 }
2432 if (has_msr_hv_crash) {
2433 int j;
2434
2435 for (j = 0; j < HV_CRASH_PARAMS; j++) {
2436 kvm_msr_entry_add(cpu, HV_X64_MSR_CRASH_P0 + j, 0);
2437 }
2438 }
2439 if (has_msr_hv_runtime) {
2440 kvm_msr_entry_add(cpu, HV_X64_MSR_VP_RUNTIME, 0);
2441 }
2442 if (cpu->hyperv_synic) {
2443 uint32_t msr;
2444
2445 kvm_msr_entry_add(cpu, HV_X64_MSR_SCONTROL, 0);
2446 kvm_msr_entry_add(cpu, HV_X64_MSR_SIEFP, 0);
2447 kvm_msr_entry_add(cpu, HV_X64_MSR_SIMP, 0);
2448 for (msr = HV_X64_MSR_SINT0; msr <= HV_X64_MSR_SINT15; msr++) {
2449 kvm_msr_entry_add(cpu, msr, 0);
2450 }
2451 }
2452 if (has_msr_hv_stimer) {
2453 uint32_t msr;
2454
2455 for (msr = HV_X64_MSR_STIMER0_CONFIG; msr <= HV_X64_MSR_STIMER3_COUNT;
2456 msr++) {
2457 kvm_msr_entry_add(cpu, msr, 0);
2458 }
2459 }
2460 if (env->features[FEAT_1_EDX] & CPUID_MTRR) {
2461 kvm_msr_entry_add(cpu, MSR_MTRRdefType, 0);
2462 kvm_msr_entry_add(cpu, MSR_MTRRfix64K_00000, 0);
2463 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_80000, 0);
2464 kvm_msr_entry_add(cpu, MSR_MTRRfix16K_A0000, 0);
2465 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C0000, 0);
2466 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_C8000, 0);
2467 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D0000, 0);
2468 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_D8000, 0);
2469 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E0000, 0);
2470 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_E8000, 0);
2471 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F0000, 0);
2472 kvm_msr_entry_add(cpu, MSR_MTRRfix4K_F8000, 0);
2473 for (i = 0; i < MSR_MTRRcap_VCNT; i++) {
2474 kvm_msr_entry_add(cpu, MSR_MTRRphysBase(i), 0);
2475 kvm_msr_entry_add(cpu, MSR_MTRRphysMask(i), 0);
2476 }
2477 }
2478
2479 if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) {
2480 int addr_num =
2481 kvm_arch_get_supported_cpuid(kvm_state, 0x14, 1, R_EAX) & 0x7;
2482
2483 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CTL, 0);
2484 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_STATUS, 0);
2485 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_BASE, 0);
2486 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_OUTPUT_MASK, 0);
2487 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_CR3_MATCH, 0);
2488 for (i = 0; i < addr_num; i++) {
2489 kvm_msr_entry_add(cpu, MSR_IA32_RTIT_ADDR0_A + i, 0);
2490 }
2491 }
2492
2493 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf);
2494 if (ret < 0) {
2495 return ret;
2496 }
2497
2498 if (ret < cpu->kvm_msr_buf->nmsrs) {
2499 struct kvm_msr_entry *e = &cpu->kvm_msr_buf->entries[ret];
2500 error_report("error: failed to get MSR 0x%" PRIx32,
2501 (uint32_t)e->index);
2502 }
2503
2504 assert(ret == cpu->kvm_msr_buf->nmsrs);
2505 /*
2506 * MTRR masks: Each mask consists of 5 parts
2507 * a 10..0: must be zero
2508 * b 11 : valid bit
2509 * c n-1.12: actual mask bits
2510 * d 51..n: reserved must be zero
2511 * e 63.52: reserved must be zero
2512 *
2513 * 'n' is the number of physical bits supported by the CPU and is
2514 * apparently always <= 52. We know our 'n' but don't know what
2515 * the destinations 'n' is; it might be smaller, in which case
2516 * it masks (c) on loading. It might be larger, in which case
2517 * we fill 'd' so that d..c is consistent irrespetive of the 'n'
2518 * we're migrating to.
2519 */
2520
2521 if (cpu->fill_mtrr_mask) {
2522 QEMU_BUILD_BUG_ON(TARGET_PHYS_ADDR_SPACE_BITS > 52);
2523 assert(cpu->phys_bits <= TARGET_PHYS_ADDR_SPACE_BITS);
2524 mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits);
2525 } else {
2526 mtrr_top_bits = 0;
2527 }
2528
2529 for (i = 0; i < ret; i++) {
2530 uint32_t index = msrs[i].index;
2531 switch (index) {
2532 case MSR_IA32_SYSENTER_CS:
2533 env->sysenter_cs = msrs[i].data;
2534 break;
2535 case MSR_IA32_SYSENTER_ESP:
2536 env->sysenter_esp = msrs[i].data;
2537 break;
2538 case MSR_IA32_SYSENTER_EIP:
2539 env->sysenter_eip = msrs[i].data;
2540 break;
2541 case MSR_PAT:
2542 env->pat = msrs[i].data;
2543 break;
2544 case MSR_STAR:
2545 env->star = msrs[i].data;
2546 break;
2547 #ifdef TARGET_X86_64
2548 case MSR_CSTAR:
2549 env->cstar = msrs[i].data;
2550 break;
2551 case MSR_KERNELGSBASE:
2552 env->kernelgsbase = msrs[i].data;
2553 break;
2554 case MSR_FMASK:
2555 env->fmask = msrs[i].data;
2556 break;
2557 case MSR_LSTAR:
2558 env->lstar = msrs[i].data;
2559 break;
2560 #endif
2561 case MSR_IA32_TSC:
2562 env->tsc = msrs[i].data;
2563 break;
2564 case MSR_TSC_AUX:
2565 env->tsc_aux = msrs[i].data;
2566 break;
2567 case MSR_TSC_ADJUST:
2568 env->tsc_adjust = msrs[i].data;
2569 break;
2570 case MSR_IA32_TSCDEADLINE:
2571 env->tsc_deadline = msrs[i].data;
2572 break;
2573 case MSR_VM_HSAVE_PA:
2574 env->vm_hsave = msrs[i].data;
2575 break;
2576 case MSR_KVM_SYSTEM_TIME:
2577 env->system_time_msr = msrs[i].data;
2578 break;
2579 case MSR_KVM_WALL_CLOCK:
2580 env->wall_clock_msr = msrs[i].data;
2581 break;
2582 case MSR_MCG_STATUS:
2583 env->mcg_status = msrs[i].data;
2584 break;
2585 case MSR_MCG_CTL:
2586 env->mcg_ctl = msrs[i].data;
2587 break;
2588 case MSR_MCG_EXT_CTL:
2589 env->mcg_ext_ctl = msrs[i].data;
2590 break;
2591 case MSR_IA32_MISC_ENABLE:
2592 env->msr_ia32_misc_enable = msrs[i].data;
2593 break;
2594 case MSR_IA32_SMBASE:
2595 env->smbase = msrs[i].data;
2596 break;
2597 case MSR_SMI_COUNT:
2598 env->msr_smi_count = msrs[i].data;
2599 break;
2600 case MSR_IA32_FEATURE_CONTROL:
2601 env->msr_ia32_feature_control = msrs[i].data;
2602 break;
2603 case MSR_IA32_BNDCFGS:
2604 env->msr_bndcfgs = msrs[i].data;
2605 break;
2606 case MSR_IA32_XSS:
2607 env->xss = msrs[i].data;
2608 break;
2609 default:
2610 if (msrs[i].index >= MSR_MC0_CTL &&
2611 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
2612 env->mce_banks[msrs[i].index - MSR_MC0_CTL] = msrs[i].data;
2613 }
2614 break;
2615 case MSR_KVM_ASYNC_PF_EN:
2616 env->async_pf_en_msr = msrs[i].data;
2617 break;
2618 case MSR_KVM_PV_EOI_EN:
2619 env->pv_eoi_en_msr = msrs[i].data;
2620 break;
2621 case MSR_KVM_STEAL_TIME:
2622 env->steal_time_msr = msrs[i].data;
2623 break;
2624 case MSR_CORE_PERF_FIXED_CTR_CTRL:
2625 env->msr_fixed_ctr_ctrl = msrs[i].data;
2626 break;
2627 case MSR_CORE_PERF_GLOBAL_CTRL:
2628 env->msr_global_ctrl = msrs[i].data;
2629 break;
2630 case MSR_CORE_PERF_GLOBAL_STATUS:
2631 env->msr_global_status = msrs[i].data;
2632 break;
2633 case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
2634 env->msr_global_ovf_ctrl = msrs[i].data;
2635 break;
2636 case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
2637 env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
2638 break;
2639 case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR0 + MAX_GP_COUNTERS - 1:
2640 env->msr_gp_counters[index - MSR_P6_PERFCTR0] = msrs[i].data;
2641 break;
2642 case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1:
2643 env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] = msrs[i].data;
2644 break;
2645 case HV_X64_MSR_HYPERCALL:
2646 env->msr_hv_hypercall = msrs[i].data;
2647 break;
2648 case HV_X64_MSR_GUEST_OS_ID:
2649 env->msr_hv_guest_os_id = msrs[i].data;
2650 break;
2651 case HV_X64_MSR_APIC_ASSIST_PAGE:
2652 env->msr_hv_vapic = msrs[i].data;
2653 break;
2654 case HV_X64_MSR_REFERENCE_TSC:
2655 env->msr_hv_tsc = msrs[i].data;
2656 break;
2657 case HV_X64_MSR_CRASH_P0 ... HV_X64_MSR_CRASH_P4:
2658 env->msr_hv_crash_params[index - HV_X64_MSR_CRASH_P0] = msrs[i].data;
2659 break;
2660 case HV_X64_MSR_VP_RUNTIME:
2661 env->msr_hv_runtime = msrs[i].data;
2662 break;
2663 case HV_X64_MSR_SCONTROL:
2664 env->msr_hv_synic_control = msrs[i].data;
2665 break;
2666 case HV_X64_MSR_SIEFP:
2667 env->msr_hv_synic_evt_page = msrs[i].data;
2668 break;
2669 case HV_X64_MSR_SIMP:
2670 env->msr_hv_synic_msg_page = msrs[i].data;
2671 break;
2672 case HV_X64_MSR_SINT0 ... HV_X64_MSR_SINT15:
2673 env->msr_hv_synic_sint[index - HV_X64_MSR_SINT0] = msrs[i].data;
2674 break;
2675 case HV_X64_MSR_STIMER0_CONFIG:
2676 case HV_X64_MSR_STIMER1_CONFIG:
2677 case HV_X64_MSR_STIMER2_CONFIG:
2678 case HV_X64_MSR_STIMER3_CONFIG:
2679 env->msr_hv_stimer_config[(index - HV_X64_MSR_STIMER0_CONFIG)/2] =
2680 msrs[i].data;
2681 break;
2682 case HV_X64_MSR_STIMER0_COUNT:
2683 case HV_X64_MSR_STIMER1_COUNT:
2684 case HV_X64_MSR_STIMER2_COUNT:
2685 case HV_X64_MSR_STIMER3_COUNT:
2686 env->msr_hv_stimer_count[(index - HV_X64_MSR_STIMER0_COUNT)/2] =
2687 msrs[i].data;
2688 break;
2689 case HV_X64_MSR_REENLIGHTENMENT_CONTROL:
2690 env->msr_hv_reenlightenment_control = msrs[i].data;
2691 break;
2692 case HV_X64_MSR_TSC_EMULATION_CONTROL:
2693 env->msr_hv_tsc_emulation_control = msrs[i].data;
2694 break;
2695 case HV_X64_MSR_TSC_EMULATION_STATUS:
2696 env->msr_hv_tsc_emulation_status = msrs[i].data;
2697 break;
2698 case MSR_MTRRdefType:
2699 env->mtrr_deftype = msrs[i].data;
2700 break;
2701 case MSR_MTRRfix64K_00000:
2702 env->mtrr_fixed[0] = msrs[i].data;
2703 break;
2704 case MSR_MTRRfix16K_80000:
2705 env->mtrr_fixed[1] = msrs[i].data;
2706 break;
2707 case MSR_MTRRfix16K_A0000:
2708 env->mtrr_fixed[2] = msrs[i].data;
2709 break;
2710 case MSR_MTRRfix4K_C0000:
2711 env->mtrr_fixed[3] = msrs[i].data;
2712 break;
2713 case MSR_MTRRfix4K_C8000:
2714 env->mtrr_fixed[4] = msrs[i].data;
2715 break;
2716 case MSR_MTRRfix4K_D0000:
2717 env->mtrr_fixed[5] = msrs[i].data;
2718 break;
2719 case MSR_MTRRfix4K_D8000:
2720 env->mtrr_fixed[6] = msrs[i].data;
2721 break;
2722 case MSR_MTRRfix4K_E0000:
2723 env->mtrr_fixed[7] = msrs[i].data;
2724 break;
2725 case MSR_MTRRfix4K_E8000:
2726 env->mtrr_fixed[8] = msrs[i].data;
2727 break;
2728 case MSR_MTRRfix4K_F0000:
2729 env->mtrr_fixed[9] = msrs[i].data;
2730 break;
2731 case MSR_MTRRfix4K_F8000:
2732 env->mtrr_fixed[10] = msrs[i].data;
2733 break;
2734 case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1):
2735 if (index & 1) {
2736 env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data |
2737 mtrr_top_bits;
2738 } else {
2739 env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data;
2740 }
2741 break;
2742 case MSR_IA32_SPEC_CTRL:
2743 env->spec_ctrl = msrs[i].data;
2744 break;
2745 case MSR_VIRT_SSBD:
2746 env->virt_ssbd = msrs[i].data;
2747 break;
2748 case MSR_IA32_RTIT_CTL:
2749 env->msr_rtit_ctrl = msrs[i].data;
2750 break;
2751 case MSR_IA32_RTIT_STATUS:
2752 env->msr_rtit_status = msrs[i].data;
2753 break;
2754 case MSR_IA32_RTIT_OUTPUT_BASE:
2755 env->msr_rtit_output_base = msrs[i].data;
2756 break;
2757 case MSR_IA32_RTIT_OUTPUT_MASK:
2758 env->msr_rtit_output_mask = msrs[i].data;
2759 break;
2760 case MSR_IA32_RTIT_CR3_MATCH:
2761 env->msr_rtit_cr3_match = msrs[i].data;
2762 break;
2763 case MSR_IA32_RTIT_ADDR0_A ... MSR_IA32_RTIT_ADDR3_B:
2764 env->msr_rtit_addrs[index - MSR_IA32_RTIT_ADDR0_A] = msrs[i].data;
2765 break;
2766 }
2767 }
2768
2769 return 0;
2770 }
2771
2772 static int kvm_put_mp_state(X86CPU *cpu)
2773 {
2774 struct kvm_mp_state mp_state = { .mp_state = cpu->env.mp_state };
2775
2776 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MP_STATE, &mp_state);
2777 }
2778
2779 static int kvm_get_mp_state(X86CPU *cpu)
2780 {
2781 CPUState *cs = CPU(cpu);
2782 CPUX86State *env = &cpu->env;
2783 struct kvm_mp_state mp_state;
2784 int ret;
2785
2786 ret = kvm_vcpu_ioctl(cs, KVM_GET_MP_STATE, &mp_state);
2787 if (ret < 0) {
2788 return ret;
2789 }
2790 env->mp_state = mp_state.mp_state;
2791 if (kvm_irqchip_in_kernel()) {
2792 cs->halted = (mp_state.mp_state == KVM_MP_STATE_HALTED);
2793 }
2794 return 0;
2795 }
2796
2797 static int kvm_get_apic(X86CPU *cpu)
2798 {
2799 DeviceState *apic = cpu->apic_state;
2800 struct kvm_lapic_state kapic;
2801 int ret;
2802
2803 if (apic && kvm_irqchip_in_kernel()) {
2804 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_LAPIC, &kapic);
2805 if (ret < 0) {
2806 return ret;
2807 }
2808
2809 kvm_get_apic_state(apic, &kapic);
2810 }
2811 return 0;
2812 }
2813
2814 static int kvm_put_vcpu_events(X86CPU *cpu, int level)
2815 {
2816 CPUState *cs = CPU(cpu);
2817 CPUX86State *env = &cpu->env;
2818 struct kvm_vcpu_events events = {};
2819
2820 if (!kvm_has_vcpu_events()) {
2821 return 0;
2822 }
2823
2824 events.exception.injected = (env->exception_injected >= 0);
2825 events.exception.nr = env->exception_injected;
2826 events.exception.has_error_code = env->has_error_code;
2827 events.exception.error_code = env->error_code;
2828
2829 events.interrupt.injected = (env->interrupt_injected >= 0);
2830 events.interrupt.nr = env->interrupt_injected;
2831 events.interrupt.soft = env->soft_interrupt;
2832
2833 events.nmi.injected = env->nmi_injected;
2834 events.nmi.pending = env->nmi_pending;
2835 events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
2836
2837 events.sipi_vector = env->sipi_vector;
2838 events.flags = 0;
2839
2840 if (has_msr_smbase) {
2841 events.smi.smm = !!(env->hflags & HF_SMM_MASK);
2842 events.smi.smm_inside_nmi = !!(env->hflags2 & HF2_SMM_INSIDE_NMI_MASK);
2843 if (kvm_irqchip_in_kernel()) {
2844 /* As soon as these are moved to the kernel, remove them
2845 * from cs->interrupt_request.
2846 */
2847 events.smi.pending = cs->interrupt_request & CPU_INTERRUPT_SMI;
2848 events.smi.latched_init = cs->interrupt_request & CPU_INTERRUPT_INIT;
2849 cs->interrupt_request &= ~(CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI);
2850 } else {
2851 /* Keep these in cs->interrupt_request. */
2852 events.smi.pending = 0;
2853 events.smi.latched_init = 0;
2854 }
2855 /* Stop SMI delivery on old machine types to avoid a reboot
2856 * on an inward migration of an old VM.
2857 */
2858 if (!cpu->kvm_no_smi_migration) {
2859 events.flags |= KVM_VCPUEVENT_VALID_SMM;
2860 }
2861 }
2862
2863 if (level >= KVM_PUT_RESET_STATE) {
2864 events.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
2865 if (env->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
2866 events.flags |= KVM_VCPUEVENT_VALID_SIPI_VECTOR;
2867 }
2868 }
2869
2870 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_VCPU_EVENTS, &events);
2871 }
2872
2873 static int kvm_get_vcpu_events(X86CPU *cpu)
2874 {
2875 CPUX86State *env = &cpu->env;
2876 struct kvm_vcpu_events events;
2877 int ret;
2878
2879 if (!kvm_has_vcpu_events()) {
2880 return 0;
2881 }
2882
2883 memset(&events, 0, sizeof(events));
2884 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_VCPU_EVENTS, &events);
2885 if (ret < 0) {
2886 return ret;
2887 }
2888 env->exception_injected =
2889 events.exception.injected ? events.exception.nr : -1;
2890 env->has_error_code = events.exception.has_error_code;
2891 env->error_code = events.exception.error_code;
2892
2893 env->interrupt_injected =
2894 events.interrupt.injected ? events.interrupt.nr : -1;
2895 env->soft_interrupt = events.interrupt.soft;
2896
2897 env->nmi_injected = events.nmi.injected;
2898 env->nmi_pending = events.nmi.pending;
2899 if (events.nmi.masked) {
2900 env->hflags2 |= HF2_NMI_MASK;
2901 } else {
2902 env->hflags2 &= ~HF2_NMI_MASK;
2903 }
2904
2905 if (events.flags & KVM_VCPUEVENT_VALID_SMM) {
2906 if (events.smi.smm) {
2907 env->hflags |= HF_SMM_MASK;
2908 } else {
2909 env->hflags &= ~HF_SMM_MASK;
2910 }
2911 if (events.smi.pending) {
2912 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2913 } else {
2914 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_SMI);
2915 }
2916 if (events.smi.smm_inside_nmi) {
2917 env->hflags2 |= HF2_SMM_INSIDE_NMI_MASK;
2918 } else {
2919 env->hflags2 &= ~HF2_SMM_INSIDE_NMI_MASK;
2920 }
2921 if (events.smi.latched_init) {
2922 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2923 } else {
2924 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_INIT);
2925 }
2926 }
2927
2928 env->sipi_vector = events.sipi_vector;
2929
2930 return 0;
2931 }
2932
2933 static int kvm_guest_debug_workarounds(X86CPU *cpu)
2934 {
2935 CPUState *cs = CPU(cpu);
2936 CPUX86State *env = &cpu->env;
2937 int ret = 0;
2938 unsigned long reinject_trap = 0;
2939
2940 if (!kvm_has_vcpu_events()) {
2941 if (env->exception_injected == 1) {
2942 reinject_trap = KVM_GUESTDBG_INJECT_DB;
2943 } else if (env->exception_injected == 3) {
2944 reinject_trap = KVM_GUESTDBG_INJECT_BP;
2945 }
2946 env->exception_injected = -1;
2947 }
2948
2949 /*
2950 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
2951 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
2952 * by updating the debug state once again if single-stepping is on.
2953 * Another reason to call kvm_update_guest_debug here is a pending debug
2954 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
2955 * reinject them via SET_GUEST_DEBUG.
2956 */
2957 if (reinject_trap ||
2958 (!kvm_has_robust_singlestep() && cs->singlestep_enabled)) {
2959 ret = kvm_update_guest_debug(cs, reinject_trap);
2960 }
2961 return ret;
2962 }
2963
2964 static int kvm_put_debugregs(X86CPU *cpu)
2965 {
2966 CPUX86State *env = &cpu->env;
2967 struct kvm_debugregs dbgregs;
2968 int i;
2969
2970 if (!kvm_has_debugregs()) {
2971 return 0;
2972 }
2973
2974 for (i = 0; i < 4; i++) {
2975 dbgregs.db[i] = env->dr[i];
2976 }
2977 dbgregs.dr6 = env->dr[6];
2978 dbgregs.dr7 = env->dr[7];
2979 dbgregs.flags = 0;
2980
2981 return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_DEBUGREGS, &dbgregs);
2982 }
2983
2984 static int kvm_get_debugregs(X86CPU *cpu)
2985 {
2986 CPUX86State *env = &cpu->env;
2987 struct kvm_debugregs dbgregs;
2988 int i, ret;
2989
2990 if (!kvm_has_debugregs()) {
2991 return 0;
2992 }
2993
2994 ret = kvm_vcpu_ioctl(CPU(cpu), KVM_GET_DEBUGREGS, &dbgregs);
2995 if (ret < 0) {
2996 return ret;
2997 }
2998 for (i = 0; i < 4; i++) {
2999 env->dr[i] = dbgregs.db[i];
3000 }
3001 env->dr[4] = env->dr[6] = dbgregs.dr6;
3002 env->dr[5] = env->dr[7] = dbgregs.dr7;
3003
3004 return 0;
3005 }
3006
3007 int kvm_arch_put_registers(CPUState *cpu, int level)
3008 {
3009 X86CPU *x86_cpu = X86_CPU(cpu);
3010 int ret;
3011
3012 assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu));
3013
3014 if (level >= KVM_PUT_RESET_STATE) {
3015 ret = kvm_put_msr_feature_control(x86_cpu);
3016 if (ret < 0) {
3017 return ret;
3018 }
3019 }
3020
3021 if (level == KVM_PUT_FULL_STATE) {
3022 /* We don't check for kvm_arch_set_tsc_khz() errors here,
3023 * because TSC frequency mismatch shouldn't abort migration,
3024 * unless the user explicitly asked for a more strict TSC
3025 * setting (e.g. using an explicit "tsc-freq" option).
3026 */
3027 kvm_arch_set_tsc_khz(cpu);
3028 }
3029
3030 ret = kvm_getput_regs(x86_cpu, 1);
3031 if (ret < 0) {
3032 return ret;
3033 }
3034 ret = kvm_put_xsave(x86_cpu);
3035 if (ret < 0) {
3036 return ret;
3037 }
3038 ret = kvm_put_xcrs(x86_cpu);
3039 if (ret < 0) {
3040 return ret;
3041 }
3042 ret = kvm_put_sregs(x86_cpu);
3043 if (ret < 0) {
3044 return ret;
3045 }
3046 /* must be before kvm_put_msrs */
3047 ret = kvm_inject_mce_oldstyle(x86_cpu);
3048 if (ret < 0) {
3049 return ret;
3050 }
3051 ret = kvm_put_msrs(x86_cpu, level);
3052 if (ret < 0) {
3053 return ret;
3054 }
3055 ret = kvm_put_vcpu_events(x86_cpu, level);
3056 if (ret < 0) {
3057 return ret;
3058 }
3059 if (level >= KVM_PUT_RESET_STATE) {
3060 ret = kvm_put_mp_state(x86_cpu);
3061 if (ret < 0) {
3062 return ret;
3063 }
3064 }
3065
3066 ret = kvm_put_tscdeadline_msr(x86_cpu);
3067 if (ret < 0) {
3068 return ret;
3069 }
3070 ret = kvm_put_debugregs(x86_cpu);
3071 if (ret < 0) {
3072 return ret;
3073 }
3074 /* must be last */
3075 ret = kvm_guest_debug_workarounds(x86_cpu);
3076 if (ret < 0) {
3077 return ret;
3078 }
3079 return 0;
3080 }
3081
3082 int kvm_arch_get_registers(CPUState *cs)
3083 {
3084 X86CPU *cpu = X86_CPU(cs);
3085 int ret;
3086
3087 assert(cpu_is_stopped(cs) || qemu_cpu_is_self(cs));
3088
3089 ret = kvm_get_vcpu_events(cpu);
3090 if (ret < 0) {
3091 goto out;
3092 }
3093 /*
3094 * KVM_GET_MPSTATE can modify CS and RIP, call it before
3095 * KVM_GET_REGS and KVM_GET_SREGS.
3096 */
3097 ret = kvm_get_mp_state(cpu);
3098 if (ret < 0) {
3099 goto out;
3100 }
3101 ret = kvm_getput_regs(cpu, 0);
3102 if (ret < 0) {
3103 goto out;
3104 }
3105 ret = kvm_get_xsave(cpu);
3106 if (ret < 0) {
3107 goto out;
3108 }
3109 ret = kvm_get_xcrs(cpu);
3110 if (ret < 0) {
3111 goto out;
3112 }
3113 ret = kvm_get_sregs(cpu);
3114 if (ret < 0) {
3115 goto out;
3116 }
3117 ret = kvm_get_msrs(cpu);
3118 if (ret < 0) {
3119 goto out;
3120 }
3121 ret = kvm_get_apic(cpu);
3122 if (ret < 0) {
3123 goto out;
3124 }
3125 ret = kvm_get_debugregs(cpu);
3126 if (ret < 0) {
3127 goto out;
3128 }
3129 ret = 0;
3130 out:
3131 cpu_sync_bndcs_hflags(&cpu->env);
3132 return ret;
3133 }
3134
3135 void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *run)
3136 {
3137 X86CPU *x86_cpu = X86_CPU(cpu);
3138 CPUX86State *env = &x86_cpu->env;
3139 int ret;
3140
3141 /* Inject NMI */
3142 if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) {
3143 if (cpu->interrupt_request & CPU_INTERRUPT_NMI) {
3144 qemu_mutex_lock_iothread();
3145 cpu->interrupt_request &= ~CPU_INTERRUPT_NMI;
3146 qemu_mutex_unlock_iothread();
3147 DPRINTF("injected NMI\n");
3148 ret = kvm_vcpu_ioctl(cpu, KVM_NMI);
3149 if (ret < 0) {
3150 fprintf(stderr, "KVM: injection failed, NMI lost (%s)\n",
3151 strerror(-ret));
3152 }
3153 }
3154 if (cpu->interrupt_request & CPU_INTERRUPT_SMI) {
3155 qemu_mutex_lock_iothread();
3156 cpu->interrupt_request &= ~CPU_INTERRUPT_SMI;
3157 qemu_mutex_unlock_iothread();
3158 DPRINTF("injected SMI\n");
3159 ret = kvm_vcpu_ioctl(cpu, KVM_SMI);
3160 if (ret < 0) {
3161 fprintf(stderr, "KVM: injection failed, SMI lost (%s)\n",
3162 strerror(-ret));
3163 }
3164 }
3165 }
3166
3167 if (!kvm_pic_in_kernel()) {
3168 qemu_mutex_lock_iothread();
3169 }
3170
3171 /* Force the VCPU out of its inner loop to process any INIT requests
3172 * or (for userspace APIC, but it is cheap to combine the checks here)
3173 * pending TPR access reports.
3174 */
3175 if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) {
3176 if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) &&
3177 !(env->hflags & HF_SMM_MASK)) {
3178 cpu->exit_request = 1;
3179 }
3180 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) {
3181 cpu->exit_request = 1;
3182 }
3183 }
3184
3185 if (!kvm_pic_in_kernel()) {
3186 /* Try to inject an interrupt if the guest can accept it */
3187 if (run->ready_for_interrupt_injection &&
3188 (cpu->interrupt_request & CPU_INTERRUPT_HARD) &&
3189 (env->eflags & IF_MASK)) {
3190 int irq;
3191
3192 cpu->interrupt_request &= ~CPU_INTERRUPT_HARD;
3193 irq = cpu_get_pic_interrupt(env);
3194 if (irq >= 0) {
3195 struct kvm_interrupt intr;
3196
3197 intr.irq = irq;
3198 DPRINTF("injected interrupt %d\n", irq);
3199 ret = kvm_vcpu_ioctl(cpu, KVM_INTERRUPT, &intr);
3200 if (ret < 0) {
3201 fprintf(stderr,
3202 "KVM: injection failed, interrupt lost (%s)\n",
3203 strerror(-ret));
3204 }
3205 }
3206 }
3207
3208 /* If we have an interrupt but the guest is not ready to receive an
3209 * interrupt, request an interrupt window exit. This will
3210 * cause a return to userspace as soon as the guest is ready to
3211 * receive interrupts. */
3212 if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) {
3213 run->request_interrupt_window = 1;
3214 } else {
3215 run->request_interrupt_window = 0;
3216 }
3217
3218 DPRINTF("setting tpr\n");
3219 run->cr8 = cpu_get_apic_tpr(x86_cpu->apic_state);
3220
3221 qemu_mutex_unlock_iothread();
3222 }
3223 }
3224
3225 MemTxAttrs kvm_arch_post_run(CPUState *cpu, struct kvm_run *run)
3226 {
3227 X86CPU *x86_cpu = X86_CPU(cpu);
3228 CPUX86State *env = &x86_cpu->env;
3229
3230 if (run->flags & KVM_RUN_X86_SMM) {
3231 env->hflags |= HF_SMM_MASK;
3232 } else {
3233 env->hflags &= ~HF_SMM_MASK;
3234 }
3235 if (run->if_flag) {
3236 env->eflags |= IF_MASK;
3237 } else {
3238 env->eflags &= ~IF_MASK;
3239 }
3240
3241 /* We need to protect the apic state against concurrent accesses from
3242 * different threads in case the userspace irqchip is used. */
3243 if (!kvm_irqchip_in_kernel()) {
3244 qemu_mutex_lock_iothread();
3245 }
3246 cpu_set_apic_tpr(x86_cpu->apic_state, run->cr8);
3247 cpu_set_apic_base(x86_cpu->apic_state, run->apic_base);
3248 if (!kvm_irqchip_in_kernel()) {
3249 qemu_mutex_unlock_iothread();
3250 }
3251 return cpu_get_mem_attrs(env);
3252 }
3253
3254 int kvm_arch_process_async_events(CPUState *cs)
3255 {
3256 X86CPU *cpu = X86_CPU(cs);
3257 CPUX86State *env = &cpu->env;
3258
3259 if (cs->interrupt_request & CPU_INTERRUPT_MCE) {
3260 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
3261 assert(env->mcg_cap);
3262
3263 cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
3264
3265 kvm_cpu_synchronize_state(cs);
3266
3267 if (env->exception_injected == EXCP08_DBLE) {
3268 /* this means triple fault */
3269 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
3270 cs->exit_request = 1;
3271 return 0;
3272 }
3273 env->exception_injected = EXCP12_MCHK;
3274 env->has_error_code = 0;
3275
3276 cs->halted = 0;
3277 if (kvm_irqchip_in_kernel() && env->mp_state == KVM_MP_STATE_HALTED) {
3278 env->mp_state = KVM_MP_STATE_RUNNABLE;
3279 }
3280 }
3281
3282 if ((cs->interrupt_request & CPU_INTERRUPT_INIT) &&
3283 !(env->hflags & HF_SMM_MASK)) {
3284 kvm_cpu_synchronize_state(cs);
3285 do_cpu_init(cpu);
3286 }
3287
3288 if (kvm_irqchip_in_kernel()) {
3289 return 0;
3290 }
3291
3292 if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
3293 cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
3294 apic_poll_irq(cpu->apic_state);
3295 }
3296 if (((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3297 (env->eflags & IF_MASK)) ||
3298 (cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3299 cs->halted = 0;
3300 }
3301 if (cs->interrupt_request & CPU_INTERRUPT_SIPI) {
3302 kvm_cpu_synchronize_state(cs);
3303 do_cpu_sipi(cpu);
3304 }
3305 if (cs->interrupt_request & CPU_INTERRUPT_TPR) {
3306 cs->interrupt_request &= ~CPU_INTERRUPT_TPR;
3307 kvm_cpu_synchronize_state(cs);
3308 apic_handle_tpr_access_report(cpu->apic_state, env->eip,
3309 env->tpr_access_type);
3310 }
3311
3312 return cs->halted;
3313 }
3314
3315 static int kvm_handle_halt(X86CPU *cpu)
3316 {
3317 CPUState *cs = CPU(cpu);
3318 CPUX86State *env = &cpu->env;
3319
3320 if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
3321 (env->eflags & IF_MASK)) &&
3322 !(cs->interrupt_request & CPU_INTERRUPT_NMI)) {
3323 cs->halted = 1;
3324 return EXCP_HLT;
3325 }
3326
3327 return 0;
3328 }
3329
3330 static int kvm_handle_tpr_access(X86CPU *cpu)
3331 {
3332 CPUState *cs = CPU(cpu);
3333 struct kvm_run *run = cs->kvm_run;
3334
3335 apic_handle_tpr_access_report(cpu->apic_state, run->tpr_access.rip,
3336 run->tpr_access.is_write ? TPR_ACCESS_WRITE
3337 : TPR_ACCESS_READ);
3338 return 1;
3339 }
3340
3341 int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3342 {
3343 static const uint8_t int3 = 0xcc;
3344
3345 if (cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
3346 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&int3, 1, 1)) {
3347 return -EINVAL;
3348 }
3349 return 0;
3350 }
3351
3352 int kvm_arch_remove_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint *bp)
3353 {
3354 uint8_t int3;
3355
3356 if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
3357 cpu_memory_rw_debug(cs, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1)) {
3358 return -EINVAL;
3359 }
3360 return 0;
3361 }
3362
3363 static struct {
3364 target_ulong addr;
3365 int len;
3366 int type;
3367 } hw_breakpoint[4];
3368
3369 static int nb_hw_breakpoint;
3370
3371 static int find_hw_breakpoint(target_ulong addr, int len, int type)
3372 {
3373 int n;
3374
3375 for (n = 0; n < nb_hw_breakpoint; n++) {
3376 if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
3377 (hw_breakpoint[n].len == len || len == -1)) {
3378 return n;
3379 }
3380 }
3381 return -1;
3382 }
3383
3384 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
3385 target_ulong len, int type)
3386 {
3387 switch (type) {
3388 case GDB_BREAKPOINT_HW:
3389 len = 1;
3390 break;
3391 case GDB_WATCHPOINT_WRITE:
3392 case GDB_WATCHPOINT_ACCESS:
3393 switch (len) {
3394 case 1:
3395 break;
3396 case 2:
3397 case 4:
3398 case 8:
3399 if (addr & (len - 1)) {
3400 return -EINVAL;
3401 }
3402 break;
3403 default:
3404 return -EINVAL;
3405 }
3406 break;
3407 default:
3408 return -ENOSYS;
3409 }
3410
3411 if (nb_hw_breakpoint == 4) {
3412 return -ENOBUFS;
3413 }
3414 if (find_hw_breakpoint(addr, len, type) >= 0) {
3415 return -EEXIST;
3416 }
3417 hw_breakpoint[nb_hw_breakpoint].addr = addr;
3418 hw_breakpoint[nb_hw_breakpoint].len = len;
3419 hw_breakpoint[nb_hw_breakpoint].type = type;
3420 nb_hw_breakpoint++;
3421
3422 return 0;
3423 }
3424
3425 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
3426 target_ulong len, int type)
3427 {
3428 int n;
3429
3430 n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
3431 if (n < 0) {
3432 return -ENOENT;
3433 }
3434 nb_hw_breakpoint--;
3435 hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
3436
3437 return 0;
3438 }
3439
3440 void kvm_arch_remove_all_hw_breakpoints(void)
3441 {
3442 nb_hw_breakpoint = 0;
3443 }
3444
3445 static CPUWatchpoint hw_watchpoint;
3446
3447 static int kvm_handle_debug(X86CPU *cpu,
3448 struct kvm_debug_exit_arch *arch_info)
3449 {
3450 CPUState *cs = CPU(cpu);
3451 CPUX86State *env = &cpu->env;
3452 int ret = 0;
3453 int n;
3454
3455 if (arch_info->exception == 1) {
3456 if (arch_info->dr6 & (1 << 14)) {
3457 if (cs->singlestep_enabled) {
3458 ret = EXCP_DEBUG;
3459 }
3460 } else {
3461 for (n = 0; n < 4; n++) {
3462 if (arch_info->dr6 & (1 << n)) {
3463 switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
3464 case 0x0:
3465 ret = EXCP_DEBUG;
3466 break;
3467 case 0x1:
3468 ret = EXCP_DEBUG;
3469 cs->watchpoint_hit = &hw_watchpoint;
3470 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3471 hw_watchpoint.flags = BP_MEM_WRITE;
3472 break;
3473 case 0x3:
3474 ret = EXCP_DEBUG;
3475 cs->watchpoint_hit = &hw_watchpoint;
3476 hw_watchpoint.vaddr = hw_breakpoint[n].addr;
3477 hw_watchpoint.flags = BP_MEM_ACCESS;
3478 break;
3479 }
3480 }
3481 }
3482 }
3483 } else if (kvm_find_sw_breakpoint(cs, arch_info->pc)) {
3484 ret = EXCP_DEBUG;
3485 }
3486 if (ret == 0) {
3487 cpu_synchronize_state(cs);
3488 assert(env->exception_injected == -1);
3489
3490 /* pass to guest */
3491 env->exception_injected = arch_info->exception;
3492 env->has_error_code = 0;
3493 }
3494
3495 return ret;
3496 }
3497
3498 void kvm_arch_update_guest_debug(CPUState *cpu, struct kvm_guest_debug *dbg)
3499 {
3500 const uint8_t type_code[] = {
3501 [GDB_BREAKPOINT_HW] = 0x0,
3502 [GDB_WATCHPOINT_WRITE] = 0x1,
3503 [GDB_WATCHPOINT_ACCESS] = 0x3
3504 };
3505 const uint8_t len_code[] = {
3506 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
3507 };
3508 int n;
3509
3510 if (kvm_sw_breakpoints_active(cpu)) {
3511 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
3512 }
3513 if (nb_hw_breakpoint > 0) {
3514 dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
3515 dbg->arch.debugreg[7] = 0x0600;
3516 for (n = 0; n < nb_hw_breakpoint; n++) {
3517 dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
3518 dbg->arch.debugreg[7] |= (2 << (n * 2)) |
3519 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
3520 ((uint32_t)len_code[hw_breakpoint[n].len] << (18 + n*4));
3521 }
3522 }
3523 }
3524
3525 static bool host_supports_vmx(void)
3526 {
3527 uint32_t ecx, unused;
3528
3529 host_cpuid(1, 0, &unused, &unused, &ecx, &unused);
3530 return ecx & CPUID_EXT_VMX;
3531 }
3532
3533 #define VMX_INVALID_GUEST_STATE 0x80000021
3534
3535 int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
3536 {
3537 X86CPU *cpu = X86_CPU(cs);
3538 uint64_t code;
3539 int ret;
3540
3541 switch (run->exit_reason) {
3542 case KVM_EXIT_HLT:
3543 DPRINTF("handle_hlt\n");
3544 qemu_mutex_lock_iothread();
3545 ret = kvm_handle_halt(cpu);
3546 qemu_mutex_unlock_iothread();
3547 break;
3548 case KVM_EXIT_SET_TPR:
3549 ret = 0;
3550 break;
3551 case KVM_EXIT_TPR_ACCESS:
3552 qemu_mutex_lock_iothread();
3553 ret = kvm_handle_tpr_access(cpu);
3554 qemu_mutex_unlock_iothread();
3555 break;
3556 case KVM_EXIT_FAIL_ENTRY:
3557 code = run->fail_entry.hardware_entry_failure_reason;
3558 fprintf(stderr, "KVM: entry failed, hardware error 0x%" PRIx64 "\n",
3559 code);
3560 if (host_supports_vmx() && code == VMX_INVALID_GUEST_STATE) {
3561 fprintf(stderr,
3562 "\nIf you're running a guest on an Intel machine without "
3563 "unrestricted mode\n"
3564 "support, the failure can be most likely due to the guest "
3565 "entering an invalid\n"
3566 "state for Intel VT. For example, the guest maybe running "
3567 "in big real mode\n"
3568 "which is not supported on less recent Intel processors."
3569 "\n\n");
3570 }
3571 ret = -1;
3572 break;
3573 case KVM_EXIT_EXCEPTION:
3574 fprintf(stderr, "KVM: exception %d exit (error code 0x%x)\n",
3575 run->ex.exception, run->ex.error_code);
3576 ret = -1;
3577 break;
3578 case KVM_EXIT_DEBUG:
3579 DPRINTF("kvm_exit_debug\n");
3580 qemu_mutex_lock_iothread();
3581 ret = kvm_handle_debug(cpu, &run->debug.arch);
3582 qemu_mutex_unlock_iothread();
3583 break;
3584 case KVM_EXIT_HYPERV:
3585 ret = kvm_hv_handle_exit(cpu, &run->hyperv);
3586 break;
3587 case KVM_EXIT_IOAPIC_EOI:
3588 ioapic_eoi_broadcast(run->eoi.vector);
3589 ret = 0;
3590 break;
3591 default:
3592 fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);
3593 ret = -1;
3594 break;
3595 }
3596
3597 return ret;
3598 }
3599
3600 bool kvm_arch_stop_on_emulation_error(CPUState *cs)
3601 {
3602 X86CPU *cpu = X86_CPU(cs);
3603 CPUX86State *env = &cpu->env;
3604
3605 kvm_cpu_synchronize_state(cs);
3606 return !(env->cr[0] & CR0_PE_MASK) ||
3607 ((env->segs[R_CS].selector & 3) != 3);
3608 }
3609
3610 void kvm_arch_init_irq_routing(KVMState *s)
3611 {
3612 if (!kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
3613 /* If kernel can't do irq routing, interrupt source
3614 * override 0->2 cannot be set up as required by HPET.
3615 * So we have to disable it.
3616 */
3617 no_hpet = 1;
3618 }
3619 /* We know at this point that we're using the in-kernel
3620 * irqchip, so we can use irqfds, and on x86 we know
3621 * we can use msi via irqfd and GSI routing.
3622 */
3623 kvm_msi_via_irqfd_allowed = true;
3624 kvm_gsi_routing_allowed = true;
3625
3626 if (kvm_irqchip_is_split()) {
3627 int i;
3628
3629 /* If the ioapic is in QEMU and the lapics are in KVM, reserve
3630 MSI routes for signaling interrupts to the local apics. */
3631 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
3632 if (kvm_irqchip_add_msi_route(s, 0, NULL) < 0) {
3633 error_report("Could not enable split IRQ mode.");
3634 exit(1);
3635 }
3636 }
3637 }
3638 }
3639
3640 int kvm_arch_irqchip_create(MachineState *ms, KVMState *s)
3641 {
3642 int ret;
3643 if (machine_kernel_irqchip_split(ms)) {
3644 ret = kvm_vm_enable_cap(s, KVM_CAP_SPLIT_IRQCHIP, 0, 24);
3645 if (ret) {
3646 error_report("Could not enable split irqchip mode: %s",
3647 strerror(-ret));
3648 exit(1);
3649 } else {
3650 DPRINTF("Enabled KVM_CAP_SPLIT_IRQCHIP\n");
3651 kvm_split_irqchip = true;
3652 return 1;
3653 }
3654 } else {
3655 return 0;
3656 }
3657 }
3658
3659 /* Classic KVM device assignment interface. Will remain x86 only. */
3660 int kvm_device_pci_assign(KVMState *s, PCIHostDeviceAddress *dev_addr,
3661 uint32_t flags, uint32_t *dev_id)
3662 {
3663 struct kvm_assigned_pci_dev dev_data = {
3664 .segnr = dev_addr->domain,
3665 .busnr = dev_addr->bus,
3666 .devfn = PCI_DEVFN(dev_addr->slot, dev_addr->function),
3667 .flags = flags,
3668 };
3669 int ret;
3670
3671 dev_data.assigned_dev_id =
3672 (dev_addr->domain << 16) | (dev_addr->bus << 8) | dev_data.devfn;
3673
3674 ret = kvm_vm_ioctl(s, KVM_ASSIGN_PCI_DEVICE, &dev_data);
3675 if (ret < 0) {
3676 return ret;
3677 }
3678
3679 *dev_id = dev_data.assigned_dev_id;
3680
3681 return 0;
3682 }
3683
3684 int kvm_device_pci_deassign(KVMState *s, uint32_t dev_id)
3685 {
3686 struct kvm_assigned_pci_dev dev_data = {
3687 .assigned_dev_id = dev_id,
3688 };
3689
3690 return kvm_vm_ioctl(s, KVM_DEASSIGN_PCI_DEVICE, &dev_data);
3691 }
3692
3693 static int kvm_assign_irq_internal(KVMState *s, uint32_t dev_id,
3694 uint32_t irq_type, uint32_t guest_irq)
3695 {
3696 struct kvm_assigned_irq assigned_irq = {
3697 .assigned_dev_id = dev_id,
3698 .guest_irq = guest_irq,
3699 .flags = irq_type,
3700 };
3701
3702 if (kvm_check_extension(s, KVM_CAP_ASSIGN_DEV_IRQ)) {
3703 return kvm_vm_ioctl(s, KVM_ASSIGN_DEV_IRQ, &assigned_irq);
3704 } else {
3705 return kvm_vm_ioctl(s, KVM_ASSIGN_IRQ, &assigned_irq);
3706 }
3707 }
3708
3709 int kvm_device_intx_assign(KVMState *s, uint32_t dev_id, bool use_host_msi,
3710 uint32_t guest_irq)
3711 {
3712 uint32_t irq_type = KVM_DEV_IRQ_GUEST_INTX |
3713 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX);
3714
3715 return kvm_assign_irq_internal(s, dev_id, irq_type, guest_irq);
3716 }
3717
3718 int kvm_device_intx_set_mask(KVMState *s, uint32_t dev_id, bool masked)
3719 {
3720 struct kvm_assigned_pci_dev dev_data = {
3721 .assigned_dev_id = dev_id,
3722 .flags = masked ? KVM_DEV_ASSIGN_MASK_INTX : 0,
3723 };
3724
3725 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_INTX_MASK, &dev_data);
3726 }
3727
3728 static int kvm_deassign_irq_internal(KVMState *s, uint32_t dev_id,
3729 uint32_t type)
3730 {
3731 struct kvm_assigned_irq assigned_irq = {
3732 .assigned_dev_id = dev_id,
3733 .flags = type,
3734 };
3735
3736 return kvm_vm_ioctl(s, KVM_DEASSIGN_DEV_IRQ, &assigned_irq);
3737 }
3738
3739 int kvm_device_intx_deassign(KVMState *s, uint32_t dev_id, bool use_host_msi)
3740 {
3741 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_INTX |
3742 (use_host_msi ? KVM_DEV_IRQ_HOST_MSI : KVM_DEV_IRQ_HOST_INTX));
3743 }
3744
3745 int kvm_device_msi_assign(KVMState *s, uint32_t dev_id, int virq)
3746 {
3747 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSI |
3748 KVM_DEV_IRQ_GUEST_MSI, virq);
3749 }
3750
3751 int kvm_device_msi_deassign(KVMState *s, uint32_t dev_id)
3752 {
3753 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSI |
3754 KVM_DEV_IRQ_HOST_MSI);
3755 }
3756
3757 bool kvm_device_msix_supported(KVMState *s)
3758 {
3759 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
3760 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
3761 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, NULL) == -EFAULT;
3762 }
3763
3764 int kvm_device_msix_init_vectors(KVMState *s, uint32_t dev_id,
3765 uint32_t nr_vectors)
3766 {
3767 struct kvm_assigned_msix_nr msix_nr = {
3768 .assigned_dev_id = dev_id,
3769 .entry_nr = nr_vectors,
3770 };
3771
3772 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_NR, &msix_nr);
3773 }
3774
3775 int kvm_device_msix_set_vector(KVMState *s, uint32_t dev_id, uint32_t vector,
3776 int virq)
3777 {
3778 struct kvm_assigned_msix_entry msix_entry = {
3779 .assigned_dev_id = dev_id,
3780 .gsi = virq,
3781 .entry = vector,
3782 };
3783
3784 return kvm_vm_ioctl(s, KVM_ASSIGN_SET_MSIX_ENTRY, &msix_entry);
3785 }
3786
3787 int kvm_device_msix_assign(KVMState *s, uint32_t dev_id)
3788 {
3789 return kvm_assign_irq_internal(s, dev_id, KVM_DEV_IRQ_HOST_MSIX |
3790 KVM_DEV_IRQ_GUEST_MSIX, 0);
3791 }
3792
3793 int kvm_device_msix_deassign(KVMState *s, uint32_t dev_id)
3794 {
3795 return kvm_deassign_irq_internal(s, dev_id, KVM_DEV_IRQ_GUEST_MSIX |
3796 KVM_DEV_IRQ_HOST_MSIX);
3797 }
3798
3799 int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
3800 uint64_t address, uint32_t data, PCIDevice *dev)
3801 {
3802 X86IOMMUState *iommu = x86_iommu_get_default();
3803
3804 if (iommu) {
3805 int ret;
3806 MSIMessage src, dst;
3807 X86IOMMUClass *class = X86_IOMMU_GET_CLASS(iommu);
3808
3809 if (!class->int_remap) {
3810 return 0;
3811 }
3812
3813 src.address = route->u.msi.address_hi;
3814 src.address <<= VTD_MSI_ADDR_HI_SHIFT;
3815 src.address |= route->u.msi.address_lo;
3816 src.data = route->u.msi.data;
3817
3818 ret = class->int_remap(iommu, &src, &dst, dev ? \
3819 pci_requester_id(dev) : \
3820 X86_IOMMU_SID_INVALID);
3821 if (ret) {
3822 trace_kvm_x86_fixup_msi_error(route->gsi);
3823 return 1;
3824 }
3825
3826 route->u.msi.address_hi = dst.address >> VTD_MSI_ADDR_HI_SHIFT;
3827 route->u.msi.address_lo = dst.address & VTD_MSI_ADDR_LO_MASK;
3828 route->u.msi.data = dst.data;
3829 }
3830
3831 return 0;
3832 }
3833
3834 typedef struct MSIRouteEntry MSIRouteEntry;
3835
3836 struct MSIRouteEntry {
3837 PCIDevice *dev; /* Device pointer */
3838 int vector; /* MSI/MSIX vector index */
3839 int virq; /* Virtual IRQ index */
3840 QLIST_ENTRY(MSIRouteEntry) list;
3841 };
3842
3843 /* List of used GSI routes */
3844 static QLIST_HEAD(, MSIRouteEntry) msi_route_list = \
3845 QLIST_HEAD_INITIALIZER(msi_route_list);
3846
3847 static void kvm_update_msi_routes_all(void *private, bool global,
3848 uint32_t index, uint32_t mask)
3849 {
3850 int cnt = 0;
3851 MSIRouteEntry *entry;
3852 MSIMessage msg;
3853 PCIDevice *dev;
3854
3855 /* TODO: explicit route update */
3856 QLIST_FOREACH(entry, &msi_route_list, list) {
3857 cnt++;
3858 dev = entry->dev;
3859 if (!msix_enabled(dev) && !msi_enabled(dev)) {
3860 continue;
3861 }
3862 msg = pci_get_msi_message(dev, entry->vector);
3863 kvm_irqchip_update_msi_route(kvm_state, entry->virq, msg, dev);
3864 }
3865 kvm_irqchip_commit_routes(kvm_state);
3866 trace_kvm_x86_update_msi_routes(cnt);
3867 }
3868
3869 int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route,
3870 int vector, PCIDevice *dev)
3871 {
3872 static bool notify_list_inited = false;
3873 MSIRouteEntry *entry;
3874
3875 if (!dev) {
3876 /* These are (possibly) IOAPIC routes only used for split
3877 * kernel irqchip mode, while what we are housekeeping are
3878 * PCI devices only. */
3879 return 0;
3880 }
3881
3882 entry = g_new0(MSIRouteEntry, 1);
3883 entry->dev = dev;
3884 entry->vector = vector;
3885 entry->virq = route->gsi;
3886 QLIST_INSERT_HEAD(&msi_route_list, entry, list);
3887
3888 trace_kvm_x86_add_msi_route(route->gsi);
3889
3890 if (!notify_list_inited) {
3891 /* For the first time we do add route, add ourselves into
3892 * IOMMU's IEC notify list if needed. */
3893 X86IOMMUState *iommu = x86_iommu_get_default();
3894 if (iommu) {
3895 x86_iommu_iec_register_notifier(iommu,
3896 kvm_update_msi_routes_all,
3897 NULL);
3898 }
3899 notify_list_inited = true;
3900 }
3901 return 0;
3902 }
3903
3904 int kvm_arch_release_virq_post(int virq)
3905 {
3906 MSIRouteEntry *entry, *next;
3907 QLIST_FOREACH_SAFE(entry, &msi_route_list, list, next) {
3908 if (entry->virq == virq) {
3909 trace_kvm_x86_remove_msi_route(virq);
3910 QLIST_REMOVE(entry, list);
3911 g_free(entry);
3912 break;
3913 }
3914 }
3915 return 0;
3916 }
3917
3918 int kvm_arch_msi_data_to_gsi(uint32_t data)
3919 {
3920 abort();
3921 }
QEmu