linux-user/ppc/signal.c

   1 /*
   2  *  Emulation of Linux signals
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "qemu/osdep.h"
  20 #include "qemu.h"
  21 #include "user-internals.h"
  22 #include "signal-common.h"
  23 #include "linux-user/trace.h"
  24
  25 /* Size of dummy stack frame allocated when calling signal handler.
  26    See arch/powerpc/include/asm/ptrace.h.  */
  27 #if defined(TARGET_PPC64)
  28 #define SIGNAL_FRAMESIZE 128
  29 #else
  30 #define SIGNAL_FRAMESIZE 64
  31 #endif
  32
  33 /* See arch/powerpc/include/asm/ucontext.h.  Only used for 32-bit PPC;
  34    on 64-bit PPC, sigcontext and mcontext are one and the same.  */
  35 struct target_mcontext {
  36     target_ulong mc_gregs[48];
  37     /* Includes fpscr.  */
  38     uint64_t mc_fregs[33];
  39
  40 #if defined(TARGET_PPC64)
  41     /* Pointer to the vector regs */
  42     target_ulong v_regs;
  43     /*
  44      * On ppc64, this mcontext structure is naturally *unaligned*,
  45      * or rather it is aligned on a 8 bytes boundary but not on
  46      * a 16 byte boundary.  This pad fixes it up.  This is why we
  47      * cannot use ppc_avr_t, which would force alignment.  This is
  48      * also why the vector regs are referenced in the ABI by the
  49      * v_regs pointer above so any amount of padding can be added here.
  50      */
  51     target_ulong pad;
  52     /* VSCR and VRSAVE are saved separately.  Also reserve space for VSX. */
  53     struct {
  54         uint64_t altivec[34 + 16][2];
  55     } mc_vregs;
  56 #else
  57     target_ulong mc_pad[2];
  58
  59     /* We need to handle Altivec and SPE at the same time, which no
  60        kernel needs to do.  Fortunately, the kernel defines this bit to
  61        be Altivec-register-large all the time, rather than trying to
  62        twiddle it based on the specific platform.  */
  63     union {
  64         /* SPE vector registers.  One extra for SPEFSCR.  */
  65         uint32_t spe[33];
  66         /*
  67          * Altivec vector registers.  One extra for VRSAVE.
  68          * On ppc32, we are already aligned to 16 bytes.  We could
  69          * use ppc_avr_t, but choose to share the same type as ppc64.
  70          */
  71         uint64_t altivec[33][2];
  72     } mc_vregs;
  73 #endif
  74 };
  75
  76 /* See arch/powerpc/include/asm/sigcontext.h.  */
  77 struct target_sigcontext {
  78     target_ulong _unused[4];
  79     int32_t signal;
  80 #if defined(TARGET_PPC64)
  81     int32_t pad0;
  82 #endif
  83     target_ulong handler;
  84     target_ulong oldmask;
  85     target_ulong regs;      /* struct pt_regs __user * */
  86 #if defined(TARGET_PPC64)
  87     struct target_mcontext mcontext;
  88 #endif
  89 };
  90
  91 /* Indices for target_mcontext.mc_gregs, below.
  92    See arch/powerpc/include/asm/ptrace.h for details.  */
  93 enum {
  94     TARGET_PT_R0 = 0,
  95     TARGET_PT_R1 = 1,
  96     TARGET_PT_R2 = 2,
  97     TARGET_PT_R3 = 3,
  98     TARGET_PT_R4 = 4,
  99     TARGET_PT_R5 = 5,
 100     TARGET_PT_R6 = 6,
 101     TARGET_PT_R7 = 7,
 102     TARGET_PT_R8 = 8,
 103     TARGET_PT_R9 = 9,
 104     TARGET_PT_R10 = 10,
 105     TARGET_PT_R11 = 11,
 106     TARGET_PT_R12 = 12,
 107     TARGET_PT_R13 = 13,
 108     TARGET_PT_R14 = 14,
 109     TARGET_PT_R15 = 15,
 110     TARGET_PT_R16 = 16,
 111     TARGET_PT_R17 = 17,
 112     TARGET_PT_R18 = 18,
 113     TARGET_PT_R19 = 19,
 114     TARGET_PT_R20 = 20,
 115     TARGET_PT_R21 = 21,
 116     TARGET_PT_R22 = 22,
 117     TARGET_PT_R23 = 23,
 118     TARGET_PT_R24 = 24,
 119     TARGET_PT_R25 = 25,
 120     TARGET_PT_R26 = 26,
 121     TARGET_PT_R27 = 27,
 122     TARGET_PT_R28 = 28,
 123     TARGET_PT_R29 = 29,
 124     TARGET_PT_R30 = 30,
 125     TARGET_PT_R31 = 31,
 126     TARGET_PT_NIP = 32,
 127     TARGET_PT_MSR = 33,
 128     TARGET_PT_ORIG_R3 = 34,
 129     TARGET_PT_CTR = 35,
 130     TARGET_PT_LNK = 36,
 131     TARGET_PT_XER = 37,
 132     TARGET_PT_CCR = 38,
 133     /* Yes, there are two registers with #39.  One is 64-bit only.  */
 134     TARGET_PT_MQ = 39,
 135     TARGET_PT_SOFTE = 39,
 136     TARGET_PT_TRAP = 40,
 137     TARGET_PT_DAR = 41,
 138     TARGET_PT_DSISR = 42,
 139     TARGET_PT_RESULT = 43,
 140     TARGET_PT_REGS_COUNT = 44
 141 };
 142
 143
 144 struct target_ucontext {
 145     target_ulong tuc_flags;
 146     target_ulong tuc_link;    /* ucontext_t __user * */
 147     struct target_sigaltstack tuc_stack;
 148 #if !defined(TARGET_PPC64)
 149     int32_t tuc_pad[7];
 150     target_ulong tuc_regs;    /* struct mcontext __user *
 151                                 points to uc_mcontext field */
 152 #endif
 153     target_sigset_t tuc_sigmask;
 154 #if defined(TARGET_PPC64)
 155     target_sigset_t unused[15]; /* Allow for uc_sigmask growth */
 156     struct target_sigcontext tuc_sigcontext;
 157 #else
 158     int32_t tuc_maskext[30];
 159     int32_t tuc_pad2[3];
 160     struct target_mcontext tuc_mcontext;
 161 #endif
 162 };
 163
 164 /* See arch/powerpc/kernel/signal_32.c.  */
 165 struct target_sigframe {
 166     struct target_sigcontext sctx;
 167     struct target_mcontext mctx;
 168     int32_t abigap[56];
 169 };
 170
 171 #if defined(TARGET_PPC64)
 172
 173 #define TARGET_TRAMP_SIZE 6
 174
 175 struct target_rt_sigframe {
 176     /* sys_rt_sigreturn requires the ucontext be the first field */
 177     struct target_ucontext uc;
 178     target_ulong  _unused[2];
 179     uint32_t trampoline[TARGET_TRAMP_SIZE];
 180     target_ulong pinfo; /* struct siginfo __user * */
 181     target_ulong puc; /* void __user * */
 182     struct target_siginfo info;
 183     /* 64 bit ABI allows for 288 bytes below sp before decrementing it. */
 184     char abigap[288];
 185 } __attribute__((aligned(16)));
 186
 187 #else
 188
 189 struct target_rt_sigframe {
 190     struct target_siginfo info;
 191     struct target_ucontext uc;
 192     int32_t abigap[56];
 193 };
 194
 195 #endif
 196
 197 #if defined(TARGET_PPC64)
 198
 199 struct target_func_ptr {
 200     target_ulong entry;
 201     target_ulong toc;
 202 };
 203
 204 #endif
 205
 206 /* See arch/powerpc/kernel/signal.c.  */
 207 static target_ulong get_sigframe(struct target_sigaction *ka,
 208                                  CPUPPCState *env,
 209                                  int frame_size)
 210 {
 211     target_ulong oldsp;
 212
 213     oldsp = target_sigsp(get_sp_from_cpustate(env), ka);
 214
 215     return (oldsp - frame_size) & ~0xFUL;
 216 }
 217
 218 #if TARGET_BIG_ENDIAN == HOST_BIG_ENDIAN
 219 #define PPC_VEC_HI      0
 220 #define PPC_VEC_LO      1
 221 #else
 222 #define PPC_VEC_HI      1
 223 #define PPC_VEC_LO      0
 224 #endif
 225
 226
 227 static void save_user_regs(CPUPPCState *env, struct target_mcontext *frame)
 228 {
 229     target_ulong msr = env->msr;
 230     int i;
 231     uint32_t ccr = 0;
 232
 233     /* In general, the kernel attempts to be intelligent about what it
 234        needs to save for Altivec/FP/SPE registers.  We don't care that
 235        much, so we just go ahead and save everything.  */
 236
 237     /* Save general registers.  */
 238     for (i = 0; i < ARRAY_SIZE(env->gpr); i++) {
 239         __put_user(env->gpr[i], &frame->mc_gregs[i]);
 240     }
 241     __put_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]);
 242     __put_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]);
 243     __put_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]);
 244     __put_user(cpu_read_xer(env), &frame->mc_gregs[TARGET_PT_XER]);
 245
 246     for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
 247         ccr |= env->crf[i] << (32 - ((i + 1) * 4));
 248     }
 249     __put_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
 250
 251     /* Save Altivec registers if necessary.  */
 252     if (env->insns_flags & PPC_ALTIVEC) {
 253         uint32_t *vrsave;
 254         for (i = 0; i < 32; i++) {
 255             ppc_avr_t *avr = cpu_avr_ptr(env, i);
 256             ppc_avr_t *vreg = (ppc_avr_t *)&frame->mc_vregs.altivec[i];
 257
 258             __put_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]);
 259             __put_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]);
 260         }
 261 #if defined(TARGET_PPC64)
 262         vrsave = (uint32_t *)&frame->mc_vregs.altivec[33];
 263         /* 64-bit needs to put a pointer to the vectors in the frame */
 264         __put_user(h2g(frame->mc_vregs.altivec), &frame->v_regs);
 265 #else
 266         vrsave = (uint32_t *)&frame->mc_vregs.altivec[32];
 267 #endif
 268         __put_user((uint32_t)env->spr[SPR_VRSAVE], vrsave);
 269     }
 270
 271 #if defined(TARGET_PPC64)
 272     /* Save VSX second halves */
 273     if (env->insns_flags2 & PPC2_VSX) {
 274         uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34];
 275         for (i = 0; i < 32; i++) {
 276             uint64_t *vsrl = cpu_vsrl_ptr(env, i);
 277             __put_user(*vsrl, &vsregs[i]);
 278         }
 279     }
 280 #endif
 281
 282     /* Save floating point registers.  */
 283     if (env->insns_flags & PPC_FLOAT) {
 284         for (i = 0; i < 32; i++) {
 285             uint64_t *fpr = cpu_fpr_ptr(env, i);
 286             __put_user(*fpr, &frame->mc_fregs[i]);
 287         }
 288         __put_user((uint64_t) env->fpscr, &frame->mc_fregs[32]);
 289     }
 290
 291 #if !defined(TARGET_PPC64)
 292     /* Save SPE registers.  The kernel only saves the high half.  */
 293     if (env->insns_flags & PPC_SPE) {
 294         for (i = 0; i < ARRAY_SIZE(env->gprh); i++) {
 295             __put_user(env->gprh[i], &frame->mc_vregs.spe[i]);
 296         }
 297         __put_user(env->spe_fscr, &frame->mc_vregs.spe[32]);
 298     }
 299 #endif
 300
 301     /* Store MSR.  */
 302     __put_user(msr, &frame->mc_gregs[TARGET_PT_MSR]);
 303 }
 304
 305 static void encode_trampoline(int sigret, uint32_t *tramp)
 306 {
 307     /* Set up the sigreturn trampoline: li r0,sigret; sc.  */
 308     __put_user(0x38000000 | sigret, &tramp[0]);
 309     __put_user(0x44000002, &tramp[1]);
 310 }
 311
 312 static void restore_user_regs(CPUPPCState *env,
 313                               struct target_mcontext *frame, int sig)
 314 {
 315     target_ulong save_r2 = 0;
 316     target_ulong msr;
 317     target_ulong xer;
 318     target_ulong ccr;
 319
 320     int i;
 321
 322     if (!sig) {
 323         save_r2 = env->gpr[2];
 324     }
 325
 326     /* Restore general registers.  */
 327     for (i = 0; i < ARRAY_SIZE(env->gpr); i++) {
 328         __get_user(env->gpr[i], &frame->mc_gregs[i]);
 329     }
 330     __get_user(env->nip, &frame->mc_gregs[TARGET_PT_NIP]);
 331     __get_user(env->ctr, &frame->mc_gregs[TARGET_PT_CTR]);
 332     __get_user(env->lr, &frame->mc_gregs[TARGET_PT_LNK]);
 333
 334     __get_user(xer, &frame->mc_gregs[TARGET_PT_XER]);
 335     cpu_write_xer(env, xer);
 336
 337     __get_user(ccr, &frame->mc_gregs[TARGET_PT_CCR]);
 338     for (i = 0; i < ARRAY_SIZE(env->crf); i++) {
 339         env->crf[i] = (ccr >> (32 - ((i + 1) * 4))) & 0xf;
 340     }
 341
 342     if (!sig) {
 343         env->gpr[2] = save_r2;
 344     }
 345     /* Restore MSR.  */
 346     __get_user(msr, &frame->mc_gregs[TARGET_PT_MSR]);
 347
 348     /* If doing signal return, restore the previous little-endian mode.  */
 349     if (sig) {
 350         ppc_store_msr(env, ((env->msr & ~(1ull << MSR_LE)) |
 351                             (msr & (1ull << MSR_LE))));
 352     }
 353
 354     /* Restore Altivec registers if necessary.  */
 355     if (env->insns_flags & PPC_ALTIVEC) {
 356         ppc_avr_t *v_regs;
 357         uint32_t *vrsave;
 358 #if defined(TARGET_PPC64)
 359         uint64_t v_addr;
 360         /* 64-bit needs to recover the pointer to the vectors from the frame */
 361         __get_user(v_addr, &frame->v_regs);
 362         v_regs = g2h(env_cpu(env), v_addr);
 363 #else
 364         v_regs = (ppc_avr_t *)frame->mc_vregs.altivec;
 365 #endif
 366         for (i = 0; i < 32; i++) {
 367             ppc_avr_t *avr = cpu_avr_ptr(env, i);
 368             ppc_avr_t *vreg = &v_regs[i];
 369
 370             __get_user(avr->u64[PPC_VEC_HI], &vreg->u64[0]);
 371             __get_user(avr->u64[PPC_VEC_LO], &vreg->u64[1]);
 372         }
 373 #if defined(TARGET_PPC64)
 374         vrsave = (uint32_t *)&v_regs[33];
 375 #else
 376         vrsave = (uint32_t *)&v_regs[32];
 377 #endif
 378         __get_user(env->spr[SPR_VRSAVE], vrsave);
 379     }
 380
 381 #if defined(TARGET_PPC64)
 382     /* Restore VSX second halves */
 383     if (env->insns_flags2 & PPC2_VSX) {
 384         uint64_t *vsregs = (uint64_t *)&frame->mc_vregs.altivec[34];
 385         for (i = 0; i < 32; i++) {
 386             uint64_t *vsrl = cpu_vsrl_ptr(env, i);
 387             __get_user(*vsrl, &vsregs[i]);
 388         }
 389     }
 390 #endif
 391
 392     /* Restore floating point registers.  */
 393     if (env->insns_flags & PPC_FLOAT) {
 394         uint64_t fpscr;
 395         for (i = 0; i < 32; i++) {
 396             uint64_t *fpr = cpu_fpr_ptr(env, i);
 397             __get_user(*fpr, &frame->mc_fregs[i]);
 398         }
 399         __get_user(fpscr, &frame->mc_fregs[32]);
 400         env->fpscr = (uint32_t) fpscr;
 401     }
 402
 403 #if !defined(TARGET_PPC64)
 404     /* Save SPE registers.  The kernel only saves the high half.  */
 405     if (env->insns_flags & PPC_SPE) {
 406         for (i = 0; i < ARRAY_SIZE(env->gprh); i++) {
 407             __get_user(env->gprh[i], &frame->mc_vregs.spe[i]);
 408         }
 409         __get_user(env->spe_fscr, &frame->mc_vregs.spe[32]);
 410     }
 411 #endif
 412 }
 413
 414 #if !defined(TARGET_PPC64)
 415 void setup_frame(int sig, struct target_sigaction *ka,
 416                  target_sigset_t *set, CPUPPCState *env)
 417 {
 418     struct target_sigframe *frame;
 419     struct target_sigcontext *sc;
 420     target_ulong frame_addr, newsp;
 421     int err = 0;
 422
 423     frame_addr = get_sigframe(ka, env, sizeof(*frame));
 424     trace_user_setup_frame(env, frame_addr);
 425     if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 1))
 426         goto sigsegv;
 427     sc = &frame->sctx;
 428
 429     __put_user(ka->_sa_handler, &sc->handler);
 430     __put_user(set->sig[0], &sc->oldmask);
 431     __put_user(set->sig[1], &sc->_unused[3]);
 432     __put_user(h2g(&frame->mctx), &sc->regs);
 433     __put_user(sig, &sc->signal);
 434
 435     /* Save user regs.  */
 436     save_user_regs(env, &frame->mctx);
 437
 438     env->lr = default_sigreturn;
 439
 440     /* Turn off all fp exceptions.  */
 441     env->fpscr = 0;
 442
 443     /* Create a stack frame for the caller of the handler.  */
 444     newsp = frame_addr - SIGNAL_FRAMESIZE;
 445     err |= put_user(env->gpr[1], newsp, target_ulong);
 446
 447     if (err)
 448         goto sigsegv;
 449
 450     /* Set up registers for signal handler.  */
 451     env->gpr[1] = newsp;
 452     env->gpr[3] = sig;
 453     env->gpr[4] = frame_addr + offsetof(struct target_sigframe, sctx);
 454
 455     env->nip = (target_ulong) ka->_sa_handler;
 456
 457     /* Signal handlers are entered in big-endian mode.  */
 458     ppc_store_msr(env, env->msr & ~(1ull << MSR_LE));
 459
 460     unlock_user_struct(frame, frame_addr, 1);
 461     return;
 462
 463 sigsegv:
 464     unlock_user_struct(frame, frame_addr, 1);
 465     force_sigsegv(sig);
 466 }
 467 #endif /* !defined(TARGET_PPC64) */
 468
 469 void setup_rt_frame(int sig, struct target_sigaction *ka,
 470                     target_siginfo_t *info,
 471                     target_sigset_t *set, CPUPPCState *env)
 472 {
 473     struct target_rt_sigframe *rt_sf;
 474     struct target_mcontext *mctx = 0;
 475     target_ulong rt_sf_addr, newsp = 0;
 476     int i, err = 0;
 477 #if defined(TARGET_PPC64)
 478     struct target_sigcontext *sc = 0;
 479     struct image_info *image = ((TaskState *)thread_cpu->opaque)->info;
 480 #endif
 481
 482     rt_sf_addr = get_sigframe(ka, env, sizeof(*rt_sf));
 483     if (!lock_user_struct(VERIFY_WRITE, rt_sf, rt_sf_addr, 1))
 484         goto sigsegv;
 485
 486     tswap_siginfo(&rt_sf->info, info);
 487
 488     __put_user(0, &rt_sf->uc.tuc_flags);
 489     __put_user(0, &rt_sf->uc.tuc_link);
 490     target_save_altstack(&rt_sf->uc.tuc_stack, env);
 491 #if !defined(TARGET_PPC64)
 492     __put_user(h2g (&rt_sf->uc.tuc_mcontext),
 493                &rt_sf->uc.tuc_regs);
 494 #endif
 495     for(i = 0; i < TARGET_NSIG_WORDS; i++) {
 496         __put_user(set->sig[i], &rt_sf->uc.tuc_sigmask.sig[i]);
 497     }
 498
 499 #if defined(TARGET_PPC64)
 500     mctx = &rt_sf->uc.tuc_sigcontext.mcontext;
 501
 502     sc = &rt_sf->uc.tuc_sigcontext;
 503     __put_user(h2g(mctx), &sc->regs);
 504     __put_user(sig, &sc->signal);
 505 #else
 506     mctx = &rt_sf->uc.tuc_mcontext;
 507 #endif
 508
 509     save_user_regs(env, mctx);
 510
 511     env->lr = default_rt_sigreturn;
 512
 513     /* Turn off all fp exceptions.  */
 514     env->fpscr = 0;
 515
 516     /* Create a stack frame for the caller of the handler.  */
 517     newsp = rt_sf_addr - (SIGNAL_FRAMESIZE + 16);
 518     err |= put_user(env->gpr[1], newsp, target_ulong);
 519
 520     if (err)
 521         goto sigsegv;
 522
 523     /* Set up registers for signal handler.  */
 524     env->gpr[1] = newsp;
 525     env->gpr[3] = (target_ulong) sig;
 526     env->gpr[4] = (target_ulong) h2g(&rt_sf->info);
 527     env->gpr[5] = (target_ulong) h2g(&rt_sf->uc);
 528     env->gpr[6] = (target_ulong) h2g(rt_sf);
 529
 530 #if defined(TARGET_PPC64)
 531     if (get_ppc64_abi(image) < 2) {
 532         /* ELFv1 PPC64 function pointers are pointers to OPD entries. */
 533         struct target_func_ptr *handler =
 534             (struct target_func_ptr *)g2h(env_cpu(env), ka->_sa_handler);
 535         env->nip = tswapl(handler->entry);
 536         env->gpr[2] = tswapl(handler->toc);
 537     } else {
 538         /* ELFv2 PPC64 function pointers are entry points. R12 must also be set. */
 539         env->gpr[12] = env->nip = ka->_sa_handler;
 540     }
 541 #else
 542     env->nip = (target_ulong) ka->_sa_handler;
 543 #endif
 544
 545 #if TARGET_BIG_ENDIAN
 546     /* Signal handlers are entered in big-endian mode.  */
 547     ppc_store_msr(env, env->msr & ~(1ull << MSR_LE));
 548 #else
 549     /* Signal handlers are entered in little-endian mode.  */
 550     ppc_store_msr(env, env->msr | (1ull << MSR_LE));
 551 #endif
 552
 553     unlock_user_struct(rt_sf, rt_sf_addr, 1);
 554     return;
 555
 556 sigsegv:
 557     unlock_user_struct(rt_sf, rt_sf_addr, 1);
 558     force_sigsegv(sig);
 559
 560 }
 561
 562 #if !defined(TARGET_PPC64)
 563 long do_sigreturn(CPUPPCState *env)
 564 {
 565     struct target_sigcontext *sc = NULL;
 566     struct target_mcontext *sr = NULL;
 567     target_ulong sr_addr = 0, sc_addr;
 568     sigset_t blocked;
 569     target_sigset_t set;
 570
 571     sc_addr = env->gpr[1] + SIGNAL_FRAMESIZE;
 572     if (!lock_user_struct(VERIFY_READ, sc, sc_addr, 1))
 573         goto sigsegv;
 574
 575     __get_user(set.sig[0], &sc->oldmask);
 576     __get_user(set.sig[1], &sc->_unused[3]);
 577
 578     target_to_host_sigset_internal(&blocked, &set);
 579     set_sigmask(&blocked);
 580
 581     __get_user(sr_addr, &sc->regs);
 582     if (!lock_user_struct(VERIFY_READ, sr, sr_addr, 1))
 583         goto sigsegv;
 584     restore_user_regs(env, sr, 1);
 585
 586     unlock_user_struct(sr, sr_addr, 1);
 587     unlock_user_struct(sc, sc_addr, 1);
 588     return -QEMU_ESIGRETURN;
 589
 590 sigsegv:
 591     unlock_user_struct(sr, sr_addr, 1);
 592     unlock_user_struct(sc, sc_addr, 1);
 593     force_sig(TARGET_SIGSEGV);
 594     return -QEMU_ESIGRETURN;
 595 }
 596 #endif /* !defined(TARGET_PPC64) */
 597
 598 /* See arch/powerpc/kernel/signal_32.c.  */
 599 static int do_setcontext(struct target_ucontext *ucp, CPUPPCState *env, int sig)
 600 {
 601     struct target_mcontext *mcp;
 602     target_ulong mcp_addr;
 603     sigset_t blocked;
 604     target_sigset_t set;
 605
 606     if (copy_from_user(&set, h2g(ucp) + offsetof(struct target_ucontext, tuc_sigmask),
 607                        sizeof (set)))
 608         return 1;
 609
 610 #if defined(TARGET_PPC64)
 611     mcp_addr = h2g(ucp) +
 612         offsetof(struct target_ucontext, tuc_sigcontext.mcontext);
 613 #else
 614     __get_user(mcp_addr, &ucp->tuc_regs);
 615 #endif
 616
 617     if (!lock_user_struct(VERIFY_READ, mcp, mcp_addr, 1))
 618         return 1;
 619
 620     target_to_host_sigset_internal(&blocked, &set);
 621     set_sigmask(&blocked);
 622     restore_user_regs(env, mcp, sig);
 623
 624     unlock_user_struct(mcp, mcp_addr, 1);
 625     return 0;
 626 }
 627
 628 long do_rt_sigreturn(CPUPPCState *env)
 629 {
 630     struct target_rt_sigframe *rt_sf = NULL;
 631     target_ulong rt_sf_addr;
 632
 633     rt_sf_addr = env->gpr[1] + SIGNAL_FRAMESIZE + 16;
 634     if (!lock_user_struct(VERIFY_READ, rt_sf, rt_sf_addr, 1))
 635         goto sigsegv;
 636
 637     if (do_setcontext(&rt_sf->uc, env, 1))
 638         goto sigsegv;
 639
 640     target_restore_altstack(&rt_sf->uc.tuc_stack, env);
 641
 642     unlock_user_struct(rt_sf, rt_sf_addr, 1);
 643     return -QEMU_ESIGRETURN;
 644
 645 sigsegv:
 646     unlock_user_struct(rt_sf, rt_sf_addr, 1);
 647     force_sig(TARGET_SIGSEGV);
 648     return -QEMU_ESIGRETURN;
 649 }
 650
 651 /* This syscall implements {get,set,swap}context for userland.  */
 652 abi_long do_swapcontext(CPUArchState *env, abi_ulong uold_ctx,
 653                         abi_ulong unew_ctx, abi_long ctx_size)
 654 {
 655     struct target_ucontext *uctx;
 656     struct target_mcontext *mctx;
 657
 658     /* For ppc32, ctx_size is "reserved for future use".
 659      * For ppc64, we do not yet support the VSX extension.
 660      */
 661     if (ctx_size < sizeof(struct target_ucontext)) {
 662         return -TARGET_EINVAL;
 663     }
 664
 665     if (uold_ctx) {
 666         TaskState *ts = (TaskState *)thread_cpu->opaque;
 667
 668         if (!lock_user_struct(VERIFY_WRITE, uctx, uold_ctx, 1)) {
 669             return -TARGET_EFAULT;
 670         }
 671
 672 #ifdef TARGET_PPC64
 673         mctx = &uctx->tuc_sigcontext.mcontext;
 674 #else
 675         /* ??? The kernel aligns the pointer down here into padding, but
 676          * in setup_rt_frame we don't.  Be self-compatible for now.
 677          */
 678         mctx = &uctx->tuc_mcontext;
 679         __put_user(h2g(mctx), &uctx->tuc_regs);
 680 #endif
 681
 682         save_user_regs(env, mctx);
 683         host_to_target_sigset(&uctx->tuc_sigmask, &ts->signal_mask);
 684
 685         unlock_user_struct(uctx, uold_ctx, 1);
 686     }
 687
 688     if (unew_ctx) {
 689         int err;
 690
 691         if (!lock_user_struct(VERIFY_READ, uctx, unew_ctx, 1)) {
 692             return -TARGET_EFAULT;
 693         }
 694         err = do_setcontext(uctx, env, 0);
 695         unlock_user_struct(uctx, unew_ctx, 1);
 696
 697         if (err) {
 698             /* We cannot return to a partially updated context.  */
 699             force_sig(TARGET_SIGSEGV);
 700         }
 701         return -QEMU_ESIGRETURN;
 702     }
 703
 704     return 0;
 705 }
 706
 707 void setup_sigtramp(abi_ulong sigtramp_page)
 708 {
 709     uint32_t *tramp = lock_user(VERIFY_WRITE, sigtramp_page, 2 * 8, 0);
 710     assert(tramp != NULL);
 711
 712 #ifdef TARGET_ARCH_HAS_SETUP_FRAME
 713     default_sigreturn = sigtramp_page;
 714     encode_trampoline(TARGET_NR_sigreturn, tramp + 0);
 715 #endif
 716
 717     default_rt_sigreturn = sigtramp_page + 8;
 718     encode_trampoline(TARGET_NR_rt_sigreturn, tramp + 2);
 719
 720     unlock_user(tramp, sigtramp_page, 2 * 8);
 721 }