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ppc/pnv: enable user created pnv-phb for powernv9
[qemu.git] / hw / ppc / pnv.c
blobf45f02be4c2d3af02108899629952639bd807892
1 /*
2 * QEMU PowerPC PowerNV machine model
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/datadir.h"
22 #include "qemu/units.h"
23 #include "qemu/cutils.h"
24 #include "qapi/error.h"
25 #include "sysemu/qtest.h"
26 #include "sysemu/sysemu.h"
27 #include "sysemu/numa.h"
28 #include "sysemu/reset.h"
29 #include "sysemu/runstate.h"
30 #include "sysemu/cpus.h"
31 #include "sysemu/device_tree.h"
32 #include "sysemu/hw_accel.h"
33 #include "target/ppc/cpu.h"
34 #include "hw/ppc/fdt.h"
35 #include "hw/ppc/ppc.h"
36 #include "hw/ppc/pnv.h"
37 #include "hw/ppc/pnv_core.h"
38 #include "hw/loader.h"
39 #include "hw/nmi.h"
40 #include "qapi/visitor.h"
41 #include "monitor/monitor.h"
42 #include "hw/intc/intc.h"
43 #include "hw/ipmi/ipmi.h"
44 #include "target/ppc/mmu-hash64.h"
45 #include "hw/pci/msi.h"
46 #include "hw/pci-host/pnv_phb.h"
47
48 #include "hw/ppc/xics.h"
49 #include "hw/qdev-properties.h"
50 #include "hw/ppc/pnv_xscom.h"
51 #include "hw/ppc/pnv_pnor.h"
52
53 #include "hw/isa/isa.h"
54 #include "hw/char/serial.h"
55 #include "hw/rtc/mc146818rtc.h"
56
57 #include <libfdt.h>
58
59 #define FDT_MAX_SIZE (1 * MiB)
60
61 #define FW_FILE_NAME "skiboot.lid"
62 #define FW_LOAD_ADDR 0x0
63 #define FW_MAX_SIZE (16 * MiB)
64
65 #define KERNEL_LOAD_ADDR 0x20000000
66 #define KERNEL_MAX_SIZE (128 * MiB)
67 #define INITRD_LOAD_ADDR 0x28000000
68 #define INITRD_MAX_SIZE (128 * MiB)
69
70 static const char *pnv_chip_core_typename(const PnvChip *o)
71 {
72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o)));
73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX);
74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type);
75 const char *core_type = object_class_get_name(object_class_by_name(s));
76 g_free(s);
77 return core_type;
78 }
79
80 /*
81 * On Power Systems E880 (POWER8), the max cpus (threads) should be :
82 * 4 * 4 sockets * 12 cores * 8 threads = 1536
83 * Let's make it 2^11
84 */
85 #define MAX_CPUS 2048
86
87 /*
88 * Memory nodes are created by hostboot, one for each range of memory
89 * that has a different "affinity". In practice, it means one range
90 * per chip.
91 */
92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size)
93 {
94 char *mem_name;
95 uint64_t mem_reg_property[2];
96 int off;
97
98 mem_reg_property[0] = cpu_to_be64(start);
99 mem_reg_property[1] = cpu_to_be64(size);
100
101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start);
102 off = fdt_add_subnode(fdt, 0, mem_name);
103 g_free(mem_name);
104
105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory")));
106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property,
107 sizeof(mem_reg_property))));
108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id)));
109 }
110
111 static int get_cpus_node(void *fdt)
112 {
113 int cpus_offset = fdt_path_offset(fdt, "/cpus");
114
115 if (cpus_offset < 0) {
116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus");
117 if (cpus_offset) {
118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1)));
119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0)));
120 }
121 }
122 _FDT(cpus_offset);
123 return cpus_offset;
124 }
125
126 /*
127 * The PowerNV cores (and threads) need to use real HW ids and not an
128 * incremental index like it has been done on other platforms. This HW
129 * id is stored in the CPU PIR, it is used to create cpu nodes in the
130 * device tree, used in XSCOM to address cores and in interrupt
131 * servers.
132 */
133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt)
134 {
135 PowerPCCPU *cpu = pc->threads[0];
136 CPUState *cs = CPU(cpu);
137 DeviceClass *dc = DEVICE_GET_CLASS(cs);
138 int smt_threads = CPU_CORE(pc)->nr_threads;
139 CPUPPCState *env = &cpu->env;
140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs);
141 uint32_t servers_prop[smt_threads];
142 int i;
143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
144 0xffffffff, 0xffffffff};
145 uint32_t tbfreq = PNV_TIMEBASE_FREQ;
146 uint32_t cpufreq = 1000000000;
147 uint32_t page_sizes_prop[64];
148 size_t page_sizes_prop_size;
149 const uint8_t pa_features[] = { 24, 0,
150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0,
151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 };
154 int offset;
155 char *nodename;
156 int cpus_offset = get_cpus_node(fdt);
157
158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir);
159 offset = fdt_add_subnode(fdt, cpus_offset, nodename);
160 _FDT(offset);
161 g_free(nodename);
162
163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id)));
164
165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir)));
166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir)));
167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu")));
168
169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR])));
170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size",
171 env->dcache_line_size)));
172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size",
173 env->dcache_line_size)));
174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size",
175 env->icache_line_size)));
176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size",
177 env->icache_line_size)));
178
179 if (pcc->l1_dcache_size) {
180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size",
181 pcc->l1_dcache_size)));
182 } else {
183 warn_report("Unknown L1 dcache size for cpu");
184 }
185 if (pcc->l1_icache_size) {
186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size",
187 pcc->l1_icache_size)));
188 } else {
189 warn_report("Unknown L1 icache size for cpu");
190 }
191
192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq)));
193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq)));
194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size",
195 cpu->hash64_opts->slb_size)));
196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay")));
197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0)));
198
199 if (ppc_has_spr(cpu, SPR_PURR)) {
200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0)));
201 }
202
203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) {
204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes",
205 segs, sizeof(segs))));
206 }
207
208 /*
209 * Advertise VMX/VSX (vector extensions) if available
210 * 0 / no property == no vector extensions
211 * 1 == VMX / Altivec available
212 * 2 == VSX available
213 */
214 if (env->insns_flags & PPC_ALTIVEC) {
215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1;
216
217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx)));
218 }
219
220 /*
221 * Advertise DFP (Decimal Floating Point) if available
222 * 0 / no property == no DFP
223 * 1 == DFP available
224 */
225 if (env->insns_flags2 & PPC2_DFP) {
226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1)));
227 }
228
229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop,
230 sizeof(page_sizes_prop));
231 if (page_sizes_prop_size) {
232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes",
233 page_sizes_prop, page_sizes_prop_size)));
234 }
235
236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features",
237 pa_features, sizeof(pa_features))));
238
239 /* Build interrupt servers properties */
240 for (i = 0; i < smt_threads; i++) {
241 servers_prop[i] = cpu_to_be32(pc->pir + i);
242 }
243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s",
244 servers_prop, sizeof(servers_prop))));
245 }
246
247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir,
248 uint32_t nr_threads)
249 {
250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12);
251 char *name;
252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
253 uint32_t irange[2], i, rsize;
254 uint64_t *reg;
255 int offset;
256
257 irange[0] = cpu_to_be32(pir);
258 irange[1] = cpu_to_be32(nr_threads);
259
260 rsize = sizeof(uint64_t) * 2 * nr_threads;
261 reg = g_malloc(rsize);
262 for (i = 0; i < nr_threads; i++) {
263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000));
264 reg[i * 2 + 1] = cpu_to_be64(0x1000);
265 }
266
267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
268 offset = fdt_add_subnode(fdt, 0, name);
269 _FDT(offset);
270 g_free(name);
271
272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat))));
273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize)));
274 _FDT((fdt_setprop_string(fdt, offset, "device_type",
275 "PowerPC-External-Interrupt-Presentation")));
276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0)));
277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges",
278 irange, sizeof(irange))));
279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1)));
280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0)));
281 g_free(reg);
282 }
283
284 static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb,
285 Error **errp)
286 {
287 Pnv9Chip *chip9 = PNV9_CHIP(chip);
288 int chip_id = phb->chip_id;
289 int index = phb->phb_id;
290 int i, j;
291
292 for (i = 0; i < chip->num_pecs; i++) {
293 /*
294 * For each PEC, check the amount of phbs it supports
295 * and see if the given phb4 index matches an index.
296 */
297 PnvPhb4PecState *pec = &chip9->pecs[i];
298
299 for (j = 0; j < pec->num_phbs; j++) {
300 if (index == pnv_phb4_pec_get_phb_id(pec, j)) {
301 return pec;
302 }
303 }
304 }
305 error_setg(errp,
306 "pnv-phb4 chip-id %d index %d didn't match any existing PEC",
307 chip_id, index);
308
309 return NULL;
310 }
311
312 /*
313 * Adds a PnvPHB to the chip. Returns the parent obj of the
314 * PHB which varies with each version (phb version 3 is parented
315 * by the chip, version 4 and 5 are parented by the PEC
316 * device).
317 *
318 * TODO: for version 3 we're still parenting the PHB with the
319 * chip. We should parent with a (so far not implemented)
320 * PHB3 PEC device.
321 */
322 Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp)
323 {
324 if (phb->version == 3) {
325 Pnv8Chip *chip8 = PNV8_CHIP(chip);
326
327 phb->chip = chip;
328
329 chip8->phbs[chip8->num_phbs] = phb;
330 chip8->num_phbs++;
331
332 return OBJECT(chip);
333 }
334
335 phb->pec = pnv_phb4_get_pec(chip, PNV_PHB4(phb->backend), errp);
336
337 return OBJECT(phb->pec);
338 }
339
340 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt)
341 {
342 static const char compat[] = "ibm,power8-xscom\0ibm,xscom";
343 int i;
344
345 pnv_dt_xscom(chip, fdt, 0,
346 cpu_to_be64(PNV_XSCOM_BASE(chip)),
347 cpu_to_be64(PNV_XSCOM_SIZE),
348 compat, sizeof(compat));
349
350 for (i = 0; i < chip->nr_cores; i++) {
351 PnvCore *pnv_core = chip->cores[i];
352
353 pnv_dt_core(chip, pnv_core, fdt);
354
355 /* Interrupt Control Presenters (ICP). One per core. */
356 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads);
357 }
358
359 if (chip->ram_size) {
360 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
361 }
362 }
363
364 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt)
365 {
366 static const char compat[] = "ibm,power9-xscom\0ibm,xscom";
367 int i;
368
369 pnv_dt_xscom(chip, fdt, 0,
370 cpu_to_be64(PNV9_XSCOM_BASE(chip)),
371 cpu_to_be64(PNV9_XSCOM_SIZE),
372 compat, sizeof(compat));
373
374 for (i = 0; i < chip->nr_cores; i++) {
375 PnvCore *pnv_core = chip->cores[i];
376
377 pnv_dt_core(chip, pnv_core, fdt);
378 }
379
380 if (chip->ram_size) {
381 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
382 }
383
384 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE);
385 }
386
387 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt)
388 {
389 static const char compat[] = "ibm,power10-xscom\0ibm,xscom";
390 int i;
391
392 pnv_dt_xscom(chip, fdt, 0,
393 cpu_to_be64(PNV10_XSCOM_BASE(chip)),
394 cpu_to_be64(PNV10_XSCOM_SIZE),
395 compat, sizeof(compat));
396
397 for (i = 0; i < chip->nr_cores; i++) {
398 PnvCore *pnv_core = chip->cores[i];
399
400 pnv_dt_core(chip, pnv_core, fdt);
401 }
402
403 if (chip->ram_size) {
404 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size);
405 }
406
407 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE);
408 }
409
410 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off)
411 {
412 uint32_t io_base = d->ioport_id;
413 uint32_t io_regs[] = {
414 cpu_to_be32(1),
415 cpu_to_be32(io_base),
416 cpu_to_be32(2)
417 };
418 char *name;
419 int node;
420
421 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
422 node = fdt_add_subnode(fdt, lpc_off, name);
423 _FDT(node);
424 g_free(name);
425
426 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
427 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00")));
428 }
429
430 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off)
431 {
432 const char compatible[] = "ns16550\0pnpPNP,501";
433 uint32_t io_base = d->ioport_id;
434 uint32_t io_regs[] = {
435 cpu_to_be32(1),
436 cpu_to_be32(io_base),
437 cpu_to_be32(8)
438 };
439 uint32_t irq;
440 char *name;
441 int node;
442
443 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal);
444
445 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
446 node = fdt_add_subnode(fdt, lpc_off, name);
447 _FDT(node);
448 g_free(name);
449
450 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
451 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
452 sizeof(compatible))));
453
454 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200)));
455 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200)));
456 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
457 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
458 fdt_get_phandle(fdt, lpc_off))));
459
460 /* This is needed by Linux */
461 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial")));
462 }
463
464 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off)
465 {
466 const char compatible[] = "bt\0ipmi-bt";
467 uint32_t io_base;
468 uint32_t io_regs[] = {
469 cpu_to_be32(1),
470 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */
471 cpu_to_be32(3)
472 };
473 uint32_t irq;
474 char *name;
475 int node;
476
477 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal);
478 io_regs[1] = cpu_to_be32(io_base);
479
480 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal);
481
482 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base);
483 node = fdt_add_subnode(fdt, lpc_off, name);
484 _FDT(node);
485 g_free(name);
486
487 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs))));
488 _FDT((fdt_setprop(fdt, node, "compatible", compatible,
489 sizeof(compatible))));
490
491 /* Mark it as reserved to avoid Linux trying to claim it */
492 _FDT((fdt_setprop_string(fdt, node, "status", "reserved")));
493 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq)));
494 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent",
495 fdt_get_phandle(fdt, lpc_off))));
496 }
497
498 typedef struct ForeachPopulateArgs {
499 void *fdt;
500 int offset;
501 } ForeachPopulateArgs;
502
503 static int pnv_dt_isa_device(DeviceState *dev, void *opaque)
504 {
505 ForeachPopulateArgs *args = opaque;
506 ISADevice *d = ISA_DEVICE(dev);
507
508 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) {
509 pnv_dt_rtc(d, args->fdt, args->offset);
510 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) {
511 pnv_dt_serial(d, args->fdt, args->offset);
512 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) {
513 pnv_dt_ipmi_bt(d, args->fdt, args->offset);
514 } else {
515 error_report("unknown isa device %s@i%x", qdev_fw_name(dev),
516 d->ioport_id);
517 }
518
519 return 0;
520 }
521
522 /*
523 * The default LPC bus of a multichip system is on chip 0. It's
524 * recognized by the firmware (skiboot) using a "primary" property.
525 */
526 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt)
527 {
528 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename);
529 ForeachPopulateArgs args = {
530 .fdt = fdt,
531 .offset = isa_offset,
532 };
533 uint32_t phandle;
534
535 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0)));
536
537 phandle = qemu_fdt_alloc_phandle(fdt);
538 assert(phandle > 0);
539 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle)));
540
541 /*
542 * ISA devices are not necessarily parented to the ISA bus so we
543 * can not use object_child_foreach()
544 */
545 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL,
546 &args);
547 }
548
549 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt)
550 {
551 int off;
552
553 off = fdt_add_subnode(fdt, 0, "ibm,opal");
554 off = fdt_add_subnode(fdt, off, "power-mgt");
555
556 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000));
557 }
558
559 static void *pnv_dt_create(MachineState *machine)
560 {
561 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine);
562 PnvMachineState *pnv = PNV_MACHINE(machine);
563 void *fdt;
564 char *buf;
565 int off;
566 int i;
567
568 fdt = g_malloc0(FDT_MAX_SIZE);
569 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE)));
570
571 /* /qemu node */
572 _FDT((fdt_add_subnode(fdt, 0, "qemu")));
573
574 /* Root node */
575 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2)));
576 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2)));
577 _FDT((fdt_setprop_string(fdt, 0, "model",
578 "IBM PowerNV (emulated by qemu)")));
579 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size)));
580
581 buf = qemu_uuid_unparse_strdup(&qemu_uuid);
582 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf)));
583 if (qemu_uuid_set) {
584 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf)));
585 }
586 g_free(buf);
587
588 off = fdt_add_subnode(fdt, 0, "chosen");
589 if (machine->kernel_cmdline) {
590 _FDT((fdt_setprop_string(fdt, off, "bootargs",
591 machine->kernel_cmdline)));
592 }
593
594 if (pnv->initrd_size) {
595 uint32_t start_prop = cpu_to_be32(pnv->initrd_base);
596 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size);
597
598 _FDT((fdt_setprop(fdt, off, "linux,initrd-start",
599 &start_prop, sizeof(start_prop))));
600 _FDT((fdt_setprop(fdt, off, "linux,initrd-end",
601 &end_prop, sizeof(end_prop))));
602 }
603
604 /* Populate device tree for each chip */
605 for (i = 0; i < pnv->num_chips; i++) {
606 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt);
607 }
608
609 /* Populate ISA devices on chip 0 */
610 pnv_dt_isa(pnv, fdt);
611
612 if (pnv->bmc) {
613 pnv_dt_bmc_sensors(pnv->bmc, fdt);
614 }
615
616 /* Create an extra node for power management on machines that support it */
617 if (pmc->dt_power_mgt) {
618 pmc->dt_power_mgt(pnv, fdt);
619 }
620
621 return fdt;
622 }
623
624 static void pnv_powerdown_notify(Notifier *n, void *opaque)
625 {
626 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier);
627
628 if (pnv->bmc) {
629 pnv_bmc_powerdown(pnv->bmc);
630 }
631 }
632
633 static void pnv_reset(MachineState *machine)
634 {
635 PnvMachineState *pnv = PNV_MACHINE(machine);
636 IPMIBmc *bmc;
637 void *fdt;
638
639 qemu_devices_reset();
640
641 /*
642 * The machine should provide by default an internal BMC simulator.
643 * If not, try to use the BMC device that was provided on the command
644 * line.
645 */
646 bmc = pnv_bmc_find(&error_fatal);
647 if (!pnv->bmc) {
648 if (!bmc) {
649 if (!qtest_enabled()) {
650 warn_report("machine has no BMC device. Use '-device "
651 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' "
652 "to define one");
653 }
654 } else {
655 pnv_bmc_set_pnor(bmc, pnv->pnor);
656 pnv->bmc = bmc;
657 }
658 }
659
660 fdt = pnv_dt_create(machine);
661
662 /* Pack resulting tree */
663 _FDT((fdt_pack(fdt)));
664
665 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt));
666 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt));
667
668 g_free(fdt);
669 }
670
671 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp)
672 {
673 Pnv8Chip *chip8 = PNV8_CHIP(chip);
674 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL);
675
676 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
677 return pnv_lpc_isa_create(&chip8->lpc, true, errp);
678 }
679
680 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp)
681 {
682 Pnv8Chip *chip8 = PNV8_CHIP(chip);
683 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C);
684
685 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq);
686 return pnv_lpc_isa_create(&chip8->lpc, false, errp);
687 }
688
689 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp)
690 {
691 Pnv9Chip *chip9 = PNV9_CHIP(chip);
692 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC);
693
694 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq);
695 return pnv_lpc_isa_create(&chip9->lpc, false, errp);
696 }
697
698 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp)
699 {
700 Pnv10Chip *chip10 = PNV10_CHIP(chip);
701 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC);
702
703 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq);
704 return pnv_lpc_isa_create(&chip10->lpc, false, errp);
705 }
706
707 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp)
708 {
709 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp);
710 }
711
712 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon)
713 {
714 Pnv8Chip *chip8 = PNV8_CHIP(chip);
715 int i;
716
717 ics_pic_print_info(&chip8->psi.ics, mon);
718
719 for (i = 0; i < chip8->num_phbs; i++) {
720 PnvPHB *phb = chip8->phbs[i];
721 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
722
723 pnv_phb3_msi_pic_print_info(&phb3->msis, mon);
724 ics_pic_print_info(&phb3->lsis, mon);
725 }
726 }
727
728 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque)
729 {
730 Monitor *mon = opaque;
731 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB);
732
733 if (!phb) {
734 return 0;
735 }
736
737 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon);
738
739 return 0;
740 }
741
742 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon)
743 {
744 Pnv9Chip *chip9 = PNV9_CHIP(chip);
745
746 pnv_xive_pic_print_info(&chip9->xive, mon);
747 pnv_psi_pic_print_info(&chip9->psi, mon);
748
749 object_child_foreach_recursive(OBJECT(chip),
750 pnv_chip_power9_pic_print_info_child, mon);
751 }
752
753 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip,
754 uint32_t core_id)
755 {
756 return PNV_XSCOM_EX_BASE(core_id);
757 }
758
759 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip,
760 uint32_t core_id)
761 {
762 return PNV9_XSCOM_EC_BASE(core_id);
763 }
764
765 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip,
766 uint32_t core_id)
767 {
768 return PNV10_XSCOM_EC_BASE(core_id);
769 }
770
771 static bool pnv_match_cpu(const char *default_type, const char *cpu_type)
772 {
773 PowerPCCPUClass *ppc_default =
774 POWERPC_CPU_CLASS(object_class_by_name(default_type));
775 PowerPCCPUClass *ppc =
776 POWERPC_CPU_CLASS(object_class_by_name(cpu_type));
777
778 return ppc_default->pvr_match(ppc_default, ppc->pvr, false);
779 }
780
781 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq)
782 {
783 ISADevice *dev = isa_new("isa-ipmi-bt");
784
785 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal);
786 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal);
787 isa_realize_and_unref(dev, bus, &error_fatal);
788 }
789
790 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon)
791 {
792 Pnv10Chip *chip10 = PNV10_CHIP(chip);
793
794 pnv_xive2_pic_print_info(&chip10->xive, mon);
795 pnv_psi_pic_print_info(&chip10->psi, mon);
796
797 object_child_foreach_recursive(OBJECT(chip),
798 pnv_chip_power9_pic_print_info_child, mon);
799 }
800
801 /* Always give the first 1GB to chip 0 else we won't boot */
802 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id)
803 {
804 MachineState *machine = MACHINE(pnv);
805 uint64_t ram_per_chip;
806
807 assert(machine->ram_size >= 1 * GiB);
808
809 ram_per_chip = machine->ram_size / pnv->num_chips;
810 if (ram_per_chip >= 1 * GiB) {
811 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
812 }
813
814 assert(pnv->num_chips > 1);
815
816 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1);
817 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB);
818 }
819
820 static void pnv_init(MachineState *machine)
821 {
822 const char *bios_name = machine->firmware ?: FW_FILE_NAME;
823 PnvMachineState *pnv = PNV_MACHINE(machine);
824 MachineClass *mc = MACHINE_GET_CLASS(machine);
825 char *fw_filename;
826 long fw_size;
827 uint64_t chip_ram_start = 0;
828 int i;
829 char *chip_typename;
830 DriveInfo *pnor = drive_get(IF_MTD, 0, 0);
831 DeviceState *dev;
832
833 if (kvm_enabled()) {
834 error_report("The powernv machine does not work with KVM acceleration");
835 exit(EXIT_FAILURE);
836 }
837
838 /* allocate RAM */
839 if (machine->ram_size < mc->default_ram_size) {
840 char *sz = size_to_str(mc->default_ram_size);
841 error_report("Invalid RAM size, should be bigger than %s", sz);
842 g_free(sz);
843 exit(EXIT_FAILURE);
844 }
845 memory_region_add_subregion(get_system_memory(), 0, machine->ram);
846
847 /*
848 * Create our simple PNOR device
849 */
850 dev = qdev_new(TYPE_PNV_PNOR);
851 if (pnor) {
852 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor));
853 }
854 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
855 pnv->pnor = PNV_PNOR(dev);
856
857 /* load skiboot firmware */
858 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
859 if (!fw_filename) {
860 error_report("Could not find OPAL firmware '%s'", bios_name);
861 exit(1);
862 }
863
864 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE);
865 if (fw_size < 0) {
866 error_report("Could not load OPAL firmware '%s'", fw_filename);
867 exit(1);
868 }
869 g_free(fw_filename);
870
871 /* load kernel */
872 if (machine->kernel_filename) {
873 long kernel_size;
874
875 kernel_size = load_image_targphys(machine->kernel_filename,
876 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE);
877 if (kernel_size < 0) {
878 error_report("Could not load kernel '%s'",
879 machine->kernel_filename);
880 exit(1);
881 }
882 }
883
884 /* load initrd */
885 if (machine->initrd_filename) {
886 pnv->initrd_base = INITRD_LOAD_ADDR;
887 pnv->initrd_size = load_image_targphys(machine->initrd_filename,
888 pnv->initrd_base, INITRD_MAX_SIZE);
889 if (pnv->initrd_size < 0) {
890 error_report("Could not load initial ram disk '%s'",
891 machine->initrd_filename);
892 exit(1);
893 }
894 }
895
896 /* MSIs are supported on this platform */
897 msi_nonbroken = true;
898
899 /*
900 * Check compatibility of the specified CPU with the machine
901 * default.
902 */
903 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) {
904 error_report("invalid CPU model '%s' for %s machine",
905 machine->cpu_type, mc->name);
906 exit(1);
907 }
908
909 /* Create the processor chips */
910 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX);
911 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"),
912 i, machine->cpu_type);
913 if (!object_class_by_name(chip_typename)) {
914 error_report("invalid chip model '%.*s' for %s machine",
915 i, machine->cpu_type, mc->name);
916 exit(1);
917 }
918
919 pnv->num_chips =
920 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads);
921 /*
922 * TODO: should we decide on how many chips we can create based
923 * on #cores and Venice vs. Murano vs. Naples chip type etc...,
924 */
925 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) {
926 error_report("invalid number of chips: '%d'", pnv->num_chips);
927 error_printf(
928 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n");
929 exit(1);
930 }
931
932 pnv->chips = g_new0(PnvChip *, pnv->num_chips);
933 for (i = 0; i < pnv->num_chips; i++) {
934 char chip_name[32];
935 Object *chip = OBJECT(qdev_new(chip_typename));
936 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i);
937
938 pnv->chips[i] = PNV_CHIP(chip);
939
940 /* Distribute RAM among the chips */
941 object_property_set_int(chip, "ram-start", chip_ram_start,
942 &error_fatal);
943 object_property_set_int(chip, "ram-size", chip_ram_size,
944 &error_fatal);
945 chip_ram_start += chip_ram_size;
946
947 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i);
948 object_property_add_child(OBJECT(pnv), chip_name, chip);
949 object_property_set_int(chip, "chip-id", i, &error_fatal);
950 object_property_set_int(chip, "nr-cores", machine->smp.cores,
951 &error_fatal);
952 object_property_set_int(chip, "nr-threads", machine->smp.threads,
953 &error_fatal);
954 /*
955 * The POWER8 machine use the XICS interrupt interface.
956 * Propagate the XICS fabric to the chip and its controllers.
957 */
958 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) {
959 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort);
960 }
961 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) {
962 object_property_set_link(chip, "xive-fabric", OBJECT(pnv),
963 &error_abort);
964 }
965 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal);
966 }
967 g_free(chip_typename);
968
969 /* Instantiate ISA bus on chip 0 */
970 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal);
971
972 /* Create serial port */
973 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS);
974
975 /* Create an RTC ISA device too */
976 mc146818_rtc_init(pnv->isa_bus, 2000, NULL);
977
978 /*
979 * Create the machine BMC simulator and the IPMI BT device for
980 * communication with the BMC
981 */
982 if (defaults_enabled()) {
983 pnv->bmc = pnv_bmc_create(pnv->pnor);
984 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10);
985 }
986
987 /*
988 * The PNOR is mapped on the LPC FW address space by the BMC.
989 * Since we can not reach the remote BMC machine with LPC memops,
990 * map it always for now.
991 */
992 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET,
993 &pnv->pnor->mmio);
994
995 /*
996 * OpenPOWER systems use a IPMI SEL Event message to notify the
997 * host to powerdown
998 */
999 pnv->powerdown_notifier.notify = pnv_powerdown_notify;
1000 qemu_register_powerdown_notifier(&pnv->powerdown_notifier);
1001 }
1002
1003 /*
1004 * 0:21 Reserved - Read as zeros
1005 * 22:24 Chip ID
1006 * 25:28 Core number
1007 * 29:31 Thread ID
1008 */
1009 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
1010 {
1011 return (chip->chip_id << 7) | (core_id << 3);
1012 }
1013
1014 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1015 Error **errp)
1016 {
1017 Pnv8Chip *chip8 = PNV8_CHIP(chip);
1018 Error *local_err = NULL;
1019 Object *obj;
1020 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1021
1022 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err);
1023 if (local_err) {
1024 error_propagate(errp, local_err);
1025 return;
1026 }
1027
1028 pnv_cpu->intc = obj;
1029 }
1030
1031
1032 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1033 {
1034 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1035
1036 icp_reset(ICP(pnv_cpu->intc));
1037 }
1038
1039 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1040 {
1041 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1042
1043 icp_destroy(ICP(pnv_cpu->intc));
1044 pnv_cpu->intc = NULL;
1045 }
1046
1047 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1048 Monitor *mon)
1049 {
1050 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon);
1051 }
1052
1053 /*
1054 * 0:48 Reserved - Read as zeroes
1055 * 49:52 Node ID
1056 * 53:55 Chip ID
1057 * 56 Reserved - Read as zero
1058 * 57:61 Core number
1059 * 62:63 Thread ID
1060 *
1061 * We only care about the lower bits. uint32_t is fine for the moment.
1062 */
1063 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id)
1064 {
1065 return (chip->chip_id << 8) | (core_id << 2);
1066 }
1067
1068 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id)
1069 {
1070 return (chip->chip_id << 8) | (core_id << 2);
1071 }
1072
1073 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1074 Error **errp)
1075 {
1076 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1077 Error *local_err = NULL;
1078 Object *obj;
1079 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1080
1081 /*
1082 * The core creates its interrupt presenter but the XIVE interrupt
1083 * controller object is initialized afterwards. Hopefully, it's
1084 * only used at runtime.
1085 */
1086 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive),
1087 &local_err);
1088 if (local_err) {
1089 error_propagate(errp, local_err);
1090 return;
1091 }
1092
1093 pnv_cpu->intc = obj;
1094 }
1095
1096 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1097 {
1098 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1099
1100 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1101 }
1102
1103 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1104 {
1105 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1106
1107 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1108 pnv_cpu->intc = NULL;
1109 }
1110
1111 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1112 Monitor *mon)
1113 {
1114 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1115 }
1116
1117 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu,
1118 Error **errp)
1119 {
1120 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1121 Error *local_err = NULL;
1122 Object *obj;
1123 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1124
1125 /*
1126 * The core creates its interrupt presenter but the XIVE2 interrupt
1127 * controller object is initialized afterwards. Hopefully, it's
1128 * only used at runtime.
1129 */
1130 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive),
1131 &local_err);
1132 if (local_err) {
1133 error_propagate(errp, local_err);
1134 return;
1135 }
1136
1137 pnv_cpu->intc = obj;
1138 }
1139
1140 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu)
1141 {
1142 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1143
1144 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc));
1145 }
1146
1147 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu)
1148 {
1149 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu);
1150
1151 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc));
1152 pnv_cpu->intc = NULL;
1153 }
1154
1155 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu,
1156 Monitor *mon)
1157 {
1158 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon);
1159 }
1160
1161 /*
1162 * Allowed core identifiers on a POWER8 Processor Chip :
1163 *
1164 * <EX0 reserved>
1165 * EX1 - Venice only
1166 * EX2 - Venice only
1167 * EX3 - Venice only
1168 * EX4
1169 * EX5
1170 * EX6
1171 * <EX7,8 reserved> <reserved>
1172 * EX9 - Venice only
1173 * EX10 - Venice only
1174 * EX11 - Venice only
1175 * EX12
1176 * EX13
1177 * EX14
1178 * <EX15 reserved>
1179 */
1180 #define POWER8E_CORE_MASK (0x7070ull)
1181 #define POWER8_CORE_MASK (0x7e7eull)
1182
1183 /*
1184 * POWER9 has 24 cores, ids starting at 0x0
1185 */
1186 #define POWER9_CORE_MASK (0xffffffffffffffull)
1187
1188
1189 #define POWER10_CORE_MASK (0xffffffffffffffull)
1190
1191 static void pnv_chip_power8_instance_init(Object *obj)
1192 {
1193 Pnv8Chip *chip8 = PNV8_CHIP(obj);
1194 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1195 int i;
1196
1197 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC,
1198 (Object **)&chip8->xics,
1199 object_property_allow_set_link,
1200 OBJ_PROP_LINK_STRONG);
1201
1202 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI);
1203
1204 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC);
1205
1206 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC);
1207
1208 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER);
1209
1210 if (defaults_enabled()) {
1211 chip8->num_phbs = pcc->num_phbs;
1212
1213 for (i = 0; i < chip8->num_phbs; i++) {
1214 Object *phb = object_new(TYPE_PNV_PHB);
1215
1216 /*
1217 * We need the chip to parent the PHB to allow the DT
1218 * to build correctly (via pnv_xscom_dt()).
1219 *
1220 * TODO: the PHB should be parented by a PEC device that, at
1221 * this moment, is not modelled powernv8/phb3.
1222 */
1223 object_property_add_child(obj, "phb[*]", phb);
1224 chip8->phbs[i] = PNV_PHB(phb);
1225 }
1226 }
1227
1228 }
1229
1230 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp)
1231 {
1232 PnvChip *chip = PNV_CHIP(chip8);
1233 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1234 int i, j;
1235 char *name;
1236
1237 name = g_strdup_printf("icp-%x", chip->chip_id);
1238 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE);
1239 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio);
1240 g_free(name);
1241
1242 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip));
1243
1244 /* Map the ICP registers for each thread */
1245 for (i = 0; i < chip->nr_cores; i++) {
1246 PnvCore *pnv_core = chip->cores[i];
1247 int core_hwid = CPU_CORE(pnv_core)->core_id;
1248
1249 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) {
1250 uint32_t pir = pcc->core_pir(chip, core_hwid) + j;
1251 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir));
1252
1253 memory_region_add_subregion(&chip8->icp_mmio, pir << 12,
1254 &icp->mmio);
1255 }
1256 }
1257 }
1258
1259 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
1260 {
1261 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1262 PnvChip *chip = PNV_CHIP(dev);
1263 Pnv8Chip *chip8 = PNV8_CHIP(dev);
1264 Pnv8Psi *psi8 = &chip8->psi;
1265 Error *local_err = NULL;
1266 int i;
1267
1268 assert(chip8->xics);
1269
1270 /* XSCOM bridge is first */
1271 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err);
1272 if (local_err) {
1273 error_propagate(errp, local_err);
1274 return;
1275 }
1276 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip));
1277
1278 pcc->parent_realize(dev, &local_err);
1279 if (local_err) {
1280 error_propagate(errp, local_err);
1281 return;
1282 }
1283
1284 /* Processor Service Interface (PSI) Host Bridge */
1285 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip),
1286 &error_fatal);
1287 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS,
1288 OBJECT(chip8->xics), &error_abort);
1289 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) {
1290 return;
1291 }
1292 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE,
1293 &PNV_PSI(psi8)->xscom_regs);
1294
1295 /* Create LPC controller */
1296 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal);
1297 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs);
1298
1299 chip->fw_mr = &chip8->lpc.isa_fw;
1300 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x",
1301 (uint64_t) PNV_XSCOM_BASE(chip),
1302 PNV_XSCOM_LPC_BASE);
1303
1304 /*
1305 * Interrupt Management Area. This is the memory region holding
1306 * all the Interrupt Control Presenter (ICP) registers
1307 */
1308 pnv_chip_icp_realize(chip8, &local_err);
1309 if (local_err) {
1310 error_propagate(errp, local_err);
1311 return;
1312 }
1313
1314 /* Create the simplified OCC model */
1315 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) {
1316 return;
1317 }
1318 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
1319 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0,
1320 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC));
1321
1322 /* OCC SRAM model */
1323 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip),
1324 &chip8->occ.sram_regs);
1325
1326 /* HOMER */
1327 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip),
1328 &error_abort);
1329 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) {
1330 return;
1331 }
1332 /* Homer Xscom region */
1333 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
1334
1335 /* Homer mmio region */
1336 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
1337 &chip8->homer.regs);
1338
1339 /* PHB controllers */
1340 for (i = 0; i < chip8->num_phbs; i++) {
1341 PnvPHB *phb = chip8->phbs[i];
1342
1343 object_property_set_int(OBJECT(phb), "index", i, &error_fatal);
1344 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id,
1345 &error_fatal);
1346 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip),
1347 &error_fatal);
1348 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) {
1349 return;
1350 }
1351 }
1352 }
1353
1354 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
1355 {
1356 addr &= (PNV_XSCOM_SIZE - 1);
1357 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
1358 }
1359
1360 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
1361 {
1362 DeviceClass *dc = DEVICE_CLASS(klass);
1363 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1364
1365 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */
1366 k->cores_mask = POWER8E_CORE_MASK;
1367 k->num_phbs = 3;
1368 k->core_pir = pnv_chip_core_pir_p8;
1369 k->intc_create = pnv_chip_power8_intc_create;
1370 k->intc_reset = pnv_chip_power8_intc_reset;
1371 k->intc_destroy = pnv_chip_power8_intc_destroy;
1372 k->intc_print_info = pnv_chip_power8_intc_print_info;
1373 k->isa_create = pnv_chip_power8_isa_create;
1374 k->dt_populate = pnv_chip_power8_dt_populate;
1375 k->pic_print_info = pnv_chip_power8_pic_print_info;
1376 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1377 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1378 dc->desc = "PowerNV Chip POWER8E";
1379
1380 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1381 &k->parent_realize);
1382 }
1383
1384 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
1385 {
1386 DeviceClass *dc = DEVICE_CLASS(klass);
1387 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1388
1389 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */
1390 k->cores_mask = POWER8_CORE_MASK;
1391 k->num_phbs = 3;
1392 k->core_pir = pnv_chip_core_pir_p8;
1393 k->intc_create = pnv_chip_power8_intc_create;
1394 k->intc_reset = pnv_chip_power8_intc_reset;
1395 k->intc_destroy = pnv_chip_power8_intc_destroy;
1396 k->intc_print_info = pnv_chip_power8_intc_print_info;
1397 k->isa_create = pnv_chip_power8_isa_create;
1398 k->dt_populate = pnv_chip_power8_dt_populate;
1399 k->pic_print_info = pnv_chip_power8_pic_print_info;
1400 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1401 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1402 dc->desc = "PowerNV Chip POWER8";
1403
1404 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1405 &k->parent_realize);
1406 }
1407
1408 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
1409 {
1410 DeviceClass *dc = DEVICE_CLASS(klass);
1411 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1412
1413 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */
1414 k->cores_mask = POWER8_CORE_MASK;
1415 k->num_phbs = 4;
1416 k->core_pir = pnv_chip_core_pir_p8;
1417 k->intc_create = pnv_chip_power8_intc_create;
1418 k->intc_reset = pnv_chip_power8_intc_reset;
1419 k->intc_destroy = pnv_chip_power8_intc_destroy;
1420 k->intc_print_info = pnv_chip_power8_intc_print_info;
1421 k->isa_create = pnv_chip_power8nvl_isa_create;
1422 k->dt_populate = pnv_chip_power8_dt_populate;
1423 k->pic_print_info = pnv_chip_power8_pic_print_info;
1424 k->xscom_core_base = pnv_chip_power8_xscom_core_base;
1425 k->xscom_pcba = pnv_chip_power8_xscom_pcba;
1426 dc->desc = "PowerNV Chip POWER8NVL";
1427
1428 device_class_set_parent_realize(dc, pnv_chip_power8_realize,
1429 &k->parent_realize);
1430 }
1431
1432 static void pnv_chip_power9_instance_init(Object *obj)
1433 {
1434 PnvChip *chip = PNV_CHIP(obj);
1435 Pnv9Chip *chip9 = PNV9_CHIP(obj);
1436 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1437 int i;
1438
1439 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE);
1440 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive),
1441 "xive-fabric");
1442
1443 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI);
1444
1445 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC);
1446
1447 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC);
1448
1449 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE);
1450
1451 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER);
1452
1453 /* Number of PECs is the chip default */
1454 chip->num_pecs = pcc->num_pecs;
1455
1456 for (i = 0; i < chip->num_pecs; i++) {
1457 object_initialize_child(obj, "pec[*]", &chip9->pecs[i],
1458 TYPE_PNV_PHB4_PEC);
1459 }
1460 }
1461
1462 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq,
1463 PnvCore *pnv_core)
1464 {
1465 char eq_name[32];
1466 int core_id = CPU_CORE(pnv_core)->core_id;
1467
1468 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id);
1469 object_initialize_child_with_props(OBJECT(chip), eq_name, eq,
1470 sizeof(*eq), TYPE_PNV_QUAD,
1471 &error_fatal, NULL);
1472
1473 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal);
1474 qdev_realize(DEVICE(eq), NULL, &error_fatal);
1475 }
1476
1477 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp)
1478 {
1479 PnvChip *chip = PNV_CHIP(chip9);
1480 int i;
1481
1482 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1483 chip9->quads = g_new0(PnvQuad, chip9->nr_quads);
1484
1485 for (i = 0; i < chip9->nr_quads; i++) {
1486 PnvQuad *eq = &chip9->quads[i];
1487
1488 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
1489
1490 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id),
1491 &eq->xscom_regs);
1492 }
1493 }
1494
1495 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp)
1496 {
1497 Pnv9Chip *chip9 = PNV9_CHIP(chip);
1498 int i;
1499
1500 for (i = 0; i < chip->num_pecs; i++) {
1501 PnvPhb4PecState *pec = &chip9->pecs[i];
1502 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1503 uint32_t pec_nest_base;
1504 uint32_t pec_pci_base;
1505
1506 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1507 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1508 &error_fatal);
1509 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1510 &error_fatal);
1511 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1512 return;
1513 }
1514
1515 pec_nest_base = pecc->xscom_nest_base(pec);
1516 pec_pci_base = pecc->xscom_pci_base(pec);
1517
1518 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1519 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1520 }
1521 }
1522
1523 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
1524 {
1525 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1526 Pnv9Chip *chip9 = PNV9_CHIP(dev);
1527 PnvChip *chip = PNV_CHIP(dev);
1528 Pnv9Psi *psi9 = &chip9->psi;
1529 Error *local_err = NULL;
1530
1531 /* XSCOM bridge is first */
1532 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err);
1533 if (local_err) {
1534 error_propagate(errp, local_err);
1535 return;
1536 }
1537 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip));
1538
1539 pcc->parent_realize(dev, &local_err);
1540 if (local_err) {
1541 error_propagate(errp, local_err);
1542 return;
1543 }
1544
1545 pnv_chip_quad_realize(chip9, &local_err);
1546 if (local_err) {
1547 error_propagate(errp, local_err);
1548 return;
1549 }
1550
1551 /* XIVE interrupt controller (POWER9) */
1552 object_property_set_int(OBJECT(&chip9->xive), "ic-bar",
1553 PNV9_XIVE_IC_BASE(chip), &error_fatal);
1554 object_property_set_int(OBJECT(&chip9->xive), "vc-bar",
1555 PNV9_XIVE_VC_BASE(chip), &error_fatal);
1556 object_property_set_int(OBJECT(&chip9->xive), "pc-bar",
1557 PNV9_XIVE_PC_BASE(chip), &error_fatal);
1558 object_property_set_int(OBJECT(&chip9->xive), "tm-bar",
1559 PNV9_XIVE_TM_BASE(chip), &error_fatal);
1560 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip),
1561 &error_abort);
1562 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) {
1563 return;
1564 }
1565 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE,
1566 &chip9->xive.xscom_regs);
1567
1568 /* Processor Service Interface (PSI) Host Bridge */
1569 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip),
1570 &error_fatal);
1571 /* This is the only device with 4k ESB pages */
1572 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K,
1573 &error_fatal);
1574 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) {
1575 return;
1576 }
1577 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE,
1578 &PNV_PSI(psi9)->xscom_regs);
1579
1580 /* LPC */
1581 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) {
1582 return;
1583 }
1584 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip),
1585 &chip9->lpc.xscom_regs);
1586
1587 chip->fw_mr = &chip9->lpc.isa_fw;
1588 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1589 (uint64_t) PNV9_LPCM_BASE(chip));
1590
1591 /* Create the simplified OCC model */
1592 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) {
1593 return;
1594 }
1595 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
1596 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in(
1597 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC));
1598
1599 /* OCC SRAM model */
1600 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip),
1601 &chip9->occ.sram_regs);
1602
1603 /* SBE */
1604 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) {
1605 return;
1606 }
1607 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE,
1608 &chip9->sbe.xscom_ctrl_regs);
1609 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE,
1610 &chip9->sbe.xscom_mbox_regs);
1611 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in(
1612 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU));
1613
1614 /* HOMER */
1615 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip),
1616 &error_abort);
1617 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) {
1618 return;
1619 }
1620 /* Homer Xscom region */
1621 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
1622
1623 /* Homer mmio region */
1624 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
1625 &chip9->homer.regs);
1626
1627 /* PEC PHBs */
1628 pnv_chip_power9_pec_realize(chip, &local_err);
1629 if (local_err) {
1630 error_propagate(errp, local_err);
1631 return;
1632 }
1633 }
1634
1635 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
1636 {
1637 addr &= (PNV9_XSCOM_SIZE - 1);
1638 return addr >> 3;
1639 }
1640
1641 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
1642 {
1643 DeviceClass *dc = DEVICE_CLASS(klass);
1644 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1645
1646 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */
1647 k->cores_mask = POWER9_CORE_MASK;
1648 k->core_pir = pnv_chip_core_pir_p9;
1649 k->intc_create = pnv_chip_power9_intc_create;
1650 k->intc_reset = pnv_chip_power9_intc_reset;
1651 k->intc_destroy = pnv_chip_power9_intc_destroy;
1652 k->intc_print_info = pnv_chip_power9_intc_print_info;
1653 k->isa_create = pnv_chip_power9_isa_create;
1654 k->dt_populate = pnv_chip_power9_dt_populate;
1655 k->pic_print_info = pnv_chip_power9_pic_print_info;
1656 k->xscom_core_base = pnv_chip_power9_xscom_core_base;
1657 k->xscom_pcba = pnv_chip_power9_xscom_pcba;
1658 dc->desc = "PowerNV Chip POWER9";
1659 k->num_pecs = PNV9_CHIP_MAX_PEC;
1660
1661 device_class_set_parent_realize(dc, pnv_chip_power9_realize,
1662 &k->parent_realize);
1663 }
1664
1665 static void pnv_chip_power10_instance_init(Object *obj)
1666 {
1667 PnvChip *chip = PNV_CHIP(obj);
1668 Pnv10Chip *chip10 = PNV10_CHIP(obj);
1669 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj);
1670 int i;
1671
1672 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2);
1673 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive),
1674 "xive-fabric");
1675 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI);
1676 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC);
1677 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC);
1678 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE);
1679 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER);
1680
1681 chip->num_pecs = pcc->num_pecs;
1682
1683 for (i = 0; i < chip->num_pecs; i++) {
1684 object_initialize_child(obj, "pec[*]", &chip10->pecs[i],
1685 TYPE_PNV_PHB5_PEC);
1686 }
1687 }
1688
1689 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp)
1690 {
1691 PnvChip *chip = PNV_CHIP(chip10);
1692 int i;
1693
1694 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4);
1695 chip10->quads = g_new0(PnvQuad, chip10->nr_quads);
1696
1697 for (i = 0; i < chip10->nr_quads; i++) {
1698 PnvQuad *eq = &chip10->quads[i];
1699
1700 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]);
1701
1702 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id),
1703 &eq->xscom_regs);
1704 }
1705 }
1706
1707 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp)
1708 {
1709 Pnv10Chip *chip10 = PNV10_CHIP(chip);
1710 int i;
1711
1712 for (i = 0; i < chip->num_pecs; i++) {
1713 PnvPhb4PecState *pec = &chip10->pecs[i];
1714 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec);
1715 uint32_t pec_nest_base;
1716 uint32_t pec_pci_base;
1717
1718 object_property_set_int(OBJECT(pec), "index", i, &error_fatal);
1719 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id,
1720 &error_fatal);
1721 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip),
1722 &error_fatal);
1723 if (!qdev_realize(DEVICE(pec), NULL, errp)) {
1724 return;
1725 }
1726
1727 pec_nest_base = pecc->xscom_nest_base(pec);
1728 pec_pci_base = pecc->xscom_pci_base(pec);
1729
1730 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr);
1731 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr);
1732 }
1733 }
1734
1735 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
1736 {
1737 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev);
1738 PnvChip *chip = PNV_CHIP(dev);
1739 Pnv10Chip *chip10 = PNV10_CHIP(dev);
1740 Error *local_err = NULL;
1741
1742 /* XSCOM bridge is first */
1743 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err);
1744 if (local_err) {
1745 error_propagate(errp, local_err);
1746 return;
1747 }
1748 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip));
1749
1750 pcc->parent_realize(dev, &local_err);
1751 if (local_err) {
1752 error_propagate(errp, local_err);
1753 return;
1754 }
1755
1756 pnv_chip_power10_quad_realize(chip10, &local_err);
1757 if (local_err) {
1758 error_propagate(errp, local_err);
1759 return;
1760 }
1761
1762 /* XIVE2 interrupt controller (POWER10) */
1763 object_property_set_int(OBJECT(&chip10->xive), "ic-bar",
1764 PNV10_XIVE2_IC_BASE(chip), &error_fatal);
1765 object_property_set_int(OBJECT(&chip10->xive), "esb-bar",
1766 PNV10_XIVE2_ESB_BASE(chip), &error_fatal);
1767 object_property_set_int(OBJECT(&chip10->xive), "end-bar",
1768 PNV10_XIVE2_END_BASE(chip), &error_fatal);
1769 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar",
1770 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal);
1771 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar",
1772 PNV10_XIVE2_NVC_BASE(chip), &error_fatal);
1773 object_property_set_int(OBJECT(&chip10->xive), "tm-bar",
1774 PNV10_XIVE2_TM_BASE(chip), &error_fatal);
1775 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip),
1776 &error_abort);
1777 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) {
1778 return;
1779 }
1780 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE,
1781 &chip10->xive.xscom_regs);
1782
1783 /* Processor Service Interface (PSI) Host Bridge */
1784 object_property_set_int(OBJECT(&chip10->psi), "bar",
1785 PNV10_PSIHB_BASE(chip), &error_fatal);
1786 /* PSI can now be configured to use 64k ESB pages on POWER10 */
1787 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K,
1788 &error_fatal);
1789 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) {
1790 return;
1791 }
1792 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE,
1793 &PNV_PSI(&chip10->psi)->xscom_regs);
1794
1795 /* LPC */
1796 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) {
1797 return;
1798 }
1799 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip),
1800 &chip10->lpc.xscom_regs);
1801
1802 chip->fw_mr = &chip10->lpc.isa_fw;
1803 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0",
1804 (uint64_t) PNV10_LPCM_BASE(chip));
1805
1806 /* Create the simplified OCC model */
1807 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) {
1808 return;
1809 }
1810 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE,
1811 &chip10->occ.xscom_regs);
1812 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in(
1813 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC));
1814
1815 /* OCC SRAM model */
1816 memory_region_add_subregion(get_system_memory(),
1817 PNV10_OCC_SENSOR_BASE(chip),
1818 &chip10->occ.sram_regs);
1819
1820 /* SBE */
1821 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) {
1822 return;
1823 }
1824 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE,
1825 &chip10->sbe.xscom_ctrl_regs);
1826 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE,
1827 &chip10->sbe.xscom_mbox_regs);
1828 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in(
1829 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU));
1830
1831 /* HOMER */
1832 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip),
1833 &error_abort);
1834 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) {
1835 return;
1836 }
1837 /* Homer Xscom region */
1838 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE,
1839 &chip10->homer.pba_regs);
1840
1841 /* Homer mmio region */
1842 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip),
1843 &chip10->homer.regs);
1844
1845 /* PHBs */
1846 pnv_chip_power10_phb_realize(chip, &local_err);
1847 if (local_err) {
1848 error_propagate(errp, local_err);
1849 return;
1850 }
1851 }
1852
1853 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
1854 {
1855 addr &= (PNV10_XSCOM_SIZE - 1);
1856 return addr >> 3;
1857 }
1858
1859 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
1860 {
1861 DeviceClass *dc = DEVICE_CLASS(klass);
1862 PnvChipClass *k = PNV_CHIP_CLASS(klass);
1863
1864 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */
1865 k->cores_mask = POWER10_CORE_MASK;
1866 k->core_pir = pnv_chip_core_pir_p10;
1867 k->intc_create = pnv_chip_power10_intc_create;
1868 k->intc_reset = pnv_chip_power10_intc_reset;
1869 k->intc_destroy = pnv_chip_power10_intc_destroy;
1870 k->intc_print_info = pnv_chip_power10_intc_print_info;
1871 k->isa_create = pnv_chip_power10_isa_create;
1872 k->dt_populate = pnv_chip_power10_dt_populate;
1873 k->pic_print_info = pnv_chip_power10_pic_print_info;
1874 k->xscom_core_base = pnv_chip_power10_xscom_core_base;
1875 k->xscom_pcba = pnv_chip_power10_xscom_pcba;
1876 dc->desc = "PowerNV Chip POWER10";
1877 k->num_pecs = PNV10_CHIP_MAX_PEC;
1878
1879 device_class_set_parent_realize(dc, pnv_chip_power10_realize,
1880 &k->parent_realize);
1881 }
1882
1883 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp)
1884 {
1885 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1886 int cores_max;
1887
1888 /*
1889 * No custom mask for this chip, let's use the default one from *
1890 * the chip class
1891 */
1892 if (!chip->cores_mask) {
1893 chip->cores_mask = pcc->cores_mask;
1894 }
1895
1896 /* filter alien core ids ! some are reserved */
1897 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) {
1898 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !",
1899 chip->cores_mask);
1900 return;
1901 }
1902 chip->cores_mask &= pcc->cores_mask;
1903
1904 /* now that we have a sane layout, let check the number of cores */
1905 cores_max = ctpop64(chip->cores_mask);
1906 if (chip->nr_cores > cores_max) {
1907 error_setg(errp, "warning: too many cores for chip ! Limit is %d",
1908 cores_max);
1909 return;
1910 }
1911 }
1912
1913 static void pnv_chip_core_realize(PnvChip *chip, Error **errp)
1914 {
1915 Error *error = NULL;
1916 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
1917 const char *typename = pnv_chip_core_typename(chip);
1918 int i, core_hwid;
1919 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
1920
1921 if (!object_class_by_name(typename)) {
1922 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
1923 return;
1924 }
1925
1926 /* Cores */
1927 pnv_chip_core_sanitize(chip, &error);
1928 if (error) {
1929 error_propagate(errp, error);
1930 return;
1931 }
1932
1933 chip->cores = g_new0(PnvCore *, chip->nr_cores);
1934
1935 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
1936 && (i < chip->nr_cores); core_hwid++) {
1937 char core_name[32];
1938 PnvCore *pnv_core;
1939 uint64_t xscom_core_base;
1940
1941 if (!(chip->cores_mask & (1ull << core_hwid))) {
1942 continue;
1943 }
1944
1945 pnv_core = PNV_CORE(object_new(typename));
1946
1947 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid);
1948 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core));
1949 chip->cores[i] = pnv_core;
1950 object_property_set_int(OBJECT(pnv_core), "nr-threads",
1951 chip->nr_threads, &error_fatal);
1952 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID,
1953 core_hwid, &error_fatal);
1954 object_property_set_int(OBJECT(pnv_core), "pir",
1955 pcc->core_pir(chip, core_hwid), &error_fatal);
1956 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr,
1957 &error_fatal);
1958 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip),
1959 &error_abort);
1960 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal);
1961
1962 /* Each core has an XSCOM MMIO region */
1963 xscom_core_base = pcc->xscom_core_base(chip, core_hwid);
1964
1965 pnv_xscom_add_subregion(chip, xscom_core_base,
1966 &pnv_core->xscom_regs);
1967 i++;
1968 }
1969 }
1970
1971 static void pnv_chip_realize(DeviceState *dev, Error **errp)
1972 {
1973 PnvChip *chip = PNV_CHIP(dev);
1974 Error *error = NULL;
1975
1976 /* Cores */
1977 pnv_chip_core_realize(chip, &error);
1978 if (error) {
1979 error_propagate(errp, error);
1980 return;
1981 }
1982 }
1983
1984 static Property pnv_chip_properties[] = {
1985 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0),
1986 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0),
1987 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0),
1988 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1),
1989 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0),
1990 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1),
1991 DEFINE_PROP_END_OF_LIST(),
1992 };
1993
1994 static void pnv_chip_class_init(ObjectClass *klass, void *data)
1995 {
1996 DeviceClass *dc = DEVICE_CLASS(klass);
1997
1998 set_bit(DEVICE_CATEGORY_CPU, dc->categories);
1999 dc->realize = pnv_chip_realize;
2000 device_class_set_props(dc, pnv_chip_properties);
2001 dc->desc = "PowerNV Chip";
2002 }
2003
2004 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir)
2005 {
2006 int i, j;
2007
2008 for (i = 0; i < chip->nr_cores; i++) {
2009 PnvCore *pc = chip->cores[i];
2010 CPUCore *cc = CPU_CORE(pc);
2011
2012 for (j = 0; j < cc->nr_threads; j++) {
2013 if (ppc_cpu_pir(pc->threads[j]) == pir) {
2014 return pc->threads[j];
2015 }
2016 }
2017 }
2018 return NULL;
2019 }
2020
2021 static ICSState *pnv_ics_get(XICSFabric *xi, int irq)
2022 {
2023 PnvMachineState *pnv = PNV_MACHINE(xi);
2024 int i, j;
2025
2026 for (i = 0; i < pnv->num_chips; i++) {
2027 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2028
2029 if (ics_valid_irq(&chip8->psi.ics, irq)) {
2030 return &chip8->psi.ics;
2031 }
2032
2033 for (j = 0; j < chip8->num_phbs; j++) {
2034 PnvPHB *phb = chip8->phbs[j];
2035 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2036
2037 if (ics_valid_irq(&phb3->lsis, irq)) {
2038 return &phb3->lsis;
2039 }
2040
2041 if (ics_valid_irq(ICS(&phb3->msis), irq)) {
2042 return ICS(&phb3->msis);
2043 }
2044 }
2045 }
2046 return NULL;
2047 }
2048
2049 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id)
2050 {
2051 int i;
2052
2053 for (i = 0; i < pnv->num_chips; i++) {
2054 PnvChip *chip = pnv->chips[i];
2055 if (chip->chip_id == chip_id) {
2056 return chip;
2057 }
2058 }
2059 return NULL;
2060 }
2061
2062 static void pnv_ics_resend(XICSFabric *xi)
2063 {
2064 PnvMachineState *pnv = PNV_MACHINE(xi);
2065 int i, j;
2066
2067 for (i = 0; i < pnv->num_chips; i++) {
2068 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]);
2069
2070 ics_resend(&chip8->psi.ics);
2071
2072 for (j = 0; j < chip8->num_phbs; j++) {
2073 PnvPHB *phb = chip8->phbs[j];
2074 PnvPHB3 *phb3 = PNV_PHB3(phb->backend);
2075
2076 ics_resend(&phb3->lsis);
2077 ics_resend(ICS(&phb3->msis));
2078 }
2079 }
2080 }
2081
2082 static ICPState *pnv_icp_get(XICSFabric *xi, int pir)
2083 {
2084 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir);
2085
2086 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL;
2087 }
2088
2089 static void pnv_pic_print_info(InterruptStatsProvider *obj,
2090 Monitor *mon)
2091 {
2092 PnvMachineState *pnv = PNV_MACHINE(obj);
2093 int i;
2094 CPUState *cs;
2095
2096 CPU_FOREACH(cs) {
2097 PowerPCCPU *cpu = POWERPC_CPU(cs);
2098
2099 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */
2100 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu,
2101 mon);
2102 }
2103
2104 for (i = 0; i < pnv->num_chips; i++) {
2105 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon);
2106 }
2107 }
2108
2109 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format,
2110 uint8_t nvt_blk, uint32_t nvt_idx,
2111 bool cam_ignore, uint8_t priority,
2112 uint32_t logic_serv,
2113 XiveTCTXMatch *match)
2114 {
2115 PnvMachineState *pnv = PNV_MACHINE(xfb);
2116 int total_count = 0;
2117 int i;
2118
2119 for (i = 0; i < pnv->num_chips; i++) {
2120 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]);
2121 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive);
2122 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2123 int count;
2124
2125 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2126 priority, logic_serv, match);
2127
2128 if (count < 0) {
2129 return count;
2130 }
2131
2132 total_count += count;
2133 }
2134
2135 return total_count;
2136 }
2137
2138 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format,
2139 uint8_t nvt_blk, uint32_t nvt_idx,
2140 bool cam_ignore, uint8_t priority,
2141 uint32_t logic_serv,
2142 XiveTCTXMatch *match)
2143 {
2144 PnvMachineState *pnv = PNV_MACHINE(xfb);
2145 int total_count = 0;
2146 int i;
2147
2148 for (i = 0; i < pnv->num_chips; i++) {
2149 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]);
2150 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive);
2151 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr);
2152 int count;
2153
2154 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore,
2155 priority, logic_serv, match);
2156
2157 if (count < 0) {
2158 return count;
2159 }
2160
2161 total_count += count;
2162 }
2163
2164 return total_count;
2165 }
2166
2167 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data)
2168 {
2169 MachineClass *mc = MACHINE_CLASS(oc);
2170 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc);
2171 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2172 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv";
2173
2174 static GlobalProperty phb_compat[] = {
2175 { TYPE_PNV_PHB, "version", "3" },
2176 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" },
2177 };
2178
2179 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8";
2180 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0");
2181 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2182
2183 xic->icp_get = pnv_icp_get;
2184 xic->ics_get = pnv_ics_get;
2185 xic->ics_resend = pnv_ics_resend;
2186
2187 pmc->compat = compat;
2188 pmc->compat_size = sizeof(compat);
2189
2190 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2191 }
2192
2193 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data)
2194 {
2195 MachineClass *mc = MACHINE_CLASS(oc);
2196 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2197 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2198 static const char compat[] = "qemu,powernv9\0ibm,powernv";
2199
2200 static GlobalProperty phb_compat[] = {
2201 { TYPE_PNV_PHB, "version", "4" },
2202 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" },
2203 };
2204
2205 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9";
2206 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0");
2207 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2208
2209 xfc->match_nvt = pnv_match_nvt;
2210
2211 mc->alias = "powernv";
2212
2213 pmc->compat = compat;
2214 pmc->compat_size = sizeof(compat);
2215 pmc->dt_power_mgt = pnv_dt_power_mgt;
2216
2217 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
2218 }
2219
2220 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data)
2221 {
2222 MachineClass *mc = MACHINE_CLASS(oc);
2223 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc);
2224 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc);
2225 static const char compat[] = "qemu,powernv10\0ibm,powernv";
2226
2227 static GlobalProperty phb_compat[] = {
2228 { TYPE_PNV_PHB, "version", "5" },
2229 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" },
2230 };
2231
2232 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10";
2233 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0");
2234 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat));
2235
2236 pmc->compat = compat;
2237 pmc->compat_size = sizeof(compat);
2238 pmc->dt_power_mgt = pnv_dt_power_mgt;
2239
2240 xfc->match_nvt = pnv10_xive_match_nvt;
2241 }
2242
2243 static bool pnv_machine_get_hb(Object *obj, Error **errp)
2244 {
2245 PnvMachineState *pnv = PNV_MACHINE(obj);
2246
2247 return !!pnv->fw_load_addr;
2248 }
2249
2250 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp)
2251 {
2252 PnvMachineState *pnv = PNV_MACHINE(obj);
2253
2254 if (value) {
2255 pnv->fw_load_addr = 0x8000000;
2256 }
2257 }
2258
2259 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg)
2260 {
2261 PowerPCCPU *cpu = POWERPC_CPU(cs);
2262 CPUPPCState *env = &cpu->env;
2263
2264 cpu_synchronize_state(cs);
2265 ppc_cpu_do_system_reset(cs);
2266 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) {
2267 /*
2268 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the
2269 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100
2270 * (PPC_BIT(43)).
2271 */
2272 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) {
2273 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason");
2274 env->spr[SPR_SRR1] |= SRR1_WAKERESET;
2275 }
2276 } else {
2277 /*
2278 * For non-powersave system resets, SRR1[42:45] are defined to be
2279 * implementation-dependent. The POWER9 User Manual specifies that
2280 * an external (SCOM driven, which may come from a BMC nmi command or
2281 * another CPU requesting a NMI IPI) system reset exception should be
2282 * 0b0010 (PPC_BIT(44)).
2283 */
2284 env->spr[SPR_SRR1] |= SRR1_WAKESCOM;
2285 }
2286 }
2287
2288 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp)
2289 {
2290 CPUState *cs;
2291
2292 CPU_FOREACH(cs) {
2293 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL);
2294 }
2295 }
2296
2297 static void pnv_machine_class_init(ObjectClass *oc, void *data)
2298 {
2299 MachineClass *mc = MACHINE_CLASS(oc);
2300 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc);
2301 NMIClass *nc = NMI_CLASS(oc);
2302
2303 mc->desc = "IBM PowerNV (Non-Virtualized)";
2304 mc->init = pnv_init;
2305 mc->reset = pnv_reset;
2306 mc->max_cpus = MAX_CPUS;
2307 /* Pnv provides a AHCI device for storage */
2308 mc->block_default_type = IF_IDE;
2309 mc->no_parallel = 1;
2310 mc->default_boot_order = NULL;
2311 /*
2312 * RAM defaults to less than 2048 for 32-bit hosts, and large
2313 * enough to fit the maximum initrd size at it's load address
2314 */
2315 mc->default_ram_size = 1 * GiB;
2316 mc->default_ram_id = "pnv.ram";
2317 ispc->print_info = pnv_pic_print_info;
2318 nc->nmi_monitor_handler = pnv_nmi;
2319
2320 object_class_property_add_bool(oc, "hb-mode",
2321 pnv_machine_get_hb, pnv_machine_set_hb);
2322 object_class_property_set_description(oc, "hb-mode",
2323 "Use a hostboot like boot loader");
2324 }
2325
2326 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \
2327 { \
2328 .name = type, \
2329 .class_init = class_initfn, \
2330 .parent = TYPE_PNV8_CHIP, \
2331 }
2332
2333 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \
2334 { \
2335 .name = type, \
2336 .class_init = class_initfn, \
2337 .parent = TYPE_PNV9_CHIP, \
2338 }
2339
2340 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \
2341 { \
2342 .name = type, \
2343 .class_init = class_initfn, \
2344 .parent = TYPE_PNV10_CHIP, \
2345 }
2346
2347 static const TypeInfo types[] = {
2348 {
2349 .name = MACHINE_TYPE_NAME("powernv10"),
2350 .parent = TYPE_PNV_MACHINE,
2351 .class_init = pnv_machine_power10_class_init,
2352 .interfaces = (InterfaceInfo[]) {
2353 { TYPE_XIVE_FABRIC },
2354 { },
2355 },
2356 },
2357 {
2358 .name = MACHINE_TYPE_NAME("powernv9"),
2359 .parent = TYPE_PNV_MACHINE,
2360 .class_init = pnv_machine_power9_class_init,
2361 .interfaces = (InterfaceInfo[]) {
2362 { TYPE_XIVE_FABRIC },
2363 { },
2364 },
2365 },
2366 {
2367 .name = MACHINE_TYPE_NAME("powernv8"),
2368 .parent = TYPE_PNV_MACHINE,
2369 .class_init = pnv_machine_power8_class_init,
2370 .interfaces = (InterfaceInfo[]) {
2371 { TYPE_XICS_FABRIC },
2372 { },
2373 },
2374 },
2375 {
2376 .name = TYPE_PNV_MACHINE,
2377 .parent = TYPE_MACHINE,
2378 .abstract = true,
2379 .instance_size = sizeof(PnvMachineState),
2380 .class_init = pnv_machine_class_init,
2381 .class_size = sizeof(PnvMachineClass),
2382 .interfaces = (InterfaceInfo[]) {
2383 { TYPE_INTERRUPT_STATS_PROVIDER },
2384 { TYPE_NMI },
2385 { },
2386 },
2387 },
2388 {
2389 .name = TYPE_PNV_CHIP,
2390 .parent = TYPE_SYS_BUS_DEVICE,
2391 .class_init = pnv_chip_class_init,
2392 .instance_size = sizeof(PnvChip),
2393 .class_size = sizeof(PnvChipClass),
2394 .abstract = true,
2395 },
2396
2397 /*
2398 * P10 chip and variants
2399 */
2400 {
2401 .name = TYPE_PNV10_CHIP,
2402 .parent = TYPE_PNV_CHIP,
2403 .instance_init = pnv_chip_power10_instance_init,
2404 .instance_size = sizeof(Pnv10Chip),
2405 },
2406 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init),
2407
2408 /*
2409 * P9 chip and variants
2410 */
2411 {
2412 .name = TYPE_PNV9_CHIP,
2413 .parent = TYPE_PNV_CHIP,
2414 .instance_init = pnv_chip_power9_instance_init,
2415 .instance_size = sizeof(Pnv9Chip),
2416 },
2417 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init),
2418
2419 /*
2420 * P8 chip and variants
2421 */
2422 {
2423 .name = TYPE_PNV8_CHIP,
2424 .parent = TYPE_PNV_CHIP,
2425 .instance_init = pnv_chip_power8_instance_init,
2426 .instance_size = sizeof(Pnv8Chip),
2427 },
2428 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init),
2429 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init),
2430 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL,
2431 pnv_chip_power8nvl_class_init),
2432 };
2433
2434 DEFINE_TYPES(types)
QEmu