2 * Copyright (c) 2007, Neocleus Corporation.
4 * This work is licensed under the terms of the GNU GPL, version 2. See
5 * the COPYING file in the top-level directory.
8 * Assign a PCI device from the host to a guest VM.
10 * This implementation uses the classic device assignment interface of KVM
11 * and is only available on x86 hosts. It is expected to be obsoleted by VFIO
12 * based device assignment.
14 * Adapted for KVM (qemu-kvm) by Qumranet. QEMU version was based on qemu-kvm
15 * revision 4144fe9d48. See its repository for the history.
17 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
18 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
19 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
20 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
21 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
27 #include <sys/types.h>
30 #include "hw/i386/pc.h"
31 #include "qemu/error-report.h"
32 #include "ui/console.h"
33 #include "hw/loader.h"
34 #include "monitor/monitor.h"
35 #include "qemu/range.h"
36 #include "sysemu/sysemu.h"
37 #include "hw/pci/pci.h"
38 #include "hw/pci/msi.h"
41 #define MSIX_PAGE_SIZE 0x1000
43 /* From linux/ioport.h */
44 #define IORESOURCE_IO 0x00000100 /* Resource type */
45 #define IORESOURCE_MEM 0x00000200
46 #define IORESOURCE_IRQ 0x00000400
47 #define IORESOURCE_DMA 0x00000800
48 #define IORESOURCE_PREFETCH 0x00002000 /* No side effects */
49 #define IORESOURCE_MEM_64 0x00100000
51 //#define DEVICE_ASSIGNMENT_DEBUG
53 #ifdef DEVICE_ASSIGNMENT_DEBUG
54 #define DEBUG(fmt, ...) \
56 fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__); \
59 #define DEBUG(fmt, ...)
62 typedef struct PCIRegion
{
63 int type
; /* Memory or port I/O */
66 uint64_t size
; /* size of the region */
70 typedef struct PCIDevRegions
{
71 uint8_t bus
, dev
, func
; /* Bus inside domain, device and function */
72 int irq
; /* IRQ number */
73 uint16_t region_number
; /* number of active regions */
75 /* Port I/O or MMIO Regions */
76 PCIRegion regions
[PCI_NUM_REGIONS
- 1];
80 typedef struct AssignedDevRegion
{
81 MemoryRegion container
;
82 MemoryRegion real_iomem
;
84 uint8_t *r_virtbase
; /* mmapped access address for memory regions */
85 uint32_t r_baseport
; /* the base guest port for I/O regions */
87 pcibus_t e_size
; /* emulated size of region in bytes */
88 pcibus_t r_size
; /* real size of region in bytes */
92 #define ASSIGNED_DEVICE_PREFER_MSI_BIT 0
93 #define ASSIGNED_DEVICE_SHARE_INTX_BIT 1
95 #define ASSIGNED_DEVICE_PREFER_MSI_MASK (1 << ASSIGNED_DEVICE_PREFER_MSI_BIT)
96 #define ASSIGNED_DEVICE_SHARE_INTX_MASK (1 << ASSIGNED_DEVICE_SHARE_INTX_BIT)
98 typedef struct MSIXTableEntry
{
105 typedef enum AssignedIRQType
{
106 ASSIGNED_IRQ_NONE
= 0,
107 ASSIGNED_IRQ_INTX_HOST_INTX
,
108 ASSIGNED_IRQ_INTX_HOST_MSI
,
113 typedef struct AssignedDevice
{
115 PCIHostDeviceAddress host
;
119 AssignedDevRegion v_addrs
[PCI_NUM_REGIONS
- 1];
120 PCIDevRegions real_device
;
121 PCIINTxRoute intx_route
;
122 AssignedIRQType assigned_irq_type
;
124 #define ASSIGNED_DEVICE_CAP_MSI (1 << 0)
125 #define ASSIGNED_DEVICE_CAP_MSIX (1 << 1)
127 #define ASSIGNED_DEVICE_MSI_ENABLED (1 << 0)
128 #define ASSIGNED_DEVICE_MSIX_ENABLED (1 << 1)
129 #define ASSIGNED_DEVICE_MSIX_MASKED (1 << 2)
132 uint8_t emulate_config_read
[PCI_CONFIG_SPACE_SIZE
];
133 uint8_t emulate_config_write
[PCI_CONFIG_SPACE_SIZE
];
136 MSIXTableEntry
*msix_table
;
137 hwaddr msix_table_addr
;
144 static void assigned_dev_update_irq_routing(PCIDevice
*dev
);
146 static void assigned_dev_load_option_rom(AssignedDevice
*dev
);
148 static void assigned_dev_unregister_msix_mmio(AssignedDevice
*dev
);
150 static uint64_t assigned_dev_ioport_rw(AssignedDevRegion
*dev_region
,
151 hwaddr addr
, int size
,
155 int fd
= dev_region
->region
->resource_fd
;
158 DEBUG("pwrite data=%" PRIx64
", size=%d, e_phys=" TARGET_FMT_plx
159 ", addr="TARGET_FMT_plx
"\n", *data
, size
, addr
, addr
);
160 if (pwrite(fd
, data
, size
, addr
) != size
) {
161 error_report("%s - pwrite failed %s", __func__
, strerror(errno
));
164 if (pread(fd
, &val
, size
, addr
) != size
) {
165 error_report("%s - pread failed %s", __func__
, strerror(errno
));
166 val
= (1UL << (size
* 8)) - 1;
168 DEBUG("pread val=%" PRIx64
", size=%d, e_phys=" TARGET_FMT_plx
169 ", addr=" TARGET_FMT_plx
"\n", val
, size
, addr
, addr
);
174 static void assigned_dev_ioport_write(void *opaque
, hwaddr addr
,
175 uint64_t data
, unsigned size
)
177 assigned_dev_ioport_rw(opaque
, addr
, size
, &data
);
180 static uint64_t assigned_dev_ioport_read(void *opaque
,
181 hwaddr addr
, unsigned size
)
183 return assigned_dev_ioport_rw(opaque
, addr
, size
, NULL
);
186 static uint32_t slow_bar_readb(void *opaque
, hwaddr addr
)
188 AssignedDevRegion
*d
= opaque
;
189 uint8_t *in
= d
->u
.r_virtbase
+ addr
;
193 DEBUG("addr=0x" TARGET_FMT_plx
" val=0x%08x\n", addr
, r
);
198 static uint32_t slow_bar_readw(void *opaque
, hwaddr addr
)
200 AssignedDevRegion
*d
= opaque
;
201 uint16_t *in
= (uint16_t *)(d
->u
.r_virtbase
+ addr
);
205 DEBUG("addr=0x" TARGET_FMT_plx
" val=0x%08x\n", addr
, r
);
210 static uint32_t slow_bar_readl(void *opaque
, hwaddr addr
)
212 AssignedDevRegion
*d
= opaque
;
213 uint32_t *in
= (uint32_t *)(d
->u
.r_virtbase
+ addr
);
217 DEBUG("addr=0x" TARGET_FMT_plx
" val=0x%08x\n", addr
, r
);
222 static void slow_bar_writeb(void *opaque
, hwaddr addr
, uint32_t val
)
224 AssignedDevRegion
*d
= opaque
;
225 uint8_t *out
= d
->u
.r_virtbase
+ addr
;
227 DEBUG("addr=0x" TARGET_FMT_plx
" val=0x%02x\n", addr
, val
);
231 static void slow_bar_writew(void *opaque
, hwaddr addr
, uint32_t val
)
233 AssignedDevRegion
*d
= opaque
;
234 uint16_t *out
= (uint16_t *)(d
->u
.r_virtbase
+ addr
);
236 DEBUG("addr=0x" TARGET_FMT_plx
" val=0x%04x\n", addr
, val
);
240 static void slow_bar_writel(void *opaque
, hwaddr addr
, uint32_t val
)
242 AssignedDevRegion
*d
= opaque
;
243 uint32_t *out
= (uint32_t *)(d
->u
.r_virtbase
+ addr
);
245 DEBUG("addr=0x" TARGET_FMT_plx
" val=0x%08x\n", addr
, val
);
249 static const MemoryRegionOps slow_bar_ops
= {
251 .read
= { slow_bar_readb
, slow_bar_readw
, slow_bar_readl
, },
252 .write
= { slow_bar_writeb
, slow_bar_writew
, slow_bar_writel
, },
254 .endianness
= DEVICE_NATIVE_ENDIAN
,
257 static void assigned_dev_iomem_setup(PCIDevice
*pci_dev
, int region_num
,
260 AssignedDevice
*r_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
261 AssignedDevRegion
*region
= &r_dev
->v_addrs
[region_num
];
262 PCIRegion
*real_region
= &r_dev
->real_device
.regions
[region_num
];
265 memory_region_init(®ion
->container
, OBJECT(pci_dev
),
266 "assigned-dev-container", e_size
);
267 memory_region_add_subregion(®ion
->container
, 0, ®ion
->real_iomem
);
269 /* deal with MSI-X MMIO page */
270 if (real_region
->base_addr
<= r_dev
->msix_table_addr
&&
271 real_region
->base_addr
+ real_region
->size
>
272 r_dev
->msix_table_addr
) {
273 uint64_t offset
= r_dev
->msix_table_addr
- real_region
->base_addr
;
275 memory_region_add_subregion_overlap(®ion
->container
,
283 static const MemoryRegionOps assigned_dev_ioport_ops
= {
284 .read
= assigned_dev_ioport_read
,
285 .write
= assigned_dev_ioport_write
,
286 .endianness
= DEVICE_NATIVE_ENDIAN
,
289 static void assigned_dev_ioport_setup(PCIDevice
*pci_dev
, int region_num
,
292 AssignedDevice
*r_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
293 AssignedDevRegion
*region
= &r_dev
->v_addrs
[region_num
];
295 region
->e_size
= size
;
296 memory_region_init(®ion
->container
, OBJECT(pci_dev
),
297 "assigned-dev-container", size
);
298 memory_region_init_io(®ion
->real_iomem
, OBJECT(pci_dev
),
299 &assigned_dev_ioport_ops
, r_dev
->v_addrs
+ region_num
,
300 "assigned-dev-iomem", size
);
301 memory_region_add_subregion(®ion
->container
, 0, ®ion
->real_iomem
);
304 static uint32_t assigned_dev_pci_read(PCIDevice
*d
, int pos
, int len
)
306 AssignedDevice
*pci_dev
= DO_UPCAST(AssignedDevice
, dev
, d
);
309 int fd
= pci_dev
->real_device
.config_fd
;
312 ret
= pread(fd
, &val
, len
, pos
);
314 if ((ret
< 0) && (errno
== EINTR
|| errno
== EAGAIN
)) {
318 hw_error("pci read failed, ret = %zd errno = %d\n", ret
, errno
);
324 static uint8_t assigned_dev_pci_read_byte(PCIDevice
*d
, int pos
)
326 return (uint8_t)assigned_dev_pci_read(d
, pos
, 1);
329 static void assigned_dev_pci_write(PCIDevice
*d
, int pos
, uint32_t val
, int len
)
331 AssignedDevice
*pci_dev
= DO_UPCAST(AssignedDevice
, dev
, d
);
333 int fd
= pci_dev
->real_device
.config_fd
;
336 ret
= pwrite(fd
, &val
, len
, pos
);
338 if ((ret
< 0) && (errno
== EINTR
|| errno
== EAGAIN
)) {
342 hw_error("pci write failed, ret = %zd errno = %d\n", ret
, errno
);
346 static void assigned_dev_emulate_config_read(AssignedDevice
*dev
,
347 uint32_t offset
, uint32_t len
)
349 memset(dev
->emulate_config_read
+ offset
, 0xff, len
);
352 static void assigned_dev_direct_config_read(AssignedDevice
*dev
,
353 uint32_t offset
, uint32_t len
)
355 memset(dev
->emulate_config_read
+ offset
, 0, len
);
358 static void assigned_dev_direct_config_write(AssignedDevice
*dev
,
359 uint32_t offset
, uint32_t len
)
361 memset(dev
->emulate_config_write
+ offset
, 0, len
);
364 static uint8_t pci_find_cap_offset(PCIDevice
*d
, uint8_t cap
, uint8_t start
)
368 int pos
= start
? start
: PCI_CAPABILITY_LIST
;
371 status
= assigned_dev_pci_read_byte(d
, PCI_STATUS
);
372 if ((status
& PCI_STATUS_CAP_LIST
) == 0) {
377 pos
= assigned_dev_pci_read_byte(d
, pos
);
383 id
= assigned_dev_pci_read_byte(d
, pos
+ PCI_CAP_LIST_ID
);
392 pos
+= PCI_CAP_LIST_NEXT
;
397 static void assigned_dev_register_regions(PCIRegion
*io_regions
,
398 unsigned long regions_num
,
399 AssignedDevice
*pci_dev
,
403 PCIRegion
*cur_region
= io_regions
;
405 for (i
= 0; i
< regions_num
; i
++, cur_region
++) {
406 if (!cur_region
->valid
) {
410 /* handle memory io regions */
411 if (cur_region
->type
& IORESOURCE_MEM
) {
412 int t
= PCI_BASE_ADDRESS_SPACE_MEMORY
;
413 if (cur_region
->type
& IORESOURCE_PREFETCH
) {
414 t
|= PCI_BASE_ADDRESS_MEM_PREFETCH
;
416 if (cur_region
->type
& IORESOURCE_MEM_64
) {
417 t
|= PCI_BASE_ADDRESS_MEM_TYPE_64
;
420 /* map physical memory */
421 pci_dev
->v_addrs
[i
].u
.r_virtbase
= mmap(NULL
, cur_region
->size
,
422 PROT_WRITE
| PROT_READ
,
424 cur_region
->resource_fd
,
427 if (pci_dev
->v_addrs
[i
].u
.r_virtbase
== MAP_FAILED
) {
428 pci_dev
->v_addrs
[i
].u
.r_virtbase
= NULL
;
429 error_setg_errno(errp
, errno
, "Couldn't mmap 0x%" PRIx64
"!",
430 cur_region
->base_addr
);
434 pci_dev
->v_addrs
[i
].r_size
= cur_region
->size
;
435 pci_dev
->v_addrs
[i
].e_size
= 0;
438 pci_dev
->v_addrs
[i
].u
.r_virtbase
+=
439 (cur_region
->base_addr
& 0xFFF);
441 if (cur_region
->size
& 0xFFF) {
442 error_report("PCI region %d at address 0x%" PRIx64
" has "
443 "size 0x%" PRIx64
", which is not a multiple of "
444 "4K. You might experience some performance hit "
446 i
, cur_region
->base_addr
, cur_region
->size
);
447 memory_region_init_io(&pci_dev
->v_addrs
[i
].real_iomem
,
448 OBJECT(pci_dev
), &slow_bar_ops
,
449 &pci_dev
->v_addrs
[i
],
450 "assigned-dev-slow-bar",
453 void *virtbase
= pci_dev
->v_addrs
[i
].u
.r_virtbase
;
455 snprintf(name
, sizeof(name
), "%s.bar%d",
456 object_get_typename(OBJECT(pci_dev
)), i
);
457 memory_region_init_ram_ptr(&pci_dev
->v_addrs
[i
].real_iomem
,
458 OBJECT(pci_dev
), name
,
459 cur_region
->size
, virtbase
);
460 vmstate_register_ram(&pci_dev
->v_addrs
[i
].real_iomem
,
464 assigned_dev_iomem_setup(&pci_dev
->dev
, i
, cur_region
->size
);
465 pci_register_bar((PCIDevice
*) pci_dev
, i
, t
,
466 &pci_dev
->v_addrs
[i
].container
);
469 /* handle port io regions */
473 /* Test kernel support for ioport resource read/write. Old
474 * kernels return EIO. New kernels only allow 1/2/4 byte reads
475 * so should return EINVAL for a 3 byte read */
476 ret
= pread(pci_dev
->v_addrs
[i
].region
->resource_fd
, &val
, 3, 0);
478 error_report("Unexpected return from I/O port read: %d", ret
);
480 } else if (errno
!= EINVAL
) {
481 error_report("Kernel doesn't support ioport resource "
482 "access, hiding this region.");
483 close(pci_dev
->v_addrs
[i
].region
->resource_fd
);
484 cur_region
->valid
= 0;
488 pci_dev
->v_addrs
[i
].u
.r_baseport
= cur_region
->base_addr
;
489 pci_dev
->v_addrs
[i
].r_size
= cur_region
->size
;
490 pci_dev
->v_addrs
[i
].e_size
= 0;
492 assigned_dev_ioport_setup(&pci_dev
->dev
, i
, cur_region
->size
);
493 pci_register_bar((PCIDevice
*) pci_dev
, i
,
494 PCI_BASE_ADDRESS_SPACE_IO
,
495 &pci_dev
->v_addrs
[i
].container
);
502 static void get_real_id(const char *devpath
, const char *idname
, uint16_t *val
,
509 snprintf(name
, sizeof(name
), "%s%s", devpath
, idname
);
510 f
= fopen(name
, "r");
512 error_setg_file_open(errp
, errno
, name
);
515 if (fscanf(f
, "%li\n", &id
) == 1) {
518 error_setg(errp
, "Failed to parse contents of '%s'", name
);
523 static void get_real_vendor_id(const char *devpath
, uint16_t *val
,
526 get_real_id(devpath
, "vendor", val
, errp
);
529 static void get_real_device_id(const char *devpath
, uint16_t *val
,
532 get_real_id(devpath
, "device", val
, errp
);
535 static void get_real_device(AssignedDevice
*pci_dev
, Error
**errp
)
537 char dir
[128], name
[128];
540 uint64_t start
, end
, size
, flags
;
543 PCIDevRegions
*dev
= &pci_dev
->real_device
;
544 Error
*local_err
= NULL
;
546 dev
->region_number
= 0;
548 snprintf(dir
, sizeof(dir
), "/sys/bus/pci/devices/%04x:%02x:%02x.%x/",
549 pci_dev
->host
.domain
, pci_dev
->host
.bus
,
550 pci_dev
->host
.slot
, pci_dev
->host
.function
);
552 snprintf(name
, sizeof(name
), "%sconfig", dir
);
554 if (pci_dev
->configfd_name
&& *pci_dev
->configfd_name
) {
555 dev
->config_fd
= monitor_handle_fd_param2(cur_mon
,
556 pci_dev
->configfd_name
,
559 error_propagate(errp
, local_err
);
563 dev
->config_fd
= open(name
, O_RDWR
);
565 if (dev
->config_fd
== -1) {
566 error_setg_file_open(errp
, errno
, name
);
571 r
= read(dev
->config_fd
, pci_dev
->dev
.config
,
572 pci_config_size(&pci_dev
->dev
));
574 if (errno
== EINTR
|| errno
== EAGAIN
) {
577 error_setg_errno(errp
, errno
, "read(\"%s\")",
578 (pci_dev
->configfd_name
&& *pci_dev
->configfd_name
) ?
579 pci_dev
->configfd_name
: name
);
583 /* Restore or clear multifunction, this is always controlled by qemu */
584 if (pci_dev
->dev
.cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
585 pci_dev
->dev
.config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
587 pci_dev
->dev
.config
[PCI_HEADER_TYPE
] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
590 /* Clear host resource mapping info. If we choose not to register a
591 * BAR, such as might be the case with the option ROM, we can get
592 * confusing, unwritable, residual addresses from the host here. */
593 memset(&pci_dev
->dev
.config
[PCI_BASE_ADDRESS_0
], 0, 24);
594 memset(&pci_dev
->dev
.config
[PCI_ROM_ADDRESS
], 0, 4);
596 snprintf(name
, sizeof(name
), "%sresource", dir
);
598 f
= fopen(name
, "r");
600 error_setg_file_open(errp
, errno
, name
);
604 for (r
= 0; r
< PCI_ROM_SLOT
; r
++) {
605 if (fscanf(f
, "%" SCNi64
" %" SCNi64
" %" SCNi64
"\n",
606 &start
, &end
, &flags
) != 3) {
610 rp
= dev
->regions
+ r
;
612 rp
->resource_fd
= -1;
613 size
= end
- start
+ 1;
614 flags
&= IORESOURCE_IO
| IORESOURCE_MEM
| IORESOURCE_PREFETCH
616 if (size
== 0 || (flags
& ~IORESOURCE_PREFETCH
) == 0) {
619 if (flags
& IORESOURCE_MEM
) {
620 flags
&= ~IORESOURCE_IO
;
622 flags
&= ~IORESOURCE_PREFETCH
;
624 snprintf(name
, sizeof(name
), "%sresource%d", dir
, r
);
625 fd
= open(name
, O_RDWR
);
629 rp
->resource_fd
= fd
;
633 rp
->base_addr
= start
;
635 pci_dev
->v_addrs
[r
].region
= rp
;
636 DEBUG("region %d size %" PRIu64
" start 0x%" PRIx64
637 " type %d resource_fd %d\n",
638 r
, rp
->size
, start
, rp
->type
, rp
->resource_fd
);
643 /* read and fill vendor ID */
644 get_real_vendor_id(dir
, &id
, &local_err
);
646 error_propagate(errp
, local_err
);
649 pci_dev
->dev
.config
[0] = id
& 0xff;
650 pci_dev
->dev
.config
[1] = (id
& 0xff00) >> 8;
652 /* read and fill device ID */
653 get_real_device_id(dir
, &id
, &local_err
);
655 error_propagate(errp
, local_err
);
658 pci_dev
->dev
.config
[2] = id
& 0xff;
659 pci_dev
->dev
.config
[3] = (id
& 0xff00) >> 8;
661 pci_word_test_and_clear_mask(pci_dev
->emulate_config_write
+ PCI_COMMAND
,
662 PCI_COMMAND_MASTER
| PCI_COMMAND_INTX_DISABLE
);
664 dev
->region_number
= r
;
667 static void free_msi_virqs(AssignedDevice
*dev
)
671 for (i
= 0; i
< dev
->msi_virq_nr
; i
++) {
672 if (dev
->msi_virq
[i
] >= 0) {
673 kvm_irqchip_release_virq(kvm_state
, dev
->msi_virq
[i
]);
674 dev
->msi_virq
[i
] = -1;
677 g_free(dev
->msi_virq
);
678 dev
->msi_virq
= NULL
;
679 dev
->msi_virq_nr
= 0;
682 static void free_assigned_device(AssignedDevice
*dev
)
686 if (dev
->cap
.available
& ASSIGNED_DEVICE_CAP_MSIX
) {
687 assigned_dev_unregister_msix_mmio(dev
);
689 for (i
= 0; i
< dev
->real_device
.region_number
; i
++) {
690 PCIRegion
*pci_region
= &dev
->real_device
.regions
[i
];
691 AssignedDevRegion
*region
= &dev
->v_addrs
[i
];
693 if (!pci_region
->valid
) {
696 if (pci_region
->type
& IORESOURCE_IO
) {
697 if (region
->u
.r_baseport
) {
698 memory_region_del_subregion(®ion
->container
,
699 ®ion
->real_iomem
);
701 } else if (pci_region
->type
& IORESOURCE_MEM
) {
702 if (region
->u
.r_virtbase
) {
703 memory_region_del_subregion(®ion
->container
,
704 ®ion
->real_iomem
);
706 /* Remove MSI-X table subregion */
707 if (pci_region
->base_addr
<= dev
->msix_table_addr
&&
708 pci_region
->base_addr
+ pci_region
->size
>
709 dev
->msix_table_addr
) {
710 memory_region_del_subregion(®ion
->container
,
713 if (munmap(region
->u
.r_virtbase
,
714 (pci_region
->size
+ 0xFFF) & 0xFFFFF000)) {
715 error_report("Failed to unmap assigned device region: %s",
720 if (pci_region
->resource_fd
>= 0) {
721 close(pci_region
->resource_fd
);
725 if (dev
->real_device
.config_fd
>= 0) {
726 close(dev
->real_device
.config_fd
);
732 /* This function tries to determine the cause of the PCI assignment failure. It
733 * always returns the cause as a dynamically allocated, human readable string.
734 * If the function fails to determine the cause for any internal reason, then
735 * the returned string will state that fact.
737 static char *assign_failed_examine(const AssignedDevice
*dev
)
739 char name
[PATH_MAX
], dir
[PATH_MAX
], driver
[PATH_MAX
] = {}, *ns
;
740 uint16_t vendor_id
, device_id
;
742 Error
*local_err
= NULL
;
744 snprintf(dir
, sizeof(dir
), "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/",
745 dev
->host
.domain
, dev
->host
.bus
, dev
->host
.slot
,
748 snprintf(name
, sizeof(name
), "%sdriver", dir
);
750 r
= readlink(name
, driver
, sizeof(driver
));
751 if ((r
<= 0) || r
>= sizeof(driver
)) {
756 ns
= strrchr(driver
, '/');
763 if ((get_real_vendor_id(dir
, &vendor_id
, &local_err
), local_err
) ||
764 (get_real_device_id(dir
, &device_id
, &local_err
), local_err
)) {
765 /* We're already analyzing an assignment error, so we suppress this
766 * one just like the others above.
768 error_free(local_err
);
772 return g_strdup_printf(
773 "*** The driver '%s' is occupying your device %04x:%02x:%02x.%x.\n"
775 "*** You can try the following commands to free it:\n"
777 "*** $ echo \"%04x %04x\" > /sys/bus/pci/drivers/pci-stub/new_id\n"
778 "*** $ echo \"%04x:%02x:%02x.%x\" > /sys/bus/pci/drivers/%s/unbind\n"
779 "*** $ echo \"%04x:%02x:%02x.%x\" > /sys/bus/pci/drivers/"
781 "*** $ echo \"%04x %04x\" > /sys/bus/pci/drivers/pci-stub/remove_id\n"
783 ns
, dev
->host
.domain
, dev
->host
.bus
, dev
->host
.slot
,
784 dev
->host
.function
, vendor_id
, device_id
,
785 dev
->host
.domain
, dev
->host
.bus
, dev
->host
.slot
, dev
->host
.function
,
786 ns
, dev
->host
.domain
, dev
->host
.bus
, dev
->host
.slot
,
787 dev
->host
.function
, vendor_id
, device_id
);
790 return g_strdup("Couldn't find out why.");
793 static void assign_device(AssignedDevice
*dev
, Error
**errp
)
795 uint32_t flags
= KVM_DEV_ASSIGN_ENABLE_IOMMU
;
798 /* Only pass non-zero PCI segment to capable module */
799 if (!kvm_check_extension(kvm_state
, KVM_CAP_PCI_SEGMENT
) &&
801 error_setg(errp
, "Can't assign device inside non-zero PCI segment "
802 "as this KVM module doesn't support it.");
806 if (!kvm_check_extension(kvm_state
, KVM_CAP_IOMMU
)) {
807 error_setg(errp
, "No IOMMU found. Unable to assign device \"%s\"",
812 if (dev
->features
& ASSIGNED_DEVICE_SHARE_INTX_MASK
&&
813 kvm_has_intx_set_mask()) {
814 flags
|= KVM_DEV_ASSIGN_PCI_2_3
;
817 r
= kvm_device_pci_assign(kvm_state
, &dev
->host
, flags
, &dev
->dev_id
);
823 cause
= assign_failed_examine(dev
);
824 error_setg_errno(errp
, -r
, "Failed to assign device \"%s\"\n%s",
825 dev
->dev
.qdev
.id
, cause
);
830 error_setg_errno(errp
, -r
, "Failed to assign device \"%s\"",
837 static void verify_irqchip_in_kernel(Error
**errp
)
839 if (kvm_irqchip_in_kernel()) {
842 error_setg(errp
, "pci-assign requires KVM with in-kernel irqchip enabled");
845 static int assign_intx(AssignedDevice
*dev
, Error
**errp
)
847 AssignedIRQType new_type
;
848 PCIINTxRoute intx_route
;
851 Error
*local_err
= NULL
;
853 /* Interrupt PIN 0 means don't use INTx */
854 if (assigned_dev_pci_read_byte(&dev
->dev
, PCI_INTERRUPT_PIN
) == 0) {
855 pci_device_set_intx_routing_notifier(&dev
->dev
, NULL
);
859 verify_irqchip_in_kernel(&local_err
);
861 error_propagate(errp
, local_err
);
865 pci_device_set_intx_routing_notifier(&dev
->dev
,
866 assigned_dev_update_irq_routing
);
868 intx_route
= pci_device_route_intx_to_irq(&dev
->dev
, dev
->intpin
);
869 assert(intx_route
.mode
!= PCI_INTX_INVERTED
);
871 if (!pci_intx_route_changed(&dev
->intx_route
, &intx_route
)) {
875 switch (dev
->assigned_irq_type
) {
876 case ASSIGNED_IRQ_INTX_HOST_INTX
:
877 case ASSIGNED_IRQ_INTX_HOST_MSI
:
878 intx_host_msi
= dev
->assigned_irq_type
== ASSIGNED_IRQ_INTX_HOST_MSI
;
879 r
= kvm_device_intx_deassign(kvm_state
, dev
->dev_id
, intx_host_msi
);
881 case ASSIGNED_IRQ_MSI
:
882 r
= kvm_device_msi_deassign(kvm_state
, dev
->dev_id
);
884 case ASSIGNED_IRQ_MSIX
:
885 r
= kvm_device_msix_deassign(kvm_state
, dev
->dev_id
);
892 perror("assign_intx: deassignment of previous interrupt failed");
894 dev
->assigned_irq_type
= ASSIGNED_IRQ_NONE
;
896 if (intx_route
.mode
== PCI_INTX_DISABLED
) {
897 dev
->intx_route
= intx_route
;
902 if (dev
->features
& ASSIGNED_DEVICE_PREFER_MSI_MASK
&&
903 dev
->cap
.available
& ASSIGNED_DEVICE_CAP_MSI
) {
904 intx_host_msi
= true;
905 new_type
= ASSIGNED_IRQ_INTX_HOST_MSI
;
907 intx_host_msi
= false;
908 new_type
= ASSIGNED_IRQ_INTX_HOST_INTX
;
911 r
= kvm_device_intx_assign(kvm_state
, dev
->dev_id
, intx_host_msi
,
914 if (r
== -EIO
&& !(dev
->features
& ASSIGNED_DEVICE_PREFER_MSI_MASK
) &&
915 dev
->cap
.available
& ASSIGNED_DEVICE_CAP_MSI
) {
916 /* Retry with host-side MSI. There might be an IRQ conflict and
917 * either the kernel or the device doesn't support sharing. */
918 error_report("Host-side INTx sharing not supported, "
919 "using MSI instead");
920 error_printf("Some devices do not work properly in this mode.\n");
921 dev
->features
|= ASSIGNED_DEVICE_PREFER_MSI_MASK
;
924 error_setg_errno(errp
, -r
,
925 "Failed to assign irq for \"%s\"\n"
926 "Perhaps you are assigning a device "
927 "that shares an IRQ with another device?",
932 dev
->intx_route
= intx_route
;
933 dev
->assigned_irq_type
= new_type
;
937 static void deassign_device(AssignedDevice
*dev
)
941 r
= kvm_device_pci_deassign(kvm_state
, dev
->dev_id
);
945 /* The pci config space got updated. Check if irq numbers have changed
948 static void assigned_dev_update_irq_routing(PCIDevice
*dev
)
950 AssignedDevice
*assigned_dev
= DO_UPCAST(AssignedDevice
, dev
, dev
);
954 r
= assign_intx(assigned_dev
, &err
);
956 error_report("%s", error_get_pretty(err
));
959 qdev_unplug(&dev
->qdev
, &err
);
964 static void assigned_dev_update_msi(PCIDevice
*pci_dev
)
966 AssignedDevice
*assigned_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
967 uint8_t ctrl_byte
= pci_get_byte(pci_dev
->config
+ pci_dev
->msi_cap
+
971 /* Some guests gratuitously disable MSI even if they're not using it,
972 * try to catch this by only deassigning irqs if the guest is using
973 * MSI or intends to start. */
974 if (assigned_dev
->assigned_irq_type
== ASSIGNED_IRQ_MSI
||
975 (ctrl_byte
& PCI_MSI_FLAGS_ENABLE
)) {
976 r
= kvm_device_msi_deassign(kvm_state
, assigned_dev
->dev_id
);
977 /* -ENXIO means no assigned irq */
978 if (r
&& r
!= -ENXIO
) {
979 perror("assigned_dev_update_msi: deassign irq");
982 free_msi_virqs(assigned_dev
);
984 assigned_dev
->assigned_irq_type
= ASSIGNED_IRQ_NONE
;
985 pci_device_set_intx_routing_notifier(pci_dev
, NULL
);
988 if (ctrl_byte
& PCI_MSI_FLAGS_ENABLE
) {
989 MSIMessage msg
= msi_get_message(pci_dev
, 0);
992 virq
= kvm_irqchip_add_msi_route(kvm_state
, msg
);
994 perror("assigned_dev_update_msi: kvm_irqchip_add_msi_route");
998 assigned_dev
->msi_virq
= g_malloc(sizeof(*assigned_dev
->msi_virq
));
999 assigned_dev
->msi_virq_nr
= 1;
1000 assigned_dev
->msi_virq
[0] = virq
;
1001 if (kvm_device_msi_assign(kvm_state
, assigned_dev
->dev_id
, virq
) < 0) {
1002 perror("assigned_dev_update_msi: kvm_device_msi_assign");
1005 assigned_dev
->intx_route
.mode
= PCI_INTX_DISABLED
;
1006 assigned_dev
->intx_route
.irq
= -1;
1007 assigned_dev
->assigned_irq_type
= ASSIGNED_IRQ_MSI
;
1009 Error
*local_err
= NULL
;
1011 assign_intx(assigned_dev
, &local_err
);
1013 error_report("%s", error_get_pretty(local_err
));
1014 error_free(local_err
);
1019 static void assigned_dev_update_msi_msg(PCIDevice
*pci_dev
)
1021 AssignedDevice
*assigned_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1022 uint8_t ctrl_byte
= pci_get_byte(pci_dev
->config
+ pci_dev
->msi_cap
+
1025 if (assigned_dev
->assigned_irq_type
!= ASSIGNED_IRQ_MSI
||
1026 !(ctrl_byte
& PCI_MSI_FLAGS_ENABLE
)) {
1030 kvm_irqchip_update_msi_route(kvm_state
, assigned_dev
->msi_virq
[0],
1031 msi_get_message(pci_dev
, 0));
1034 static bool assigned_dev_msix_masked(MSIXTableEntry
*entry
)
1036 return (entry
->ctrl
& cpu_to_le32(0x1)) != 0;
1040 * When MSI-X is first enabled the vector table typically has all the
1041 * vectors masked, so we can't use that as the obvious test to figure out
1042 * how many vectors to initially enable. Instead we look at the data field
1043 * because this is what worked for pci-assign for a long time. This makes
1044 * sure the physical MSI-X state tracks the guest's view, which is important
1045 * for some VF/PF and PF/fw communication channels.
1047 static bool assigned_dev_msix_skipped(MSIXTableEntry
*entry
)
1049 return !entry
->data
;
1052 static int assigned_dev_update_msix_mmio(PCIDevice
*pci_dev
)
1054 AssignedDevice
*adev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1055 uint16_t entries_nr
= 0;
1057 MSIXTableEntry
*entry
= adev
->msix_table
;
1060 /* Get the usable entry number for allocating */
1061 for (i
= 0; i
< adev
->msix_max
; i
++, entry
++) {
1062 if (assigned_dev_msix_skipped(entry
)) {
1068 DEBUG("MSI-X entries: %d\n", entries_nr
);
1070 /* It's valid to enable MSI-X with all entries masked */
1075 r
= kvm_device_msix_init_vectors(kvm_state
, adev
->dev_id
, entries_nr
);
1077 error_report("fail to set MSI-X entry number for MSIX! %s",
1082 free_msi_virqs(adev
);
1084 adev
->msi_virq_nr
= adev
->msix_max
;
1085 adev
->msi_virq
= g_malloc(adev
->msix_max
* sizeof(*adev
->msi_virq
));
1087 entry
= adev
->msix_table
;
1088 for (i
= 0; i
< adev
->msix_max
; i
++, entry
++) {
1089 adev
->msi_virq
[i
] = -1;
1091 if (assigned_dev_msix_skipped(entry
)) {
1095 msg
.address
= entry
->addr_lo
| ((uint64_t)entry
->addr_hi
<< 32);
1096 msg
.data
= entry
->data
;
1097 r
= kvm_irqchip_add_msi_route(kvm_state
, msg
);
1101 adev
->msi_virq
[i
] = r
;
1103 DEBUG("MSI-X vector %d, gsi %d, addr %08x_%08x, data %08x\n", i
,
1104 r
, entry
->addr_hi
, entry
->addr_lo
, entry
->data
);
1106 r
= kvm_device_msix_set_vector(kvm_state
, adev
->dev_id
, i
,
1109 error_report("fail to set MSI-X entry! %s", strerror(-r
));
1117 static void assigned_dev_update_msix(PCIDevice
*pci_dev
)
1119 AssignedDevice
*assigned_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1120 uint16_t ctrl_word
= pci_get_word(pci_dev
->config
+ pci_dev
->msix_cap
+
1124 /* Some guests gratuitously disable MSIX even if they're not using it,
1125 * try to catch this by only deassigning irqs if the guest is using
1126 * MSIX or intends to start. */
1127 if ((assigned_dev
->assigned_irq_type
== ASSIGNED_IRQ_MSIX
) ||
1128 (ctrl_word
& PCI_MSIX_FLAGS_ENABLE
)) {
1129 r
= kvm_device_msix_deassign(kvm_state
, assigned_dev
->dev_id
);
1130 /* -ENXIO means no assigned irq */
1131 if (r
&& r
!= -ENXIO
) {
1132 perror("assigned_dev_update_msix: deassign irq");
1135 free_msi_virqs(assigned_dev
);
1137 assigned_dev
->assigned_irq_type
= ASSIGNED_IRQ_NONE
;
1138 pci_device_set_intx_routing_notifier(pci_dev
, NULL
);
1141 if (ctrl_word
& PCI_MSIX_FLAGS_ENABLE
) {
1142 if (assigned_dev_update_msix_mmio(pci_dev
) < 0) {
1143 perror("assigned_dev_update_msix_mmio");
1147 if (assigned_dev
->msi_virq_nr
> 0) {
1148 if (kvm_device_msix_assign(kvm_state
, assigned_dev
->dev_id
) < 0) {
1149 perror("assigned_dev_enable_msix: assign irq");
1153 assigned_dev
->intx_route
.mode
= PCI_INTX_DISABLED
;
1154 assigned_dev
->intx_route
.irq
= -1;
1155 assigned_dev
->assigned_irq_type
= ASSIGNED_IRQ_MSIX
;
1157 Error
*local_err
= NULL
;
1159 assign_intx(assigned_dev
, &local_err
);
1161 error_report("%s", error_get_pretty(local_err
));
1162 error_free(local_err
);
1167 static uint32_t assigned_dev_pci_read_config(PCIDevice
*pci_dev
,
1168 uint32_t address
, int len
)
1170 AssignedDevice
*assigned_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1171 uint32_t virt_val
= pci_default_read_config(pci_dev
, address
, len
);
1172 uint32_t real_val
, emulate_mask
, full_emulation_mask
;
1175 memcpy(&emulate_mask
, assigned_dev
->emulate_config_read
+ address
, len
);
1176 emulate_mask
= le32_to_cpu(emulate_mask
);
1178 full_emulation_mask
= 0xffffffff >> (32 - len
* 8);
1180 if (emulate_mask
!= full_emulation_mask
) {
1181 real_val
= assigned_dev_pci_read(pci_dev
, address
, len
);
1182 return (virt_val
& emulate_mask
) | (real_val
& ~emulate_mask
);
1188 static void assigned_dev_pci_write_config(PCIDevice
*pci_dev
, uint32_t address
,
1189 uint32_t val
, int len
)
1191 AssignedDevice
*assigned_dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1192 uint16_t old_cmd
= pci_get_word(pci_dev
->config
+ PCI_COMMAND
);
1193 uint32_t emulate_mask
, full_emulation_mask
;
1196 pci_default_write_config(pci_dev
, address
, val
, len
);
1198 if (kvm_has_intx_set_mask() &&
1199 range_covers_byte(address
, len
, PCI_COMMAND
+ 1)) {
1200 bool intx_masked
= (pci_get_word(pci_dev
->config
+ PCI_COMMAND
) &
1201 PCI_COMMAND_INTX_DISABLE
);
1203 if (intx_masked
!= !!(old_cmd
& PCI_COMMAND_INTX_DISABLE
)) {
1204 ret
= kvm_device_intx_set_mask(kvm_state
, assigned_dev
->dev_id
,
1207 perror("assigned_dev_pci_write_config: set intx mask");
1211 if (assigned_dev
->cap
.available
& ASSIGNED_DEVICE_CAP_MSI
) {
1212 if (range_covers_byte(address
, len
,
1213 pci_dev
->msi_cap
+ PCI_MSI_FLAGS
)) {
1214 assigned_dev_update_msi(pci_dev
);
1215 } else if (ranges_overlap(address
, len
, /* 32bit MSI only */
1216 pci_dev
->msi_cap
+ PCI_MSI_ADDRESS_LO
, 6)) {
1217 assigned_dev_update_msi_msg(pci_dev
);
1220 if (assigned_dev
->cap
.available
& ASSIGNED_DEVICE_CAP_MSIX
) {
1221 if (range_covers_byte(address
, len
,
1222 pci_dev
->msix_cap
+ PCI_MSIX_FLAGS
+ 1)) {
1223 assigned_dev_update_msix(pci_dev
);
1228 memcpy(&emulate_mask
, assigned_dev
->emulate_config_write
+ address
, len
);
1229 emulate_mask
= le32_to_cpu(emulate_mask
);
1231 full_emulation_mask
= 0xffffffff >> (32 - len
* 8);
1233 if (emulate_mask
!= full_emulation_mask
) {
1235 val
&= ~emulate_mask
;
1236 val
|= assigned_dev_pci_read(pci_dev
, address
, len
) & emulate_mask
;
1238 assigned_dev_pci_write(pci_dev
, address
, val
, len
);
1242 static void assigned_dev_setup_cap_read(AssignedDevice
*dev
, uint32_t offset
,
1245 assigned_dev_direct_config_read(dev
, offset
, len
);
1246 assigned_dev_emulate_config_read(dev
, offset
+ PCI_CAP_LIST_NEXT
, 1);
1249 static int assigned_device_pci_cap_init(PCIDevice
*pci_dev
, Error
**errp
)
1251 AssignedDevice
*dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1252 PCIRegion
*pci_region
= dev
->real_device
.regions
;
1254 Error
*local_err
= NULL
;
1256 /* Clear initial capabilities pointer and status copied from hw */
1257 pci_set_byte(pci_dev
->config
+ PCI_CAPABILITY_LIST
, 0);
1258 pci_set_word(pci_dev
->config
+ PCI_STATUS
,
1259 pci_get_word(pci_dev
->config
+ PCI_STATUS
) &
1260 ~PCI_STATUS_CAP_LIST
);
1262 /* Expose MSI capability
1263 * MSI capability is the 1st capability in capability config */
1264 pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_MSI
, 0);
1265 if (pos
!= 0 && kvm_check_extension(kvm_state
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
1266 verify_irqchip_in_kernel(&local_err
);
1268 error_propagate(errp
, local_err
);
1271 dev
->cap
.available
|= ASSIGNED_DEVICE_CAP_MSI
;
1272 /* Only 32-bit/no-mask currently supported */
1273 ret
= pci_add_capability2(pci_dev
, PCI_CAP_ID_MSI
, pos
, 10,
1276 error_propagate(errp
, local_err
);
1279 pci_dev
->msi_cap
= pos
;
1281 pci_set_word(pci_dev
->config
+ pos
+ PCI_MSI_FLAGS
,
1282 pci_get_word(pci_dev
->config
+ pos
+ PCI_MSI_FLAGS
) &
1283 PCI_MSI_FLAGS_QMASK
);
1284 pci_set_long(pci_dev
->config
+ pos
+ PCI_MSI_ADDRESS_LO
, 0);
1285 pci_set_word(pci_dev
->config
+ pos
+ PCI_MSI_DATA_32
, 0);
1287 /* Set writable fields */
1288 pci_set_word(pci_dev
->wmask
+ pos
+ PCI_MSI_FLAGS
,
1289 PCI_MSI_FLAGS_QSIZE
| PCI_MSI_FLAGS_ENABLE
);
1290 pci_set_long(pci_dev
->wmask
+ pos
+ PCI_MSI_ADDRESS_LO
, 0xfffffffc);
1291 pci_set_word(pci_dev
->wmask
+ pos
+ PCI_MSI_DATA_32
, 0xffff);
1293 /* Expose MSI-X capability */
1294 pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_MSIX
, 0);
1295 if (pos
!= 0 && kvm_device_msix_supported(kvm_state
)) {
1297 uint32_t msix_table_entry
;
1300 verify_irqchip_in_kernel(&local_err
);
1302 error_propagate(errp
, local_err
);
1305 dev
->cap
.available
|= ASSIGNED_DEVICE_CAP_MSIX
;
1306 ret
= pci_add_capability2(pci_dev
, PCI_CAP_ID_MSIX
, pos
, 12,
1309 error_propagate(errp
, local_err
);
1312 pci_dev
->msix_cap
= pos
;
1314 msix_max
= (pci_get_word(pci_dev
->config
+ pos
+ PCI_MSIX_FLAGS
) &
1315 PCI_MSIX_FLAGS_QSIZE
) + 1;
1316 msix_max
= MIN(msix_max
, KVM_MAX_MSIX_PER_DEV
);
1317 pci_set_word(pci_dev
->config
+ pos
+ PCI_MSIX_FLAGS
, msix_max
- 1);
1319 /* Only enable and function mask bits are writable */
1320 pci_set_word(pci_dev
->wmask
+ pos
+ PCI_MSIX_FLAGS
,
1321 PCI_MSIX_FLAGS_ENABLE
| PCI_MSIX_FLAGS_MASKALL
);
1323 msix_table_entry
= pci_get_long(pci_dev
->config
+ pos
+ PCI_MSIX_TABLE
);
1324 bar_nr
= msix_table_entry
& PCI_MSIX_FLAGS_BIRMASK
;
1325 msix_table_entry
&= ~PCI_MSIX_FLAGS_BIRMASK
;
1326 dev
->msix_table_addr
= pci_region
[bar_nr
].base_addr
+ msix_table_entry
;
1327 dev
->msix_max
= msix_max
;
1330 /* Minimal PM support, nothing writable, device appears to NAK changes */
1331 pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_PM
, 0);
1335 ret
= pci_add_capability2(pci_dev
, PCI_CAP_ID_PM
, pos
, PCI_PM_SIZEOF
,
1338 error_propagate(errp
, local_err
);
1342 assigned_dev_setup_cap_read(dev
, pos
, PCI_PM_SIZEOF
);
1344 pmc
= pci_get_word(pci_dev
->config
+ pos
+ PCI_CAP_FLAGS
);
1345 pmc
&= (PCI_PM_CAP_VER_MASK
| PCI_PM_CAP_DSI
);
1346 pci_set_word(pci_dev
->config
+ pos
+ PCI_CAP_FLAGS
, pmc
);
1348 /* assign_device will bring the device up to D0, so we don't need
1349 * to worry about doing that ourselves here. */
1350 pci_set_word(pci_dev
->config
+ pos
+ PCI_PM_CTRL
,
1351 PCI_PM_CTRL_NO_SOFT_RESET
);
1353 pci_set_byte(pci_dev
->config
+ pos
+ PCI_PM_PPB_EXTENSIONS
, 0);
1354 pci_set_byte(pci_dev
->config
+ pos
+ PCI_PM_DATA_REGISTER
, 0);
1357 pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_EXP
, 0);
1359 uint8_t version
, size
= 0;
1360 uint16_t type
, devctl
, lnksta
;
1361 uint32_t devcap
, lnkcap
;
1363 version
= pci_get_byte(pci_dev
->config
+ pos
+ PCI_EXP_FLAGS
);
1364 version
&= PCI_EXP_FLAGS_VERS
;
1367 } else if (version
== 2) {
1369 * Check for non-std size, accept reduced size to 0x34,
1370 * which is what bcm5761 implemented, violating the
1371 * PCIe v3.0 spec that regs should exist and be read as 0,
1372 * not optionally provided and shorten the struct size.
1374 size
= MIN(0x3c, PCI_CONFIG_SPACE_SIZE
- pos
);
1376 error_setg(errp
, "Invalid size PCIe cap-id 0x%x",
1379 } else if (size
!= 0x3c) {
1380 error_report("WARNING, %s: PCIe cap-id 0x%x has "
1381 "non-standard size 0x%x; std size should be 0x3c",
1382 __func__
, PCI_CAP_ID_EXP
, size
);
1384 } else if (version
== 0) {
1386 vid
= pci_get_word(pci_dev
->config
+ PCI_VENDOR_ID
);
1387 did
= pci_get_word(pci_dev
->config
+ PCI_DEVICE_ID
);
1388 if (vid
== PCI_VENDOR_ID_INTEL
&& did
== 0x10ed) {
1390 * quirk for Intel 82599 VF with invalid PCIe capability
1391 * version, should really be version 2 (same as PF)
1398 error_setg(errp
, "Unsupported PCI express capability version %d",
1403 ret
= pci_add_capability2(pci_dev
, PCI_CAP_ID_EXP
, pos
, size
,
1406 error_propagate(errp
, local_err
);
1410 assigned_dev_setup_cap_read(dev
, pos
, size
);
1412 type
= pci_get_word(pci_dev
->config
+ pos
+ PCI_EXP_FLAGS
);
1413 type
= (type
& PCI_EXP_FLAGS_TYPE
) >> 4;
1414 if (type
!= PCI_EXP_TYPE_ENDPOINT
&&
1415 type
!= PCI_EXP_TYPE_LEG_END
&& type
!= PCI_EXP_TYPE_RC_END
) {
1416 error_setg(errp
, "Device assignment only supports endpoint "
1417 "assignment, device type %d", type
);
1421 /* capabilities, pass existing read-only copy
1422 * PCI_EXP_FLAGS_IRQ: updated by hardware, should be direct read */
1424 /* device capabilities: hide FLR */
1425 devcap
= pci_get_long(pci_dev
->config
+ pos
+ PCI_EXP_DEVCAP
);
1426 devcap
&= ~PCI_EXP_DEVCAP_FLR
;
1427 pci_set_long(pci_dev
->config
+ pos
+ PCI_EXP_DEVCAP
, devcap
);
1429 /* device control: clear all error reporting enable bits, leaving
1430 * only a few host values. Note, these are
1431 * all writable, but not passed to hw.
1433 devctl
= pci_get_word(pci_dev
->config
+ pos
+ PCI_EXP_DEVCTL
);
1434 devctl
= (devctl
& (PCI_EXP_DEVCTL_READRQ
| PCI_EXP_DEVCTL_PAYLOAD
)) |
1435 PCI_EXP_DEVCTL_RELAX_EN
| PCI_EXP_DEVCTL_NOSNOOP_EN
;
1436 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_DEVCTL
, devctl
);
1437 devctl
= PCI_EXP_DEVCTL_BCR_FLR
| PCI_EXP_DEVCTL_AUX_PME
;
1438 pci_set_word(pci_dev
->wmask
+ pos
+ PCI_EXP_DEVCTL
, ~devctl
);
1440 /* Clear device status */
1441 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_DEVSTA
, 0);
1443 /* Link capabilities, expose links and latencues, clear reporting */
1444 lnkcap
= pci_get_long(pci_dev
->config
+ pos
+ PCI_EXP_LNKCAP
);
1445 lnkcap
&= (PCI_EXP_LNKCAP_SLS
| PCI_EXP_LNKCAP_MLW
|
1446 PCI_EXP_LNKCAP_ASPMS
| PCI_EXP_LNKCAP_L0SEL
|
1447 PCI_EXP_LNKCAP_L1EL
);
1448 pci_set_long(pci_dev
->config
+ pos
+ PCI_EXP_LNKCAP
, lnkcap
);
1450 /* Link control, pass existing read-only copy. Should be writable? */
1452 /* Link status, only expose current speed and width */
1453 lnksta
= pci_get_word(pci_dev
->config
+ pos
+ PCI_EXP_LNKSTA
);
1454 lnksta
&= (PCI_EXP_LNKSTA_CLS
| PCI_EXP_LNKSTA_NLW
);
1455 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_LNKSTA
, lnksta
);
1458 /* Slot capabilities, control, status - not needed for endpoints */
1459 pci_set_long(pci_dev
->config
+ pos
+ PCI_EXP_SLTCAP
, 0);
1460 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_SLTCTL
, 0);
1461 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_SLTSTA
, 0);
1463 /* Root control, capabilities, status - not needed for endpoints */
1464 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_RTCTL
, 0);
1465 pci_set_word(pci_dev
->config
+ pos
+ PCI_EXP_RTCAP
, 0);
1466 pci_set_long(pci_dev
->config
+ pos
+ PCI_EXP_RTSTA
, 0);
1468 /* Device capabilities/control 2, pass existing read-only copy */
1469 /* Link control 2, pass existing read-only copy */
1473 pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_PCIX
, 0);
1478 /* Only expose the minimum, 8 byte capability */
1479 ret
= pci_add_capability2(pci_dev
, PCI_CAP_ID_PCIX
, pos
, 8,
1482 error_propagate(errp
, local_err
);
1486 assigned_dev_setup_cap_read(dev
, pos
, 8);
1488 /* Command register, clear upper bits, including extended modes */
1489 cmd
= pci_get_word(pci_dev
->config
+ pos
+ PCI_X_CMD
);
1490 cmd
&= (PCI_X_CMD_DPERR_E
| PCI_X_CMD_ERO
| PCI_X_CMD_MAX_READ
|
1491 PCI_X_CMD_MAX_SPLIT
);
1492 pci_set_word(pci_dev
->config
+ pos
+ PCI_X_CMD
, cmd
);
1494 /* Status register, update with emulated PCI bus location, clear
1495 * error bits, leave the rest. */
1496 status
= pci_get_long(pci_dev
->config
+ pos
+ PCI_X_STATUS
);
1497 status
&= ~(PCI_X_STATUS_BUS
| PCI_X_STATUS_DEVFN
);
1498 status
|= (pci_bus_num(pci_dev
->bus
) << 8) | pci_dev
->devfn
;
1499 status
&= ~(PCI_X_STATUS_SPL_DISC
| PCI_X_STATUS_UNX_SPL
|
1500 PCI_X_STATUS_SPL_ERR
);
1501 pci_set_long(pci_dev
->config
+ pos
+ PCI_X_STATUS
, status
);
1504 pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_VPD
, 0);
1506 /* Direct R/W passthrough */
1507 ret
= pci_add_capability2(pci_dev
, PCI_CAP_ID_VPD
, pos
, 8,
1510 error_propagate(errp
, local_err
);
1514 assigned_dev_setup_cap_read(dev
, pos
, 8);
1516 /* direct write for cap content */
1517 assigned_dev_direct_config_write(dev
, pos
+ 2, 6);
1520 /* Devices can have multiple vendor capabilities, get them all */
1521 for (pos
= 0; (pos
= pci_find_cap_offset(pci_dev
, PCI_CAP_ID_VNDR
, pos
));
1522 pos
+= PCI_CAP_LIST_NEXT
) {
1523 uint8_t len
= pci_get_byte(pci_dev
->config
+ pos
+ PCI_CAP_FLAGS
);
1524 /* Direct R/W passthrough */
1525 ret
= pci_add_capability2(pci_dev
, PCI_CAP_ID_VNDR
, pos
, len
,
1528 error_propagate(errp
, local_err
);
1532 assigned_dev_setup_cap_read(dev
, pos
, len
);
1534 /* direct write for cap content */
1535 assigned_dev_direct_config_write(dev
, pos
+ 2, len
- 2);
1538 /* If real and virtual capability list status bits differ, virtualize the
1540 if ((pci_get_word(pci_dev
->config
+ PCI_STATUS
) & PCI_STATUS_CAP_LIST
) !=
1541 (assigned_dev_pci_read_byte(pci_dev
, PCI_STATUS
) &
1542 PCI_STATUS_CAP_LIST
)) {
1543 dev
->emulate_config_read
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
1550 assigned_dev_msix_mmio_read(void *opaque
, hwaddr addr
,
1553 AssignedDevice
*adev
= opaque
;
1556 memcpy(&val
, (void *)((uint8_t *)adev
->msix_table
+ addr
), size
);
1561 static void assigned_dev_msix_mmio_write(void *opaque
, hwaddr addr
,
1562 uint64_t val
, unsigned size
)
1564 AssignedDevice
*adev
= opaque
;
1565 PCIDevice
*pdev
= &adev
->dev
;
1567 MSIXTableEntry orig
;
1570 if (i
>= adev
->msix_max
) {
1571 return; /* Drop write */
1574 ctrl
= pci_get_word(pdev
->config
+ pdev
->msix_cap
+ PCI_MSIX_FLAGS
);
1576 DEBUG("write to MSI-X table offset 0x%lx, val 0x%lx\n", addr
, val
);
1578 if (ctrl
& PCI_MSIX_FLAGS_ENABLE
) {
1579 orig
= adev
->msix_table
[i
];
1582 memcpy((uint8_t *)adev
->msix_table
+ addr
, &val
, size
);
1584 if (ctrl
& PCI_MSIX_FLAGS_ENABLE
) {
1585 MSIXTableEntry
*entry
= &adev
->msix_table
[i
];
1587 if (!assigned_dev_msix_masked(&orig
) &&
1588 assigned_dev_msix_masked(entry
)) {
1590 * Vector masked, disable it
1592 * XXX It's not clear if we can or should actually attempt
1593 * to mask or disable the interrupt. KVM doesn't have
1594 * support for pending bits and kvm_assign_set_msix_entry
1595 * doesn't modify the device hardware mask. Interrupts
1596 * while masked are simply not injected to the guest, so
1597 * are lost. Can we get away with always injecting an
1598 * interrupt on unmask?
1600 } else if (assigned_dev_msix_masked(&orig
) &&
1601 !assigned_dev_msix_masked(entry
)) {
1602 /* Vector unmasked */
1603 if (i
>= adev
->msi_virq_nr
|| adev
->msi_virq
[i
] < 0) {
1604 /* Previously unassigned vector, start from scratch */
1605 assigned_dev_update_msix(pdev
);
1608 /* Update an existing, previously masked vector */
1612 msg
.address
= entry
->addr_lo
|
1613 ((uint64_t)entry
->addr_hi
<< 32);
1614 msg
.data
= entry
->data
;
1616 ret
= kvm_irqchip_update_msi_route(kvm_state
,
1617 adev
->msi_virq
[i
], msg
);
1619 error_report("Error updating irq routing entry (%d)", ret
);
1626 static const MemoryRegionOps assigned_dev_msix_mmio_ops
= {
1627 .read
= assigned_dev_msix_mmio_read
,
1628 .write
= assigned_dev_msix_mmio_write
,
1629 .endianness
= DEVICE_NATIVE_ENDIAN
,
1631 .min_access_size
= 4,
1632 .max_access_size
= 8,
1635 .min_access_size
= 4,
1636 .max_access_size
= 8,
1640 static void assigned_dev_msix_reset(AssignedDevice
*dev
)
1642 MSIXTableEntry
*entry
;
1645 if (!dev
->msix_table
) {
1649 memset(dev
->msix_table
, 0, MSIX_PAGE_SIZE
);
1651 for (i
= 0, entry
= dev
->msix_table
; i
< dev
->msix_max
; i
++, entry
++) {
1652 entry
->ctrl
= cpu_to_le32(0x1); /* Masked */
1656 static void assigned_dev_register_msix_mmio(AssignedDevice
*dev
, Error
**errp
)
1658 dev
->msix_table
= mmap(NULL
, MSIX_PAGE_SIZE
, PROT_READ
|PROT_WRITE
,
1659 MAP_ANONYMOUS
|MAP_PRIVATE
, 0, 0);
1660 if (dev
->msix_table
== MAP_FAILED
) {
1661 error_setg_errno(errp
, errno
, "failed to allocate msix_table");
1662 dev
->msix_table
= NULL
;
1666 assigned_dev_msix_reset(dev
);
1668 memory_region_init_io(&dev
->mmio
, OBJECT(dev
), &assigned_dev_msix_mmio_ops
,
1669 dev
, "assigned-dev-msix", MSIX_PAGE_SIZE
);
1672 static void assigned_dev_unregister_msix_mmio(AssignedDevice
*dev
)
1674 if (!dev
->msix_table
) {
1678 if (munmap(dev
->msix_table
, MSIX_PAGE_SIZE
) == -1) {
1679 error_report("error unmapping msix_table! %s", strerror(errno
));
1681 dev
->msix_table
= NULL
;
1684 static const VMStateDescription vmstate_assigned_device
= {
1685 .name
= "pci-assign",
1689 static void reset_assigned_device(DeviceState
*dev
)
1691 PCIDevice
*pci_dev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
1692 AssignedDevice
*adev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1693 char reset_file
[64];
1694 const char reset
[] = "1";
1698 * If a guest is reset without being shutdown, MSI/MSI-X can still
1699 * be running. We want to return the device to a known state on
1700 * reset, so disable those here. We especially do not want MSI-X
1701 * enabled since it lives in MMIO space, which is about to get
1704 if (adev
->assigned_irq_type
== ASSIGNED_IRQ_MSIX
) {
1705 uint16_t ctrl
= pci_get_word(pci_dev
->config
+
1706 pci_dev
->msix_cap
+ PCI_MSIX_FLAGS
);
1708 pci_set_word(pci_dev
->config
+ pci_dev
->msix_cap
+ PCI_MSIX_FLAGS
,
1709 ctrl
& ~PCI_MSIX_FLAGS_ENABLE
);
1710 assigned_dev_update_msix(pci_dev
);
1711 } else if (adev
->assigned_irq_type
== ASSIGNED_IRQ_MSI
) {
1712 uint8_t ctrl
= pci_get_byte(pci_dev
->config
+
1713 pci_dev
->msi_cap
+ PCI_MSI_FLAGS
);
1715 pci_set_byte(pci_dev
->config
+ pci_dev
->msi_cap
+ PCI_MSI_FLAGS
,
1716 ctrl
& ~PCI_MSI_FLAGS_ENABLE
);
1717 assigned_dev_update_msi(pci_dev
);
1720 snprintf(reset_file
, sizeof(reset_file
),
1721 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/reset",
1722 adev
->host
.domain
, adev
->host
.bus
, adev
->host
.slot
,
1723 adev
->host
.function
);
1726 * Issue a device reset via pci-sysfs. Note that we use write(2) here
1727 * and ignore the return value because some kernels have a bug that
1728 * returns 0 rather than bytes written on success, sending us into an
1729 * infinite retry loop using other write mechanisms.
1731 fd
= open(reset_file
, O_WRONLY
);
1733 ret
= write(fd
, reset
, strlen(reset
));
1739 * When a 0 is written to the bus master register, the device is logically
1740 * disconnected from the PCI bus. This avoids further DMA transfers.
1742 assigned_dev_pci_write_config(pci_dev
, PCI_COMMAND
, 0, 1);
1745 static int assigned_initfn(struct PCIDevice
*pci_dev
)
1747 AssignedDevice
*dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1750 Error
*local_err
= NULL
;
1752 if (!kvm_enabled()) {
1753 error_setg(&local_err
, "pci-assign requires KVM support");
1754 goto exit_with_error
;
1757 if (!dev
->host
.domain
&& !dev
->host
.bus
&& !dev
->host
.slot
&&
1758 !dev
->host
.function
) {
1759 error_setg(&local_err
, "no host device specified");
1760 goto exit_with_error
;
1764 * Set up basic config space access control. Will be further refined during
1765 * device initialization.
1767 assigned_dev_emulate_config_read(dev
, 0, PCI_CONFIG_SPACE_SIZE
);
1768 assigned_dev_direct_config_read(dev
, PCI_STATUS
, 2);
1769 assigned_dev_direct_config_read(dev
, PCI_REVISION_ID
, 1);
1770 assigned_dev_direct_config_read(dev
, PCI_CLASS_PROG
, 3);
1771 assigned_dev_direct_config_read(dev
, PCI_CACHE_LINE_SIZE
, 1);
1772 assigned_dev_direct_config_read(dev
, PCI_LATENCY_TIMER
, 1);
1773 assigned_dev_direct_config_read(dev
, PCI_BIST
, 1);
1774 assigned_dev_direct_config_read(dev
, PCI_CARDBUS_CIS
, 4);
1775 assigned_dev_direct_config_read(dev
, PCI_SUBSYSTEM_VENDOR_ID
, 2);
1776 assigned_dev_direct_config_read(dev
, PCI_SUBSYSTEM_ID
, 2);
1777 assigned_dev_direct_config_read(dev
, PCI_CAPABILITY_LIST
+ 1, 7);
1778 assigned_dev_direct_config_read(dev
, PCI_MIN_GNT
, 1);
1779 assigned_dev_direct_config_read(dev
, PCI_MAX_LAT
, 1);
1780 memcpy(dev
->emulate_config_write
, dev
->emulate_config_read
,
1781 sizeof(dev
->emulate_config_read
));
1783 get_real_device(dev
, &local_err
);
1788 if (assigned_device_pci_cap_init(pci_dev
, &local_err
) < 0) {
1792 /* intercept MSI-X entry page in the MMIO */
1793 if (dev
->cap
.available
& ASSIGNED_DEVICE_CAP_MSIX
) {
1794 assigned_dev_register_msix_mmio(dev
, &local_err
);
1800 /* handle real device's MMIO/PIO BARs */
1801 assigned_dev_register_regions(dev
->real_device
.regions
,
1802 dev
->real_device
.region_number
, dev
,
1808 /* handle interrupt routing */
1809 e_intx
= dev
->dev
.config
[PCI_INTERRUPT_PIN
] - 1;
1810 dev
->intpin
= e_intx
;
1811 dev
->intx_route
.mode
= PCI_INTX_DISABLED
;
1812 dev
->intx_route
.irq
= -1;
1814 /* assign device to guest */
1815 assign_device(dev
, &local_err
);
1820 /* assign legacy INTx to the device */
1821 r
= assign_intx(dev
, &local_err
);
1826 assigned_dev_load_option_rom(dev
);
1831 deassign_device(dev
);
1834 free_assigned_device(dev
);
1838 qerror_report_err(local_err
);
1839 error_free(local_err
);
1843 static void assigned_exitfn(struct PCIDevice
*pci_dev
)
1845 AssignedDevice
*dev
= DO_UPCAST(AssignedDevice
, dev
, pci_dev
);
1847 deassign_device(dev
);
1848 free_assigned_device(dev
);
1851 static void assigned_dev_instance_init(Object
*obj
)
1853 PCIDevice
*pci_dev
= PCI_DEVICE(obj
);
1854 AssignedDevice
*d
= DO_UPCAST(AssignedDevice
, dev
, PCI_DEVICE(obj
));
1856 device_add_bootindex_property(obj
, &d
->bootindex
,
1858 &pci_dev
->qdev
, NULL
);
1861 static Property assigned_dev_properties
[] = {
1862 DEFINE_PROP_PCI_HOST_DEVADDR("host", AssignedDevice
, host
),
1863 DEFINE_PROP_BIT("prefer_msi", AssignedDevice
, features
,
1864 ASSIGNED_DEVICE_PREFER_MSI_BIT
, false),
1865 DEFINE_PROP_BIT("share_intx", AssignedDevice
, features
,
1866 ASSIGNED_DEVICE_SHARE_INTX_BIT
, true),
1867 DEFINE_PROP_STRING("configfd", AssignedDevice
, configfd_name
),
1868 DEFINE_PROP_END_OF_LIST(),
1871 static void assign_class_init(ObjectClass
*klass
, void *data
)
1873 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1874 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1876 k
->init
= assigned_initfn
;
1877 k
->exit
= assigned_exitfn
;
1878 k
->config_read
= assigned_dev_pci_read_config
;
1879 k
->config_write
= assigned_dev_pci_write_config
;
1880 dc
->props
= assigned_dev_properties
;
1881 dc
->vmsd
= &vmstate_assigned_device
;
1882 dc
->reset
= reset_assigned_device
;
1883 set_bit(DEVICE_CATEGORY_MISC
, dc
->categories
);
1884 dc
->desc
= "KVM-based PCI passthrough";
1887 static const TypeInfo assign_info
= {
1888 .name
= "kvm-pci-assign",
1889 .parent
= TYPE_PCI_DEVICE
,
1890 .instance_size
= sizeof(AssignedDevice
),
1891 .class_init
= assign_class_init
,
1892 .instance_init
= assigned_dev_instance_init
,
1895 static void assign_register_types(void)
1897 type_register_static(&assign_info
);
1900 type_init(assign_register_types
)
1903 * Scan the assigned devices for the devices that have an option ROM, and then
1904 * load the corresponding ROM data to RAM. If an error occurs while loading an
1905 * option ROM, we just ignore that option ROM and continue with the next one.
1907 static void assigned_dev_load_option_rom(AssignedDevice
*dev
)
1909 char name
[32], rom_file
[64];
1915 /* If loading ROM from file, pci handles it */
1916 if (dev
->dev
.romfile
|| !dev
->dev
.rom_bar
) {
1920 snprintf(rom_file
, sizeof(rom_file
),
1921 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/rom",
1922 dev
->host
.domain
, dev
->host
.bus
, dev
->host
.slot
,
1923 dev
->host
.function
);
1925 if (stat(rom_file
, &st
)) {
1929 if (access(rom_file
, F_OK
)) {
1930 error_report("pci-assign: Insufficient privileges for %s", rom_file
);
1934 /* Write "1" to the ROM file to enable it */
1935 fp
= fopen(rom_file
, "r+");
1940 if (fwrite(&val
, 1, 1, fp
) != 1) {
1943 fseek(fp
, 0, SEEK_SET
);
1945 snprintf(name
, sizeof(name
), "%s.rom",
1946 object_get_typename(OBJECT(dev
)));
1947 memory_region_init_ram(&dev
->dev
.rom
, OBJECT(dev
), name
, st
.st_size
,
1949 vmstate_register_ram(&dev
->dev
.rom
, &dev
->dev
.qdev
);
1950 ptr
= memory_region_get_ram_ptr(&dev
->dev
.rom
);
1951 memset(ptr
, 0xff, st
.st_size
);
1953 if (!fread(ptr
, 1, st
.st_size
, fp
)) {
1954 error_report("pci-assign: Cannot read from host %s", rom_file
);
1955 error_printf("Device option ROM contents are probably invalid "
1956 "(check dmesg).\nSkip option ROM probe with rombar=0, "
1957 "or load from file with romfile=\n");
1961 pci_register_bar(&dev
->dev
, PCI_ROM_SLOT
, 0, &dev
->dev
.rom
);
1962 dev
->dev
.has_rom
= true;
1964 /* Write "0" to disable ROM */
1965 fseek(fp
, 0, SEEK_SET
);
1967 if (!fwrite(&val
, 1, 1, fp
)) {
1968 DEBUG("%s\n", "Failed to disable pci-sysfs rom file");