target-moxie/translate.c

   1 /*
   2  *  Moxie emulation for qemu: main translation routines.
   3  *
   4  *  Copyright (c) 2009, 2013 Anthony Green
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public License
   8  * as published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful, but
  12  * WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /* For information on the Moxie architecture, see
  21  *    http://moxielogic.org/wiki
  22  */
  23
  24 #include "qemu/osdep.h"
  25
  26 #include "cpu.h"
  27 #include "exec/exec-all.h"
  28 #include "disas/disas.h"
  29 #include "tcg-op.h"
  30 #include "exec/cpu_ldst.h"
  31
  32 #include "exec/helper-proto.h"
  33 #include "exec/helper-gen.h"
  34 #include "exec/log.h"
  35
  36 /* This is the state at translation time.  */
  37 typedef struct DisasContext {
  38     struct TranslationBlock *tb;
  39     target_ulong pc, saved_pc;
  40     uint32_t opcode;
  41     uint32_t fp_status;
  42     /* Routine used to access memory */
  43     int memidx;
  44     int bstate;
  45     target_ulong btarget;
  46     int singlestep_enabled;
  47 } DisasContext;
  48
  49 enum {
  50     BS_NONE     = 0, /* We go out of the TB without reaching a branch or an
  51                       * exception condition */
  52     BS_STOP     = 1, /* We want to stop translation for any reason */
  53     BS_BRANCH   = 2, /* We reached a branch condition     */
  54     BS_EXCP     = 3, /* We reached an exception condition */
  55 };
  56
  57 static TCGv cpu_pc;
  58 static TCGv cpu_gregs[16];
  59 static TCGv_env cpu_env;
  60 static TCGv cc_a, cc_b;
  61
  62 #include "exec/gen-icount.h"
  63
  64 #define REG(x) (cpu_gregs[x])
  65
  66 /* Extract the signed 10-bit offset from a 16-bit branch
  67    instruction.  */
  68 static int extract_branch_offset(int opcode)
  69 {
  70   return (((signed short)((opcode & ((1 << 10) - 1)) << 6)) >> 6) << 1;
  71 }
  72
  73 void moxie_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
  74                           int flags)
  75 {
  76     MoxieCPU *cpu = MOXIE_CPU(cs);
  77     CPUMoxieState *env = &cpu->env;
  78     int i;
  79     cpu_fprintf(f, "pc=0x%08x\n", env->pc);
  80     cpu_fprintf(f, "$fp=0x%08x $sp=0x%08x $r0=0x%08x $r1=0x%08x\n",
  81                 env->gregs[0], env->gregs[1], env->gregs[2], env->gregs[3]);
  82     for (i = 4; i < 16; i += 4) {
  83         cpu_fprintf(f, "$r%d=0x%08x $r%d=0x%08x $r%d=0x%08x $r%d=0x%08x\n",
  84                     i-2, env->gregs[i], i-1, env->gregs[i + 1],
  85                     i, env->gregs[i + 2], i+1, env->gregs[i + 3]);
  86     }
  87     for (i = 4; i < 16; i += 4) {
  88         cpu_fprintf(f, "sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x sr%d=0x%08x\n",
  89                     i-2, env->sregs[i], i-1, env->sregs[i + 1],
  90                     i, env->sregs[i + 2], i+1, env->sregs[i + 3]);
  91     }
  92 }
  93
  94 void moxie_translate_init(void)
  95 {
  96     int i;
  97     static int done_init;
  98     static const char * const gregnames[16] = {
  99         "$fp", "$sp", "$r0", "$r1",
 100         "$r2", "$r3", "$r4", "$r5",
 101         "$r6", "$r7", "$r8", "$r9",
 102         "$r10", "$r11", "$r12", "$r13"
 103     };
 104
 105     if (done_init) {
 106         return;
 107     }
 108     cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
 109     cpu_pc = tcg_global_mem_new_i32(cpu_env,
 110                                     offsetof(CPUMoxieState, pc), "$pc");
 111     for (i = 0; i < 16; i++)
 112         cpu_gregs[i] = tcg_global_mem_new_i32(cpu_env,
 113                                               offsetof(CPUMoxieState, gregs[i]),
 114                                               gregnames[i]);
 115
 116     cc_a = tcg_global_mem_new_i32(cpu_env,
 117                                   offsetof(CPUMoxieState, cc_a), "cc_a");
 118     cc_b = tcg_global_mem_new_i32(cpu_env,
 119                                   offsetof(CPUMoxieState, cc_b), "cc_b");
 120
 121     done_init = 1;
 122 }
 123
 124 static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
 125 {
 126     if (unlikely(ctx->singlestep_enabled)) {
 127         return false;
 128     }
 129
 130 #ifndef CONFIG_USER_ONLY
 131     return (ctx->tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
 132 #else
 133     return true;
 134 #endif
 135 }
 136
 137 static inline void gen_goto_tb(CPUMoxieState *env, DisasContext *ctx,
 138                                int n, target_ulong dest)
 139 {
 140     if (use_goto_tb(ctx, dest)) {
 141         tcg_gen_goto_tb(n);
 142         tcg_gen_movi_i32(cpu_pc, dest);
 143         tcg_gen_exit_tb((uintptr_t)ctx->tb + n);
 144     } else {
 145         tcg_gen_movi_i32(cpu_pc, dest);
 146         if (ctx->singlestep_enabled) {
 147             gen_helper_debug(cpu_env);
 148         }
 149         tcg_gen_exit_tb(0);
 150     }
 151 }
 152
 153 static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
 154 {
 155     CPUMoxieState *env = &cpu->env;
 156
 157     /* Local cache for the instruction opcode.  */
 158     int opcode;
 159     /* Set the default instruction length.  */
 160     int length = 2;
 161
 162     /* Examine the 16-bit opcode.  */
 163     opcode = ctx->opcode;
 164
 165     /* Decode instruction.  */
 166     if (opcode & (1 << 15)) {
 167         if (opcode & (1 << 14)) {
 168             /* This is a Form 3 instruction.  */
 169             int inst = (opcode >> 10 & 0xf);
 170
 171 #define BRANCH(cond)                                                         \
 172     do {                                                                     \
 173         TCGLabel *l1 = gen_new_label();                                      \
 174         tcg_gen_brcond_i32(cond, cc_a, cc_b, l1);                            \
 175         gen_goto_tb(env, ctx, 1, ctx->pc+2);                                 \
 176         gen_set_label(l1);                                                   \
 177         gen_goto_tb(env, ctx, 0, extract_branch_offset(opcode) + ctx->pc+2); \
 178         ctx->bstate = BS_BRANCH;                                             \
 179     } while (0)
 180
 181             switch (inst) {
 182             case 0x00: /* beq */
 183                 BRANCH(TCG_COND_EQ);
 184                 break;
 185             case 0x01: /* bne */
 186                 BRANCH(TCG_COND_NE);
 187                 break;
 188             case 0x02: /* blt */
 189                 BRANCH(TCG_COND_LT);
 190                 break;
 191             case 0x03: /* bgt */
 192                 BRANCH(TCG_COND_GT);
 193                 break;
 194             case 0x04: /* bltu */
 195                 BRANCH(TCG_COND_LTU);
 196                 break;
 197             case 0x05: /* bgtu */
 198                 BRANCH(TCG_COND_GTU);
 199                 break;
 200             case 0x06: /* bge */
 201                 BRANCH(TCG_COND_GE);
 202                 break;
 203             case 0x07: /* ble */
 204                 BRANCH(TCG_COND_LE);
 205                 break;
 206             case 0x08: /* bgeu */
 207                 BRANCH(TCG_COND_GEU);
 208                 break;
 209             case 0x09: /* bleu */
 210                 BRANCH(TCG_COND_LEU);
 211                 break;
 212             default:
 213                 {
 214                     TCGv temp = tcg_temp_new_i32();
 215                     tcg_gen_movi_i32(cpu_pc, ctx->pc);
 216                     tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
 217                     gen_helper_raise_exception(cpu_env, temp);
 218                     tcg_temp_free_i32(temp);
 219                 }
 220                 break;
 221             }
 222         } else {
 223             /* This is a Form 2 instruction.  */
 224             int inst = (opcode >> 12 & 0x3);
 225             switch (inst) {
 226             case 0x00: /* inc */
 227                 {
 228                     int a = (opcode >> 8) & 0xf;
 229                     unsigned int v = (opcode & 0xff);
 230                     tcg_gen_addi_i32(REG(a), REG(a), v);
 231                 }
 232                 break;
 233             case 0x01: /* dec */
 234                 {
 235                     int a = (opcode >> 8) & 0xf;
 236                     unsigned int v = (opcode & 0xff);
 237                     tcg_gen_subi_i32(REG(a), REG(a), v);
 238                 }
 239                 break;
 240             case 0x02: /* gsr */
 241                 {
 242                     int a = (opcode >> 8) & 0xf;
 243                     unsigned v = (opcode & 0xff);
 244                     tcg_gen_ld_i32(REG(a), cpu_env,
 245                                    offsetof(CPUMoxieState, sregs[v]));
 246                 }
 247                 break;
 248             case 0x03: /* ssr */
 249                 {
 250                     int a = (opcode >> 8) & 0xf;
 251                     unsigned v = (opcode & 0xff);
 252                     tcg_gen_st_i32(REG(a), cpu_env,
 253                                    offsetof(CPUMoxieState, sregs[v]));
 254                 }
 255                 break;
 256             default:
 257                 {
 258                     TCGv temp = tcg_temp_new_i32();
 259                     tcg_gen_movi_i32(cpu_pc, ctx->pc);
 260                     tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
 261                     gen_helper_raise_exception(cpu_env, temp);
 262                     tcg_temp_free_i32(temp);
 263                 }
 264                 break;
 265             }
 266         }
 267     } else {
 268         /* This is a Form 1 instruction.  */
 269         int inst = opcode >> 8;
 270         switch (inst) {
 271         case 0x00: /* nop */
 272             break;
 273         case 0x01: /* ldi.l (immediate) */
 274             {
 275                 int reg = (opcode >> 4) & 0xf;
 276                 int val = cpu_ldl_code(env, ctx->pc+2);
 277                 tcg_gen_movi_i32(REG(reg), val);
 278                 length = 6;
 279             }
 280             break;
 281         case 0x02: /* mov (register-to-register) */
 282             {
 283                 int dest  = (opcode >> 4) & 0xf;
 284                 int src = opcode & 0xf;
 285                 tcg_gen_mov_i32(REG(dest), REG(src));
 286             }
 287             break;
 288         case 0x03: /* jsra */
 289             {
 290                 TCGv t1 = tcg_temp_new_i32();
 291                 TCGv t2 = tcg_temp_new_i32();
 292
 293                 tcg_gen_movi_i32(t1, ctx->pc + 6);
 294
 295                 /* Make space for the static chain and return address.  */
 296                 tcg_gen_subi_i32(t2, REG(1), 8);
 297                 tcg_gen_mov_i32(REG(1), t2);
 298                 tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
 299
 300                 /* Push the current frame pointer.  */
 301                 tcg_gen_subi_i32(t2, REG(1), 4);
 302                 tcg_gen_mov_i32(REG(1), t2);
 303                 tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
 304
 305                 /* Set the pc and $fp.  */
 306                 tcg_gen_mov_i32(REG(0), REG(1));
 307
 308                 gen_goto_tb(env, ctx, 0, cpu_ldl_code(env, ctx->pc+2));
 309
 310                 tcg_temp_free_i32(t1);
 311                 tcg_temp_free_i32(t2);
 312
 313                 ctx->bstate = BS_BRANCH;
 314                 length = 6;
 315             }
 316             break;
 317         case 0x04: /* ret */
 318             {
 319                 TCGv t1 = tcg_temp_new_i32();
 320
 321                 /* The new $sp is the old $fp.  */
 322                 tcg_gen_mov_i32(REG(1), REG(0));
 323
 324                 /* Pop the frame pointer.  */
 325                 tcg_gen_qemu_ld32u(REG(0), REG(1), ctx->memidx);
 326                 tcg_gen_addi_i32(t1, REG(1), 4);
 327                 tcg_gen_mov_i32(REG(1), t1);
 328
 329
 330                 /* Pop the return address and skip over the static chain
 331                    slot.  */
 332                 tcg_gen_qemu_ld32u(cpu_pc, REG(1), ctx->memidx);
 333                 tcg_gen_addi_i32(t1, REG(1), 8);
 334                 tcg_gen_mov_i32(REG(1), t1);
 335
 336                 tcg_temp_free_i32(t1);
 337
 338                 /* Jump... */
 339                 tcg_gen_exit_tb(0);
 340
 341                 ctx->bstate = BS_BRANCH;
 342             }
 343             break;
 344         case 0x05: /* add.l */
 345             {
 346                 int a = (opcode >> 4) & 0xf;
 347                 int b = opcode & 0xf;
 348
 349                 tcg_gen_add_i32(REG(a), REG(a), REG(b));
 350             }
 351             break;
 352         case 0x06: /* push */
 353             {
 354                 int a = (opcode >> 4) & 0xf;
 355                 int b = opcode & 0xf;
 356
 357                 TCGv t1 = tcg_temp_new_i32();
 358                 tcg_gen_subi_i32(t1, REG(a), 4);
 359                 tcg_gen_mov_i32(REG(a), t1);
 360                 tcg_gen_qemu_st32(REG(b), REG(a), ctx->memidx);
 361                 tcg_temp_free_i32(t1);
 362             }
 363             break;
 364         case 0x07: /* pop */
 365             {
 366                 int a = (opcode >> 4) & 0xf;
 367                 int b = opcode & 0xf;
 368                 TCGv t1 = tcg_temp_new_i32();
 369
 370                 tcg_gen_qemu_ld32u(REG(b), REG(a), ctx->memidx);
 371                 tcg_gen_addi_i32(t1, REG(a), 4);
 372                 tcg_gen_mov_i32(REG(a), t1);
 373                 tcg_temp_free_i32(t1);
 374             }
 375             break;
 376         case 0x08: /* lda.l */
 377             {
 378                 int reg = (opcode >> 4) & 0xf;
 379
 380                 TCGv ptr = tcg_temp_new_i32();
 381                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 382                 tcg_gen_qemu_ld32u(REG(reg), ptr, ctx->memidx);
 383                 tcg_temp_free_i32(ptr);
 384
 385                 length = 6;
 386             }
 387             break;
 388         case 0x09: /* sta.l */
 389             {
 390                 int val = (opcode >> 4) & 0xf;
 391
 392                 TCGv ptr = tcg_temp_new_i32();
 393                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 394                 tcg_gen_qemu_st32(REG(val), ptr, ctx->memidx);
 395                 tcg_temp_free_i32(ptr);
 396
 397                 length = 6;
 398             }
 399             break;
 400         case 0x0a: /* ld.l (register indirect) */
 401             {
 402                 int src  = opcode & 0xf;
 403                 int dest = (opcode >> 4) & 0xf;
 404
 405                 tcg_gen_qemu_ld32u(REG(dest), REG(src), ctx->memidx);
 406             }
 407             break;
 408         case 0x0b: /* st.l */
 409             {
 410                 int dest = (opcode >> 4) & 0xf;
 411                 int val  = opcode & 0xf;
 412
 413                 tcg_gen_qemu_st32(REG(val), REG(dest), ctx->memidx);
 414             }
 415             break;
 416         case 0x0c: /* ldo.l */
 417             {
 418                 int a = (opcode >> 4) & 0xf;
 419                 int b = opcode & 0xf;
 420
 421                 TCGv t1 = tcg_temp_new_i32();
 422                 TCGv t2 = tcg_temp_new_i32();
 423                 tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
 424                 tcg_gen_qemu_ld32u(t2, t1, ctx->memidx);
 425                 tcg_gen_mov_i32(REG(a), t2);
 426
 427                 tcg_temp_free_i32(t1);
 428                 tcg_temp_free_i32(t2);
 429
 430                 length = 6;
 431             }
 432             break;
 433         case 0x0d: /* sto.l */
 434             {
 435                 int a = (opcode >> 4) & 0xf;
 436                 int b = opcode & 0xf;
 437
 438                 TCGv t1 = tcg_temp_new_i32();
 439                 TCGv t2 = tcg_temp_new_i32();
 440                 tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
 441                 tcg_gen_qemu_st32(REG(b), t1, ctx->memidx);
 442
 443                 tcg_temp_free_i32(t1);
 444                 tcg_temp_free_i32(t2);
 445
 446                 length = 6;
 447             }
 448             break;
 449         case 0x0e: /* cmp */
 450             {
 451                 int a  = (opcode >> 4) & 0xf;
 452                 int b  = opcode & 0xf;
 453
 454                 tcg_gen_mov_i32(cc_a, REG(a));
 455                 tcg_gen_mov_i32(cc_b, REG(b));
 456             }
 457             break;
 458         case 0x19: /* jsr */
 459             {
 460                 int fnreg = (opcode >> 4) & 0xf;
 461
 462                 /* Load the stack pointer into T0.  */
 463                 TCGv t1 = tcg_temp_new_i32();
 464                 TCGv t2 = tcg_temp_new_i32();
 465
 466                 tcg_gen_movi_i32(t1, ctx->pc+2);
 467
 468                 /* Make space for the static chain and return address.  */
 469                 tcg_gen_subi_i32(t2, REG(1), 8);
 470                 tcg_gen_mov_i32(REG(1), t2);
 471                 tcg_gen_qemu_st32(t1, REG(1), ctx->memidx);
 472
 473                 /* Push the current frame pointer.  */
 474                 tcg_gen_subi_i32(t2, REG(1), 4);
 475                 tcg_gen_mov_i32(REG(1), t2);
 476                 tcg_gen_qemu_st32(REG(0), REG(1), ctx->memidx);
 477
 478                 /* Set the pc and $fp.  */
 479                 tcg_gen_mov_i32(REG(0), REG(1));
 480                 tcg_gen_mov_i32(cpu_pc, REG(fnreg));
 481                 tcg_temp_free_i32(t1);
 482                 tcg_temp_free_i32(t2);
 483                 tcg_gen_exit_tb(0);
 484                 ctx->bstate = BS_BRANCH;
 485             }
 486             break;
 487         case 0x1a: /* jmpa */
 488             {
 489                 tcg_gen_movi_i32(cpu_pc, cpu_ldl_code(env, ctx->pc+2));
 490                 tcg_gen_exit_tb(0);
 491                 ctx->bstate = BS_BRANCH;
 492                 length = 6;
 493             }
 494             break;
 495         case 0x1b: /* ldi.b (immediate) */
 496             {
 497                 int reg = (opcode >> 4) & 0xf;
 498                 int val = cpu_ldl_code(env, ctx->pc+2);
 499                 tcg_gen_movi_i32(REG(reg), val);
 500                 length = 6;
 501             }
 502             break;
 503         case 0x1c: /* ld.b (register indirect) */
 504             {
 505                 int src  = opcode & 0xf;
 506                 int dest = (opcode >> 4) & 0xf;
 507
 508                 tcg_gen_qemu_ld8u(REG(dest), REG(src), ctx->memidx);
 509             }
 510             break;
 511         case 0x1d: /* lda.b */
 512             {
 513                 int reg = (opcode >> 4) & 0xf;
 514
 515                 TCGv ptr = tcg_temp_new_i32();
 516                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 517                 tcg_gen_qemu_ld8u(REG(reg), ptr, ctx->memidx);
 518                 tcg_temp_free_i32(ptr);
 519
 520                 length = 6;
 521             }
 522             break;
 523         case 0x1e: /* st.b */
 524             {
 525                 int dest = (opcode >> 4) & 0xf;
 526                 int val  = opcode & 0xf;
 527
 528                 tcg_gen_qemu_st8(REG(val), REG(dest), ctx->memidx);
 529             }
 530             break;
 531         case 0x1f: /* sta.b */
 532             {
 533                 int val = (opcode >> 4) & 0xf;
 534
 535                 TCGv ptr = tcg_temp_new_i32();
 536                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 537                 tcg_gen_qemu_st8(REG(val), ptr, ctx->memidx);
 538                 tcg_temp_free_i32(ptr);
 539
 540                 length = 6;
 541             }
 542             break;
 543         case 0x20: /* ldi.s (immediate) */
 544             {
 545                 int reg = (opcode >> 4) & 0xf;
 546                 int val = cpu_ldl_code(env, ctx->pc+2);
 547                 tcg_gen_movi_i32(REG(reg), val);
 548                 length = 6;
 549             }
 550             break;
 551         case 0x21: /* ld.s (register indirect) */
 552             {
 553                 int src  = opcode & 0xf;
 554                 int dest = (opcode >> 4) & 0xf;
 555
 556                 tcg_gen_qemu_ld16u(REG(dest), REG(src), ctx->memidx);
 557             }
 558             break;
 559         case 0x22: /* lda.s */
 560             {
 561                 int reg = (opcode >> 4) & 0xf;
 562
 563                 TCGv ptr = tcg_temp_new_i32();
 564                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 565                 tcg_gen_qemu_ld16u(REG(reg), ptr, ctx->memidx);
 566                 tcg_temp_free_i32(ptr);
 567
 568                 length = 6;
 569             }
 570             break;
 571         case 0x23: /* st.s */
 572             {
 573                 int dest = (opcode >> 4) & 0xf;
 574                 int val  = opcode & 0xf;
 575
 576                 tcg_gen_qemu_st16(REG(val), REG(dest), ctx->memidx);
 577             }
 578             break;
 579         case 0x24: /* sta.s */
 580             {
 581                 int val = (opcode >> 4) & 0xf;
 582
 583                 TCGv ptr = tcg_temp_new_i32();
 584                 tcg_gen_movi_i32(ptr, cpu_ldl_code(env, ctx->pc+2));
 585                 tcg_gen_qemu_st16(REG(val), ptr, ctx->memidx);
 586                 tcg_temp_free_i32(ptr);
 587
 588                 length = 6;
 589             }
 590             break;
 591         case 0x25: /* jmp */
 592             {
 593                 int reg = (opcode >> 4) & 0xf;
 594                 tcg_gen_mov_i32(cpu_pc, REG(reg));
 595                 tcg_gen_exit_tb(0);
 596                 ctx->bstate = BS_BRANCH;
 597             }
 598             break;
 599         case 0x26: /* and */
 600             {
 601                 int a = (opcode >> 4) & 0xf;
 602                 int b = opcode & 0xf;
 603
 604                 tcg_gen_and_i32(REG(a), REG(a), REG(b));
 605             }
 606             break;
 607         case 0x27: /* lshr */
 608             {
 609                 int a = (opcode >> 4) & 0xf;
 610                 int b = opcode & 0xf;
 611
 612                 TCGv sv = tcg_temp_new_i32();
 613                 tcg_gen_andi_i32(sv, REG(b), 0x1f);
 614                 tcg_gen_shr_i32(REG(a), REG(a), sv);
 615                 tcg_temp_free_i32(sv);
 616             }
 617             break;
 618         case 0x28: /* ashl */
 619             {
 620                 int a = (opcode >> 4) & 0xf;
 621                 int b = opcode & 0xf;
 622
 623                 TCGv sv = tcg_temp_new_i32();
 624                 tcg_gen_andi_i32(sv, REG(b), 0x1f);
 625                 tcg_gen_shl_i32(REG(a), REG(a), sv);
 626                 tcg_temp_free_i32(sv);
 627             }
 628             break;
 629         case 0x29: /* sub.l */
 630             {
 631                 int a = (opcode >> 4) & 0xf;
 632                 int b = opcode & 0xf;
 633
 634                 tcg_gen_sub_i32(REG(a), REG(a), REG(b));
 635             }
 636             break;
 637         case 0x2a: /* neg */
 638             {
 639                 int a = (opcode >> 4) & 0xf;
 640                 int b = opcode & 0xf;
 641
 642                 tcg_gen_neg_i32(REG(a), REG(b));
 643             }
 644             break;
 645         case 0x2b: /* or */
 646             {
 647                 int a = (opcode >> 4) & 0xf;
 648                 int b = opcode & 0xf;
 649
 650                 tcg_gen_or_i32(REG(a), REG(a), REG(b));
 651             }
 652             break;
 653         case 0x2c: /* not */
 654             {
 655                 int a = (opcode >> 4) & 0xf;
 656                 int b = opcode & 0xf;
 657
 658                 tcg_gen_not_i32(REG(a), REG(b));
 659             }
 660             break;
 661         case 0x2d: /* ashr */
 662             {
 663                 int a = (opcode >> 4) & 0xf;
 664                 int b = opcode & 0xf;
 665
 666                 TCGv sv = tcg_temp_new_i32();
 667                 tcg_gen_andi_i32(sv, REG(b), 0x1f);
 668                 tcg_gen_sar_i32(REG(a), REG(a), sv);
 669                 tcg_temp_free_i32(sv);
 670             }
 671             break;
 672         case 0x2e: /* xor */
 673             {
 674                 int a = (opcode >> 4) & 0xf;
 675                 int b = opcode & 0xf;
 676
 677                 tcg_gen_xor_i32(REG(a), REG(a), REG(b));
 678             }
 679             break;
 680         case 0x2f: /* mul.l */
 681             {
 682                 int a = (opcode >> 4) & 0xf;
 683                 int b = opcode & 0xf;
 684
 685                 tcg_gen_mul_i32(REG(a), REG(a), REG(b));
 686             }
 687             break;
 688         case 0x30: /* swi */
 689             {
 690                 int val = cpu_ldl_code(env, ctx->pc+2);
 691
 692                 TCGv temp = tcg_temp_new_i32();
 693                 tcg_gen_movi_i32(temp, val);
 694                 tcg_gen_st_i32(temp, cpu_env,
 695                                offsetof(CPUMoxieState, sregs[3]));
 696                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 697                 tcg_gen_movi_i32(temp, MOXIE_EX_SWI);
 698                 gen_helper_raise_exception(cpu_env, temp);
 699                 tcg_temp_free_i32(temp);
 700
 701                 length = 6;
 702             }
 703             break;
 704         case 0x31: /* div.l */
 705             {
 706                 int a = (opcode >> 4) & 0xf;
 707                 int b = opcode & 0xf;
 708                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 709                 gen_helper_div(REG(a), cpu_env, REG(a), REG(b));
 710             }
 711             break;
 712         case 0x32: /* udiv.l */
 713             {
 714                 int a = (opcode >> 4) & 0xf;
 715                 int b = opcode & 0xf;
 716                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 717                 gen_helper_udiv(REG(a), cpu_env, REG(a), REG(b));
 718             }
 719             break;
 720         case 0x33: /* mod.l */
 721             {
 722                 int a = (opcode >> 4) & 0xf;
 723                 int b = opcode & 0xf;
 724                 tcg_gen_rem_i32(REG(a), REG(a), REG(b));
 725             }
 726             break;
 727         case 0x34: /* umod.l */
 728             {
 729                 int a = (opcode >> 4) & 0xf;
 730                 int b = opcode & 0xf;
 731                 tcg_gen_remu_i32(REG(a), REG(a), REG(b));
 732             }
 733             break;
 734         case 0x35: /* brk */
 735             {
 736                 TCGv temp = tcg_temp_new_i32();
 737                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 738                 tcg_gen_movi_i32(temp, MOXIE_EX_BREAK);
 739                 gen_helper_raise_exception(cpu_env, temp);
 740                 tcg_temp_free_i32(temp);
 741             }
 742             break;
 743         case 0x36: /* ldo.b */
 744             {
 745                 int a = (opcode >> 4) & 0xf;
 746                 int b = opcode & 0xf;
 747
 748                 TCGv t1 = tcg_temp_new_i32();
 749                 TCGv t2 = tcg_temp_new_i32();
 750                 tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
 751                 tcg_gen_qemu_ld8u(t2, t1, ctx->memidx);
 752                 tcg_gen_mov_i32(REG(a), t2);
 753
 754                 tcg_temp_free_i32(t1);
 755                 tcg_temp_free_i32(t2);
 756
 757                 length = 6;
 758             }
 759             break;
 760         case 0x37: /* sto.b */
 761             {
 762                 int a = (opcode >> 4) & 0xf;
 763                 int b = opcode & 0xf;
 764
 765                 TCGv t1 = tcg_temp_new_i32();
 766                 TCGv t2 = tcg_temp_new_i32();
 767                 tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
 768                 tcg_gen_qemu_st8(REG(b), t1, ctx->memidx);
 769
 770                 tcg_temp_free_i32(t1);
 771                 tcg_temp_free_i32(t2);
 772
 773                 length = 6;
 774             }
 775             break;
 776         case 0x38: /* ldo.s */
 777             {
 778                 int a = (opcode >> 4) & 0xf;
 779                 int b = opcode & 0xf;
 780
 781                 TCGv t1 = tcg_temp_new_i32();
 782                 TCGv t2 = tcg_temp_new_i32();
 783                 tcg_gen_addi_i32(t1, REG(b), cpu_ldl_code(env, ctx->pc+2));
 784                 tcg_gen_qemu_ld16u(t2, t1, ctx->memidx);
 785                 tcg_gen_mov_i32(REG(a), t2);
 786
 787                 tcg_temp_free_i32(t1);
 788                 tcg_temp_free_i32(t2);
 789
 790                 length = 6;
 791             }
 792             break;
 793         case 0x39: /* sto.s */
 794             {
 795                 int a = (opcode >> 4) & 0xf;
 796                 int b = opcode & 0xf;
 797
 798                 TCGv t1 = tcg_temp_new_i32();
 799                 TCGv t2 = tcg_temp_new_i32();
 800                 tcg_gen_addi_i32(t1, REG(a), cpu_ldl_code(env, ctx->pc+2));
 801                 tcg_gen_qemu_st16(REG(b), t1, ctx->memidx);
 802                 tcg_temp_free_i32(t1);
 803                 tcg_temp_free_i32(t2);
 804
 805                 length = 6;
 806             }
 807             break;
 808         default:
 809             {
 810                 TCGv temp = tcg_temp_new_i32();
 811                 tcg_gen_movi_i32(cpu_pc, ctx->pc);
 812                 tcg_gen_movi_i32(temp, MOXIE_EX_BAD);
 813                 gen_helper_raise_exception(cpu_env, temp);
 814                 tcg_temp_free_i32(temp);
 815              }
 816             break;
 817         }
 818     }
 819
 820     return length;
 821 }
 822
 823 /* generate intermediate code for basic block 'tb'.  */
 824 void gen_intermediate_code(CPUMoxieState *env, struct TranslationBlock *tb)
 825 {
 826     MoxieCPU *cpu = moxie_env_get_cpu(env);
 827     CPUState *cs = CPU(cpu);
 828     DisasContext ctx;
 829     target_ulong pc_start;
 830     int num_insns, max_insns;
 831
 832     pc_start = tb->pc;
 833     ctx.pc = pc_start;
 834     ctx.saved_pc = -1;
 835     ctx.tb = tb;
 836     ctx.memidx = 0;
 837     ctx.singlestep_enabled = 0;
 838     ctx.bstate = BS_NONE;
 839     num_insns = 0;
 840     max_insns = tb->cflags & CF_COUNT_MASK;
 841     if (max_insns == 0) {
 842         max_insns = CF_COUNT_MASK;
 843     }
 844     if (max_insns > TCG_MAX_INSNS) {
 845         max_insns = TCG_MAX_INSNS;
 846     }
 847
 848     gen_tb_start(tb);
 849     do {
 850         tcg_gen_insn_start(ctx.pc);
 851         num_insns++;
 852
 853         if (unlikely(cpu_breakpoint_test(cs, ctx.pc, BP_ANY))) {
 854             tcg_gen_movi_i32(cpu_pc, ctx.pc);
 855             gen_helper_debug(cpu_env);
 856             ctx.bstate = BS_EXCP;
 857             /* The address covered by the breakpoint must be included in
 858                [tb->pc, tb->pc + tb->size) in order to for it to be
 859                properly cleared -- thus we increment the PC here so that
 860                the logic setting tb->size below does the right thing.  */
 861             ctx.pc += 2;
 862             goto done_generating;
 863         }
 864
 865         ctx.opcode = cpu_lduw_code(env, ctx.pc);
 866         ctx.pc += decode_opc(cpu, &ctx);
 867
 868         if (num_insns >= max_insns) {
 869             break;
 870         }
 871         if (cs->singlestep_enabled) {
 872             break;
 873         }
 874         if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) {
 875             break;
 876         }
 877     } while (ctx.bstate == BS_NONE && !tcg_op_buf_full());
 878
 879     if (cs->singlestep_enabled) {
 880         tcg_gen_movi_tl(cpu_pc, ctx.pc);
 881         gen_helper_debug(cpu_env);
 882     } else {
 883         switch (ctx.bstate) {
 884         case BS_STOP:
 885         case BS_NONE:
 886             gen_goto_tb(env, &ctx, 0, ctx.pc);
 887             break;
 888         case BS_EXCP:
 889             tcg_gen_exit_tb(0);
 890             break;
 891         case BS_BRANCH:
 892         default:
 893             break;
 894         }
 895     }
 896  done_generating:
 897     gen_tb_end(tb, num_insns);
 898
 899     tb->size = ctx.pc - pc_start;
 900     tb->icount = num_insns;
 901 }
 902
 903 void restore_state_to_opc(CPUMoxieState *env, TranslationBlock *tb,
 904                           target_ulong *data)
 905 {
 906     env->pc = data[0];
 907 }