hw/soc_dma.h

   1 /*
   2  * On-chip DMA controller framework.
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  * Written by Andrzej Zaborowski <andrew@openedhand.com>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 or
  10  * (at your option) version 3 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along
  18  * with this program; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "memory.h"
  22 #include "hw/irq.h"
  23
  24 struct soc_dma_s;
  25 struct soc_dma_ch_s;
  26 typedef void (*soc_dma_io_t)(void *opaque, uint8_t *buf, int len);
  27 typedef void (*soc_dma_transfer_t)(struct soc_dma_ch_s *ch);
  28
  29 enum soc_dma_port_type {
  30     soc_dma_port_mem,
  31     soc_dma_port_fifo,
  32     soc_dma_port_other,
  33 };
  34
  35 enum soc_dma_access_type {
  36     soc_dma_access_const,
  37     soc_dma_access_linear,
  38     soc_dma_access_other,
  39 };
  40
  41 struct soc_dma_ch_s {
  42     /* Private */
  43     struct soc_dma_s *dma;
  44     int num;
  45     QEMUTimer *timer;
  46
  47     /* Set by soc_dma.c */
  48     int enable;
  49     int update;
  50
  51     /* This should be set by dma->setup_fn().  */
  52     int bytes;
  53     /* Initialised by the DMA module, call soc_dma_ch_update after writing.  */
  54     enum soc_dma_access_type type[2];
  55     hwaddr vaddr[2];    /* Updated by .transfer_fn().  */
  56     /* Private */
  57     void *paddr[2];
  58     soc_dma_io_t io_fn[2];
  59     void *io_opaque[2];
  60
  61     int running;
  62     soc_dma_transfer_t transfer_fn;
  63
  64     /* Set and used by the DMA module.  */
  65     void *opaque;
  66 };
  67
  68 struct soc_dma_s {
  69     /* Following fields are set by the SoC DMA module and can be used
  70      * by anybody.  */
  71     uint64_t drqbmp;    /* Is zeroed by soc_dma_reset() */
  72     qemu_irq *drq;
  73     void *opaque;
  74     int64_t freq;
  75     soc_dma_transfer_t transfer_fn;
  76     soc_dma_transfer_t setup_fn;
  77     /* Set by soc_dma_init() for use by the DMA module.  */
  78     struct soc_dma_ch_s *ch;
  79 };
  80
  81 /* Call to activate or stop a DMA channel.  */
  82 void soc_dma_set_request(struct soc_dma_ch_s *ch, int level);
  83 /* Call after every write to one of the following fields and before
  84  * calling soc_dma_set_request(ch, 1):
  85  *   ch->type[0...1],
  86  *   ch->vaddr[0...1],
  87  *   ch->paddr[0...1],
  88  * or after a soc_dma_port_add_fifo() or soc_dma_port_add_mem().  */
  89 void soc_dma_ch_update(struct soc_dma_ch_s *ch);
  90
  91 /* The SoC should call this when the DMA module is being reset.  */
  92 void soc_dma_reset(struct soc_dma_s *s);
  93 struct soc_dma_s *soc_dma_init(int n);
  94
  95 void soc_dma_port_add_fifo(struct soc_dma_s *dma, hwaddr virt_base,
  96                 soc_dma_io_t fn, void *opaque, int out);
  97 void soc_dma_port_add_mem(struct soc_dma_s *dma, uint8_t *phys_base,
  98                 hwaddr virt_base, size_t size);
  99
 100 static inline void soc_dma_port_add_fifo_in(struct soc_dma_s *dma,
 101                 hwaddr virt_base, soc_dma_io_t fn, void *opaque)
 102 {
 103     return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 0);
 104 }
 105
 106 static inline void soc_dma_port_add_fifo_out(struct soc_dma_s *dma,
 107                 hwaddr virt_base, soc_dma_io_t fn, void *opaque)
 108 {
 109     return soc_dma_port_add_fifo(dma, virt_base, fn, opaque, 1);
 110 }