hw/smbus_ich9.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 /*
  19  *  Copyright (c) 2009 Isaku Yamahata <yamahata at valinux co jp>
  20  *                     VA Linux Systems Japan K.K.
  21  *  Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
  22  *
  23  *  This is based on acpi.c, but heavily rewritten.
  24  */
  25 #include "hw.h"
  26 #include "pc.h"
  27 #include "pm_smbus.h"
  28 #include "pci.h"
  29 #include "sysemu.h"
  30 #include "i2c.h"
  31 #include "smbus.h"
  32
  33 #include "ich9.h"
  34
  35 #define TYPE_ICH9_SMB_DEVICE "ICH9 SMB"
  36 #define ICH9_SMB_DEVICE(obj) \
  37      OBJECT_CHECK(ICH9SMBState, (obj), TYPE_ICH9_SMB_DEVICE)
  38
  39 typedef struct ICH9SMBState {
  40     PCIDevice dev;
  41
  42     PMSMBus smb;
  43     MemoryRegion mem_bar;
  44 } ICH9SMBState;
  45
  46 static const VMStateDescription vmstate_ich9_smbus = {
  47     .name = "ich9_smb",
  48     .version_id = 1,
  49     .minimum_version_id = 1,
  50     .minimum_version_id_old = 1,
  51     .fields = (VMStateField[]) {
  52         VMSTATE_PCI_DEVICE(dev, struct ICH9SMBState),
  53         VMSTATE_END_OF_LIST()
  54     }
  55 };
  56
  57 static void ich9_smb_ioport_writeb(void *opaque, hwaddr addr,
  58                                    uint64_t val, unsigned size)
  59 {
  60     ICH9SMBState *s = opaque;
  61     uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
  62
  63     if ((hostc & ICH9_SMB_HOSTC_HST_EN) && !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
  64         uint64_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR].addr;
  65         smb_ioport_writeb(&s->smb, offset, val);
  66     }
  67 }
  68
  69 static uint64_t ich9_smb_ioport_readb(void *opaque, hwaddr addr,
  70                                       unsigned size)
  71 {
  72     ICH9SMBState *s = opaque;
  73     uint8_t hostc = s->dev.config[ICH9_SMB_HOSTC];
  74
  75     if ((hostc & ICH9_SMB_HOSTC_HST_EN) && !(hostc & ICH9_SMB_HOSTC_I2C_EN)) {
  76         uint64_t offset = addr - s->dev.io_regions[ICH9_SMB_SMB_BASE_BAR].addr;
  77         return smb_ioport_readb(&s->smb, offset);
  78     }
  79
  80     return 0xff;
  81 }
  82
  83 static const MemoryRegionOps lpc_smb_mmio_ops = {
  84     .read = ich9_smb_ioport_readb,
  85     .write = ich9_smb_ioport_writeb,
  86     .endianness = DEVICE_LITTLE_ENDIAN,
  87     .impl = {
  88         .min_access_size = 1,
  89         .max_access_size = 1,
  90     },
  91 };
  92
  93 static int ich9_smbus_initfn(PCIDevice *d)
  94 {
  95     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
  96
  97     /* TODO? D31IP.SMIP in chipset configuration space */
  98     pci_config_set_interrupt_pin(d->config, 0x01); /* interrupt pin 1 */
  99
 100     pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
 101
 102     /*
 103      * update parameters based on
 104      * paralell_hds[0]
 105      * serial_hds[0]
 106      * serial_hds[0]
 107      * fdc
 108      *
 109      * Is there any OS that depends on them?
 110      */
 111
 112     /* TODO smb_io_base */
 113     pci_set_byte(d->config + ICH9_SMB_HOSTC, 0);
 114     /* TODO bar0, bar1: 64bit BAR support*/
 115
 116     memory_region_init_io(&s->mem_bar, &lpc_smb_mmio_ops, s, "ich9-smbus-bar",
 117                             ICH9_SMB_SMB_BASE_SIZE);
 118     pci_register_bar(d, ICH9_SMB_SMB_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
 119                         &s->mem_bar);
 120     pm_smbus_init(&d->qdev, &s->smb);
 121     return 0;
 122 }
 123
 124 static void ich9_smb_class_init(ObjectClass *klass, void *data)
 125 {
 126     DeviceClass *dc = DEVICE_CLASS(klass);
 127     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 128
 129     k->vendor_id = PCI_VENDOR_ID_INTEL;
 130     k->device_id = PCI_DEVICE_ID_INTEL_ICH9_6;
 131     k->revision = ICH9_A2_SMB_REVISION;
 132     k->class_id = PCI_CLASS_SERIAL_SMBUS;
 133     dc->no_user = 1;
 134     dc->vmsd = &vmstate_ich9_smbus;
 135     dc->desc = "ICH9 SMBUS Bridge";
 136     k->init = ich9_smbus_initfn;
 137 }
 138
 139 i2c_bus *ich9_smb_init(PCIBus *bus, int devfn, uint32_t smb_io_base)
 140 {
 141     PCIDevice *d =
 142         pci_create_simple_multifunction(bus, devfn, true, TYPE_ICH9_SMB_DEVICE);
 143     ICH9SMBState *s = ICH9_SMB_DEVICE(d);
 144     return s->smb.smbus;
 145 }
 146
 147 static const TypeInfo ich9_smb_info = {
 148     .name   = TYPE_ICH9_SMB_DEVICE,
 149     .parent = TYPE_PCI_DEVICE,
 150     .instance_size = sizeof(ICH9SMBState),
 151     .class_init = ich9_smb_class_init,
 152 };
 153
 154 static void ich9_smb_register(void)
 155 {
 156     type_register_static(&ich9_smb_info);
 157 }
 158
 159 type_init(ich9_smb_register);