12 #include "pcie_host.h"
13 #include "pci_bridge.h"
15 #include "acpi_ich9.h"
17 #include "pci_internals.h"
19 void ich9_lpc_set_irq(void *opaque
, int irq_num
, int level
);
20 int ich9_lpc_map_irq(PCIDevice
*pci_dev
, int intx
);
21 void ich9_lpc_pm_init(PCIDevice
*pci_lpc
, qemu_irq cmos_s3
);
22 PCIBus
*ich9_d2pbr_init(PCIBus
*bus
, int devfn
, int sec_bus
);
23 i2c_bus
*ich9_smb_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
);
25 #define ICH9_CC_SIZE (16 * 1024) /* 16KB */
27 #define TYPE_ICH9_LPC_DEVICE "ICH9 LPC"
28 #define ICH9_LPC_DEVICE(obj) \
29 OBJECT_CHECK(ICH9LPCState, (obj), TYPE_ICH9_LPC_DEVICE)
31 typedef struct ICH9LPCState
{
32 /* ICH9 LPC PCI to ISA bridge */
35 /* (pci device, intx) -> pirq
36 * In real chipset case, the unused slots are never used
37 * as ICH9 supports only D25-D32 irq routing.
38 * On the other hand in qemu case, any slot/function can be populated
39 * via command line option.
40 * So fallback interrupt routing for any devices in any slots is necessary.
42 uint8_t irr
[PCI_SLOT_MAX
][PCI_NUM_PINS
];
46 uint32_t sci_level
; /* track sci level */
48 /* 10.1 Chipset Configuration registers(Memory Space)
49 which is pointed by RCBA */
50 uint8_t chip_config
[ICH9_CC_SIZE
];
53 MemoryRegion rbca_mem
;
59 #define Q35_MASK(bit, ms_bit, ls_bit) \
60 ((uint##bit##_t)(((1ULL << ((ms_bit) + 1)) - 1) & ~((1ULL << ls_bit) - 1)))
62 /* ICH9: Chipset Configuration Registers */
63 #define ICH9_CC_ADDR_MASK (ICH9_CC_SIZE - 1)
66 #define ICH9_CC_D28IP 0x310C
67 #define ICH9_CC_D28IP_SHIFT 4
68 #define ICH9_CC_D28IP_MASK 0xf
69 #define ICH9_CC_D28IP_DEFAULT 0x00214321
70 #define ICH9_CC_D31IR 0x3140
71 #define ICH9_CC_D30IR 0x3142
72 #define ICH9_CC_D29IR 0x3144
73 #define ICH9_CC_D28IR 0x3146
74 #define ICH9_CC_D27IR 0x3148
75 #define ICH9_CC_D26IR 0x314C
76 #define ICH9_CC_D25IR 0x3150
77 #define ICH9_CC_DIR_DEFAULT 0x3210
78 #define ICH9_CC_D30IR_DEFAULT 0x0
79 #define ICH9_CC_DIR_SHIFT 4
80 #define ICH9_CC_DIR_MASK 0x7
81 #define ICH9_CC_OIC 0x31FF
82 #define ICH9_CC_OIC_AEN 0x1
85 #define ICH9_PCIE_DEV 28
86 #define ICH9_PCIE_FUNC_MAX 6
89 /* D29:F0 USB UHCI Controller #1 */
90 #define ICH9_USB_UHCI1_DEV 29
91 #define ICH9_USB_UHCI1_FUNC 0
93 /* D30:F0 DMI-to-PCI brdige */
94 #define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
95 #define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0
97 #define ICH9_D2P_BRIDGE_DEV 30
98 #define ICH9_D2P_BRIDGE_FUNC 0
100 #define ICH9_D2P_SECONDARY_DEFAULT (256 - 8)
102 #define ICH9_D2P_A2_REVISION 0x92
105 /* D31:F1 LPC controller */
106 #define ICH9_A2_LPC "ICH9 A2 LPC"
107 #define ICH9_A2_LPC_SAVEVM_VERSION 0
109 #define ICH9_LPC_DEV 31
110 #define ICH9_LPC_FUNC 0
112 #define ICH9_A2_LPC_REVISION 0x2
113 #define ICH9_LPC_NB_PIRQS 8 /* PCI A-H */
115 #define ICH9_LPC_PMBASE 0x40
116 #define ICH9_LPC_PMBASE_BASE_ADDRESS_MASK Q35_MASK(32, 15, 7)
117 #define ICH9_LPC_PMBASE_RTE 0x1
118 #define ICH9_LPC_PMBASE_DEFAULT 0x1
119 #define ICH9_LPC_ACPI_CTRL 0x44
120 #define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
121 #define ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK Q35_MASK(8, 2, 0)
122 #define ICH9_LPC_ACPI_CTRL_9 0x0
123 #define ICH9_LPC_ACPI_CTRL_10 0x1
124 #define ICH9_LPC_ACPI_CTRL_11 0x2
125 #define ICH9_LPC_ACPI_CTRL_20 0x4
126 #define ICH9_LPC_ACPI_CTRL_21 0x5
127 #define ICH9_LPC_ACPI_CTRL_DEFAULT 0x0
129 #define ICH9_LPC_PIRQA_ROUT 0x60
130 #define ICH9_LPC_PIRQB_ROUT 0x61
131 #define ICH9_LPC_PIRQC_ROUT 0x62
132 #define ICH9_LPC_PIRQD_ROUT 0x63
134 #define ICH9_LPC_PIRQE_ROUT 0x68
135 #define ICH9_LPC_PIRQF_ROUT 0x69
136 #define ICH9_LPC_PIRQG_ROUT 0x6a
137 #define ICH9_LPC_PIRQH_ROUT 0x6b
139 #define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
140 #define ICH9_LPC_PIRQ_ROUT_MASK Q35_MASK(8, 3, 0)
141 #define ICH9_LPC_PIRQ_ROUT_DEFAULT 0x80
143 #define ICH9_LPC_RCBA 0xf0
144 #define ICH9_LPC_RCBA_BA_MASK Q35_MASK(32, 31, 14)
145 #define ICH9_LPC_RCBA_EN 0x1
146 #define ICH9_LPC_RCBA_DEFAULT 0x0
148 #define ICH9_LPC_PIC_NUM_PINS 16
149 #define ICH9_LPC_IOAPIC_NUM_PINS 24
151 /* D31:F2 SATA Controller #1 */
152 #define ICH9_SATA1_DEV 31
153 #define ICH9_SATA1_FUNC 2
155 /* D30:F1 power management I/O registers
156 offset from the address ICH9_LPC_PMBASE */
158 /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
159 #define ICH9_PMIO_SIZE 128
160 #define ICH9_PMIO_MASK (ICH9_PMIO_SIZE - 1)
162 #define ICH9_PMIO_PM1_STS 0x00
163 #define ICH9_PMIO_PM1_EN 0x02
164 #define ICH9_PMIO_PM1_CNT 0x04
165 #define ICH9_PMIO_PM1_TMR 0x08
166 #define ICH9_PMIO_GPE0_STS 0x20
167 #define ICH9_PMIO_GPE0_EN 0x28
168 #define ICH9_PMIO_GPE0_LEN 16
169 #define ICH9_PMIO_SMI_EN 0x30
170 #define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
171 #define ICH9_PMIO_SMI_STS 0x34
173 /* FADT ACPI_ENABLE/ACPI_DISABLE */
174 #define ICH9_APM_ACPI_ENABLE 0x2
175 #define ICH9_APM_ACPI_DISABLE 0x3
178 /* D31:F3 SMBus controller */
179 #define ICH9_A2_SMB_REVISION 0x02
180 #define ICH9_SMB_PI 0x00
182 #define ICH9_SMB_SMBMBAR0 0x10
183 #define ICH9_SMB_SMBMBAR1 0x14
184 #define ICH9_SMB_SMBM_BAR 0
185 #define ICH9_SMB_SMBM_SIZE (1 << 8)
186 #define ICH9_SMB_SMB_BASE 0x20
187 #define ICH9_SMB_SMB_BASE_BAR 4
188 #define ICH9_SMB_SMB_BASE_SIZE (1 << 5)
189 #define ICH9_SMB_HOSTC 0x40
190 #define ICH9_SMB_HOSTC_SSRESET ((uint8_t)(1 << 3))
191 #define ICH9_SMB_HOSTC_I2C_EN ((uint8_t)(1 << 2))
192 #define ICH9_SMB_HOSTC_SMB_SMI_EN ((uint8_t)(1 << 1))
193 #define ICH9_SMB_HOSTC_HST_EN ((uint8_t)(1 << 0))
195 /* D31:F3 SMBus I/O and memory mapped I/O registers */
196 #define ICH9_SMB_DEV 31
197 #define ICH9_SMB_FUNC 3
199 #define ICH9_SMB_HST_STS 0x00
200 #define ICH9_SMB_HST_CNT 0x02
201 #define ICH9_SMB_HST_CMD 0x03
202 #define ICH9_SMB_XMIT_SLVA 0x04
203 #define ICH9_SMB_HST_D0 0x05
204 #define ICH9_SMB_HST_D1 0x06
205 #define ICH9_SMB_HOST_BLOCK_DB 0x07
207 #endif /* HW_ICH9_H */