include/hw/arm/iotkit.h

   1 /*
   2  * ARM IoT Kit
   3  *
   4  * Copyright (c) 2018 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 or
   9  * (at your option) any later version.
  10  */
  11
  12 /* This is a model of the Arm IoT Kit which is documented in
  13  * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
  14  * It contains:
  15  *  a Cortex-M33
  16  *  the IDAU
  17  *  some timers and watchdogs
  18  *  two peripheral protection controllers
  19  *  a memory protection controller
  20  *  a security controller
  21  *  a bus fabric which arranges that some parts of the address
  22  *  space are secure and non-secure aliases of each other
  23  *
  24  * QEMU interface:
  25  *  + QOM property "memory" is a MemoryRegion containing the devices provided
  26  *    by the board model.
  27  *  + QOM property "MAINCLK" is the frequency of the main system clock
  28  *  + QOM property "EXP_NUMIRQ" sets the number of expansion interrupts
  29  *  + Named GPIO inputs "EXP_IRQ" 0..n are the expansion interrupts, which
  30  *    are wired to the NVIC lines 32 .. n+32
  31  * Controlling up to 4 AHB expansion PPBs which a system using the IoTKit
  32  * might provide:
  33  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_nonsec[0..15]
  34  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_ap[0..15]
  35  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_enable
  36  *  + named GPIO outputs apb_ppcexp{0,1,2,3}_irq_clear
  37  *  + named GPIO inputs apb_ppcexp{0,1,2,3}_irq_status
  38  * Controlling each of the 4 expansion AHB PPCs which a system using the IoTKit
  39  * might provide:
  40  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_nonsec[0..15]
  41  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_ap[0..15]
  42  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_enable
  43  *  + named GPIO outputs ahb_ppcexp{0,1,2,3}_irq_clear
  44  *  + named GPIO inputs ahb_ppcexp{0,1,2,3}_irq_status
  45  * Controlling each of the 16 expansion MPCs which a system using the IoTKit
  46  * might provide:
  47  *  + named GPIO inputs mpcexp_status[0..15]
  48  */
  49
  50 #ifndef IOTKIT_H
  51 #define IOTKIT_H
  52
  53 #include "hw/sysbus.h"
  54 #include "hw/arm/armv7m.h"
  55 #include "hw/misc/iotkit-secctl.h"
  56 #include "hw/misc/tz-ppc.h"
  57 #include "hw/misc/tz-mpc.h"
  58 #include "hw/timer/cmsdk-apb-timer.h"
  59 #include "hw/timer/cmsdk-apb-dualtimer.h"
  60 #include "hw/watchdog/cmsdk-apb-watchdog.h"
  61 #include "hw/misc/unimp.h"
  62 #include "hw/or-irq.h"
  63 #include "hw/core/split-irq.h"
  64
  65 #define TYPE_IOTKIT "iotkit"
  66 #define IOTKIT(obj) OBJECT_CHECK(IoTKit, (obj), TYPE_IOTKIT)
  67
  68 /* We have an IRQ splitter and an OR gate input for each external PPC
  69  * and the 2 internal PPCs
  70  */
  71 #define NUM_EXTERNAL_PPCS (IOTS_NUM_AHB_EXP_PPC + IOTS_NUM_APB_EXP_PPC)
  72 #define NUM_PPCS (NUM_EXTERNAL_PPCS + 2)
  73
  74 typedef struct IoTKit {
  75     /*< private >*/
  76     SysBusDevice parent_obj;
  77
  78     /*< public >*/
  79     ARMv7MState armv7m;
  80     IoTKitSecCtl secctl;
  81     TZPPC apb_ppc0;
  82     TZPPC apb_ppc1;
  83     TZMPC mpc;
  84     CMSDKAPBTIMER timer0;
  85     CMSDKAPBTIMER timer1;
  86     qemu_or_irq ppc_irq_orgate;
  87     SplitIRQ sec_resp_splitter;
  88     SplitIRQ ppc_irq_splitter[NUM_PPCS];
  89     SplitIRQ mpc_irq_splitter[IOTS_NUM_EXP_MPC + IOTS_NUM_MPC];
  90     qemu_or_irq mpc_irq_orgate;
  91     qemu_or_irq nmi_orgate;
  92
  93     CMSDKAPBDualTimer dualtimer;
  94     UnimplementedDeviceState s32ktimer;
  95
  96     CMSDKAPBWatchdog s32kwatchdog;
  97     CMSDKAPBWatchdog nswatchdog;
  98     CMSDKAPBWatchdog swatchdog;
  99
 100     MemoryRegion container;
 101     MemoryRegion alias1;
 102     MemoryRegion alias2;
 103     MemoryRegion alias3;
 104     MemoryRegion sram0;
 105
 106     qemu_irq *exp_irqs;
 107     qemu_irq ppc0_irq;
 108     qemu_irq ppc1_irq;
 109     qemu_irq sec_resp_cfg;
 110     qemu_irq sec_resp_cfg_in;
 111     qemu_irq nsc_cfg_in;
 112
 113     qemu_irq irq_status_in[NUM_EXTERNAL_PPCS];
 114     qemu_irq mpcexp_status_in[IOTS_NUM_EXP_MPC];
 115
 116     uint32_t nsccfg;
 117
 118     /* Properties */
 119     MemoryRegion *board_memory;
 120     uint32_t exp_numirq;
 121     uint32_t mainclk_frq;
 122 } IoTKit;
 123
 124 #endif